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-rw-r--r--board/amcc/yucca/cmd_yucca.c2
-rw-r--r--board/amcc/yucca/flash.c2
-rw-r--r--board/amcc/yucca/init.S2
3 files changed, 3 insertions, 3 deletions
diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c
index 9c7afb2..e698b20 100644
--- a/board/amcc/yucca/cmd_yucca.c
+++ b/board/amcc/yucca/cmd_yucca.c
@@ -30,7 +30,7 @@
#include <asm/byteorder.h>
extern void print_evb440spe_info(void);
-static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
+static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
int flag, int argc, char *argv[]);
extern int cmd_get_data_size(char* arg, int default_size);
diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c
index c5a2e31..15b8a46 100644
--- a/board/amcc/yucca/flash.c
+++ b/board/amcc/yucca/flash.c
@@ -1004,7 +1004,7 @@ unsigned long flash_init(void)
}
} /*else if (index == 0) {*/
/* if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE)*/
-/* index = 8;*//* sram below op code flash -> new index 8*/
+/* index = 8;*/ /* sram below op code flash -> new index 8*/
/* }*/
DEBUGF("\n");
diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
index a950eac..5a3dd0e 100644
--- a/board/amcc/yucca/init.S
+++ b/board/amcc/yucca/init.S
@@ -121,7 +121,7 @@ tlbtabA:
/**************************************************************************
* TLB table for revB
*
- * Notice: revB of the 440SPe chip is very strict about PLB real addressess
+ * Notice: revB of the 440SPe chip is very strict about PLB real addresses
* and ranges to be mapped for config space: it seems to only work with
* d_nnnn_nnnn range (hangs the core upon config transaction attempts when
* set otherwise) while revA uses c_nnnn_nnnn.