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-rw-r--r--board/amcc/taishan/config.mk2
-rw-r--r--board/amcc/taishan/init.S10
-rw-r--r--board/amcc/taishan/lcd.c10
-rw-r--r--board/amcc/taishan/taishan.c28
-rw-r--r--board/amcc/taishan/u-boot.lds1
-rw-r--r--board/amcc/taishan/update.c2
6 files changed, 30 insertions, 23 deletions
diff --git a/board/amcc/taishan/config.mk b/board/amcc/taishan/config.mk
index 4eefff2..ee5eb1b 100644
--- a/board/amcc/taishan/config.mk
+++ b/board/amcc/taishan/config.mk
@@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
diff --git a/board/amcc/taishan/init.S b/board/amcc/taishan/init.S
index 8db043b..748ec0a 100644
--- a/board/amcc/taishan/init.S
+++ b/board/amcc/taishan/init.S
@@ -89,9 +89,9 @@
tlbtab:
tlbtab_start
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X )
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
tlbtab_end
diff --git a/board/amcc/taishan/lcd.c b/board/amcc/taishan/lcd.c
index 8d2dce3..624ae40 100644
--- a/board/amcc/taishan/lcd.c
+++ b/board/amcc/taishan/lcd.c
@@ -31,9 +31,9 @@
#define LCD_DELAY_NORMAL_US 100
#define LCD_DELAY_NORMAL_MS 2
-#define LCD_CMD_ADDR ((volatile char *)(CFG_EBC2_LCM_BASE))
-#define LCD_DATA_ADDR ((volatile char *)(CFG_EBC2_LCM_BASE+1))
-#define LCD_BLK_CTRL ((volatile char *)(CFG_EBC1_FPGA_BASE+0x2))
+#define LCD_CMD_ADDR ((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE))
+#define LCD_DATA_ADDR ((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE+1))
+#define LCD_BLK_CTRL ((volatile char *)(CONFIG_SYS_EBC1_FPGA_BASE+0x2))
#define mdelay(t) ({unsigned long msec=(t); while (msec--) { udelay(1000);}})
@@ -359,7 +359,7 @@ void set_phy_normal_mode(void)
static int do_led_test_off(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
volatile unsigned int *GpioOr =
- (volatile unsigned int *)(CFG_PERIPHERAL_BASE + 0x700);
+ (volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700);
*GpioOr |= 0x00300000;
return 0;
}
@@ -367,7 +367,7 @@ static int do_led_test_off(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
static int do_led_test_on(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
volatile unsigned int *GpioOr =
- (volatile unsigned int *)(CFG_PERIPHERAL_BASE + 0x700);
+ (volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700);
*GpioOr &= ~0x00300000;
return 0;
}
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index fdd82e7..28bdab5 100644
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -27,8 +27,9 @@
#include <asm/processor.h>
#include <spd_sdram.h>
#include <ppc4xx_enet.h>
+#include <netdev.h>
-#ifdef CFG_INIT_SHOW_RESET_REG
+#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
void show_reset_reg(void);
#endif
@@ -62,7 +63,7 @@ int board_early_init_f (void)
EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
- mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
+ mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);
/*-------------------------------------------------------------------------+
@@ -172,9 +173,9 @@ int board_early_init_f (void)
mtsdr(sdr_pfc1,reg);
/* Set GPIO 10 and 11 as output */
- GpioOdr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x718);
- GpioTcr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x704);
- GpioOr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x700);
+ GpioOdr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718);
+ GpioTcr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x704);
+ GpioOr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x700);
*GpioOdr &= ~(0x00300000);
*GpioTcr |= 0x00300000;
@@ -201,7 +202,7 @@ int checkboard (void)
}
putc ('\n');
-#ifdef CFG_INIT_SHOW_RESET_REG
+#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
show_reset_reg();
#endif
@@ -247,7 +248,7 @@ int pci_pre_init(struct pci_controller * hose )
* may not be sufficient for a given board.
*
************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
/*--------------------------------------------------------------------------+
@@ -262,7 +263,7 @@ void pci_target_init(struct pci_controller * hose )
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+ out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
@@ -271,12 +272,12 @@ void pci_target_init(struct pci_controller * hose )
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+ out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+ out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* is_pci_host
@@ -311,3 +312,8 @@ int post_hotkeys_pressed(void)
return (ctrlc());
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
diff --git a/board/amcc/taishan/u-boot.lds b/board/amcc/taishan/u-boot.lds
index 85d3759..e620808 100644
--- a/board/amcc/taishan/u-boot.lds
+++ b/board/amcc/taishan/u-boot.lds
@@ -137,6 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/amcc/taishan/update.c b/board/amcc/taishan/update.c
index ed2c196..96b918b 100644
--- a/board/amcc/taishan/update.c
+++ b/board/amcc/taishan/update.c
@@ -51,7 +51,7 @@ const uchar bootstrap_buf[16] = {
static int update_boot_eeprom(void)
{
ulong len = 0x10;
- uchar chip = CFG_BOOTSTRAP_IIC_ADDR;
+ uchar chip = CONFIG_SYS_BOOTSTRAP_IIC_ADDR;
uchar *pbuf = (uchar *)bootstrap_buf;
int ii, jj;
generated by cgit v1.1 at 2024-11-05 22:21:00 +0000