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-rw-r--r--board/amcc/luan/config.mk2
-rw-r--r--board/amcc/luan/flash.c20
-rw-r--r--board/amcc/luan/init.S10
-rw-r--r--board/amcc/luan/luan.c37
-rw-r--r--board/amcc/luan/u-boot.lds1
5 files changed, 36 insertions, 34 deletions
diff --git a/board/amcc/luan/config.mk b/board/amcc/luan/config.mk
index f52c206..cd02aab 100644
--- a/board/amcc/luan/config.mk
+++ b/board/amcc/luan/config.mk
@@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
diff --git a/board/amcc/luan/flash.c b/board/amcc/luan/flash.c
index d3c3c0d..2d3b154 100644
--- a/board/amcc/luan/flash.c
+++ b/board/amcc/luan/flash.c
@@ -42,7 +42,7 @@
#define DEBUGF(x...)
#endif /* DEBUG */
-static unsigned long flash_addr_table[1][CFG_MAX_FLASH_BANKS] = {
+static unsigned long flash_addr_table[1][CONFIG_SYS_MAX_FLASH_BANKS] = {
{0xff900000, 0xff980000, 0xffc00000}, /* 0:000: configuraton 3 */
};
@@ -59,7 +59,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info);
unsigned long flash_init(void)
{
unsigned long total_b = 0;
- unsigned long size_b[CFG_MAX_FLASH_BANKS];
+ unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
unsigned short index = 0;
int i;
@@ -69,7 +69,7 @@ unsigned long flash_init(void)
DEBUGF("FLASH: Index: %d\n", index);
/* Init: no FLASHes known */
- for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
@@ -92,15 +92,15 @@ unsigned long flash_init(void)
}
/* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
- CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
&flash_info[2]);
-#ifdef CFG_ENV_IS_IN_FLASH
- (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
- CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[2]);
- (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
- CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[2]);
#endif
diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S
index d5ee117..fb54dea 100644
--- a/board/amcc/luan/init.S
+++ b/board/amcc/luan/init.S
@@ -54,7 +54,7 @@ tlbtab:
tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I)
/*
* TLB entries for SDRAM are not needed on this platform.
@@ -63,12 +63,12 @@ tlbtab:
*/
/* internal ram (l2 cache) */
- tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I)
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I)
/* peripherals at f0000000 */
- tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I)
/* PCI */
- tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I)
tlbtab_end
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index b14b6e1..de3e3d8 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -25,12 +25,13 @@
#include <command.h>
#include <ppc4xx.h>
#include <asm/processor.h>
+#include <asm/ppc4xx-isram.h>
#include <spd_sdram.h>
#include "epld.h"
DECLARE_GLOBAL_DATA_PTR;
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*************************************************************************
@@ -80,7 +81,7 @@ int board_early_init_f(void)
************************************************************************/
int misc_init_r(void)
{
- volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
+ volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE;
/* set modes of operation */
x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
@@ -166,7 +167,7 @@ int pci_pre_init( struct pci_controller *hose )
* may not be sufficient for a given board.
*
************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
@@ -181,7 +182,7 @@ void pci_target_init(struct pci_controller *hose)
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+ out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
@@ -190,12 +191,12 @@ void pci_target_init(struct pci_controller *hose)
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+ out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+ out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
@@ -255,7 +256,7 @@ static int on_off( const char *s )
************************************************************************/
static void l2cache_disable(void)
{
- mtdcr( l2_cache_cfg, 0 );
+ mtdcr( L2_CACHE_CFG, 0 );
}
@@ -265,24 +266,24 @@ static void l2cache_disable(void)
************************************************************************/
static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
{
- mtdcr( l2_cache_cfg, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
+ mtdcr( L2_CACHE_CFG, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
- mtdcr( l2_cache_addr, 0 ); /* set L2_ADDR with all zeros */
+ mtdcr( L2_CACHE_ADDR, 0 ); /* set L2_ADDR with all zeros */
- mtdcr( l2_cache_cmd, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
+ mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
- while (!(mfdcr( l2_cache_stat ) & 0x80000000 )) ;; /* poll L2_SR for completion */
+ while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ;; /* poll L2_SR for completion */
- mtdcr( l2_cache_cmd, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
+ mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
- mtdcr( l2_cache_cmd, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
+ mtdcr( L2_CACHE_CMD, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
- mtdcr( l2_cache_snp0, 0 ); /* snoop registers */
- mtdcr( l2_cache_snp1, 0 );
+ mtdcr( L2_CACHE_SNP0, 0 ); /* snoop registers */
+ mtdcr( L2_CACHE_SNP1, 0 );
__asm__ volatile ("sync"); /* msync */
- mtdcr( l2_cache_cfg, 0xe0000000 ); /* inst and data use L2 */
+ mtdcr( L2_CACHE_CFG, 0xe0000000 ); /* inst and data use L2 */
__asm__ volatile ("sync");
}
@@ -294,7 +295,7 @@ static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
************************************************************************/
static int l2cache_status(void)
{
- return (mfdcr( l2_cache_cfg ) & 0x60000000) != 0;
+ return (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0;
}
diff --git a/board/amcc/luan/u-boot.lds b/board/amcc/luan/u-boot.lds
index 7911785..b66c768 100644
--- a/board/amcc/luan/u-boot.lds
+++ b/board/amcc/luan/u-boot.lds
@@ -137,6 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
generated by cgit v1.1 at 2024-11-05 19:00:59 +0000