diff options
Diffstat (limited to 'board/amcc/kilauea')
| -rw-r--r-- | board/amcc/kilauea/cmd_pll.c | 10 | ||||
| -rw-r--r-- | board/amcc/kilauea/kilauea.c | 16 |
2 files changed, 13 insertions, 13 deletions
diff --git a/board/amcc/kilauea/cmd_pll.c b/board/amcc/kilauea/cmd_pll.c index 0d2f27f..0f571fe 100644 --- a/board/amcc/kilauea/cmd_pll.c +++ b/board/amcc/kilauea/cmd_pll.c @@ -48,7 +48,7 @@ do { \ int __i; \ for (__i = 0; __i < 2; __i++) \ - eeprom_write (CFG_I2C_EEPROM_ADDR, \ + eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, \ EEPROM_CONF_OFFSET + __i*BUF_STEP, \ pll_select[freq], \ BUF_STEP + __i*BUF_STEP); \ @@ -151,7 +151,7 @@ pll_debug(int off) uchar buffer[EEPROM_SDSTP_PARAM]; memset(buffer, 0, sizeof(buffer)); - eeprom_read(CFG_I2C_EEPROM_ADDR, off, + eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off, buffer, EEPROM_SDSTP_PARAM); printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off); @@ -168,9 +168,9 @@ test_write(void) /* * Write twice, 8 bytes per write */ - eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET, + eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET, testbuf, 8); - eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8, + eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8, testbuf, 16); printf("done\n"); @@ -236,7 +236,7 @@ ret: } U_BOOT_CMD( - pllalter, CFG_MAXARGS, 1, do_pll_alter, + pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter, "pllalter- change pll frequence \n", "pllalter <selection> - change pll frequence \n\n\ ** New freq take effect after reset. ** \n\ diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index f407e19..7e84a61 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -36,7 +36,7 @@ DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* * Board early initialization function @@ -197,7 +197,7 @@ int board_early_init_f (void) SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NRB_BUSY | - (0x80000000 >> (28 + CFG_NAND_CS)); + (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); mtsdr(SDR0_CUST0, val); /* @@ -210,9 +210,9 @@ int board_early_init_f (void) /* * Configure FPGA register with PCIe reset */ - out_be32((void *)CFG_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */ + out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */ mdelay(50); - out_be32((void *)CFG_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */ + out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */ return 0; } @@ -222,7 +222,7 @@ int misc_init_r(void) #ifdef CONFIG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); #endif @@ -330,9 +330,9 @@ void pcie_setup_hoses(int busno) /* setup mem resource */ pci_set_region(hose->regions + 0, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMSIZE, PCI_REGION_MEM); hose->region_count = 1; pci_register_hose(hose); |