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-rw-r--r--board/amcc/bamboo/bamboo.c80
-rw-r--r--board/amcc/bamboo/u-boot.lds4
2 files changed, 42 insertions, 42 deletions
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index d02add5..803995a 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -31,6 +31,8 @@ void ext_bus_cntlr_init(void);
void configure_ppc440ep_pins(void);
int is_nand_selected(void);
+unsigned char cfg_simulate_spd_eeprom[128];
+
gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
#if 0
{ /* GPIO Alternate1 Alternate2 Alternate3 */
@@ -357,10 +359,7 @@ void nand_init(void)
int checkboard(void)
{
- sys_info_t sysinfo;
- unsigned char *s = getenv("serial#");
-
- get_sys_info(&sysinfo);
+ char *s = getenv("serial#");
printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
if (s != NULL) {
@@ -369,18 +368,12 @@ int checkboard(void)
}
putc('\n');
- printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
- printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
-
return (0);
}
/*************************************************************************
*
- * fixed_sdram_init -- Bamboo has one bank onboard sdram (plus DIMM)
+ * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM)
*
* Fixed memory is composed of :
* MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
@@ -397,24 +390,40 @@ int checkboard(void)
* PLB @ 133 MHz
*
************************************************************************/
-void fixed_sdram_init(void)
+static void init_spd_array(void)
{
- /*
- * clear this first, if the DDR is enabled by a debugger
- * then you can not make changes.
- */
- mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
+ cfg_simulate_spd_eeprom[8] = 0x04; /* 2.5 Volt */
+ cfg_simulate_spd_eeprom[2] = 0x07; /* DDR ram */
- /*--------------------------------------------------------------------
- * Setup for board-specific specific mem
- *------------------------------------------------------------------*/
- /*
- * Following for CAS Latency = 2.5 @ 133 MHz PLB
- */
- mtsdram(mem_b0cr, 0x00082001);
- mtsdram(mem_b1cr, 0x00000000);
- mtsdram(mem_b2cr, 0x00000000);
- mtsdram(mem_b3cr, 0x00000000);
+#ifdef CONFIG_DDR_ECC
+ cfg_simulate_spd_eeprom[11] = 0x02; /* ECC ON : 02 OFF : 00 */
+ cfg_simulate_spd_eeprom[31] = 0x08; /* bankSizeID: 32MB */
+ cfg_simulate_spd_eeprom[3] = 0x0C; /* num Row Addr: 12 */
+#else
+ cfg_simulate_spd_eeprom[11] = 0x00; /* ECC ON : 02 OFF : 00 */
+ cfg_simulate_spd_eeprom[31] = 0x10; /* bankSizeID: 64MB */
+ cfg_simulate_spd_eeprom[3] = 0x0D; /* num Row Addr: 13 */
+#endif
+
+ cfg_simulate_spd_eeprom[4] = 0x09; /* numColAddr: 9 */
+ cfg_simulate_spd_eeprom[5] = 0x01; /* numBanks: 1 */
+ cfg_simulate_spd_eeprom[0] = 0x80; /* number of SPD bytes used: 128 */
+ cfg_simulate_spd_eeprom[1] = 0x08; /* total number bytes in SPD device = 256 */
+ cfg_simulate_spd_eeprom[21] = 0x00; /* not registered: 0 registered : 0x02*/
+ cfg_simulate_spd_eeprom[6] = 0x20; /* Module data width: 32 bits */
+ cfg_simulate_spd_eeprom[7] = 0x00; /* Module data width continued: +0 */
+ cfg_simulate_spd_eeprom[15] = 0x01; /* wcsbc = 1 */
+ cfg_simulate_spd_eeprom[27] = 0x50; /* tRpNs = 20 ns */
+ cfg_simulate_spd_eeprom[29] = 0x50; /* tRcdNs = 20 ns */
+
+ cfg_simulate_spd_eeprom[30] = 45; /* tRasNs */
+
+ cfg_simulate_spd_eeprom[18] = 0x0C; /* casBit (2,2.5) */
+
+ cfg_simulate_spd_eeprom[9] = 0x75; /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
+ cfg_simulate_spd_eeprom[23] = 0xA0; /* SDRAM Cycle Time (cas latency 2) = 10 ns */
+ cfg_simulate_spd_eeprom[25] = 0x00; /* SDRAM Cycle Time (cas latency 1.5) = N.A */
+ cfg_simulate_spd_eeprom[12] = 0x82; /* refresh Rate Type: Normal (15.625us) + Self refresh */
}
long int initdram (int board_type)
@@ -422,9 +431,10 @@ long int initdram (int board_type)
long dram_size = 0;
/*
- * First init bank0 (onboard sdram) and then configure the DIMM-slots
+ * First write simulated values in eeprom array for onboard bank 0
*/
- fixed_sdram_init();
+ init_spd_array();
+
dram_size = spd_sdram (0);
return dram_size;
@@ -483,20 +493,8 @@ int testdram(void)
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
- unsigned long strap;
unsigned long addr;
- /*--------------------------------------------------------------------------+
- * Bamboo is always configured as the host & requires the
- * PCI arbiter to be enabled.
- *--------------------------------------------------------------------------*/
- mfsdr(sdr_sdstp1, strap);
- if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
- printf("PCI: SDR0_STRP1[PAE] not set.\n");
- printf("PCI: Configuration aborted.\n");
- return 0;
- }
-
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds
index c978dba..176900e 100644
--- a/board/amcc/bamboo/u-boot.lds
+++ b/board/amcc/bamboo/u-boot.lds
@@ -74,7 +74,6 @@ SECTIONS
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/440gx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
@@ -94,6 +93,7 @@ SECTIONS
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
@@ -126,11 +126,13 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;