3 files changed, 41 insertions, 41 deletions

diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
index 8d79be2..0db6199 100644
--- a/board/amcc/acadia/acadia.c
+++ b/board/amcc/acadia/acadia.c
@@ -57,7 +57,7 @@ int board_early_init_f(void)
 
 #if !defined(CONFIG_NAND_U_BOOT)
 	/* don't reinit PLL when booting via I2C bootstrap option */
-	mfsdr(SDR_PINSTP, reg);
+	mfsdr(SDR0_PINSTP, reg);
 	if (reg != 0xf0000000)
 		board_pll_init_f();
 #endif
@@ -65,18 +65,18 @@ int board_early_init_f(void)
 	acadia_gpio_init();
 
 	/* Configure 405EZ for NAND usage */
-	mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
-	mfsdr(sdrultra0, reg);
+	mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
+	mfsdr(SDR0_ULTRA0, reg);
 	reg &= ~SDR_ULTRA0_CSN_MASK;
 	reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) |
 		SDR_ULTRA0_NDGPIOBP |
 		SDR_ULTRA0_EBCRDYEN |
 		SDR_ULTRA0_NFSRSTEN;
-	mtsdr(sdrultra0, reg);
+	mtsdr(SDR0_ULTRA0, reg);
 
 	/* USB Host core needs this bit set */
-	mfsdr(sdrultra1, reg);
-	mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
+	mfsdr(SDR0_ULTRA1, reg);
+	mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
 
 	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
 	mtdcr(uicer, 0x00000000);	/* disable all ints */
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
index 3e5c80e..8c2addc 100644
--- a/board/amcc/acadia/memory.c
+++ b/board/amcc/acadia/memory.c
@@ -65,7 +65,7 @@ phys_size_t initdram(int board_type)
 	u32 reg;
 
 	/* don't reinit PLL when booting via I2C bootstrap option */
-	mfsdr(SDR_PINSTP, reg);
+	mfsdr(SDR0_PINSTP, reg);
 	if (reg != 0xf0000000)
 		board_pll_init_f();
 #endif
@@ -81,25 +81,25 @@ phys_size_t initdram(int board_type)
 	gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
 
 	/* 2. EBC in Async mode */
-	mtebc(pb1ap, 0x078F1EC0);
-	mtebc(pb2ap, 0x078F1EC0);
-	mtebc(pb1cr, 0x000BC000);
-	mtebc(pb2cr, 0x020BC000);
+	mtebc(PB1AP, 0x078F1EC0);
+	mtebc(PB2AP, 0x078F1EC0);
+	mtebc(PB1CR, 0x000BC000);
+	mtebc(PB2CR, 0x020BC000);
 
 	/* 3. Set CRAM in Sync mode */
 	cram_bcr_write(0x7012);		/* CRAM burst setting */
 
 	/* 4. EBC in Sync mode */
-	mtebc(pb1ap, 0x9C0201C0);
-	mtebc(pb2ap, 0x9C0201C0);
+	mtebc(PB1AP, 0x9C0201C0);
+	mtebc(PB2AP, 0x9C0201C0);
 
 	/* Set GPIO pins back to alternate function */
 	gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
 	gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
 
 	/* Config EBC to use RDY */
-	mfsdr(sdrultra0, val);
-	mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN);
+	mfsdr(SDR0_ULTRA0, val);
+	mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
 
 	/* Wait a short while, since for NAND booting this is too fast */
 	for (i=0; i<200000; i++)
diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c
index 9dcce35..b63813c 100644
--- a/board/amcc/acadia/pll.c
+++ b/board/amcc/acadia/pll.c
@@ -51,11 +51,11 @@ void board_pll_init_f(void)
 	 */
 
 	/* Initialize PLL */
-	mtcpr(cprpllc, 0x0000033c);
-	mtcpr(cprplld, 0x0c010200);
-	mtcpr(cprprimad, 0x04060c0c);
-	mtcpr(cprperd0, 0x000c0000);	/* SPI clk div. eq. OPB clk div. */
-	mtcpr(cprclkupd, 0x40000000);
+	mtcpr(CPR0_PLLC, 0x0000033c);
+	mtcpr(CPR0_PLLD, 0x0c010200);
+	mtcpr(CPC0_PRIMAD, 0x04060c0c);
+	mtcpr(CPC0_PERD0, 0x000c0000);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(CPR0_CLKUP, 0x40000000);
 }
 
 #elif defined(PLLMR0_266_160_80)
@@ -83,13 +83,13 @@ void board_pll_init_f(void)
 	 */
 
 	/* Initialize PLL */
-	mtcpr(cprpllc, 0x20000238);
-	mtcpr(cprplld, 0x03010400);
-	mtcpr(cprprimad, 0x03050a0a);
-	mtcpr(cprperc0, 0x00000000);
-	mtcpr(cprperd0, 0x070a0707);	/* SPI clk div. eq. OPB clk div. */
-	mtcpr(cprperd1, 0x07323200);
-	mtcpr(cprclkupd, 0x40000000);
+	mtcpr(CPR0_PLLC, 0x20000238);
+	mtcpr(CPR0_PLLD, 0x03010400);
+	mtcpr(CPC0_PRIMAD, 0x03050a0a);
+	mtcpr(CPC0_PERC0, 0x00000000);
+	mtcpr(CPC0_PERD0, 0x070a0707);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(CPC0_PERD1, 0x07323200);
+	mtcpr(CPR0_CLKUP, 0x40000000);
 }
 
 #elif defined(PLLMR0_333_166_83)
@@ -117,12 +117,12 @@ void board_pll_init_f(void)
 	 */
 
 	/* Initialize PLL */
-	mtcpr(cprpllc, 0x0000033C);
-	mtcpr(cprplld, 0x0a010000);
-	mtcpr(cprprimad, 0x02040808);
-	mtcpr(cprperd0, 0x02080505);	/* SPI clk div. eq. OPB clk div. */
-	mtcpr(cprperd1, 0xA6A60300);
-	mtcpr(cprclkupd, 0x40000000);
+	mtcpr(CPR0_PLLC, 0x0000033C);
+	mtcpr(CPR0_PLLD, 0x0a010000);
+	mtcpr(CPC0_PRIMAD, 0x02040808);
+	mtcpr(CPC0_PERD0, 0x02080505);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(CPC0_PERD1, 0xA6A60300);
+	mtcpr(CPR0_CLKUP, 0x40000000);
 }
 
 #elif defined(PLLMR0_100_100_12)
@@ -143,12 +143,12 @@ void board_pll_init_f(void)
 	 */
 
 	/* Initialize PLL */
-	mtcpr(cprpllc, 0x000003BC);
-	mtcpr(cprplld, 0x06060600);
-	mtcpr(cprprimad, 0x02020004);
-	mtcpr(cprperd0, 0x04002828);	/* SPI clk div. eq. OPB clk div. */
-	mtcpr(cprperd1, 0xC8C81600);
-	mtcpr(cprclkupd, 0x40000000);
+	mtcpr(CPR0_PLLC, 0x000003BC);
+	mtcpr(CPR0_PLLD, 0x06060600);
+	mtcpr(CPC0_PRIMAD, 0x02020004);
+	mtcpr(CPC0_PERD0, 0x04002828);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(CPC0_PERD1, 0xC8C81600);
+	mtcpr(CPR0_CLKUP, 0x40000000);
 }
 #endif				/* CPU_<speed>_405EZ */
 
@@ -167,12 +167,12 @@ unsigned long get_tbclk(void)
 	/*
 	 * Read PLL Mode registers
 	 */
-	mfcpr(cprplld, cpr_plld);
+	mfcpr(CPR0_PLLD, cpr_plld);
 
 	/*
 	 * Read CPR_PRIMAD register
 	 */
-	mfcpr(cprprimad, cpr_primad);
+	mfcpr(CPC0_PRIMAD, cpr_primad);
 
 	/*
 	 * Determine CPU clock frequency