diff options
Diffstat (limited to 'board/amcc/acadia')
| -rw-r--r-- | board/amcc/acadia/acadia.c | 34 | ||||
| -rw-r--r-- | board/amcc/acadia/cmd_acadia.c | 2 | ||||
| -rw-r--r-- | board/amcc/acadia/memory.c | 18 |
3 files changed, 27 insertions, 27 deletions
diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 8b82ea4..8d79be2 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -31,24 +31,24 @@ static void acadia_gpio_init(void) /* * GPIO0 setup (select GPIO or alternate function) */ - out32(GPIO0_OSRL, CFG_GPIO0_OSRL); - out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ - out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); - out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ - out32(GPIO0_TSRL, CFG_GPIO0_TSRL); - out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ - out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ + out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL); + out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */ + out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L); + out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */ + out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL); + out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */ + out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */ /* * Ultra (405EZ) was nice enough to add another GPIO controller */ - out32(GPIO1_OSRH, CFG_GPIO1_OSRH); /* output select */ - out32(GPIO1_OSRL, CFG_GPIO1_OSRL); - out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H); /* input select */ - out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L); - out32(GPIO1_TSRH, CFG_GPIO1_TSRH); /* three-state select */ - out32(GPIO1_TSRL, CFG_GPIO1_TSRL); - out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */ + out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH); /* output select */ + out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL); + out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H); /* input select */ + out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L); + out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH); /* three-state select */ + out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL); + out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR); /* enable output driver for outputs */ } int board_early_init_f(void) @@ -68,7 +68,7 @@ int board_early_init_f(void) mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN); mfsdr(sdrultra0, reg); reg &= ~SDR_ULTRA0_CSN_MASK; - reg |= (SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS) | + reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) | SDR_ULTRA0_NDGPIOBP | SDR_ULTRA0_EBCRDYEN | SDR_ULTRA0_NFSRSTEN; @@ -91,7 +91,7 @@ int board_early_init_f(void) int misc_init_f(void) { /* Set EPLD to take PHY out of reset */ - out8(CFG_CPLD_BASE + 0x05, 0x00); + out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00); udelay(100000); return 0; @@ -105,7 +105,7 @@ int checkboard(void) char *s = getenv("serial#"); u8 rev; - rev = in8(CFG_CPLD_BASE + 0); + rev = in8(CONFIG_SYS_CPLD_BASE + 0); printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev); if (s != NULL) { diff --git a/board/amcc/acadia/cmd_acadia.c b/board/amcc/acadia/cmd_acadia.c index fb7ea35..052cf61 100644 --- a/board/amcc/acadia/cmd_acadia.c +++ b/board/amcc/acadia/cmd_acadia.c @@ -84,7 +84,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (i2c_write(chip, 0, 1, buf, 16) != 0) printf("Error writing to EEPROM at address 0x%x\n", chip); - udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); + udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); if (i2c_write(chip, 0x10, 1, buf+16, 4) != 0) printf("Error2 writing to EEPROM at address 0x%x\n", chip); diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 48a6725..3e5c80e 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -39,7 +39,7 @@ static void cram_bcr_write(u32 wr_val) wr_val <<= 2; /* set CRAM_CRE to 1 */ - gpio_write_bit(CFG_GPIO_CRAM_CRE, 1); + gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1); /* Write BCR to CRAM on CS1 */ out32(wr_val + 0x00200000, 0); @@ -53,7 +53,7 @@ static void cram_bcr_write(u32 wr_val) eieio(); /* set CRAM_CRE back to 0 (normal operation) */ - gpio_write_bit(CFG_GPIO_CRAM_CRE, 0); + gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0); return; } @@ -75,10 +75,10 @@ phys_size_t initdram(int board_type) u32 val; /* 1. EBC need to program READY, CLK, ADV for ASync mode */ - gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); + gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); + gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); + gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); + gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); /* 2. EBC in Async mode */ mtebc(pb1ap, 0x078F1EC0); @@ -94,8 +94,8 @@ phys_size_t initdram(int board_type) mtebc(pb2ap, 0x9C0201C0); /* Set GPIO pins back to alternate function */ - gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); - gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); + gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); + gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); /* Config EBC to use RDY */ mfsdr(sdrultra0, val); @@ -106,5 +106,5 @@ phys_size_t initdram(int board_type) ; #endif - return (CFG_MBYTES_RAM << 20); + return (CONFIG_SYS_MBYTES_RAM << 20); } |