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-rw-r--r--board/amcc/acadia/Makefile2
-rw-r--r--board/amcc/acadia/acadia.c16
-rw-r--r--board/amcc/acadia/memory.c11
-rw-r--r--board/amcc/acadia/pll.c (renamed from board/amcc/acadia/cpr.c)0
4 files changed, 21 insertions, 8 deletions
diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile
index ddbcb80..c56b273 100644
--- a/board/amcc/acadia/Makefile
+++ b/board/amcc/acadia/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o cmd_acadia.o cpr.o memory.o
+COBJS = $(BOARD).o cmd_acadia.o memory.o pll.o
SOBJS =
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
index 46d63e6..8b82ea4 100644
--- a/board/amcc/acadia/acadia.c
+++ b/board/amcc/acadia/acadia.c
@@ -31,13 +31,13 @@ static void acadia_gpio_init(void)
/*
* GPIO0 setup (select GPIO or alternate function)
*/
- out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
- out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
- out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
- out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
- out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
- out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
- out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
+ out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
+ out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
+ out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
+ out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
+ out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
+ out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
+ out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
/*
* Ultra (405EZ) was nice enough to add another GPIO controller
@@ -55,10 +55,12 @@ int board_early_init_f(void)
{
unsigned int reg;
+#if !defined(CONFIG_NAND_U_BOOT)
/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
+#endif
acadia_gpio_init();
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
index 25904d3..9346d2c 100644
--- a/board/amcc/acadia/memory.c
+++ b/board/amcc/acadia/memory.c
@@ -31,6 +31,8 @@
#include <asm/io.h>
#include <asm/gpio.h>
+extern void board_pll_init_f(void);
+
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
@@ -67,6 +69,15 @@ static void cram_bcr_write(u32 wr_val)
long int initdram(int board_type)
{
+#if defined(CONFIG_NAND_SPL)
+ u32 reg;
+
+ /* don't reinit PLL when booting via I2C bootstrap option */
+ mfsdr(SDR_PINSTP, reg);
+ if (reg != 0xf0000000)
+ board_pll_init_f();
+#endif
+
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
int i;
u32 val;
diff --git a/board/amcc/acadia/cpr.c b/board/amcc/acadia/pll.c
index 9dcce35..9dcce35 100644
--- a/board/amcc/acadia/cpr.c
+++ b/board/amcc/acadia/pll.c