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Diffstat (limited to 'board/amcc/acadia/memory.c')
-rw-r--r--board/amcc/acadia/memory.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
index 3e5c80e..8c2addc 100644
--- a/board/amcc/acadia/memory.c
+++ b/board/amcc/acadia/memory.c
@@ -65,7 +65,7 @@ phys_size_t initdram(int board_type)
u32 reg;
/* don't reinit PLL when booting via I2C bootstrap option */
- mfsdr(SDR_PINSTP, reg);
+ mfsdr(SDR0_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
#endif
@@ -81,25 +81,25 @@ phys_size_t initdram(int board_type)
gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
/* 2. EBC in Async mode */
- mtebc(pb1ap, 0x078F1EC0);
- mtebc(pb2ap, 0x078F1EC0);
- mtebc(pb1cr, 0x000BC000);
- mtebc(pb2cr, 0x020BC000);
+ mtebc(PB1AP, 0x078F1EC0);
+ mtebc(PB2AP, 0x078F1EC0);
+ mtebc(PB1CR, 0x000BC000);
+ mtebc(PB2CR, 0x020BC000);
/* 3. Set CRAM in Sync mode */
cram_bcr_write(0x7012); /* CRAM burst setting */
/* 4. EBC in Sync mode */
- mtebc(pb1ap, 0x9C0201C0);
- mtebc(pb2ap, 0x9C0201C0);
+ mtebc(PB1AP, 0x9C0201C0);
+ mtebc(PB2AP, 0x9C0201C0);
/* Set GPIO pins back to alternate function */
gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
/* Config EBC to use RDY */
- mfsdr(sdrultra0, val);
- mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN);
+ mfsdr(SDR0_ULTRA0, val);
+ mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
/* Wait a short while, since for NAND booting this is too fast */
for (i=0; i<200000; i++)