diff options
Diffstat (limited to 'board/RPXlite/README')
| -rw-r--r-- | board/RPXlite/README | 877 |
1 files changed, 877 insertions, 0 deletions
diff --git a/board/RPXlite/README b/board/RPXlite/README new file mode 100644 index 0000000..3ca6711 --- /dev/null +++ b/board/RPXlite/README @@ -0,0 +1,877 @@ +# Porting U-Boot onto RPXlite board +# Written by Yoo. Jonghoon +# E-Mail : yooth@ipone.co.kr +# IP ONE Inc. + +# Since 2001. 1. 29 + +# Shell : bash +# Cross-compile tools : Montavista Hardhat +# Debugging tools : Windriver VisionProbe (PowerPC BDM) +# ppcboot ver. : ppcboot-0.8.1 + +############################################################### +# 1. Hardware setting +############################################################### + +1.1. Board, BDM settings + Install board, BDM, connect each other + +1.2. Save Register value + Boot with board-on monitor program and save the + register values with BDM. + +1.3. Configure flash programmer + Check flash memory area in the memory map. + 0xFFC00000 - 0xFFFFFFFF + + Boot monitor program is at + 0xFFF00000 + + You can program on-board flash memory with VisionClick + flash programmer. Set the target flash device as: + + 29DL800B + + (?) The flash memory device in the board *is* 29LV800B, + but I cannot program it with '29LV800B' option. + (in VisionClick flash programming tools) + I don't know why... + +1.4. Save boot monitor program *IMPORTANT* + Upload boot monitor program from board to file. + boot monitor program starts at 0xFFF00000 + +1.5. Test flash memory programming + Try to erase boot program in the flash memory, + and re-write them. + *WARNING* YOU MUST SAVE BOOT PROGRAM TO FILE + BEFORE ERASING FLASH + +############################################################### +# 2. U-Boot setting +############################################################### + +2.1. Download U-Boot tarball at + ftp://ftp.denx.de + (The latest version is ppcboot-0.8.1.tar.bz2) + + To extract the archive use the following syntax : + > bzip2 -cd ppcboot-0.8.1.tar.bz2 | tar xf - + +2.2. Add the following lines in '.profile' + export PATH=$PATH:/opt/hardhat/devkit/ppc/8xx/bin + +2.3. Make board specific config, for example: + > cd ppcboot-0.8.1 + > make TQM860L_config + + Now we can build ppcboot bin files. + After make all, you must see these files in your + ppcboot root directory. + + ppcboot + ppcboot.bin + ppcboot.srec + ppcboot.map + +2.4. Make your own board directory into the + ppcboot-0.8.1/board + and make your board-specific files here. + + For exmanple, tqm8xx files are composed of + .depend : Nothing + Makefile : To make config file + config.mk : Sets base address + flash.c : Flash memory control files + ppcboot.lds : linker(ld) script? (I don't know this yet) + tqm8xx.c : DRAM control and board check routines + + And, add your board config lines in the + ppcboot-0.8.1/Makefile + + Finally, add config_(your board).h file in the + ppcboot-0.8.1/include/ + + I've made board/rpxlite directory, and just copied + tqm8xx settings for now. + + Rebuild ppcboot for rpxlite board: + > make rpxlite_config + > make + +############################################################### +# 3. U-Boot porting +############################################################### + +3.1. My RPXlite files are based on tqm8xx board files. + > cd board + > cp -r tqm8xx RPXLITE + > cd RPXLITE + > mv tqm8xx.c RPXLITE.c + > cd ../../include + > cp config_tqm8xx.h config_RPXLITE.h + +3.2. Modified files are: + board/RPXLITE/RPXLITE.c /* DRAM-related routines */ + board/RPXLITE/flash.c /* flash-related routines */ + board/RPXLITE/config.mk /* set text base address */ + arch/powerpc/cpu/mpc8xx/serial.c /* board specific register setting */ + include/config_RPXLITE.h /* board specific registers */ + + See 'reg_config.txt' for register values in detail. + +############################################################### +# 4. Running Linux +############################################################### + + +############################################################### +# Misc Information +############################################################### + +mem_config.txt: +=============== + +Flash memory device : AM29LV800BB (1Mx8Bit) x 4 device +manufacturer id : 01 (AMD) +device id : 5B (AM29LV800B) +size : 4Mbyte +sector # : 19 + +Sector information : + +number start addr. size +00 FFC0_0000 64 +01 FFC1_0000 32 +02 FFC1_8000 32 +03 FFC2_0000 128 +04 FFC4_0000 256 +05 FFC8_0000 256 +06 FFCC_0000 256 +07 FFD0_0000 256 +08 FFD4_0000 256 +09 FFD8_0000 256 +10 FFDC_0000 256 +11 FFE0_0000 256 +12 FFE4_0000 256 +13 FFE8_0000 256 +14 FFEC_0000 256 +15 FFF0_0000 256 +16 FFF4_0000 256 +17 FFF8_0000 256 +18 FFFC_0000 256 + + +reg_config.txt: +=============== + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* SIU (System Interface Unit) */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ + + +/*### IMMR */ +/*### Internal Memory Map Register */ +/*### Chap. 11.4.1 */ + + ISB = 0xFA20 /* Set the Immap base = 0xFA20 0000 */ + PARTNUM = 0x21 + MASKNUM = 0x00 + + => 0xFA20 2100 + +--------------------------------------------------------------------- + +/*### SIUMCR */ +/*### SIU Module Configuration Register */ +/*### Chap. 11.4.2 */ +/*### Offset : 0x0000 0000 */ + + EARB = 0 + EARP = 0 + DSHW = 0 + DBGC = 0 + DBPC = 0 + FRC = 0 + DLK = 0 + OPAR = 0 + PNCS = 0 + DPC = 0 + MPRE = 0 + MLRC = 10 /* ~KR/~RETRY/~IRQ4/SPKROUT functions as ~KR/~TRTRY */ + AEME = 0 + SEME = 0 + BSC = 0 + GB5E = 0 + B2DD = 0 + B3DD = 0 + + => 0x0000 0800 + +--------------------------------------------------------------------- + +/*### SYPCR */ +/*### System Protection Control Register */ +/*### Chap. 11.4.3 */ +/*### Offset : 0x0000 0004 */ + + SWTC = 0xFFFF /* SW watchdog timer count = 0xFFFF */ + BMT = 0x06 /* BUS monitoring timing */ + BME = 1 /* BUS monitor enable */ + SWF = 1 + SWE = 0 /* SW watchdog disable */ + SWRI = 0 + SWP = 1 + + => 0xFFFF 0689 + +--------------------------------------------------------------------- + +/*### TESR */ +/*### Transfer Error Status Register */ +/*### Chap. 11.4.4 */ +/*### Offset : 0x0000 0020 */ + + IEXT = 0 + ITMT = 0 + IPB = 0000 + DEXT = 0 + DTMT = 0 + DPB = 0000 + + => 0x0000 0000 + +--------------------------------------------------------------------- + +/*### SIPEND */ +/*### SIU Interrupt Pending Register */ +/*### Chap. 11.5.4.1 */ +/*### Offset : 0x0000 0010 */ + + IRQ0~IRQ7 = 0 + LVL0~LVL7 = 0 + + => 0x0000 0000 + +--------------------------------------------------------------------- + +/*### SIMASK */ +/*### SIU Interrupt Mask Register */ +/*### Chap. 11.5.4.2 */ +/*### Offset : 0x0000 0014 */ + + IRM0~IRM7 = 0 /* Mask all interrupts */ + LVL0~LVL7 = 0 + + => 0x0000 0000 + +--------------------------------------------------------------------- + +/*### SIEL */ +/*### SIU Interrupt Edge/Level Register */ +/*### Chap. 11.5.4.3 */ +/*### Offset : 0x0000 0018 */ + + ED0~ED7 = 0 /* Low level triggered */ + WMn0~WMn7 = 0 /* Not allowed to exit from low-power mode */ + + => 0x0000 0000 + +--------------------------------------------------------------------- + +/*### SIVEC */ +/*### SIU Interrupt Vector Register */ +/*### Chap. 11.5.4.4 */ +/*### Offset : 0x0000 001C */ + + INTC = 3C /* The lowest interrupt is pending..(?) */ + + => 0x3C00 0000 + +--------------------------------------------------------------------- + +/*### SWSR */ +/*### Software Service Register */ +/*### Chap. 11.7.1 */ +/*### Offset : 0x0000 001E */ + + SEQ = 0 + + => 0x0000 + +--------------------------------------------------------------------- + +/*### SDCR */ +/*### SDMA Configuration Register */ +/*### Chap. 20.2.1 */ +/*### Offset : 0x0000 0032 */ + + FRZ = 0 + RAID = 01 /* Priority level 5 (BR5) (normal operation) */ + + => 0x0000 0001 + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* UPMA (User Programmable Machine A) */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ + +/*### Chap. 16.6.4.1 */ +/*### Offset = 0x0000 017c */ + + T0 = CFFF CC24 /* Single Read */ + T1 = 0FFF CC04 + T2 = 0CAF CC04 + T3 = 03AF CC08 + T4 = 3FBF CC27 /* last */ + T5 = FFFF CC25 + T6 = FFFF CC25 + T7 = FFFF CC25 + T8 = CFFF CC24 /* Burst Read */ + T9 = 0FFF CC04 + T10 = 0CAF CC84 + T11 = 03AF CC88 + T12 = 3FBF CC27 /* last */ + T13 = FFFF CC25 + T14 = FFFF CC25 + T15 = FFFF CC25 + T16 = FFFF CC25 + T17 = FFFF CC25 + T18 = FFFF CC25 + T19 = FFFF CC25 + T20 = FFFF CC25 + T21 = FFFF CC25 + T22 = FFFF CC25 + T23 = FFFF CC25 + T24 = CFFF CC24 /* Single Write */ + T25 = 0FFF CC04 + T26 = 0CFF CC04 + T27 = 03FF CC00 + T28 = 3FFF CC27 /* last */ + T29 = FFFF CC25 + T30 = FFFF CC25 + T31 = FFFF CC25 + T32 = CFFF CC24 /* Burst Write */ + T33 = 0FFF CC04 + T34 = 0CFF CC80 + T35 = 03FF CC8C + T36 = 0CFF CC00 + T37 = 33FF CC27 /* last */ + T38 = FFFF CC25 + T39 = FFFF CC25 + T40 = FFFF CC25 + T41 = FFFF CC25 + T42 = FFFF CC25 + T43 = FFFF CC25 + T44 = FFFF CC25 + T45 = FFFF CC25 + T46 = FFFF CC25 + T47 = FFFF CC25 + T48 = C0FF CC24 /* Refresh */ + T49 = 03FF CC24 + T50 = 0FFF CC24 + T51 = 0FFF CC24 + T52 = 3FFF CC27 /* last */ + T53 = FFFF CC25 + T54 = FFFF CC25 + T55 = FFFF CC25 + T56 = FFFF CC25 + T57 = FFFF CC25 + T58 = FFFF CC25 + T59 = FFFF CC25 + T60 = FFFF CC25 /* Exception */ + T61 = FFFF CC25 + T62 = FFFF CC25 + T63 = FFFF CC25 + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* UPMB */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +--------------------------------------------------------------------- + +/*### Chap. 16.6.4.1 */ + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* MEMC */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +--------------------------------------------------------------------- + +/*### BR0 & OR0 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR0(0x0000 0100) & OR0(0x0000 0104) */ +/*### Flash memory */ + + BA = 1111 1110 0000 0000 0 /* Base addr = 0xFE00 0000 */ + AT = 000 + PS = 00 + PARE = 0 + WP = 0 + MS = 0 /* GPCM */ + V = 1 /* Valid */ + + => 0xFE00 0001 + + AM = 1111 1110 0000 0000 0 /* 32MBytes */ + ATM = 000 + CSNT/SAM = 0 + ACS/G5LA,G5LS = 00 + BIH = 1 /* Burst inhibited */ + SCY = 0100 /* cycle length = 4 */ + SETA = 0 + TRLX = 0 + EHTR = 0 + + => 0xFE00 0140 + +/*### BR1 & OR1 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */ +/*### SDRAM */ + + BA = 0000 0000 0000 0000 0 /* Base addr = 0x0000 0000 */ + AT = 000 + PS = 00 + PARE = 0 + WP = 0 + MS = 1 /* UPMA */ + V = 1 /* Valid */ + + => 0x0000 0081 + + AM = 1111 1110 0000 0000 /* 32MBytes */ + ATM = 000 + CSNT/SAM = 1 + ACS/G5LA,G5LS = 11 + BIH = 0 + SCY = 0000 /* cycle length = 0 */ + SETA = 0 + TRLX = 0 + EHTR = 0 + + => 0xFE00 0E00 + +/*### BR2 & OR2 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */ + + BR2 & OR2 = 0x0000 0000 /* Not used */ + +/*### BR3 & OR3 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */ +/*### BCSR */ + + BA = 1111 1010 0100 0000 0 /* Base addr = 0xFA40 0000 */ + AT = 000 + PS = 00 + PARE = 0 + WP = 0 + MS = 0 /* GPCM */ + V = 1 /* Valid */ + + => 0xFA40 0001 + + AM = 1111 1111 0111 1111 1 /* (?) */ + ATM = 000 + CSNT/SAM = 1 + ACS/G5LA,G5LS = 00 + BIH = 1 /* Burst inhibited */ + SCY = 0001 /* cycle length = 1 */ + SETA = 0 + TRLX = 0 + + => 0xFF7F 8910 + +/*### BR4 & OR4 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */ +/*### NVRAM & SRAM */ + + BA = 1111 1010 0000 0000 0 /* Base addr = 0xFA00 0000 */ + AT = 000 + PS = 01 + PARE = 0 + WP = 0 + MS = 0 /* GPCM */ + V = 1 /* Valid */ + + => 0xFA00 0401 + + AM = 1111 1111 1111 1000 0 /* 8MByte */ + ATM = 000 + CSNT/SAM = 1 + ACS/G5LA,G5LS = 00 + BIH = 1 /* Burst inhibited */ + SCY = 0111 /* cycle length = 7 */ + SETA = 0 + TRLX = 0 + + => 0xFFF8 0970 + +/*### BR5 & OR5 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */ + + BR5 & OR5 = 0x0000 0000 /* Not used */ + +/*### BR6 & OR6 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */ + + BR6 & OR6 = 0x0000 0000 /* Not used */ + +/*### BR7 & OR7 */ +/*### Base Registers & Option Registers */ +/*### Chap. 16.4.1 & 16.4.2 */ +/*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */ + + BR7 & OR7 = 0x0000 0000 /* Not used */ + +/*### MAR */ +/*### Memory Address Register */ +/*### Chap. 16.4.7 */ +/*### Offset : 0x0000 0164 */ + + MA = External memory address + +/*### MCR */ +/*### Memory Command Register */ +/*### Chap. 16.4.5 */ +/*### Offset : 0x0000 0168 */ + + OP = xx /* Command op code */ + UM = 1 /* Select UPMA */ + MB = 001 /* Select CS1 */ + MCLF = xxxx /* Loop times */ + MAD = xx xxxx /* Memory array index */ + +/*### MAMR */ +/*### Machine A Mode Register */ +/*### Chap. 16.4.4 */ +/*### Offset : 0x0000 0170 */ + + PTA = 0101 1000 + PTAE = 1 /* Periodic timer A enabled */ + AMA = 010 + DSA = 00 + G0CLA = 000 + GPLA4DIS = 1 + RLFA = 0100 + WLFA = 0011 + TLFA = 0000 + + => 0x58A0 1430 + +/*### MBMR */ +/*### Machine B Mode Register */ +/*### Chap. 16.4.4 */ +/*### Offset : 0x0000 0174 */ + + PTA = 0100 1110 + PTAE = 0 /* Periodic timer B disabled */ + AMA = 000 + DSA = 00 + G0CLA = 000 + GPLA4DIS = 1 + RLFA = 0000 + WLFA = 0000 + TLFA = 0000 + + => 0x4E00 1000 + +/*### MSTAT */ +/*### Memory Status Register */ +/*### Chap. 16.4.3 */ +/*### Offset : 0x0000 0178 */ + + PER0~PER7 = Parity error + WPER = Write protection error + + => 0x0000 + +/*### MPTPR */ +/*### Memory Periodic Timer Prescaler Register */ +/*### Chap. 16.4.8 */ +/*### Offset : 0x0000 017A */ + + PTP = 0000 1000 /* Divide by 8 */ + + => 0x0800 + +/*### MDR */ +/*### Memory Data Register */ +/*### Chap. 16.4.6 */ +/*### Offset : 0x0000 017C */ + + MD = Memory data contains the RAM array word + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* TIMERS */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +--------------------------------------------------------------------- + +/*### TBREFx */ +/*### Timebase Reference Registers */ +/*### Chap. 11.9.2 */ +/*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */ +/*### (Locked) */ + + TBREFF0 = 0xFFFF FFFF + TBREFF1 = 0xFFFF FFFF + +--------------------------------------------------------------------- + +/*### TBSCR */ +/*### Timebase Status and Control Registers */ +/*### Chap. 11.9.3 */ +/*### Offset : 0x0000 0200 */ +/*### (Locked) */ + + TBIRQ = 00000000 + REF0 = 0 + REF1 = 0 + REFE0 = 0 /* Reference interrupt disable */ + REFE1 = 0 + TBF = 1 + TBE = 1 /* Timebase enable */ + + => 0x0003 + +--------------------------------------------------------------------- + +/*### RTCSC */ +/*### Real-Time Clock Status and Control Registers */ +/*### Chap. 11.10.1 */ +/*### Offset : 0x0000 0220 */ +/*### (Locked) */ + + RTCIRQ = 00000000 + SEC = 1 + ALR = 0 + 38K = 0 /* PITRTCLK is driven by 32.768KHz */ + SIE = 0 + ALE = 0 + RTF = 0 + RTE = 1 /* Real-Time clock enabled */ + + => 0x0081 + +--------------------------------------------------------------------- + +/*### RTC */ +/*### Real-Time Clock Registers */ +/*### Chap. 11.10.2 */ +/*### Offset : 0x0000 0224 */ +/*### (Locked) */ + + RTC = Real time clock measured in second + +--------------------------------------------------------------------- + +/*### RTCAL */ +/*### Real-Time Clock Alarm Registers */ +/*### Chap. 11.10.3 */ +/*### Offset : 0x0000 022C */ +/*### (Locked) */ + + ALARM = 0xFFFF FFFF + +--------------------------------------------------------------------- + +/*### RTSEC */ +/*### Real-Time Clock Alarm Second Registers */ +/*### Chap. 11.10.4 */ +/*### Offset : 0x0000 0228 */ +/*### (Locked) */ + + COUNTER = Counter bits(fraction of a second) + +--------------------------------------------------------------------- + +/*### PISCR */ +/*### Periodic Interrupt Status and Control Register */ +/*### Chap. 11.11.1 */ +/*### Offset : 0x0000 0240 */ +/*### (Locked) */ + + PIRQ = 0 + PS = 0 /* Write 1 to clear */ + PIE = 0 + PITF = 1 + PTE = 0 /* PIT disabled */ + +--------------------------------------------------------------------- + +/*### PITC */ +/*### PIT Count Register */ +/*### Chap. 11.11.2 */ +/*### Offset : 0x0000 0244 */ +/*### (Locked) */ + + PITC = PIT count + +--------------------------------------------------------------------- + +/*### PITR */ +/*### PIT Register */ +/*### Chap. 11.11.3 */ +/*### Offset : 0x0000 0248 */ +/*### (Locked) */ + + PIT = PIT count /* Read only */ + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* CLOCKS */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +--------------------------------------------------------------------- + + +--------------------------------------------------------------------- + +/*### SCCR */ +/*### System Clock and Reset Control Register */ +/*### Chap. 15.6.1 */ +/*### Offset : 0x0000 0280 */ +/*### (Locked) */ + + COM = 11 /* Clock output disabled */ + TBS = 1 /* Timebase frequency source is GCLK2 divided by 16 */ + RTDIV = 0 /* The clock is divided by 4 */ + RTSEL = 0 /* OSCM(Crystal oscillator) is selected */ + CRQEN = 0 + PRQEN = 0 + EBDF = 00 /* CLKOUT is GCLK2 divided by 1 */ + DFSYNC = 00 /* Divided by 1 (normal operation) */ + DFBRG = 00 /* Divided by 1 (normal operation) */ + DFNL = 000 + DFNH = 000 + + => 0x6200 0000 + +--------------------------------------------------------------------- + +/*### PLPRCR */ +/*### PLL, Low-Power, and Reset Control Register */ +/*### Chap. 15.6.2 */ +/*### Offset : 0x0000 0284 */ +/*### (Locked) */ + + MF = 0x005 /* 48MHz (?) ( = 8MHz * (MF+1) ) */ + SPLSS = 0 + TEXPS = 0 + TMIST = 0 + CSRC = 0 /* The general system clock is generated by the DFNH field */ + LPM = 00 /* Normal high/normal low mode */ + CSR = 0 + LOLRE = 0 + FIOPD = 0 + + => 0x0050 0000 + +--------------------------------------------------------------------- + +/*### RSR */ +/*### Reset Status Register */ +/*### Chap. 12.2 */ +/*### Offset : 0x0000 0288 */ +/*### (Locked) */ + + EHRS = External hard reset + ESRS = External soft reset + LLRS = Loss-of-lock reset + SWRS = Software watchdog reset + CSRS = Check stop reset + DBHRS = Debug port hard reset + DBSRS = Debug port soft reset + JTRS = JTAG reset + + +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +/* DMA */ +/* */ +/*------------------------------------------------------------------- */ +/*------------------------------------------------------------------- */ +--------------------------------------------------------------------- + +/*### SDSR */ +/*### SDMA Status Register */ +/*### Chap. 20.2.2 */ +/*### Offset : 0x0000 0908 */ + + SBER = 0 /* SDMA channel bus error */ + DSP2 = 0 /* DSP chain2 (Tx) interrupt */ + DSP1 = 0 /* DSP chain1 (Rx) interrupt */ + + => 0x00 + +/*### SDMR */ +/*### SDMA Mask Register */ +/*### Chap. 20.2.3 */ +/*### Offset : 0x0000 090C */ + + SBER = 0 + DSP2 = 0 + DSP1 = 0 /* All interrupts are masked */ + + => 0x00 + +/*### SDAR */ +/*### SDMA Address Register */ +/*### Chap. 20.2.4 */ +/*### Offset : 0x0000 0904 */ + + AR = 0xxxxx xxxx /* current system address */ + + => 0xFA20 23AC + +/*### IDSRx */ +/*### IDMA Status Register */ +/*### Chap. 20.3.3.2 */ +/*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */ + + AD = 0 + DONE = 0 + OB = 0 + + => 0x00 + +/*### IDMRx */ +/*### IDMA Mask Register */ +/*### Chap. 20.3.3.3 */ +/*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */ + + AD = 0 + DONE = 0 + OB = 0 |