diff options
Diffstat (limited to 'board/RPXClassic')
| -rw-r--r-- | board/RPXClassic/Makefile | 2 | ||||
| -rw-r--r-- | board/RPXClassic/RPXClassic.c | 2 | ||||
| -rw-r--r-- | board/RPXClassic/eccx.c | 452 | ||||
| -rw-r--r-- | board/RPXClassic/flash.c | 86 | ||||
| -rw-r--r-- | board/RPXClassic/u-boot.lds | 6 | ||||
| -rw-r--r-- | board/RPXClassic/u-boot.lds.debug | 6 |
6 files changed, 280 insertions, 274 deletions
diff --git a/board/RPXClassic/Makefile b/board/RPXClassic/Makefile index 857e9a8..93907ba 100644 --- a/board/RPXClassic/Makefile +++ b/board/RPXClassic/Makefile @@ -28,7 +28,7 @@ LIB = lib$(BOARD).a OBJS = $(BOARD).o flash.o eccx.o $(LIB): .depend $(OBJS) - $(AR) crv $@ $^ + $(AR) crv $@ $(OBJS) ######################################################################### diff --git a/board/RPXClassic/RPXClassic.c b/board/RPXClassic/RPXClassic.c index aed9479..5689334 100644 --- a/board/RPXClassic/RPXClassic.c +++ b/board/RPXClassic/RPXClassic.c @@ -258,7 +258,7 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize return (maxsize); } /*----------------------------------------------------------------------------- - * aschex_to_byte -- + * aschex_to_byte -- *----------------------------------------------------------------------------- */ static unsigned char aschex_to_byte (unsigned char *cp) diff --git a/board/RPXClassic/eccx.c b/board/RPXClassic/eccx.c index d5edc2b..cc76bbd 100644 --- a/board/RPXClassic/eccx.c +++ b/board/RPXClassic/eccx.c @@ -31,7 +31,6 @@ #include <sed13806.h> - /* Screen configurations: the initialization of the SD13806 depends on screen and on display mode. We handle only 8bpp and 16 bpp modes */ @@ -41,232 +40,232 @@ #define DISPLAY_HEIGHT 480 #ifdef CONFIG_VIDEO_SED13806_8BPP -static const S1D_REGS init_regs [] = +static const S1D_REGS init_regs [] = { - {0x0001,0x00}, // Miscellaneous Register - {0x01FC,0x00}, // Display Mode Register - {0x0004,0x1b}, // General IO Pins Configuration Register 0 - {0x0005,0x00}, // General IO Pins Configuration Register 1 - {0x0008,0xe5}, // General IO Pins Control Register 0 - {0x0009,0x1f}, // General IO Pins Control Register 1 - {0x0010,0x02}, // Memory Clock Configuration Register - {0x0014,0x10}, // LCD Pixel Clock Configuration Register - {0x0018,0x02}, // CRT/TV Pixel Clock Configuration Register - {0x001C,0x02}, // MediaPlug Clock Configuration Register - {0x001E,0x01}, // CPU To Memory Wait State Select Register - {0x0021,0x04}, // DRAM Refresh Rate Register - {0x002A,0x00}, // DRAM Timings Control Register 0 - {0x002B,0x01}, // DRAM Timings Control Register 1 - {0x0020,0x80}, // Memory Configuration Register - {0x0030,0x25}, // Panel Type Register - {0x0031,0x00}, // MOD Rate Register - {0x0032,0x4F}, // LCD Horizontal Display Width Register - {0x0034,0x13}, // LCD Horizontal Non-Display Period Register - {0x0035,0x01}, // TFT FPLINE Start Position Register - {0x0036,0x0B}, // TFT FPLINE Pulse Width Register - {0x0038,0xDF}, // LCD Vertical Display Height Register 0 - {0x0039,0x01}, // LCD Vertical Display Height Register 1 - {0x003A,0x2C}, // LCD Vertical Non-Display Period Register - {0x003B,0x00}, // TFT FPFRAME Start Position Register - {0x003C,0x01}, // TFT FPFRAME Pulse Width Register - {0x0040,0x03}, // LCD Display Mode Register - {0x0041,0x02}, // LCD Miscellaneous Register - {0x0042,0x00}, // LCD Display Start Address Register 0 - {0x0043,0x00}, // LCD Display Start Address Register 1 - {0x0044,0x00}, // LCD Display Start Address Register 2 - {0x0046,0x40}, // LCD Memory Address Offset Register 0 - {0x0047,0x01}, // LCD Memory Address Offset Register 1 - {0x0048,0x00}, // LCD Pixel Panning Register - {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register - {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register - {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register - {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register - {0x0053,0x01}, // CRT/TV HRTC Start Position Register - {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register - {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0 - {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1 - {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register - {0x0059,0x09}, // CRT/TV VRTC Start Position Register - {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register - {0x005B,0x00}, // TV Output Control Register - {0x0060,0x03}, // CRT/TV Display Mode Register - {0x0062,0x00}, // CRT/TV Display Start Address Register 0 - {0x0063,0x00}, // CRT/TV Display Start Address Register 1 - {0x0064,0x00}, // CRT/TV Display Start Address Register 2 - {0x0066,0x40}, // CRT/TV Memory Address Offset Register 0 - {0x0067,0x01}, // CRT/TV Memory Address Offset Register 1 - {0x0068,0x00}, // CRT/TV Pixel Panning Register - {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register - {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register - {0x0070,0x00}, // LCD Ink/Cursor Control Register - {0x0071,0x00}, // LCD Ink/Cursor Start Address Register - {0x0072,0x00}, // LCD Cursor X Position Register 0 - {0x0073,0x00}, // LCD Cursor X Position Register 1 - {0x0074,0x00}, // LCD Cursor Y Position Register 0 - {0x0075,0x00}, // LCD Cursor Y Position Register 1 - {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register - {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register - {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register - {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register - {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register - {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register - {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register - {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register - {0x0081,0x00}, // CRT/TV Ink/Cursor Start Address Register - {0x0082,0x00}, // CRT/TV Cursor X Position Register 0 - {0x0083,0x00}, // CRT/TV Cursor X Position Register 1 - {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0 - {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1 - {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register - {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register - {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register - {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register - {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register - {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register - {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register - {0x0100,0x00}, // BitBlt Control Register 0 - {0x0101,0x00}, // BitBlt Control Register 1 - {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register - {0x0103,0x00}, // BitBlt Operation Register - {0x0104,0x00}, // BitBlt Source Start Address Register 0 - {0x0105,0x00}, // BitBlt Source Start Address Register 1 - {0x0106,0x00}, // BitBlt Source Start Address Register 2 - {0x0108,0x00}, // BitBlt Destination Start Address Register 0 - {0x0109,0x00}, // BitBlt Destination Start Address Register 1 - {0x010A,0x00}, // BitBlt Destination Start Address Register 2 - {0x010C,0x00}, // BitBlt Memory Address Offset Register 0 - {0x010D,0x00}, // BitBlt Memory Address Offset Register 1 - {0x0110,0x00}, // BitBlt Width Register 0 - {0x0111,0x00}, // BitBlt Width Register 1 - {0x0112,0x00}, // BitBlt Height Register 0 - {0x0113,0x00}, // BitBlt Height Register 1 - {0x0114,0x00}, // BitBlt Background Color Register 0 - {0x0115,0x00}, // BitBlt Background Color Register 1 - {0x0118,0x00}, // BitBlt Foreground Color Register 0 - {0x0119,0x00}, // BitBlt Foreground Color Register 1 - {0x01E0,0x00}, // Look-Up Table Mode Register - {0x01E2,0x00}, // Look-Up Table Address Register - {0x01E4,0x00}, // Look-Up Table Data Register - {0x01F0,0x10}, // Power Save Configuration Register - {0x01F1,0x00}, // Power Save Status Register - {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register - {0x01FC,0x01}, // Display Mode Register + {0x0001,0x00}, /* Miscellaneous Register */ + {0x01FC,0x00}, /* Display Mode Register */ + {0x0004,0x1b}, /* General IO Pins Configuration Register 0 */ + {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ + {0x0008,0xe5}, /* General IO Pins Control Register 0 */ + {0x0009,0x1f}, /* General IO Pins Control Register 1 */ + {0x0010,0x02}, /* Memory Clock Configuration Register */ + {0x0014,0x10}, /* LCD Pixel Clock Configuration Register */ + {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ + {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ + {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ + {0x0021,0x04}, /* DRAM Refresh Rate Register */ + {0x002A,0x00}, /* DRAM Timings Control Register 0 */ + {0x002B,0x01}, /* DRAM Timings Control Register 1 */ + {0x0020,0x80}, /* Memory Configuration Register */ + {0x0030,0x25}, /* Panel Type Register */ + {0x0031,0x00}, /* MOD Rate Register */ + {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ + {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ + {0x0035,0x01}, /* TFT FPLINE Start Position Register */ + {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ + {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ + {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ + {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ + {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ + {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ + {0x0040,0x03}, /* LCD Display Mode Register */ + {0x0041,0x02}, /* LCD Miscellaneous Register */ + {0x0042,0x00}, /* LCD Display Start Address Register 0 */ + {0x0043,0x00}, /* LCD Display Start Address Register 1 */ + {0x0044,0x00}, /* LCD Display Start Address Register 2 */ + {0x0046,0x40}, /* LCD Memory Address Offset Register 0 */ + {0x0047,0x01}, /* LCD Memory Address Offset Register 1 */ + {0x0048,0x00}, /* LCD Pixel Panning Register */ + {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ + {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ + {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ + {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ + {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ + {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ + {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ + {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ + {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ + {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ + {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ + {0x005B,0x00}, /* TV Output Control Register */ + {0x0060,0x03}, /* CRT/TV Display Mode Register */ + {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ + {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ + {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ + {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ + {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ + {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ + {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ + {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ + {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ + {0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */ + {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ + {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ + {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ + {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ + {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ + {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ + {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ + {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ + {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ + {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ + {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ + {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ + {0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */ + {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ + {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ + {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ + {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ + {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ + {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ + {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ + {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ + {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ + {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ + {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ + {0x0100,0x00}, /* BitBlt Control Register 0 */ + {0x0101,0x00}, /* BitBlt Control Register 1 */ + {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ + {0x0103,0x00}, /* BitBlt Operation Register */ + {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ + {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ + {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ + {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ + {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ + {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ + {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ + {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ + {0x0110,0x00}, /* BitBlt Width Register 0 */ + {0x0111,0x00}, /* BitBlt Width Register 1 */ + {0x0112,0x00}, /* BitBlt Height Register 0 */ + {0x0113,0x00}, /* BitBlt Height Register 1 */ + {0x0114,0x00}, /* BitBlt Background Color Register 0 */ + {0x0115,0x00}, /* BitBlt Background Color Register 1 */ + {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ + {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ + {0x01E0,0x00}, /* Look-Up Table Mode Register */ + {0x01E2,0x00}, /* Look-Up Table Address Register */ + {0x01E4,0x00}, /* Look-Up Table Data Register */ + {0x01F0,0x10}, /* Power Save Configuration Register */ + {0x01F1,0x00}, /* Power Save Status Register */ + {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ + {0x01FC,0x01}, /* Display Mode Register */ {0, 0} }; #endif /* CONFIG_VIDEO_SED13806_8BPP */ #ifdef CONFIG_VIDEO_SED13806_16BPP -static const S1D_REGS init_regs [] = +static const S1D_REGS init_regs [] = { - {0x0001,0x00}, // Miscellaneous Register - {0x01FC,0x00}, // Display Mode Register - {0x0004,0x1b}, // General IO Pins Configuration Register 0 - {0x0005,0x00}, // General IO Pins Configuration Register 1 - {0x0008,0xe5}, // General IO Pins Control Register 0 - {0x0009,0x1f}, // General IO Pins Control Register 1 - {0x0010,0x02}, // Memory Clock Configuration Register - {0x0014,0x10}, // LCD Pixel Clock Configuration Register - {0x0018,0x02}, // CRT/TV Pixel Clock Configuration Register - {0x001C,0x02}, // MediaPlug Clock Configuration Register - {0x001E,0x01}, // CPU To Memory Wait State Select Register - {0x0021,0x04}, // DRAM Refresh Rate Register - {0x002A,0x00}, // DRAM Timings Control Register 0 - {0x002B,0x01}, // DRAM Timings Control Register 1 - {0x0020,0x80}, // Memory Configuration Register - {0x0030,0x25}, // Panel Type Register - {0x0031,0x00}, // MOD Rate Register - {0x0032,0x4F}, // LCD Horizontal Display Width Register - {0x0034,0x13}, // LCD Horizontal Non-Display Period Register - {0x0035,0x01}, // TFT FPLINE Start Position Register - {0x0036,0x0B}, // TFT FPLINE Pulse Width Register - {0x0038,0xDF}, // LCD Vertical Display Height Register 0 - {0x0039,0x01}, // LCD Vertical Display Height Register 1 - {0x003A,0x2C}, // LCD Vertical Non-Display Period Register - {0x003B,0x00}, // TFT FPFRAME Start Position Register - {0x003C,0x01}, // TFT FPFRAME Pulse Width Register - {0x0040,0x05}, // LCD Display Mode Register - {0x0041,0x02}, // LCD Miscellaneous Register - {0x0042,0x00}, // LCD Display Start Address Register 0 - {0x0043,0x00}, // LCD Display Start Address Register 1 - {0x0044,0x00}, // LCD Display Start Address Register 2 - {0x0046,0x80}, // LCD Memory Address Offset Register 0 - {0x0047,0x02}, // LCD Memory Address Offset Register 1 - {0x0048,0x00}, // LCD Pixel Panning Register - {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register - {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register - {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register - {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register - {0x0053,0x01}, // CRT/TV HRTC Start Position Register - {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register - {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0 - {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1 - {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register - {0x0059,0x09}, // CRT/TV VRTC Start Position Register - {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register - {0x005B,0x00}, // TV Output Control Register - {0x0060,0x05}, // CRT/TV Display Mode Register - {0x0062,0x00}, // CRT/TV Display Start Address Register 0 - {0x0063,0x00}, // CRT/TV Display Start Address Register 1 - {0x0064,0x00}, // CRT/TV Display Start Address Register 2 - {0x0066,0x80}, // CRT/TV Memory Address Offset Register 0 - {0x0067,0x02}, // CRT/TV Memory Address Offset Register 1 - {0x0068,0x00}, // CRT/TV Pixel Panning Register - {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register - {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register - {0x0070,0x00}, // LCD Ink/Cursor Control Register - {0x0071,0x00}, // LCD Ink/Cursor Start Address Register - {0x0072,0x00}, // LCD Cursor X Position Register 0 - {0x0073,0x00}, // LCD Cursor X Position Register 1 - {0x0074,0x00}, // LCD Cursor Y Position Register 0 - {0x0075,0x00}, // LCD Cursor Y Position Register 1 - {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register - {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register - {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register - {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register - {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register - {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register - {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register - {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register - {0x0081,0x00}, // CRT/TV Ink/Cursor Start Address Register - {0x0082,0x00}, // CRT/TV Cursor X Position Register 0 - {0x0083,0x00}, // CRT/TV Cursor X Position Register 1 - {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0 - {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1 - {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register - {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register - {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register - {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register - {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register - {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register - {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register - {0x0100,0x00}, // BitBlt Control Register 0 - {0x0101,0x00}, // BitBlt Control Register 1 - {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register - {0x0103,0x00}, // BitBlt Operation Register - {0x0104,0x00}, // BitBlt Source Start Address Register 0 - {0x0105,0x00}, // BitBlt Source Start Address Register 1 - {0x0106,0x00}, // BitBlt Source Start Address Register 2 - {0x0108,0x00}, // BitBlt Destination Start Address Register 0 - {0x0109,0x00}, // BitBlt Destination Start Address Register 1 - {0x010A,0x00}, // BitBlt Destination Start Address Register 2 - {0x010C,0x00}, // BitBlt Memory Address Offset Register 0 - {0x010D,0x00}, // BitBlt Memory Address Offset Register 1 - {0x0110,0x00}, // BitBlt Width Register 0 - {0x0111,0x00}, // BitBlt Width Register 1 - {0x0112,0x00}, // BitBlt Height Register 0 - {0x0113,0x00}, // BitBlt Height Register 1 - {0x0114,0x00}, // BitBlt Background Color Register 0 - {0x0115,0x00}, // BitBlt Background Color Register 1 - {0x0118,0x00}, // BitBlt Foreground Color Register 0 - {0x0119,0x00}, // BitBlt Foreground Color Register 1 - {0x01E0,0x01}, // Look-Up Table Mode Register - {0x01E2,0x00}, // Look-Up Table Address Register - {0x01E4,0x00}, // Look-Up Table Data Register - {0x01F0,0x10}, // Power Save Configuration Register - {0x01F1,0x00}, // Power Save Status Register - {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register - {0x01FC,0x01}, // Display Mode Register + {0x0001,0x00}, /* Miscellaneous Register */ + {0x01FC,0x00}, /* Display Mode Register */ + {0x0004,0x1b}, /* General IO Pins Configuration Register 0 */ + {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ + {0x0008,0xe5}, /* General IO Pins Control Register 0 */ + {0x0009,0x1f}, /* General IO Pins Control Register 1 */ + {0x0010,0x02}, /* Memory Clock Configuration Register */ + {0x0014,0x10}, /* LCD Pixel Clock Configuration Register */ + {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ + {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ + {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ + {0x0021,0x04}, /* DRAM Refresh Rate Register */ + {0x002A,0x00}, /* DRAM Timings Control Register 0 */ + {0x002B,0x01}, /* DRAM Timings Control Register 1 */ + {0x0020,0x80}, /* Memory Configuration Register */ + {0x0030,0x25}, /* Panel Type Register */ + {0x0031,0x00}, /* MOD Rate Register */ + {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ + {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ + {0x0035,0x01}, /* TFT FPLINE Start Position Register */ + {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ + {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ + {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ + {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ + {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ + {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ + {0x0040,0x05}, /* LCD Display Mode Register */ + {0x0041,0x02}, /* LCD Miscellaneous Register */ + {0x0042,0x00}, /* LCD Display Start Address Register 0 */ + {0x0043,0x00}, /* LCD Display Start Address Register 1 */ + {0x0044,0x00}, /* LCD Display Start Address Register 2 */ + {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ + {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ + {0x0048,0x00}, /* LCD Pixel Panning Register */ + {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ + {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ + {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ + {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ + {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ + {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ + {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ + {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ + {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ + {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ + {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ + {0x005B,0x00}, /* TV Output Control Register */ + {0x0060,0x05}, /* CRT/TV Display Mode Register */ + {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ + {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ + {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ + {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ + {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ + {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ + {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ + {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ + {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ + {0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */ + {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ + {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ + {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ + {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ + {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ + {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ + {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ + {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ + {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ + {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ + {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ + {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ + {0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */ + {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ + {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ + {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ + {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ + {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ + {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ + {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ + {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ + {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ + {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ + {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ + {0x0100,0x00}, /* BitBlt Control Register 0 */ + {0x0101,0x00}, /* BitBlt Control Register 1 */ + {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ + {0x0103,0x00}, /* BitBlt Operation Register */ + {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ + {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ + {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ + {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ + {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ + {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ + {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ + {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ + {0x0110,0x00}, /* BitBlt Width Register 0 */ + {0x0111,0x00}, /* BitBlt Width Register 1 */ + {0x0112,0x00}, /* BitBlt Height Register 0 */ + {0x0113,0x00}, /* BitBlt Height Register 1 */ + {0x0114,0x00}, /* BitBlt Background Color Register 0 */ + {0x0115,0x00}, /* BitBlt Background Color Register 1 */ + {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ + {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ + {0x01E0,0x01}, /* Look-Up Table Mode Register */ + {0x01E2,0x00}, /* Look-Up Table Address Register */ + {0x01E4,0x00}, /* Look-Up Table Data Register */ + {0x01F0,0x10}, /* Power Save Configuration Register */ + {0x01F1,0x00}, /* Power Save Status Register */ + {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ + {0x01FC,0x01}, /* Display Mode Register */ {0, 0} }; @@ -274,7 +273,6 @@ static const S1D_REGS init_regs [] = #endif /* CONFIG_NEC_NL6448BC20 */ - #ifdef CONFIG_CONSOLE_EXTRA_INFO /*----------------------------------------------------------------------------- @@ -286,10 +284,10 @@ static const S1D_REGS init_regs [] = void video_get_info_str (int line_number, char *info) { if (line_number == 1) { - strcpy (info, " RPXClassic board"); + strcpy (info, " RPXClassic board"); } else { - info [0] = '\0'; + info [0] = '\0'; } } @@ -308,7 +306,7 @@ unsigned int board_video_init (void) *(ECCX_CSR12) |= ECCX_860; *(ECCX_CSR8) |= ECCX_BE | ECCX_CS2; *(ECCX_CSR8) |= ECCX_ENEPSON; - + memctl->memc_or2 = SED13806_OR; memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES; @@ -316,7 +314,7 @@ unsigned int board_video_init (void) } /*----------------------------------------------------------------------------- - * board_validate_screen -- + * board_validate_screen -- *----------------------------------------------------------------------------- */ void board_validate_screen (unsigned int base) @@ -325,7 +323,7 @@ void board_validate_screen (unsigned int base) *(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80; } /*----------------------------------------------------------------------------- - * board_get_regs -- + * board_get_regs -- *----------------------------------------------------------------------------- */ const S1D_REGS *board_get_regs (void) @@ -333,7 +331,7 @@ const S1D_REGS *board_get_regs (void) return (init_regs); } /*----------------------------------------------------------------------------- - * board_get_width -- + * board_get_width -- *----------------------------------------------------------------------------- */ int board_get_width (void) @@ -342,7 +340,7 @@ int board_get_width (void) } /*----------------------------------------------------------------------------- - * board_get_height -- + * board_get_height -- *----------------------------------------------------------------------------- */ int board_get_height (void) diff --git a/board/RPXClassic/flash.c b/board/RPXClassic/flash.c index fdf90cf..2e0b8f9 100644 --- a/board/RPXClassic/flash.c +++ b/board/RPXClassic/flash.c @@ -58,7 +58,7 @@ unsigned long flash_init (void) size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); #if CFG_MONITOR_BASE >= CFG_FLASH_BASE /* monitor protection ON by default */ @@ -112,12 +112,12 @@ void flash_print_info (flash_info_t *info) } switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL323B: - printf ("AMDL323DB (16 Mbytes, bottom boot sect)\n"); - break; + case FLASH_AMDL323B: + printf ("AMDL323DB (16 Mbytes, bottom boot sect)\n"); + break; default: - printf ("Unknown Chip Type\n"); - break; + printf ("Unknown Chip Type\n"); + break; } printf (" Size: %ld MB in %d Sectors\n", @@ -152,11 +152,11 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) ulong value; ulong base = (ulong)addr; - /* Reset flash componeny */ - addr [0] = 0xf0f0f0f0; + /* Reset flash componeny */ + addr [0] = 0xf0f0f0f0; - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0xAAAAAAAA ; + /* Write auto select command: read Manufacturer ID */ + addr[0xAAA] = 0xAAAAAAAA ; addr[0x555] = 0x55555555 ; addr[0xAAA] = 0x90909090 ; @@ -176,48 +176,48 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) value = addr[2] ; /* device ID */ switch (value & 0x00FF00FF) { - case (AMD_ID_DL323B & 0x00FF00FF): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; /* 16 Mb */ + case (AMD_ID_DL323B & 0x00FF00FF): + info->flash_id += FLASH_AMDL323B; + info->sector_count = 71; + info->size = 0x01000000; /* 16 Mb */ - break; + break; default: info->flash_id = FLASH_UNKNOWN; return (0); /* => no or unknown flash */ } /* set up sector start address table */ - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000) ; - } + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x00010000; + info->start[3] = base + 0x00018000; + info->start[4] = base + 0x00020000; + info->start[5] = base + 0x00028000; + info->start[6] = base + 0x00030000; + info->start[7] = base + 0x00038000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + ((i-7) * 0x00040000) ; + } /* check for protected sectors */ - for (i = 0; i < 23; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; + for (i = 0; i < 23; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[4] & 1 ; } - /* Check for protected sectors in the 2nd bank */ - addr[0x100AAA] = 0xAAAAAAAA ; - addr[0x100555] = 0x55555555 ; - addr[0x100AAA] = 0x90909090 ; - - for (i = 23; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; + /* Check for protected sectors in the 2nd bank */ + addr[0x100AAA] = 0xAAAAAAAA ; + addr[0x100555] = 0x55555555 ; + addr[0x100AAA] = 0x90909090 ; + + for (i = 23; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[4] & 1 ; } /* @@ -330,7 +330,7 @@ DONE: addr[0] = 0xF0F0F0F0; /* reset bank */ printf (" done\n"); - return 0; + return 0; } /*----------------------------------------------------------------------- diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds index a31c362..082d8b0 100644 --- a/board/RPXClassic/u-boot.lds +++ b/board/RPXClassic/u-boot.lds @@ -110,6 +110,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + __start___ex_table = .; __ex_table : { *(__ex_table) } __stop___ex_table = .; @@ -132,4 +137,3 @@ SECTIONS _end = . ; PROVIDE (end = .); } - diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug index 22138f8..c0ee849 100644 --- a/board/RPXClassic/u-boot.lds.debug +++ b/board/RPXClassic/u-boot.lds.debug @@ -106,6 +106,11 @@ SECTIONS _edata = .; PROVIDE (edata = .); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + __start___ex_table = .; __ex_table : { *(__ex_table) } __stop___ex_table = .; @@ -128,4 +133,3 @@ SECTIONS _end = . ; PROVIDE (end = .); } - |