diff options
Diffstat (limited to 'board/Marvell/include')
-rw-r--r-- | board/Marvell/include/memory.h | 173 | ||||
-rw-r--r-- | board/Marvell/include/pci.h | 293 |
2 files changed, 0 insertions, 466 deletions
diff --git a/board/Marvell/include/memory.h b/board/Marvell/include/memory.h deleted file mode 100644 index 0947b6e..0000000 --- a/board/Marvell/include/memory.h +++ /dev/null @@ -1,173 +0,0 @@ -/* Memory.h - Memory mappings and remapping functions declarations */ - -/* Copyright - Galileo technology. */ - -#ifndef __INCmemoryh -#define __INCmemoryh - -/* includes */ - -#include "core.h" - -/* defines */ - -#define DONT_MODIFY 0xffffffff -#define PARITY_SUPPORT 0x40000000 -#define MINIMUM_MEM_BANK_SIZE 0x10000 -#define MINIMUM_DEVICE_WINDOW_SIZE 0x10000 -#define MINIMUM_PCI_WINDOW_SIZE 0x10000 -#define MINIMUM_ACCESS_WIN_SIZE 0x10000 - -#define _8BIT 0x00000000 -#define _16BIT 0x00100000 -#define _32BIT 0x00200000 -#define _64BIT 0x00300000 - -/* typedefs */ - - typedef struct deviceParam -{ /* boundary values */ - unsigned int turnOff; /* 0x0 - 0xf */ - unsigned int acc2First; /* 0x0 - 0x1f */ - unsigned int acc2Next; /* 0x0 - 0x1f */ - unsigned int ale2Wr; /* 0x0 - 0xf */ - unsigned int wrLow; /* 0x0 - 0xf */ - unsigned int wrHigh; /* 0x0 - 0xf */ - unsigned int badrSkew; /* 0x0 - 0x2 */ - unsigned int DPEn; /* 0x0 - 0x1 */ - unsigned int deviceWidth; /* in Bytes */ -} DEVICE_PARAM; - - -typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK; -typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE; - -/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \ - MEM_REGION3,MEM_REGION4,MEM_REGION5, \ - MEM_REGION6,MEM_REGION7} \ - MEMORY_PROTECT_REGION;*/ -/* There are four possible windows that can be defined as protected */ -typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2, - MEM_WINDOW3 - } MEMORY_PROTECT_WINDOW; -/* When defining a protected window , this paramter indicates whether it - is accessible or not */ -typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \ - MEMORY_ACCESS; -typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \ - MEMORY_ACCESS_WRITE; -typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \ - MEMORY_CACHE_PROTECT; -typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \ - MEMORY_SNOOP_TYPE; -typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \ - MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \ - MEMORY_SNOOP_REGION; - -/* There are 21 memory windows dedicated for the varios interfaces (PCI, - devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's - address decoding mechanism. */ -typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1, - CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3, - DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5, - DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7, - BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9, - PCI_0_MEM0_WINDOW = BIT10, - PCI_0_MEM1_WINDOW = BIT11, - PCI_0_MEM2_WINDOW = BIT12, - PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14, - PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16, - PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18, - INTEGRATED_SRAM_WINDOW = BIT19, - INTERNAL_SPACE_WINDOW = BIT20, - ALL_WINDOWS = 0X1FFFFF - } MEMORY_WINDOW; - -typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED - } MEMORY_WINDOW_STATUS; - - -typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3 -#ifdef INCLUDE_PCI_1 - ,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3 -#endif /* INCLUDE_PCI_1 */ - } PCI_MEM_WINDOW; - - -/* -------------------------------------------------------------------------------------------------*/ - -/* functions */ -unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank); -unsigned int memoryGetDeviceBaseAddress(DEVICE device); -/* New at MV6436x */ -unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow); -unsigned int memoryGetBankSize(MEMORY_BANK bank); -unsigned int memoryGetDeviceSize(DEVICE device); -unsigned int memoryGetDeviceWidth(DEVICE device); -/* New at MV6436x */ -unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow); - -/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/ -bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength); -/* Set a new base and size for one of the memory banks (CS0 - CS3) */ -bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase, - unsigned int bankSize); -bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength); - -/* Change the Internal Register Base Address to a new given Address. */ -bool memoryMapInternalRegistersSpace(unsigned int internalRegBase); -/* returns internal Register Space Base Address. */ -unsigned int memoryGetInternalRegistersSpace(void); - -/* Returns the integrated SRAM Base Address. */ -unsigned int memoryGetInternalSramBaseAddr(void); -/* -------------------------------------------------------------------------------------------------*/ - -/* Set new base address for the integrated SRAM. */ -void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress); -/* -------------------------------------------------------------------------------------------------*/ - -/* Delete a protection feature to a given space. */ -void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window); -/* -------------------------------------------------------------------------------------------------*/ - -/* Writes a new remap value to the remap register */ -unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow, - unsigned int remapValueHigh, - unsigned int remapValueLow); -/* -------------------------------------------------------------------------------------------------*/ - -/* Configurate the protection feature to a given space. */ -bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window, - MEMORY_ACCESS gtMemoryAccess, - MEMORY_ACCESS_WRITE gtMemoryWrite, - MEMORY_CACHE_PROTECT cacheProtection, - unsigned int baseAddress, - unsigned int size); - -/* Configurate the protection feature to a given space. */ -/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region, - MEMORY_ACCESS memoryAccess, - MEMORY_ACCESS_WRITE memoryWrite, - MEMORY_CACHE_PROTECT cacheProtection, - unsigned int baseAddress, - unsigned int regionLength); */ -/* Configurate the snoop feature to a given space. */ -bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region, - MEMORY_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength); - -bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue); -bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); -bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); -/* Set a new base and size for one of the PCI windows. */ -bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase, - unsigned int pciWindowSize); - -/* Disable or enable one of the 21 windows dedicated for the CPU's - address decoding mechanism */ -void MemoryDisableWindow(MEMORY_WINDOW window); -void MemoryEnableWindow (MEMORY_WINDOW window); -MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window); -#endif /* __INCmemoryh */ diff --git a/board/Marvell/include/pci.h b/board/Marvell/include/pci.h deleted file mode 100644 index 572e0d3..0000000 --- a/board/Marvell/include/pci.h +++ /dev/null @@ -1,293 +0,0 @@ -/* PCI.h - PCI functions header file */ - -/* Copyright - Galileo technology. */ - -#ifndef __INCpcih -#define __INCpcih - -/* includes */ - -#include "core.h" -#include "memory.h" - -/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */ -#define PCI_MAX_DEVICES 22 - - -/* Macros */ - -/* The next Macros configurate the initiator board (SELF) or any any agent on - the PCI to become: MASTER, response to MEMORY transactions , response to - IO transactions or TWO both MEMORY_IO transactions. Those configuration - are for both PCI0 and PCI1. */ - -#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | \ - pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE | \ - pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE | \ - pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8 & \ - pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber)) - -#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \ - pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \ - pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define MASTER_ENABLE BIT2 -#define MEMORY_ENABLE BIT1 -#define I_O_ENABLE BIT0 -#define SELF 32 - -/* Agent on the PCI bus may have up to 6 BARS. */ -#define BAR0 0x10 -#define BAR1 0x14 -#define BAR2 0x18 -#define BAR3 0x1c -#define BAR4 0x20 -#define BAR5 0x24 -#define BAR_SEL_MEM_IO BIT0 -#define BAR_MEM_TYPE_32_BIT NO_BIT -#define BAR_MEM_TYPE_BELOW_1M BIT1 -#define BAR_MEM_TYPE_64_BIT BIT2 -#define BAR_MEM_TYPE_RESERVED (BIT1 | BIT2) -#define BAR_MEM_TYPE_MASK (BIT1 | BIT2) -#define BAR_PREFETCHABLE BIT3 -#define BAR_CONFIG_MASK (BIT0 | BIT1 | BIT2 | BIT3) - -/* Defines for the access regions. */ -#define PREFETCH_ENABLE BIT12 -#define PREFETCH_DISABLE NO_BIT -#define DELAYED_READ_ENABLE BIT13 -/* #define CACHING_ENABLE BIT14 */ -/* aggressive prefetch: PCI slave prefetch two burst in advance*/ -#define AGGRESSIVE_PREFETCH BIT16 -/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/ -#define READ_LINE_AGGRESSIVE_PREFETCH BIT17 -/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/ -#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18 -#define MAX_BURST_4 NO_BIT -#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */ -#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */ -#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */ -#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */ -#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */ -#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */ -#define PCI_ACCESS_PROTECT BIT28 -#define PCI_WRITE_PROTECT BIT29 - -/* typedefs */ - -typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5, - REGION6,REGION7} PCI_ACCESS_REGIONS; - -typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO; -typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK; - -typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB} - PCI_SNOOP_TYPE; -typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1, - PCI_SNOOP_REGION2,PCI_SNOOP_REGION3} - PCI_SNOOP_REGION; - -typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST; -typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1, - PCI_REGION2,PCI_REGION3, - PCI_IO} - PCI_REGION; - -/*ronen 7/Dec/03 */ -typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR, - PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR, - PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR, - PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR, - PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR, - PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR, - PCI_LAST_BAR} PCI_INTERNAL_BAR; - -typedef struct pciBar { - unsigned int detectBase; - unsigned int base; - unsigned int size; - unsigned int type; -} PCI_BAR; - -typedef struct pciDevice { - PCI_HOST host; - char type[40]; - unsigned int deviceNum; - unsigned int venID; - unsigned int deviceID; - PCI_BAR bar[6]; -} PCI_DEVICE; - -typedef struct pciSelfBars { - unsigned int SCS0Base; - unsigned int SCS0Size; - unsigned int SCS1Base; - unsigned int SCS1Size; - unsigned int SCS2Base; - unsigned int SCS2Size; - unsigned int SCS3Base; - unsigned int SCS3Size; - unsigned int internalMemBase; - unsigned int internalIOBase; - unsigned int CS0Base; - unsigned int CS0Size; - unsigned int CS1Base; - unsigned int CS1Size; - unsigned int CS2Base; - unsigned int CS2Size; - unsigned int CS3Base; - unsigned int CS3Size; - unsigned int CSBootBase; - unsigned int CSBootSize; - unsigned int P2PMem0Base; - unsigned int P2PMem0Size; - unsigned int P2PMem1Base; - unsigned int P2PMem1Size; - unsigned int P2PIOBase; - unsigned int P2PIOSize; - unsigned int CPUBase; - unsigned int CPUSize; -} PCI_SELF_BARS; - -/* read/write configuration registers on local PCI bus. */ -void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data); -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum); - -/* read/write configuration registers on another PCI bus. */ -void pciOverBridgeWriteConfigReg(PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum,unsigned int data); -unsigned int pciOverBridgeReadConfigReg(PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum); - -/* Performs full scane on both PCI and returns all detail possible on the - agents which exist on the bus. */ -void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect, - unsigned int numberOfElment); - -/* Master`s memory space */ -bool pciMapSpace(PCI_HOST host, PCI_REGION region, - unsigned int remapBase, - unsigned int deviceBase, - unsigned int deviceLength); -unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region); -unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region); - -/* Slave`s memory space */ -void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank, - unsigned int pci0Dram0Base, unsigned int pci0Dram0Size); - -#if 0 /* GARBAGE routines - dont use till they get cleaned up */ -void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars); -void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars); -void pci0MapInternalRegSpace(unsigned int pci0InternalBase); -void pci1MapInternalRegSpace(unsigned int pci1InternalBase); -void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase); -void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase); -void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base, - unsigned int pci0Dev0Length); -void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base, - unsigned int pci1Dev0Length); -void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base, - unsigned int pci0Dev1Length); -void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base, - unsigned int pci1Dev1Length); -void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base, - unsigned int pci0Dev2Length); -void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base, - unsigned int pci1Dev2Length); -void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base, - unsigned int pci0Dev3Length); -void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base, - unsigned int pci1Dev3Length); -void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase, - unsigned int pci0DevBootLength); -void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase, - unsigned int pci1DevBootLength); -void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base, - unsigned int pci0P2pMem0Length); -void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base, - unsigned int pci1P2pMem0Length); -void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base, - unsigned int pci0P2pMem1Length); -void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base, - unsigned int pci1P2pMem1Length); -void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase, - unsigned int pci0P2pIoLength); -void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase, - unsigned int pci1P2pIoLength); - -void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs); -void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs); -#endif - -/* PCI region options */ - -bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength); - -void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region); - -/* PCI arbiter */ - -bool pciArbiterEnable(PCI_HOST host); -bool pciArbiterDisable(PCI_HOST host); -bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5); -bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5); -bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5); -bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue); -bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue); - -/* PCI-to-PCI (P2P) */ - -bool pciP2PConfig(PCI_HOST host, - unsigned int SecondBusLow,unsigned int SecondBusHigh, - unsigned int busNum,unsigned int devNum); -/* PCI Cache-coherency */ - -bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength); - -PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev); - -#endif /* __INCpcih */ |