diff options
Diffstat (limited to 'board/MAI/AmigaOneG3SE/start.txt')
| -rw-r--r-- | board/MAI/AmigaOneG3SE/start.txt | 201 |
1 files changed, 201 insertions, 0 deletions
diff --git a/board/MAI/AmigaOneG3SE/start.txt b/board/MAI/AmigaOneG3SE/start.txt new file mode 100644 index 0000000..5c7b541 --- /dev/null +++ b/board/MAI/AmigaOneG3SE/start.txt @@ -0,0 +1,201 @@ +
+ /*------------------------------------------------------*/
+ /* TERON Articia / SDRAM Init */
+ /*------------------------------------------------------*/
+
+* XD_CTL = 0x81000000 (0x74)
+
+* HBUS_ACC_CTL_0 &= 0xFFFFFDFF (0x5c)
+ /* host bus access ctl reg 2(5e) */
+ /* set - CPU read from memory data one clock after data is latched */
+
+* GLOBL_INFO_0 |= 0x00004000 (0x50)
+ /* global info register 2 (52), AGP/PCI bus 1 arbiter is addressed in Articia S */
+
+ PCI_1_SB_CONFIG_0 |= 0x00000400 (0x80d0)
+ /* PCI1 side band config reg 2 (d2), enable read acces while write buffer not empty */
+
+ MEM_RAS_CTL_0 |= 0x3f000000 (0xcc)
+ &= 0x3fffffff
+ /* RAS park control reg 0(cc), park access enable is set */
+
+ HOST_RDBUF_CTL |= 0x10000000 (0x70)
+ &= 0x10ffffff
+ /* host read buffer control reg, enable prefetch for CPU read from DRAM control */
+
+ HBUS_ACC_CTL_0 |= 0x0100001f (0x5c)
+ &= 0xf1ffffff
+ /* host bus access control register, enable CPU address bus pipe control */
+ /* two outstanding requests, *** changed to 2 from 3 */
+ /* enable line merge write control for CPU write to system memory, PCI 1 */
+ /* and PCI 0 bus memory; enable page merge write control for write to */
+ /* PCI bus 0 & bus 1 memory */
+
+ SRAM_CTL |= 0x00004000 (0xc8)
+ &= 0xffbff7ff
+ /* DRAM detail timing control register 1 (ca), bit 3 set to 0 */
+ /* DRAM start access latency control - wait for one clock */
+ /* ff9f changed to ffbf */
+
+ DIM0_TIM_CTL_0 = 0x737d737d (0xc9)
+ /* DRAM timing control for dimm0 & dimm1; set wait one clock */
+ /* cycle for next data access */
+
+ DIM2_TIM_CTL_0 = 0x737d737d (0xca)
+ /* DRAM timing control for dimm2 & dimm3; set wait one clock */
+ /* cycle for next data access */
+
+ DIM0_BNK0_CTL_0 = BNK0_RAM_SIZ_128MB (0x90)
+ /* set dimm0 bank0 for 128 MB */
+
+ DIM0_BNK1_CTL_0 = BNK1_RAM_SIZ_128MB (0x94)
+ /* set dimm0 for bank1 */
+
+ DIM0_TIM_CTL_0 = 0xf3bf0000 (0xc9)
+ /* dimm0 timing control register; RAS - CAS latency - 4 clock */
+ /* CAS access latency - 3 wait; pre-charge latency - 3 wait */
+ /* pre-charge command period control - 5 clock; wait one clock */
+ /* cycle for next data access; read to write access latency control */
+ /* - 2 clock cycles */
+
+ DRAM_GBL_CTL_0 |= 0x00000100 (0xc0)
+ &= 0xffff01ff
+ /* memory global control register - support buffer sdram on bank 0 */
+
+ DRAM_ECC_CTL_0 |= 0x00260000 (0xc4)
+ &= 0xff26ffff
+ /* enable ECC; enable read, modify, write control */
+
+ DRAM_REF_CTL_0 = DRAM_REF_DATA (0xb8)
+ /* set DRAM refresh parameters *** changed to 00940100 */
+
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ DRAM_ECC_CTL_0 |= 0x20243280 (0xc4)
+ /* turn off ecc */
+ /* for SDRAM bank 0 */
+
+ DRAM_ECC_CTL_0 |= 0x20243290 (0xc4) ?
+ /* for SDRAM bank 1 */
+
+
+/* Additional Stuff...*/
+
+ GLOBL_CTRL |= 0x20000b00 (0x54)
+
+ PCI_0_SB_CONFIG |= 0x04100007 (0xd0)
+ /* PCI 0 Side band config reg*/
+
+ 0x8000083c |= 0x00080000
+ /* Disable VGA decode on PCI Bus 1 */
+
+
+/*End Additional Stuff..*/
+
+ /*--------------------------------------------------------------*/
+ /* TERON serial port initialization code */
+ /*--------------------------------------------------------------*/
+
+ 0x84380080 |= 0x00030000
+ /* enable super IO configuration VIA chip Register 85 */
+ /* Enable super I/O config mode */
+
+ 0xfe0003f0 = 0xe2
+ bl delay1
+
+ 0xfe0003f1 = 0x0f
+ bl delay1
+ /* enable com1 & com2, parallel port disabled */
+
+ 0xfe0003f0 = 0xe7
+ bl delay1
+ /* let's make com1 base as 0x3f8 */
+
+ 0xfe0003f1 = 0xfe
+ bl delay1
+
+ 0xfe0003f0 = 0xe8
+ bl delay1
+ /* let's make com2 base as 0x2f8 */
+
+ 0xfe0003f1 = 0xbe
+
+ 0x84380080 &= 0xfffdffff
+ /* closing super IO configuration VIA chip Register 85 */
+
+
+/* -------------------------------*/
+
+ 0xfe0003fb = 0x83
+ bl delay1
+ /*latch enable word length -8 bit */ /* set mslab bit */
+ 0xfe0003f8 = 0x0c
+ bl delay1
+ /* set baud rate lsb for 9600 baud */
+ 0xfe0003f9 = 0x0
+ bl delay1
+ /* set baud rate msb for 9600 baud */
+ 0xfe0003fb = 0x03
+ bl delay1
+ /* reset mslab */
+
+ /*--------------------------------------------------------------*/
+ /* END TERON Serial Port Initialization Code */
+ /*--------------------------------------------------------------*/
+
+
+
+ /*--------------------------------------------------------------*/
+ /* END TERON Articia / SDRAM Initialization code */
+ /*--------------------------------------------------------------*/
+
+Proposed from Documentation:
+
+write dmem 0xfec00cf8 0x50000080
+write dmem 0xfee00cfc 0xc0305411
+
+ Writes to index 0x50-0x53.
+ 0x50: Global Information Register 0
+ 0xC0 = Little Endian CPU, Sequential order Burst
+ 0x51: Global Information Register 1
+ Read only, 0x30 = Provides PowerPC and X86 support
+ 0x52: Global Information Register 2
+ 0x05 = 64/128 bit CPU bus support
+ 0x53: Global Information Register 3
+ 0x80 = PCI Bus 0 grant active time is 1 clock after REQ# deasserted
+
+write dmem 0xfec00cf8 0x5c000080
+write dmem 0xfee00cfc 0xb300011F
+
+write dmem 0xfec00cf8 0xc8000080
+write dmem 0xfee00cfc 0x0020f100
+
+write dmem 0xfec00cf8 0x90000080
+write dmem 0xfee00cfc 0x007fe700
+
+write dmem 0xfec00cf8 0x9400080
+write dmem 0xfee00cfc 0x007fe700
+
+write dmem 0xfec00cf8 0xb0000080
+write dmem 0xfee00cfc 0x737d737d
+
+write dmem 0xfec00cf8 0xb4000080
+write dmem 0xfee00cfc 0x737d737d
+
+write dmem 0xfec00cf8 0xc0000080
+write dmem 0xfee00cfc 0x40005500
+
+write dmem 0xfec00cf8 0xb8000080
+write dmem 0xfee00cfc 0x00940100
+
+write dmem 0xfec00cf8 0xc4000080
+write dmem 0xfee00cfc 0x00003280
+
+write dmem 0xfec00cf8 0xc4000080
+write dmem 0xfee00cfc 0x00003290
+
+
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