diff options
Diffstat (limited to 'arch')
32 files changed, 854 insertions, 744 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index f42eee1..f0f72fa 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -95,6 +95,9 @@ int print_cpuinfo(void) case TI81XX: cpu_s = "TI81XX"; break; + case AM437X: + cpu_s = "AM437X"; + break; default: cpu_s = "Unknown CPU type"; break; @@ -110,7 +113,7 @@ int print_cpuinfo(void) else sec_s = "?"; - printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s); + printf("CPU : %s-%s rev %s\n", cpu_s, sec_s, rev_s); return 0; } diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index 1872c57..658934d 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -19,7 +19,11 @@ ENTRY(lowlevel_init) /* * Setup a temporary stack. Global data is not available yet. */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) + ldr sp, =CONFIG_SPL_STACK +#else ldr sp, =CONFIG_SYS_INIT_SP_ADDR +#endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ #ifdef CONFIG_SPL_DM mov r9, #0 diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 66a3b3d..8ce12c8 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -24,6 +24,30 @@ ENTRY(save_boot_params) str r0, [r1] b save_boot_params_ret ENDPROC(save_boot_params) + +#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE) +ENTRY(switch_to_hypervisor) + +/* + * Switch to hypervisor mode + */ + adr r0, save_sp + str sp, [r0] + adr r1, restore_from_hyp + ldr r0, =0x102 + b omap_smc1 +restore_from_hyp: + adr r0, save_sp + ldr sp, [r0] + MRC p15, 4, R0, c1, c0, 0 + ldr r1, =0X1004 @Set cache enable bits for hypervisor mode + orr r0, r0, r1 + MCR p15, 4, R0, c1, c0, 0 + b switch_to_hypervisor_ret +save_sp: + .word 0x0 +ENDPROC(switch_to_hypervisor) +#endif #endif ENTRY(omap_smc1) diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c index 579bebf..b37163a 100644 --- a/arch/arm/cpu/armv7/omap-common/omap-cache.c +++ b/arch/arm/cpu/armv7/omap-common/omap-cache.c @@ -17,7 +17,28 @@ DECLARE_GLOBAL_DATA_PTR; -#define ARMV7_DCACHE_WRITEBACK 0xe +/* + * Without LPAE short descriptors are used + * Set C - Cache Bit3 + * Set B - Buffer Bit2 + * The last 2 bits set to 0b10 + * Do Not set XN bit4 + * So value is 0xe + * + * With LPAE cache configuration happens via MAIR0 register + * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF. + * 0xFF maps to Cache writeback with Read and Write Allocate set + * The bits[1:0] should have the value 0b01 for the first level + * descriptor. + * So the value is 0xd + */ + +#ifdef CONFIG_ARMV7_LPAE +#define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC +#else +#define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK +#endif + #define ARMV7_DOMAIN_CLIENT 1 #define ARMV7_DOMAIN_MASK (0x3 << 0) @@ -32,13 +53,13 @@ void dram_bank_mmu_setup(int bank) bd_t *bd = gd->bd; int i; - u32 start = bd->bi_dram[bank].start >> 20; - u32 size = bd->bi_dram[bank].size >> 20; + u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; + u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; u32 end = start + size; debug("%s: bank: %d\n", __func__, bank); for (i = start; i < end; i++) - set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); + set_section_dcache(i, ARMV7_DCACHE_POLICY); } void arm_init_domains(void) diff --git a/arch/arm/cpu/armv7/omap4/Kconfig b/arch/arm/cpu/armv7/omap4/Kconfig index c3dc95f..2091dd7 100644 --- a/arch/arm/cpu/armv7/omap4/Kconfig +++ b/arch/arm/cpu/armv7/omap4/Kconfig @@ -33,6 +33,9 @@ config SPL_POWER_SUPPORT config SPL_SERIAL_SUPPORT default y +config SPL_DISPLAY_PRINT + default y + choice prompt "OMAP4 board select" optional diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index a947ba4..22259dc 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -33,6 +33,9 @@ config SPL_POWER_SUPPORT config SPL_SERIAL_SUPPORT default y +config SPL_DISPLAY_PRINT + default y + choice prompt "OMAP5 board select" optional diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 691e5d3..7eee54b 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -17,6 +17,7 @@ #include <config.h> #include <asm/system.h> #include <linux/linkage.h> +#include <asm/armv7.h> /************************************************************************* * @@ -30,11 +31,24 @@ .globl reset .globl save_boot_params_ret +#ifdef CONFIG_ARMV7_LPAE + .global switch_to_hypervisor_ret +#endif reset: /* Allow the board to save important registers */ b save_boot_params save_boot_params_ret: +#ifdef CONFIG_ARMV7_LPAE +/* + * check for Hypervisor support + */ + mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 + and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits + cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT) + beq switch_to_hypervisor +switch_to_hypervisor_ret: +#endif /* * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, * except if in HYP mode already @@ -103,6 +117,13 @@ ENTRY(save_boot_params) ENDPROC(save_boot_params) .weak save_boot_params +#ifdef CONFIG_ARMV7_LPAE +ENTRY(switch_to_hypervisor) + b switch_to_hypervisor_ret +ENDPROC(switch_to_hypervisor) + .weak switch_to_hypervisor +#endif + /************************************************************************* * * cpu_init_cp15 diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index e21e199..2ddd67e 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -19,12 +19,22 @@ extern void c_runtime_cpu_setup(void); #define SEC_FIRMWARE_LOADED 0x1 #define SEC_FIRMWARE_RUNNING 0x2 #define SEC_FIRMWARE_ADDR_MASK (~0x3) - /* - * Secure firmware load addr - * Flags used: 0x1 secure firmware has been loaded to secure memory - * 0x2 secure firmware is running - */ - phys_addr_t sec_firmware_addr; +/* + * Secure firmware load addr + * Flags used: 0x1 secure firmware has been loaded to secure memory + * 0x2 secure firmware is running + */ +phys_addr_t sec_firmware_addr; + +#ifndef SEC_FIRMWARE_FIT_IMAGE +#define SEC_FIRMWARE_FIT_IMAGE "firmware" +#endif +#ifndef SEC_FIRMEWARE_FIT_CNF_NAME +#define SEC_FIRMEWARE_FIT_CNF_NAME "config@1" +#endif +#ifndef SEC_FIRMWARE_TARGET_EL +#define SEC_FIRMWARE_TARGET_EL 2 +#endif static int sec_firmware_get_data(const void *sec_firmware_img, const void **data, size_t *size) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 532527d..8458f6b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -133,7 +133,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_sr1500.dtb \ socfpga_cyclone5_vining_fpga.dtb -dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb +dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ + dra72-evm-revc.dtb dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ am572x-idk.dtb dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb diff --git a/arch/arm/dts/dra72-evm-common.dtsi b/arch/arm/dts/dra72-evm-common.dtsi new file mode 100644 index 0000000..b0993e5 --- /dev/null +++ b/arch/arm/dts/dra72-evm-common.dtsi @@ -0,0 +1,513 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra72x.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; + + chosen { + stdout-path = &uart1; + tick-timer = &timer2; + }; + + aliases { + display0 = &hdmi0; + }; + + evm_3v3: fixedregulator-evm_3v3 { + compatible = "regulator-fixed"; + regulator-name = "evm_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; + }; + + extcon_usb2: extcon_usb2 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + tpd12s015: encoder { + compatible = "ti,tpd12s015"; + + gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ + <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&dra7_pmx_core { + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + dcan1_pins_default: dcan1_pins_default { + pinctrl-single,pins = < + 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ + 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ + >; + }; + + dcan1_pins_sleep: dcan1_pins_sleep { + pinctrl-single,pins = < + 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ + 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ + >; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps65917: tps65917@58 { + compatible = "ti,tps65917"; + reg = <0x58>; + + interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ + interrupt-controller; + #interrupt-cells = <2>; + + ti,system-power-controller; + + tps65917_pmic { + compatible = "ti,tps65917-pmic"; + + tps65917_regulators: regulators { + smps1_reg: smps1 { + /* VDD_MPU */ + regulator-name = "smps1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps2_reg: smps2 { + /* VDD_CORE */ + regulator-name = "smps2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1060000>; + regulator-boot-on; + regulator-always-on; + }; + + smps3_reg: smps3 { + /* VDD_GPU IVA DSPEVE */ + regulator-name = "smps3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + + smps4_reg: smps4 { + /* VDDS1V8 */ + regulator-name = "smps4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps5_reg: smps5 { + /* VDD_DDR */ + regulator-name = "smps5"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + /* LDO1_OUT --> SDIO */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-allow-bypass; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHY */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + /* VDDA_1V8_PLL */ + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldo4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + }; + }; + + tps65917_power_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps65917>; + interrupts = <1 IRQ_TYPE_NONE>; + wakeup-source; + ti,palmas-long-press-seconds = <6>; + }; + }; + + pcf_gpio_21: gpio@21 { + compatible = "ti,pcf8575"; + u-boot,i2c-offset-len = <0>; + reg = <0x21>; + lines-initial-states = <0x1408>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + pcf_hdmi: pcf8575@26 { + compatible = "nxp,pcf8575"; + u-boot,i2c-offset-len = <0>; + reg = <0x26>; + gpio-controller; + #gpio-cells = <2>; + /* + * initial state is used here to keep the mdio interface + * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and + * VIN2_S0 driven high otherwise Ethernet stops working + * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 + */ + lines-initial-states = <0x0f2b>; + + p1 { + /* vin6_sel_s0: high: VIN6, low: audio */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "vin6_sel_s0"; + }; + }; +}; + +&uart1 { + status = "okay"; + interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x3e0>; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + /* + * For the existing IOdelay configuration via U-Boot we don't + * support NAND on dra72-evm. Keep it disabled. Enabling it + * requires a different configuration by U-Boot. + */ + status = "disabled"; + ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ + nand@0,0 { + /* To use NAND, DIP switch SW5 must be set like so: + * SW5.1 (NAND_SELn) = ON (LOW) + * SW5.9 (GPMC_WPN) = OFF (HIGH) + */ + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ /* device IO registers */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <80>; + gpmc,cs-wr-off-ns = <80>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <60>; + gpmc,adv-wr-off-ns = <60>; + gpmc,we-on-ns = <10>; + gpmc,we-off-ns = <50>; + gpmc,oe-on-ns = <4>; + gpmc,oe-off-ns = <40>; + gpmc,access-ns = <40>; + gpmc,wr-access-ns = <80>; + gpmc,rd-cycle-ns = <80>; + gpmc,wr-cycle-ns = <80>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x000020000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00020000 0x00020000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00040000 0x00020000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x00060000 0x00020000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00080000 0x00040000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x000c0000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x001c0000 0x00020000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x001e0000 0x00020000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00200000 0x00800000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00a00000 0x0f600000>; + }; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldo4_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldo4_reg>; +}; + +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&usb1 { + dr_mode = "otg"; +}; + +&usb2 { + dr_mode = "host"; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + vmmc_aux-supply = <&ldo1_reg>; + bus-width = <4>; + /* + * SDCD signal is not being used here - using the fact that GPIO mode + * is a viable alternative + */ + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; + max-frequency = <192000000>; +}; + +&mmc2 { + /* SW5-3 in ON position */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; + + vmmc-supply = <&evm_3v3>; + bus-width = <8>; + ti,non-removable; + max-frequency = <192000000>; +}; + +&mac { + status = "okay"; +}; + +&dcan1 { + status = "ok"; +}; + +&qspi { + status = "okay"; + + spi-max-frequency = <76800000>; + m25p80@0 { + compatible = "s25fl256s1", "spi-flash"; + spi-max-frequency = <64000000>; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first four physical blocks + * for a valid file to boot and the flash here is + * 64KiB block size. + */ + partition@0 { + label = "QSPI.SPL"; + reg = <0x00000000 0x000010000>; + }; + partition@1 { + label = "QSPI.SPL.backup1"; + reg = <0x00010000 0x00010000>; + }; + partition@2 { + label = "QSPI.SPL.backup2"; + reg = <0x00020000 0x00010000>; + }; + partition@3 { + label = "QSPI.SPL.backup3"; + reg = <0x00030000 0x00010000>; + }; + partition@4 { + label = "QSPI.u-boot"; + reg = <0x00040000 0x00100000>; + }; + partition@5 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00140000 0x00080000>; + }; + partition@6 { + label = "QSPI.u-boot-env"; + reg = <0x001c0000 0x00010000>; + }; + partition@7 { + label = "QSPI.u-boot-env.backup1"; + reg = <0x001d0000 0x0010000>; + }; + partition@8 { + label = "QSPI.kernel"; + reg = <0x001e0000 0x0800000>; + }; + partition@9 { + label = "QSPI.file-system"; + reg = <0x009e0000 0x01620000>; + }; + }; +}; + +&dss { + status = "ok"; + + vdda_video-supply = <&ldo5_reg>; +}; + +&hdmi { + status = "ok"; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; diff --git a/arch/arm/dts/dra72-evm-revc.dts b/arch/arm/dts/dra72-evm-revc.dts new file mode 100644 index 0000000..0f8a7ef --- /dev/null +++ b/arch/arm/dts/dra72-evm-revc.dts @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "dra72-evm-common.dtsi" +#include <dt-bindings/net/ti-dp83867.h> + +/ { + model = "TI DRA722 Rev C EVM"; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ + }; +}; + +&tps65917_regulators { + ldo2_reg: ldo2 { + /* LDO2_OUT --> VDDA_1V8_PHY2 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hdmi { + vdda_video-supply = <&ldo2_reg>; +}; + +&mac { + mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, + <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ + <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ + dual_emac; +}; + +&cpsw_emac0 { + phy-handle = <&dp83867_0>; + phy-mode = "rgmii-id"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy-handle = <&dp83867_1>; + phy-mode = "rgmii-id"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + dp83867_0: ethernet-phy@2 { + reg = <2>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + ti,min-output-imepdance; + }; + + dp83867_1: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + ti,min-output-imepdance; + }; +}; diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts index e7c5db2..f81f918 100644 --- a/arch/arm/dts/dra72-evm.dts +++ b/arch/arm/dts/dra72-evm.dts @@ -5,674 +5,24 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -/dts-v1/; - -#include "dra72x.dtsi" -#include <dt-bindings/gpio/gpio.h> +#include <dra72-evm-common.dtsi> / { model = "TI DRA722"; compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; - chosen { - stdout-path = &uart1; - tick-timer = &timer2; - }; - memory { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1024 MB */ }; - - aliases { - display0 = &hdmi0; - }; - - evm_3v3: fixedregulator-evm_3v3 { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - evm_3v3_sd: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb1: extcon_usb1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb2: extcon_usb2 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - pinctrl-names = "default"; - pinctrl-0 = <&tpd12s015_pins>; - - gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ - <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; -}; - -&dra7_pmx_core { - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ - 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ - >; - }; - - nand_default: nand_default { - pinctrl-single,pins = < - 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ - 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ - 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ - 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ - 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ - 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ - 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ - 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ - 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ - 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ - 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ - 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ - 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ - 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ - 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ - 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ - 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ - 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ - 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ - 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ - 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ - 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ - >; - }; - - usb2_pins: pinmux_usb2_pins { - pinctrl-single,pins = < - 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ - >; - }; - - tps65917_pins_default: tps65917_pins_default { - pinctrl-single,pins = < - 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ - >; - }; - - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ - 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - dcan1_pins_default: dcan1_pins_default { - pinctrl-single,pins = < - 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ - 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ - >; - }; - - dcan1_pins_sleep: dcan1_pins_sleep { - pinctrl-single,pins = < - 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ - 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ - >; - }; - - qspi1_pins: pinmux_qspi1_pins { - pinctrl-single,pins = < - 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ - 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ - 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ - 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ - 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ - 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ - 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ - >; - }; - - hdmi_pins: pinmux_hdmi_pins { - pinctrl-single,pins = < - 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ - 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ - >; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; - - tps65917: tps65917@58 { - compatible = "ti,tps65917"; - reg = <0x58>; - - pinctrl-names = "default"; - pinctrl-0 = <&tps65917_pins_default>; - - interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ - interrupt-controller; - #interrupt-cells = <2>; - - ti,system-power-controller; - - tps65917_pmic { - compatible = "ti,tps65917-pmic"; - - regulators { - smps1_reg: smps1 { - /* VDD_MPU */ - regulator-name = "smps1"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps2_reg: smps2 { - /* VDD_CORE */ - regulator-name = "smps2"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1060000>; - regulator-boot-on; - regulator-always-on; - }; - - smps3_reg: smps3 { - /* VDD_GPU IVA DSPEVE */ - regulator-name = "smps3"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - regulator-always-on; - }; - - smps4_reg: smps4 { - /* VDDS1V8 */ - regulator-name = "smps4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps5_reg: smps5 { - /* VDD_DDR */ - regulator-name = "smps5"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - /* LDO1_OUT --> SDIO */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - ldo2_reg: ldo2 { - /* LDO2_OUT --> TP1017 (UNUSED) */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHY */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PLL */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldo4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; - }; - - tps65917_power_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps65917>; - interrupts = <1 IRQ_TYPE_NONE>; - wakeup-source; - ti,palmas-long-press-seconds = <6>; - }; - }; - - pcf_gpio_21: gpio@21 { - compatible = "ti,pcf8575"; - reg = <0x21>; - lines-initial-states = <0x1408>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - u-boot,i2c-offset-len = <0>; - }; }; -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - clock-frequency = <400000>; - - pcf_hdmi: pcf8575@26 { - compatible = "nxp,pcf8575"; - reg = <0x26>; - gpio-controller; - #gpio-cells = <2>; - /* - * initial state is used here to keep the mdio interface - * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and - * VIN2_S0 driven high otherwise Ethernet stops working - * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 - */ - lines-initial-states = <0x0f2b>; - u-boot,i2c-offset-len = <0>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_default>; - ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ - nand@0,0 { - /* To use NAND, DIP switch SW5 must be set like so: - * SW5.1 (NAND_SELn) = ON (LOW) - * SW5.9 (GPMC_WPN) = OFF (HIGH) - */ - reg = <0 0 4>; /* device IO registers */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <80>; - gpmc,cs-wr-off-ns = <80>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <60>; - gpmc,adv-wr-off-ns = <60>; - gpmc,we-on-ns = <10>; - gpmc,we-off-ns = <50>; - gpmc,oe-on-ns = <4>; - gpmc,oe-off-ns = <40>; - gpmc,access-ns = <40>; - gpmc,wr-access-ns = <80>; - gpmc,rd-cycle-ns = <80>; - gpmc,wr-cycle-ns = <80>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x000020000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00020000 0x00020000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00040000 0x00020000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x00060000 0x00020000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00080000 0x00040000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x000c0000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x001c0000 0x00020000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x001e0000 0x00020000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00200000 0x00800000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00a00000 0x0f600000>; - }; - }; -}; - -&usb2_phy1 { - phy-supply = <&ldo4_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldo4_reg>; -}; - -&omap_dwc3_1 { - extcon = <&extcon_usb1>; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb1 { - dr_mode = "peripheral"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; -}; - -&usb2 { - dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pins>; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; - - vmmc_aux-supply = <&ldo1_reg>; - vmmc-supply = <&evm_3v3_sd>; - bus-width = <4>; - /* - * SDCD signal is not being used here - using the fact that GPIO mode - * is a viable alternative - */ - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; -}; - -&mmc2 { - /* SW5-3 in ON position */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_default>; - - vmmc-supply = <&evm_3v3>; - bus-width = <8>; - ti,non-removable; -}; - -&dra7_pmx_core { - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 2 */ - 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ - 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ - 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ - 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ - 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ - 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ - 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ - 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ - 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ - 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ - 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ - 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ - >; - - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 2 */ - 0x198 (MUX_MODE15) - 0x19c (MUX_MODE15) - 0x1a0 (MUX_MODE15) - 0x1a4 (MUX_MODE15) - 0x1a8 (MUX_MODE15) - 0x1ac (MUX_MODE15) - 0x1b0 (MUX_MODE15) - 0x1b4 (MUX_MODE15) - 0x1b8 (MUX_MODE15) - 0x1bc (MUX_MODE15) - 0x1c0 (MUX_MODE15) - 0x1c4 (MUX_MODE15) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ - 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - 0x23c (MUX_MODE15) - 0x240 (MUX_MODE15) - >; - }; -}; - -&mac { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>; -}; &cpsw_emac0 { phy_id = <&davinci_mdio>, <3>; phy-mode = "rgmii"; }; -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; -}; - -&dcan1 { - status = "ok"; - pinctrl-names = "default", "sleep", "active"; - pinctrl-0 = <&dcan1_pins_sleep>; - pinctrl-1 = <&dcan1_pins_sleep>; - pinctrl-2 = <&dcan1_pins_default>; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi1_pins>; - - spi-max-frequency = <76800000>; - m25p80@0 { - compatible = "s25fl256s1","spi-flash"; - spi-max-frequency = <64000000>; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first four physical blocks - * for a valid file to boot and the flash here is - * 64KiB block size. - */ - partition@0 { - label = "QSPI.SPL"; - reg = <0x00000000 0x000010000>; - }; - partition@1 { - label = "QSPI.SPL.backup1"; - reg = <0x00010000 0x00010000>; - }; - partition@2 { - label = "QSPI.SPL.backup2"; - reg = <0x00020000 0x00010000>; - }; - partition@3 { - label = "QSPI.SPL.backup3"; - reg = <0x00030000 0x00010000>; - }; - partition@4 { - label = "QSPI.u-boot"; - reg = <0x00040000 0x00100000>; - }; - partition@5 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00140000 0x00080000>; - }; - partition@6 { - label = "QSPI.u-boot-env"; - reg = <0x001c0000 0x00010000>; - }; - partition@7 { - label = "QSPI.u-boot-env.backup1"; - reg = <0x001d0000 0x0010000>; - }; - partition@8 { - label = "QSPI.kernel"; - reg = <0x001e0000 0x0800000>; - }; - partition@9 { - label = "QSPI.file-system"; - reg = <0x009e0000 0x01620000>; - }; - }; -}; - &dss { status = "ok"; @@ -680,15 +30,9 @@ }; &hdmi { - status = "ok"; vdda-supply = <&ldo3_reg>; +}; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; +&mac { + mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 62bca8c..dbed776 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -43,7 +43,8 @@ #define HS_DEVICE 0x2 #define GP_DEVICE 0x3 -/* cpu-id for AM33XX and TI81XX family */ +/* cpu-id for AM43XX AM33XX and TI81XX family */ +#define AM437X 0xB98C #define AM335X 0xB944 #define TI81XX 0xB81E #define DEVICE_ID (CTRL_BASE + 0x0600) @@ -579,6 +580,8 @@ struct pwmss_regs { }; #define ECAP_CLK_EN BIT(0) #define ECAP_CLK_STOP_REQ BIT(1) +#define EPWM_CLK_EN BIT(8) +#define EPWM_CLK_STOP_REQ BIT(9) struct pwmss_ecap_regs { unsigned int tsctr; @@ -592,6 +595,40 @@ struct pwmss_ecap_regs { unsigned short ecctl2; }; +struct pwmss_epwm_regs { + unsigned short tbctl; + unsigned short tbsts; + unsigned short tbphshr; + unsigned short tbphs; + unsigned short tbcnt; + unsigned short tbprd; + unsigned short res1; + unsigned short cmpctl; + unsigned short cmpahr; + unsigned short cmpa; + unsigned short cmpb; + unsigned short aqctla; + unsigned short aqctlb; + unsigned short aqsfrc; + unsigned short aqcsfrc; + unsigned short dbctl; + unsigned short dbred; + unsigned short dbfed; + unsigned short tzsel; + unsigned short tzctl; + unsigned short tzflg; + unsigned short tzclr; + unsigned short tzfrc; + unsigned short etsel; + unsigned short etps; + unsigned short etflg; + unsigned short etclr; + unsigned short etfrc; + unsigned short pcctl; + unsigned int res2[66]; + unsigned short hrcnfg; +}; + /* Capture Control register 2 */ #define ECTRL2_SYNCOSEL_MASK (0x03 << 6) #define ECTRL2_MDSL_ECAP BIT(9) diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index d1aed58..fa9b84f 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -67,5 +67,6 @@ /* PWMSS */ #define PWMSS0_BASE 0x48300000 #define AM33XX_ECAP0_BASE 0x48300100 +#define AM33XX_EPWM_BASE 0x48300200 #endif /* __AM33XX_HARDWARE_AM33XX_H */ diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index 9b79506..171f4d9 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h @@ -21,6 +21,11 @@ #endif typedef struct { volatile int counter; } atomic_t; +#if BITS_PER_LONG == 32 +typedef struct { volatile long long counter; } atomic64_t; +#else /* BIT_PER_LONG == 32 */ +typedef struct { volatile long counter; } atomic64_t; +#endif #define ATOMIC_INIT(i) { (i) } @@ -28,7 +33,9 @@ typedef struct { volatile int counter; } atomic_t; #include <asm/proc-armv/system.h> #define atomic_read(v) ((v)->counter) -#define atomic_set(v,i) (((v)->counter) = (i)) +#define atomic_set(v, i) (((v)->counter) = (i)) +#define atomic64_read(v) atomic_read(v) +#define atomic64_set(v, i) atomic_set(v, i) static inline void atomic_add(int i, volatile atomic_t *v) { @@ -101,6 +108,65 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) local_irq_restore(flags); } +#if BITS_PER_LONG == 32 + +static inline void atomic64_add(long long i, volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic64_sub(long long i, volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} + +#else /* BIT_PER_LONG == 32 */ + +static inline void atomic64_add(long i, volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic64_sub(long i, volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} +#endif + +static inline void atomic64_inc(volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter += 1; + local_irq_restore(flags); +} + +static inline void atomic64_dec(volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter -= 1; + local_irq_restore(flags); +} + /* Atomic operations are already serializing on ARM */ #define smp_mb__before_atomic_dec() barrier() #define smp_mb__after_atomic_dec() barrier() diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 1864ab9..6b46078 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -45,7 +45,7 @@ static inline void *phys_to_virt(unsigned long x) /* * Virtual <-> DMA view memory address translations * Again, these are *only* valid on the kernel direct mapped RAM - * memory. Use of these is *depreciated*. + * memory. Use of these is *deprecated*. */ #define virt_to_bus(x) (__virt_to_bus((unsigned long)(x))) #define bus_to_virt(x) ((void *)(__bus_to_virt((unsigned long)(x)))) @@ -127,7 +127,7 @@ static inline void *phys_to_virt(unsigned long x) #endif /* - * We should really eliminate virt_to_bus() here - it's depreciated. + * We should really eliminate virt_to_bus() here - it's deprecated. */ #define page_to_bus(page) (virt_to_bus(page_address(page))) diff --git a/arch/arm/include/asm/setjmp.h b/arch/arm/include/asm/setjmp.h index f7b97ef..df9934b 100644 --- a/arch/arm/include/asm/setjmp.h +++ b/arch/arm/include/asm/setjmp.h @@ -11,29 +11,26 @@ struct jmp_buf_data { ulong target; ulong regs[5]; + int ret; }; typedef struct jmp_buf_data jmp_buf[1]; static inline int setjmp(jmp_buf jmp) { - long r = 0; + jmp->ret = 0; #ifdef CONFIG_ARM64 asm volatile( "adr x1, jmp_target\n" - "str x1, %1\n" - "stp x26, x27, %2\n" - "stp x28, x29, %3\n" + "str x1, %0\n" + "stp x26, x27, %1\n" + "stp x28, x29, %2\n" "mov x1, sp\n" - "str x1, %4\n" - "b 2f\n" + "str x1, %3\n" "jmp_target: " - "mov %0, #1\n" - "2:\n" - : "+r" (r), "=m" (jmp->target), - "=m" (jmp->regs[0]), "=m" (jmp->regs[2]), - "=m" (jmp->regs[4]) + : "=m" (jmp->target), "=m" (jmp->regs[0]), + "=m" (jmp->regs[2]), "=m" (jmp->regs[4]) : : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", @@ -49,26 +46,25 @@ static inline int setjmp(jmp_buf jmp) #else "adr r0, jmp_target\n" #endif - "mov r1, %1\n" + "mov r1, %0\n" "mov r2, sp\n" "stm r1!, {r0, r2, r4, r5, r6, r7}\n" - "b 2f\n" ".align 2\n" "jmp_target: \n" - "mov %0, #1\n" - "2:\n" - : "+l" (r) + : : "l" (&jmp->target) : "r0", "r1", "r2", "r3", /* "r4", "r5", "r6", "r7", */ "r8", "r9", "r10", "r11", /* sp, */ "ip", "lr", "cc", "memory"); #endif - return r; + return jmp->ret; } -static inline __noreturn void longjmp(jmp_buf jmp) +static inline __noreturn void longjmp(jmp_buf jmp, int ret) { + jmp->ret = ret; + #ifdef CONFIG_ARM64 asm volatile( "ldr x0, %0\n" diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index 78a7fac..3a4e902 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -132,7 +132,7 @@ struct tag_ramdisk { /* describes where the compressed ramdisk image lives (virtual address) */ /* * this one accidentally used virtual addresses - as such, - * its depreciated. + * it's deprecated. */ #define ATAG_INITRD 0x54410005 diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 6f312d6..a0bda28 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -33,15 +33,6 @@ enum { }; #endif -/** - * Board specific load method for boards that have a special way of loading - * U-Boot, which does not fit with the existing SPL code. - * - * @return 0 on success, negative errno value on failure. - */ - -int spl_board_load_image(void); - /* Linker symbols. */ extern char __bss_start[], __bss_end[]; diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 7b7b867..c18e1e3 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -223,6 +223,10 @@ void __noreturn psci_system_reset(bool smc); */ void save_boot_params_ret(void); +#ifdef CONFIG_ARMV7_LPAE +void switch_to_hypervisor_ret(void); +#endif + #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); #ifdef __ARM_ARCH_7A__ diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h index a0d0d9b..0627728 100644 --- a/arch/arm/include/asm/ti-common/keystone_net.h +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -51,9 +51,9 @@ /* MDIO module input frequency */ #ifdef CONFIG_SOC_K2G -#define EMAC_MDIO_BUS_FREQ (clk_get_rate(sys_clk0_3_clk)) +#define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(sys_clk0_3_clk)) #else -#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk)) +#define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(pass_pll_clk)) #endif /* MDIO clock output frequency */ #define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index 3587ad6..e606d47 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -47,7 +47,7 @@ void __weak board_init_f(ulong dummy) * arg: Pointer to paramter image in RAM */ #ifdef CONFIG_SPL_OS_BOOT -void __noreturn jump_to_image_linux(void *arg) +void __noreturn jump_to_image_linux(struct spl_image_info *spl_image, void *arg) { unsigned long machid = 0xffffffff; #ifdef CONFIG_MACH_TYPE @@ -58,7 +58,7 @@ void __noreturn jump_to_image_linux(void *arg) typedef void (*image_entry_arg_t)(int, int, void *) __attribute__ ((noreturn)); image_entry_arg_t image_entry = - (image_entry_arg_t)(uintptr_t) spl_image.entry_point; + (image_entry_arg_t)(uintptr_t) spl_image->entry_point; cleanup_before_linux(); image_entry(0, machid, arg); } diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index b25db1e..d8804724 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -341,7 +341,7 @@ static unsigned long pll_freq_get(int pll) return ret; } -unsigned long clk_get_rate(unsigned int clk) +unsigned long ks_clk_get_rate(unsigned int clk) { unsigned long freq = 0; @@ -381,37 +381,37 @@ unsigned long clk_get_rate(unsigned int clk) freq = pll_freq_get(CORE_PLL) / pll0div_read(4); break; case sys_clk0_2_clk: - freq = clk_get_rate(sys_clk0_clk) / 2; + freq = ks_clk_get_rate(sys_clk0_clk) / 2; break; case sys_clk0_3_clk: - freq = clk_get_rate(sys_clk0_clk) / 3; + freq = ks_clk_get_rate(sys_clk0_clk) / 3; break; case sys_clk0_4_clk: - freq = clk_get_rate(sys_clk0_clk) / 4; + freq = ks_clk_get_rate(sys_clk0_clk) / 4; break; case sys_clk0_6_clk: - freq = clk_get_rate(sys_clk0_clk) / 6; + freq = ks_clk_get_rate(sys_clk0_clk) / 6; break; case sys_clk0_8_clk: - freq = clk_get_rate(sys_clk0_clk) / 8; + freq = ks_clk_get_rate(sys_clk0_clk) / 8; break; case sys_clk0_12_clk: - freq = clk_get_rate(sys_clk0_clk) / 12; + freq = ks_clk_get_rate(sys_clk0_clk) / 12; break; case sys_clk0_24_clk: - freq = clk_get_rate(sys_clk0_clk) / 24; + freq = ks_clk_get_rate(sys_clk0_clk) / 24; break; case sys_clk1_3_clk: - freq = clk_get_rate(sys_clk1_clk) / 3; + freq = ks_clk_get_rate(sys_clk1_clk) / 3; break; case sys_clk1_4_clk: - freq = clk_get_rate(sys_clk1_clk) / 4; + freq = ks_clk_get_rate(sys_clk1_clk) / 4; break; case sys_clk1_6_clk: - freq = clk_get_rate(sys_clk1_clk) / 6; + freq = ks_clk_get_rate(sys_clk1_clk) / 6; break; case sys_clk1_12_clk: - freq = clk_get_rate(sys_clk1_clk) / 12; + freq = ks_clk_get_rate(sys_clk1_clk) / 12; break; default: break; diff --git a/arch/arm/mach-keystone/cmd_clock.c b/arch/arm/mach-keystone/cmd_clock.c index 3d5cf3f..06afa72 100644 --- a/arch/arm/mach-keystone/cmd_clock.c +++ b/arch/arm/mach-keystone/cmd_clock.c @@ -74,7 +74,7 @@ int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) clk = simple_strtoul(argv[1], NULL, 10); - freq = clk_get_rate(clk); + freq = ks_clk_get_rate(clk); if (freq) printf("clock index [%d] - frequency %lu\n", clk, freq); else diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index 72724aa..0d8a944 100644 --- a/arch/arm/mach-keystone/include/mach/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -125,9 +125,7 @@ extern int speeds[]; void init_plls(void); void init_pll(const struct pll_init_data *data); struct pll_init_data *get_pll_init_data(int pll); -unsigned long clk_get_rate(unsigned int clk); -unsigned long clk_round_rate(unsigned int clk, unsigned long hz); -int clk_set_rate(unsigned int clk, unsigned long hz); +unsigned long ks_clk_get_rate(unsigned int clk); int get_max_dev_speed(int *spds); int get_max_arm_speed(int *spds); void pll_pa_clk_sel(void); diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 6d9518d..7713813 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -133,13 +133,17 @@ static int gpio_init(void) return 0; } -int spl_board_load_image(void) +#ifdef CONFIG_SPL_BUILD +static int spl_board_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr); return_to_fel(fel_stash.sp, fel_stash.lr); return 0; } +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_BOARD, spl_board_load_image); +#endif void s_init(void) { diff --git a/arch/arm/mach-uniphier/boot-mode/spl_board.c b/arch/arm/mach-uniphier/boot-mode/spl_board.c index 86292b6..854ab05 100644 --- a/arch/arm/mach-uniphier/boot-mode/spl_board.c +++ b/arch/arm/mach-uniphier/boot-mode/spl_board.c @@ -65,7 +65,8 @@ int uniphier_rom_get_mmc_funcptr(int (**send_cmd)(u32, u32), return 0; } -int spl_board_load_image(void) +static int spl_board_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { int (*send_cmd)(u32 cmd, u32 arg); int (*card_blockaddr)(u32 rca); @@ -113,12 +114,12 @@ int spl_board_load_image(void) return ret; } - ret = spl_parse_image_header((void *)CONFIG_SYS_TEXT_BASE); + ret = spl_parse_image_header(spl_image, (void *)CONFIG_SYS_TEXT_BASE); if (ret) return ret; - ret = (*load_image)(dev_addr, spl_image.load_addr, - spl_image.size / 512); + ret = (*load_image)(dev_addr, spl_image->load_addr, + spl_image->size / 512); if (ret) { printf("failed to load image\n"); return ret; @@ -126,3 +127,4 @@ int spl_board_load_image(void) return 0; } +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_BOARD, spl_board_load_image); diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index f4bb091..8e6d926 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -29,13 +29,13 @@ void spl_board_init(void) } #ifdef CONFIG_SPL_OS_BOOT -void __noreturn jump_to_image_linux(void *arg) +void __noreturn jump_to_image_linux(struct spl_image_info *spl_image, void *arg) { debug("Entering kernel arg pointer: 0x%p\n", arg); typedef void (*image_entry_arg_t)(char *, ulong, ulong) __attribute__ ((noreturn)); image_entry_arg_t image_entry = - (image_entry_arg_t)spl_image.entry_point; + (image_entry_arg_t)spl_image->entry_point; image_entry(NULL, 0, (ulong)arg); } diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index ef08489..cabf64c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -489,7 +489,7 @@ static void dump_spd_ddr_reg(void) for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR); - puts("SPD data of all dimms (zero vaule is omitted)...\n"); + puts("SPD data of all dimms (zero value is omitted)...\n"); puts("Byte (hex) "); k = 1; for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { @@ -543,7 +543,7 @@ static void dump_spd_ddr_reg(void) } } printf("DDR registers dump for all controllers " - "(zero vaule is omitted)...\n"); + "(zero value is omitted)...\n"); puts("Offset (hex) "); for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); diff --git a/arch/powerpc/lib/spl.c b/arch/powerpc/lib/spl.c index 0e486cc..080b978 100644 --- a/arch/powerpc/lib/spl.c +++ b/arch/powerpc/lib/spl.c @@ -17,14 +17,14 @@ DECLARE_GLOBAL_DATA_PTR; * arg: Pointer to paramter image in RAM */ #ifdef CONFIG_SPL_OS_BOOT -void __noreturn jump_to_image_linux(void *arg) +void __noreturn jump_to_image_linux(struct spl_image_info *spl_image, void *arg) { debug("Entering kernel arg pointer: 0x%p\n", arg); typedef void (*image_entry_arg_t)(void *, ulong r4, ulong r5, ulong r6, ulong r7, ulong r8, ulong r9) __attribute__ ((noreturn)); image_entry_arg_t image_entry = - (image_entry_arg_t)spl_image.entry_point; + (image_entry_arg_t)spl_image->entry_point; image_entry(arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ, 0, 0); } diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index e8349c0..1ad7fb6 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -38,7 +38,8 @@ void spl_board_announce_boot_device(void) printf("%s\n", fname); } -int spl_board_load_image(void) +static int spl_board_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { char fname[256]; int ret; @@ -50,6 +51,7 @@ int spl_board_load_image(void) /* Hopefully this will not return */ return os_spl_to_uboot(fname); } +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_BOARD, spl_board_load_image); void spl_board_init(void) { diff --git a/arch/sandbox/include/asm/spl.h b/arch/sandbox/include/asm/spl.h index 59f2401..eb3cb56 100644 --- a/arch/sandbox/include/asm/spl.h +++ b/arch/sandbox/include/asm/spl.h @@ -8,14 +8,6 @@ #define CONFIG_SPL_BOARD_LOAD_IMAGE -/** - * Board-specific load method for boards that have a special way of loading - * U-Boot, which does not fit with the existing SPL code. - * - * @return 0 on success, negative errno value on failure. - */ -int spl_board_load_image(void); - enum { BOOT_DEVICE_BOARD, }; |