diff options
Diffstat (limited to 'arch')
23 files changed, 637 insertions, 55 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg new file mode 100644 index 0000000..8118767 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg @@ -0,0 +1,6 @@ +SECTION 0x0 BOOTABLE + TAG LAST + LOAD 0x0 spl/u-boot-spl.bin + CALL 0x14 0x0 + LOAD 0x40000100 u-boot.bin + CALL 0x40000100 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg new file mode 100644 index 0000000..ea772f0 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg @@ -0,0 +1,8 @@ +SECTION 0x0 BOOTABLE + TAG LAST + LOAD 0x0 spl/u-boot-spl.bin + LOAD IVT 0x8000 0x14 + CALL HAB 0x8000 0x0 + LOAD 0x40000100 u-boot.bin + LOAD IVT 0x8000 0x40000100 + CALL HAB 0x8000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index e3b6cd9..f357959 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -36,7 +36,7 @@ static void mxs_power_clock2pll(void) CLKCTRL_CLKSEQ_BYPASS_CPU); } -static void mxs_power_clear_auto_restart(void) +static void mxs_power_set_auto_restart(void) { struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE; @@ -49,10 +49,7 @@ static void mxs_power_clear_auto_restart(void) while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE) ; - /* - * Due to the hardware design bug of mx28 EVK-A - * we need to set the AUTO_RESTART bit. - */ + /* Do nothing if flag already set */ if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART) return; @@ -911,7 +908,7 @@ void mxs_power_init(void) mxs_ungate_power(); mxs_power_clock2xtal(); - mxs_power_clear_auto_restart(); + mxs_power_set_auto_restart(); mxs_power_set_linreg(); mxs_power_setup_5v_detect(); diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile index c5e9858..6d73617 100644 --- a/arch/arm/cpu/armv7/mx6/Makefile +++ b/arch/arm/cpu/armv7/mx6/Makefile @@ -11,10 +11,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS = soc.o clock.o +COBJS-y = soc.o clock.o +COBJS-$(CONFIG_SECURE_BOOT) += hab.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) all: $(obj).depend $(LIB) diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/cpu/armv7/mx6/hab.c new file mode 100644 index 0000000..5187775 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/hab.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hab.h> + +/* -------- start of HAB API updates ------------*/ +#define hab_rvt_report_event ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) +#define hab_rvt_report_status ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) +#define hab_rvt_authenticate_image \ + ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) +#define hab_rvt_entry ((hab_rvt_entry_t *)HAB_RVT_ENTRY) +#define hab_rvt_exit ((hab_rvt_exit_t *)HAB_RVT_EXIT) +#define hab_rvt_clock_init HAB_RVT_CLOCK_INIT + +bool is_hab_enabled(void) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + uint32_t reg = readl(&fuse->cfg5); + + return (reg & 0x2) == 0x2; +} + +void display_event(uint8_t *event_data, size_t bytes) +{ + uint32_t i; + + if (!(event_data && bytes > 0)) + return; + + for (i = 0; i < bytes; i++) { + if (i == 0) + printf("\t0x%02x", event_data[i]); + else if ((i % 8) == 0) + printf("\n\t0x%02x", event_data[i]); + else + printf(" 0x%02x", event_data[i]); + } +} + +int get_hab_status(void) +{ + uint32_t index = 0; /* Loop index */ + uint8_t event_data[128]; /* Event data buffer */ + size_t bytes = sizeof(event_data); /* Event size in bytes */ + enum hab_config config = 0; + enum hab_state state = 0; + + if (is_hab_enabled()) + puts("\nSecure boot enabled\n"); + else + puts("\nSecure boot disabled\n"); + + /* Check HAB status */ + if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) { + printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", + config, state); + + /* Display HAB Error events */ + while (hab_rvt_report_event(HAB_FAILURE, index, event_data, + &bytes) == HAB_SUCCESS) { + puts("\n"); + printf("--------- HAB Event %d -----------------\n", + index + 1); + puts("event data:\n"); + display_event(event_data, bytes); + puts("\n"); + bytes = sizeof(event_data); + index++; + } + } + /* Display message if no HAB events are found */ + else { + printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", + config, state); + puts("No HAB Events Found!\n\n"); + } + return 0; +} + +int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if ((argc != 1)) { + cmd_usage(cmdtp); + return 1; + } + + get_hab_status(); + + return 0; +} + +U_BOOT_CMD( + hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status, + "display HAB status", + "" + ); diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 8150bff..a390296 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -213,6 +213,34 @@ const struct boot_mode soc_boot_modes[] = { void s_init(void) { + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + int is_6q = is_cpu_type(MXC_CPU_MX6Q); + u32 mask480; + u32 mask528; + + /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs + * to make sure PFD is working right, otherwise, PFDs may + * not output clock after reset, MX6DL and MX6SL have added 396M pfd + * workaround in ROM code, as bus clock need it + */ + + mask480 = ANATOP_PFD_CLKGATE_MASK(0) | + ANATOP_PFD_CLKGATE_MASK(1) | + ANATOP_PFD_CLKGATE_MASK(2) | + ANATOP_PFD_CLKGATE_MASK(3); + mask528 = ANATOP_PFD_CLKGATE_MASK(0) | + ANATOP_PFD_CLKGATE_MASK(1) | + ANATOP_PFD_CLKGATE_MASK(3); + + /* + * Don't reset PFD2 on DL/S + */ + if (is_6q) + mask528 |= ANATOP_PFD_CLKGATE_MASK(2); + writel(mask480, &anatop->pfd_480_set); + writel(mask528, &anatop->pfd_528_set); + writel(mask480, &anatop->pfd_480_clr); + writel(mask528, &anatop->pfd_528_clr); } #ifdef CONFIG_IMX_HDMI diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index e903ed9..9f989ff 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -183,8 +183,7 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index) * if running from flash, jump to small relocated code * area in SRAM. */ - f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + - SRAM_VECT_CODE); + f_lock_pll = (void *) (SRAM_CLK_CODE); p0 = readl(&prcm_base->clken_pll); sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS); @@ -401,8 +400,7 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index) * if running from flash, jump to small relocated code * area in SRAM. */ - f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + - SRAM_VECT_CODE); + f_lock_pll = (void *) (SRAM_CLK_CODE); p0 = readl(&prcm_base->clken_pll); sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS); diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 98c3c03..6f7261b 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -69,15 +69,13 @@ ENDPROC(do_omap3_emu_romcode_call) *************************************************************************/ ENTRY(cpy_clk_code) /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ + adr r0, go_to_speed /* copy from start of go_to_speed... */ + adr r2, lowlevel_init /* ... up to start of low_level_init */ next2: ldmia r0!, {r3 - r10} /* copy from source address [r0] */ stmia r1!, {r3 - r10} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ - bne next2 + blo next2 mov pc, lr /* back to caller */ ENDPROC(cpy_clk_code) diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 310df5a..6a225c8 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -50,6 +50,7 @@ static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { /* * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430) * OMAP4430 OPP_TURBO frequency + * OMAP4470 OPP_NOM frequency */ static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -76,6 +77,7 @@ static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { }; /* OMAP4460 OPP_NOM frequency */ +/* OMAP4470 OPP_NOM (Low Power) frequency */ static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ @@ -198,6 +200,20 @@ struct dplls omap4460_dplls = { .ddr = NULL }; +struct dplls omap4470_dplls = { + .mpu = mpu_dpll_params_1600mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + struct pmic_data twl6030_4430es1 = { .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV, .step = 12660, /* 12.66 mV represented in uV */ @@ -208,6 +224,7 @@ struct pmic_data twl6030_4430es1 = { .pmic_write = omap_vc_bypass_send_value, }; +/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */ struct pmic_data twl6030 = { .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV, .step = 12660, /* 12.66 mV represented in uV */ @@ -271,6 +288,20 @@ struct vcores_data omap4460_volts = { .mm.pmic = &twl6030, }; +struct vcores_data omap4470_volts = { + .mpu.value = 1200, + .mpu.addr = SMPS_REG_ADDR_SMPS1, + .mpu.pmic = &twl6030, + + .core.value = 1126, + .core.addr = SMPS_REG_ADDR_SMPS1, + .core.pmic = &twl6030, + + .mm.value = 1137, + .mm.addr = SMPS_REG_ADDR_SMPS1, + .mm.pmic = &twl6030, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -476,6 +507,11 @@ void hw_data_init(void) *omap_vcores = &omap4460_volts; break; + case OMAP4470_ES1_0: + *dplls_data = &omap4470_dplls; + *omap_vcores = &omap4470_volts; + break; + default: printf("\n INVALID OMAP REVISION "); } diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 4da0fc0..b0598a0 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -138,6 +138,9 @@ void init_omap_revision(void) break; case MIDR_CORTEX_A9_R2P10: switch (readl(CONTROL_ID_CODE)) { + case OMAP4470_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP4470_ES1_0; + break; case OMAP4460_CONTROL_ID_CODE_ES1_1: *omap_si_rev = OMAP4460_ES1_1; break; diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index d76dde7..67a7926 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -60,6 +60,20 @@ static const struct emif_regs emif_regs_elpida_380_mhz_1cs = { .emif_ddr_phy_ctlr_1 = 0x049ff418 }; +const struct emif_regs emif_regs_elpida_400_mhz_1cs = { + .sdram_config_init = 0x80800eb2, + .sdram_config = 0x80801ab2, + .ref_ctrl = 0x00000618, + .sdram_tim1 = 0x10eb0662, + .sdram_tim2 = 0x20370dd2, + .sdram_tim3 = 0x00b1c33f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3215, + .temp_alert_config = 0x58016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + const struct emif_regs emif_regs_elpida_400_mhz_2cs = { .sdram_config_init = 0x80000eb9, .sdram_config = 0x80001ab9, @@ -107,8 +121,10 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_elpida_380_mhz_1cs; else if (omap4_rev == OMAP4430_ES2_0) *regs = &emif_regs_elpida_200_mhz_2cs; - else + else if (omap4_rev < OMAP4470_ES1_0) *regs = &emif_regs_elpida_400_mhz_2cs; + else + *regs = &emif_regs_elpida_400_mhz_1cs; } void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) __attribute__((weak, alias("emif_get_reg_dump_sdp"))); @@ -138,20 +154,31 @@ static const struct lpddr2_device_details elpida_2G_S4_details = { .manufacturer = LPDDR2_MANUFACTURER_ELPIDA }; +static const struct lpddr2_device_details elpida_4G_S4_details = { + .type = LPDDR2_TYPE_S4, + .density = LPDDR2_DENSITY_4Gb, + .io_width = LPDDR2_IO_WIDTH_32, + .manufacturer = LPDDR2_MANUFACTURER_ELPIDA +}; + struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs, struct lpddr2_device_details *lpddr2_dev_details) { u32 omap_rev = omap_revision(); /* EMIF1 & EMIF2 have identical configuration */ - if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) { - /* Nothing connected on CS1 for ES1.0 */ + if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) + && (cs == CS1)) { + /* Nothing connected on CS1 for 4430/4470 ES1.0 */ return NULL; - } else { - /* In all other cases Elpida 2G device */ + } else if (omap_rev < OMAP4470_ES1_0) { + /* In all other 4430/4460 cases Elpida 2G device */ *lpddr2_dev_details = elpida_2G_S4_details; - return lpddr2_dev_details; + } else { + /* 4470: 4G device */ + *lpddr2_dev_details = elpida_4G_S4_details; } + return lpddr2_dev_details; } struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, @@ -265,7 +292,7 @@ void emif_get_device_timings_sdp(u32 emif_nr, /* Identical devices on EMIF1 & EMIF2 */ *cs0_device_timings = &elpida_2G_S4_timings; - if (omap_rev == OMAP4430_ES1_0) + if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) *cs1_device_timings = NULL; else *cs1_device_timings = &elpida_2G_S4_timings; diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 10b56e0..73e6db8 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -46,6 +46,26 @@ #define PRM_RSTCTRL_RESET 0x01 #define PRM_RSTST_WARM_RESET_MASK 0x232 +/* + * Watchdog: + * Using the prescaler, the OMAP watchdog could go for many + * months before firing. These limits work without scaling, + * with the 60 second default assumed by most tools and docs. + */ +#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */ +#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */ +#define TIMER_MARGIN_MIN 1 + +#define PTV 0 /* prescale */ +#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1) +#define WDT_WWPS_PEND_WCLR BIT(0) +#define WDT_WWPS_PEND_WLDR BIT(2) +#define WDT_WWPS_PEND_WTGR BIT(3) +#define WDT_WWPS_PEND_WSPR BIT(4) + +#define WDT_WCLR_PRE BIT(5) +#define WDT_WCLR_PTV_OFF 2 + #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct gpmc_cs { @@ -193,7 +213,8 @@ struct cm_perpll { unsigned int dcan1clkctrl; /* offset 0xC4 */ unsigned int resv6[2]; unsigned int emiffwclkctrl; /* offset 0xD0 */ - unsigned int resv7[2]; + unsigned int epwmss0clkctrl; /* offset 0xD4 */ + unsigned int epwmss2clkctrl; /* offset 0xD8 */ unsigned int l3instrclkctrl; /* offset 0xDC */ unsigned int l3clkctrl; /* Offset 0xE0 */ unsigned int resv8[4]; @@ -204,6 +225,7 @@ struct cm_perpll { unsigned int l4hsclkctrl; /* offset 0x120 */ unsigned int resv10[8]; unsigned int cpswclkstctrl; /* offset 0x144 */ + unsigned int lcdcclkstctrl; /* offset 0x148 */ }; #else /* Encapsulating core pll registers */ @@ -366,6 +388,8 @@ struct cm_perpll { struct cm_dpll { unsigned int resv1[2]; unsigned int clktimer2clk; /* offset 0x08 */ + unsigned int resv2[10]; + unsigned int clklcdcpixelclk; /* offset 0x34 */ }; /* Control Module RTC registers */ @@ -486,6 +510,54 @@ struct ctrl_dev { unsigned int resv4[4]; unsigned int miisel; /* offset 0x50 */ }; + +/* gmii_sel register defines */ +#define GMII1_SEL_MII 0x0 +#define GMII1_SEL_RMII 0x1 +#define GMII1_SEL_RGMII 0x2 +#define GMII2_SEL_MII 0x0 +#define GMII2_SEL_RMII 0x4 +#define GMII2_SEL_RGMII 0x8 +#define RGMII1_IDMODE BIT(4) +#define RGMII2_IDMODE BIT(5) +#define RMII1_IO_CLK_EN BIT(6) +#define RMII2_IO_CLK_EN BIT(7) + +#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) +#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) +#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) +#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE) +#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN) + +/* PWMSS */ +struct pwmss_regs { + unsigned int idver; + unsigned int sysconfig; + unsigned int clkconfig; + unsigned int clkstatus; +}; +#define ECAP_CLK_EN BIT(0) +#define ECAP_CLK_STOP_REQ BIT(1) + +struct pwmss_ecap_regs { + unsigned int tsctr; + unsigned int ctrphs; + unsigned int cap1; + unsigned int cap2; + unsigned int cap3; + unsigned int cap4; + unsigned int resv1[4]; + unsigned short ecctl1; + unsigned short ecctl2; +}; + +/* Capture Control register 2 */ +#define ECTRL2_SYNCOSEL_MASK (0x03 << 6) +#define ECTRL2_MDSL_ECAP BIT(9) +#define ECTRL2_CTRSTP_FREERUN BIT(4) +#define ECTRL2_PLSL_LOW BIT(10) +#define ECTRL2_SYNC_EN BIT(5) + #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index 8973fd8..e4231c8 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -58,4 +58,11 @@ #define USB0_OTG_BASE 0x47401000 #define USB1_OTG_BASE 0x47401800 +/* LCD Controller */ +#define LCD_CNTL_BASE 0x4830E000 + +/* PWMSS */ +#define PWMSS0_BASE 0x48300000 +#define AM33XX_ECAP0_BASE 0x48300100 + #endif /* __AM33XX_HARDWARE_AM33XX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 1f84311..2250721 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -18,7 +18,7 @@ #ifdef CONFIG_AM33XX #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40310000 -#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000 +#define SRAM_SCRATCH_SPACE_ADDR 0x4030B800 #elif defined(CONFIG_TI81XX) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 diff --git a/arch/arm/include/asm/arch-mx6/hab.h b/arch/arm/include/asm/arch-mx6/hab.h new file mode 100644 index 0000000..d724f20 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/hab.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + * +*/ + +#ifndef __SECURE_MX6Q_H__ +#define __SECURE_MX6Q_H__ + +#include <linux/types.h> + +/* -------- start of HAB API updates ------------*/ +/* The following are taken from HAB4 SIS */ + +/* Status definitions */ +enum hab_status { + HAB_STS_ANY = 0x00, + HAB_FAILURE = 0x33, + HAB_WARNING = 0x69, + HAB_SUCCESS = 0xf0 +}; + +/* Security Configuration definitions */ +enum hab_config { + HAB_CFG_RETURN = 0x33, /**< Field Return IC */ + HAB_CFG_OPEN = 0xf0, /**< Non-secure IC */ + HAB_CFG_CLOSED = 0xcc /**< Secure IC */ +}; + +/* State definitions */ +enum hab_state { + HAB_STATE_INITIAL = 0x33, /**< Initialising state (transitory) */ + HAB_STATE_CHECK = 0x55, /**< Check state (non-secure) */ + HAB_STATE_NONSECURE = 0x66, /**< Non-secure state */ + HAB_STATE_TRUSTED = 0x99, /**< Trusted state */ + HAB_STATE_SECURE = 0xaa, /**< Secure state */ + HAB_STATE_FAIL_SOFT = 0xcc, /**< Soft fail state */ + HAB_STATE_FAIL_HARD = 0xff, /**< Hard fail state (terminal) */ + HAB_STATE_NONE = 0xf0, /**< No security state machine */ + HAB_STATE_MAX +}; + +/*Function prototype description*/ +typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t, + uint8_t* , size_t*); +typedef enum hab_status hab_rvt_report_status_t(enum hab_config *, + enum hab_state *); +typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*); +typedef enum hab_status hab_rvt_entry_t(void); +typedef enum hab_status hab_rvt_exit_t(void); +typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t, + void **, size_t *, hab_loader_callback_f_t); +typedef void hapi_clock_init_t(void); + +#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4) +#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8) +#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4) +#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098) +#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C) +#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D) + +#define HAB_CID_ROM 0 /**< ROM Caller ID */ +#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/ +/* ----------- end of HAB API updates ------------*/ + +#endif diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5d6bccb..7ef7152 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -456,7 +456,13 @@ struct fuse_bank0_regs { u32 uid_low; u32 rsvd1[3]; u32 uid_high; - u32 rsvd2[0x17]; + u32 rsvd2[3]; + u32 rsvd3[4]; + u32 rsvd4[4]; + u32 rsvd5[4]; + u32 cfg5; + u32 rsvd6[3]; + u32 rsvd7[4]; }; struct fuse_bank4_regs { @@ -629,29 +635,12 @@ struct anatop_regs { u32 digprog_sololite; /* 0x280 */ }; -#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0 -#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT) -#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6 -#define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT) -#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7 -#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT) -#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8 -#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT) -#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14 -#define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT) -#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15 -#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT) -#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16 -#define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT) -#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22 -#define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT) -#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23 -#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT) -#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24 -#define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT) -#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30 -#define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT) -#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31 +#define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8) +#define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n)) +#define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8)) +#define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n)) +#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8)) +#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n)) struct iomuxc_base_regs { u32 gpr[14]; /* 0x000 */ diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index bfdfd29..8c21364 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -19,6 +19,13 @@ #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); + +/* returns MXC_CPU_ value */ +#define cpu_type(rev) (((rev) >> 12)&0xff) + +/* use with MXC_CPU_ constants */ +#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu) + const char *get_imx_type(u32 imxtype); unsigned imx_ddr_size(void); diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h b/arch/arm/include/asm/arch-mxs/regs-uartapp.h new file mode 100644 index 0000000..7ceb810 --- /dev/null +++ b/arch/arm/include/asm/arch-mxs/regs-uartapp.h @@ -0,0 +1,220 @@ +/* + * Freescale MXS UARTAPP Register Definitions + * + * Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com> + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_ARM___MXS_UARTAPP_H +#define __ARCH_ARM___MXS_UARTAPP_H + +#include <asm/imx-common/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mxs_uartapp_regs { + mxs_reg_32(hw_uartapp_ctrl0) + mxs_reg_32(hw_uartapp_ctrl1) + mxs_reg_32(hw_uartapp_ctrl2) + mxs_reg_32(hw_uartapp_linectrl) + mxs_reg_32(hw_uartapp_linectrl2) + mxs_reg_32(hw_uartapp_intr) + mxs_reg_32(hw_uartapp_data) + mxs_reg_32(hw_uartapp_stat) + mxs_reg_32(hw_uartapp_debug) + mxs_reg_32(hw_uartapp_version) + mxs_reg_32(hw_uartapp_autobaud) +}; +#endif + +#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31) +#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30) +#define UARTAPP_CTRL0_RUN_MASK (1 << 29) +#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28) +#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27) +#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16 +#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16) +#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0 +#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF + +#define UARTAPP_CTRL1_RUN_MASK (1 << 28) + +#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0 +#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF + +#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31) +#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30) +#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29) +#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28) +#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27) +#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26) +#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25) +#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24) +#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20 +#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20) + +#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20) +#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20) +#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16 +#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16) +#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16) +#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15) +#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14) +#define UARTAPP_CTRL2_OUT2_MASK (1 << 13) +#define UARTAPP_CTRL2_OUT1_MASK (1 << 12) +#define UARTAPP_CTRL2_RTS_MASK (1 << 11) +#define UARTAPP_CTRL2_DTR_MASK (1 << 10) +#define UARTAPP_CTRL2_RXE_MASK (1 << 9) +#define UARTAPP_CTRL2_TXE_MASK (1 << 8) +#define UARTAPP_CTRL2_LBE_MASK (1 << 7) +#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6) + +#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2) +#define UARTAPP_CTRL2_SIREN_MASK (1 << 1) +#define UARTAPP_CTRL2_UARTEN_MASK 0x01 + +#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16 +#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16) +#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6 + +#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8 +#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8) +#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F + +#define UARTAPP_LINECTRL_SPS_MASK (1 << 7) +#define UARTAPP_LINECTRL_WLEN_OFFSET 5 +#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5) +#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5) +#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5) +#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5) +#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5) + +#define UARTAPP_LINECTRL_FEN_MASK (1 << 4) +#define UARTAPP_LINECTRL_STP2_MASK (1 << 3) +#define UARTAPP_LINECTRL_EPS_MASK (1 << 2) +#define UARTAPP_LINECTRL_PEN_MASK (1 << 1) +#define UARTAPP_LINECTRL_BRK_MASK 1 + +#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16 +#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16) +#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6 + +#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8 +#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8) +#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F + +#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7) +#define UARTAPP_LINECTRL2_WLEN_OFFSET 5 +#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5) +#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5) +#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5) +#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5) +#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5) + +#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4) +#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3) +#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2) +#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1) + +#define UARTAPP_INTR_ABDIEN_MASK (1 << 27) +#define UARTAPP_INTR_OEIEN_MASK (1 << 26) +#define UARTAPP_INTR_BEIEN_MASK (1 << 25) +#define UARTAPP_INTR_PEIEN_MASK (1 << 24) +#define UARTAPP_INTR_FEIEN_MASK (1 << 23) +#define UARTAPP_INTR_RTIEN_MASK (1 << 22) +#define UARTAPP_INTR_TXIEN_MASK (1 << 21) +#define UARTAPP_INTR_RXIEN_MASK (1 << 20) +#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19) +#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18) +#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17) +#define UARTAPP_INTR_RIMIEN_MASK (1 << 16) + +#define UARTAPP_INTR_ABDIS_MASK (1 << 11) +#define UARTAPP_INTR_OEIS_MASK (1 << 10) +#define UARTAPP_INTR_BEIS_MASK (1 << 9) +#define UARTAPP_INTR_PEIS_MASK (1 << 8) +#define UARTAPP_INTR_FEIS_MASK (1 << 7) +#define UARTAPP_INTR_RTIS_MASK (1 << 6) +#define UARTAPP_INTR_TXIS_MASK (1 << 5) +#define UARTAPP_INTR_RXIS_MASK (1 << 4) +#define UARTAPP_INTR_DSRMIS_MASK (1 << 3) +#define UARTAPP_INTR_DCDMIS_MASK (1 << 2) +#define UARTAPP_INTR_CTSMIS_MASK (1 << 1) +#define UARTAPP_INTR_RIMIS_MASK 0x1 + +#define UARTAPP_DATA_DATA_OFFSET 0 +#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF +#define UARTAPP_STAT_PRESENT_MASK (1 << 31) +#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31) +#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31) + +#define UARTAPP_STAT_HISPEED_MASK (1 << 30) +#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30) +#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30) + +#define UARTAPP_STAT_BUSY_MASK (1 << 29) +#define UARTAPP_STAT_CTS_MASK (1 << 28) +#define UARTAPP_STAT_TXFE_MASK (1 << 27) +#define UARTAPP_STAT_RXFF_MASK (1 << 26) +#define UARTAPP_STAT_TXFF_MASK (1 << 25) +#define UARTAPP_STAT_RXFE_MASK (1 << 24) +#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20 +#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20) + +#define UARTAPP_STAT_OERR_MASK (1 << 19) +#define UARTAPP_STAT_BERR_MASK (1 << 18) +#define UARTAPP_STAT_PERR_MASK (1 << 17) +#define UARTAPP_STAT_FERR_MASK (1 << 16) +#define UARTAPP_STAT_RXCOUNT_OFFSET 0 +#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF + +#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16 +#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16) + +#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10 +#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10) + +#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5) +#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4) +#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3) +#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2) +#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1) +#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01 + +#define UARTAPP_VERSION_MAJOR_OFFSET 24 +#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24) + +#define UARTAPP_VERSION_MINOR_OFFSET 16 +#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16) + +#define UARTAPP_VERSION_STEP_OFFSET 0 +#define UARTAPP_VERSION_STEP_MASK 0xFFFF + +#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24 +#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24) + +#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16 +#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16) + +#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4) +#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3) +#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2) +#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1) +#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01 +#endif /* __ARCH_ARM___UARTAPP_H */ diff --git a/arch/arm/include/asm/arch-omap3/clock.h b/arch/arm/include/asm/arch-omap3/clock.h index 514839c..be669c1 100644 --- a/arch/arm/include/asm/arch-omap3/clock.h +++ b/arch/arm/include/asm/arch-omap3/clock.h @@ -63,6 +63,4 @@ extern dpll_param *get_36x_core_dpll_param(void); extern dpll_param *get_36x_per_dpll_param(void); extern dpll_param *get_36x_per2_dpll_param(void); -extern void *_end_vect, *_start; - #endif diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h index b2e03d6..f3a682a 100644 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -149,11 +149,16 @@ /* PRM_VC_VAL_BYPASS */ #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 -/* SMPS */ +/* PMIC */ #define SMPS_I2C_SLAVE_ADDR 0x12 +/* TWL6030 SMPS */ #define SMPS_REG_ADDR_VCORE1 0x55 #define SMPS_REG_ADDR_VCORE2 0x5B #define SMPS_REG_ADDR_VCORE3 0x61 +/* TWL6032 SMPS */ +#define SMPS_REG_ADDR_SMPS1 0x55 +#define SMPS_REG_ADDR_SMPS2 0x5B +#define SMPS_REG_ADDR_SMPS5 0x49 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 3823a37..9129c0d 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -41,6 +41,7 @@ #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F +#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F /* UART */ #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 597c692..e9a51d3 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -153,6 +153,15 @@ struct s32ktimer { #define EFUSE_4 0x45145100 #endif /* __ASSEMBLY__ */ +/* + * In all cases, the TRM defines the RAM Memory Map for the processor + * and indicates the area for the downloaded image. We use all of that + * space for download and once up and running may use other parts of the + * map for our needs. We set a scratch space that is at the end of the + * OMAP5 download area, but within the DRA7xx download area (as it is + * much larger) and do not, at this time, make use of the additional + * space. + */ #ifdef CONFIG_DRA7XX #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ @@ -160,7 +169,7 @@ struct s32ktimer { #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ #endif -#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START +#define SRAM_SCRATCH_SPACE_ADDR 0x4031E000 /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4031F000 diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 66f416f..5e2f027 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -622,6 +622,7 @@ static inline u8 is_omap54xx(void) #define OMAP4430_ES2_3 0x44300230 #define OMAP4460_ES1_0 0x44600100 #define OMAP4460_ES1_1 0x44600110 +#define OMAP4470_ES1_0 0x44700100 /* omap5 */ #define OMAP5430_SILICON_ID_INVALID 0 |