21 files changed, 156 insertions, 189 deletions

diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile
index a4934ef..98991c6 100644
--- a/arch/powerpc/cpu/mpc512x/Makefile
+++ b/arch/powerpc/cpu/mpc512x/Makefile
@@ -17,6 +17,3 @@ obj-y += speed.o
 obj-$(CONFIG_FSL_DIU_FB) += diu.o
 obj-$(CONFIG_CMD_IDE) += ide.o
 obj-$(CONFIG_PCI) += pci.o
-
-# Stub implementations of cache management functions for USB
-obj-$(CONFIG_USB_EHCI) += cache.o
diff --git a/arch/powerpc/cpu/mpc512x/cache.c b/arch/powerpc/cpu/mpc512x/cache.c
deleted file mode 100644
index 66384f9..0000000
--- a/arch/powerpc/cpu/mpc512x/cache.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (C) 2012 Marek Vasut <marex@denx.de>
- *
- * This file contains stub implementation of
- *   invalidate_dcache_range()
- *   flush_dcache_range()
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
diff --git a/arch/powerpc/cpu/mpc5xxx/Makefile b/arch/powerpc/cpu/mpc5xxx/Makefile
index d122b29..5c67e1d 100644
--- a/arch/powerpc/cpu/mpc5xxx/Makefile
+++ b/arch/powerpc/cpu/mpc5xxx/Makefile
@@ -7,7 +7,6 @@
 
 extra-y	= start.o
 extra-y += traps.o
-obj-y  += cache.o
 obj-y  += io.o
 obj-y  += firmware_sc_task_bestcomm.impl.o
 obj-y += i2c.o
diff --git a/arch/powerpc/cpu/mpc5xxx/cache.c b/arch/powerpc/cpu/mpc5xxx/cache.c
deleted file mode 100644
index 5d674bc..0000000
--- a/arch/powerpc/cpu/mpc5xxx/cache.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This file contains stub implementation of
- *   invalidate_dcache_range()
- *   flush_dcache_range()
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index cf91162..a93cf13 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -35,9 +35,6 @@ obj-$(CONFIG_PCI) += pci.o
 obj-$(CONFIG_PCIE) += pcie.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 
-# Stub implementations of cache management functions for USB
-obj-y += cache.o
-
 ifndef CONFIG_SYS_FSL_DDRC_GEN2
 obj-y += spd_sdram.o
 endif
diff --git a/arch/powerpc/cpu/mpc83xx/cache.c b/arch/powerpc/cpu/mpc83xx/cache.c
deleted file mode 100644
index 66384f9..0000000
--- a/arch/powerpc/cpu/mpc83xx/cache.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (C) 2012 Marek Vasut <marex@denx.de>
- *
- * This file contains stub implementation of
- *   invalidate_dcache_range()
- *   flush_dcache_range()
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index adb5bd3..aff5fdb 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -122,15 +122,13 @@ config TARGET_T208XRDB
 	bool "Support T208xRDB"
 	select SUPPORT_SPL
 
-config TARGET_T4240EMU
-	bool "Support T4240EMU"
-
 config TARGET_T4240QDS
 	bool "Support T4240QDS"
 	select SUPPORT_SPL
 
 config TARGET_T4240RDB
 	bool "Support T4240RDB"
+	select SUPPORT_SPL
 
 config TARGET_CONTROLCENTERD
 	bool "Support controlcenterd"
@@ -153,6 +151,9 @@ config TARGET_XPEDITE537X
 config TARGET_XPEDITE550X
 	bool "Support xpedite550x"
 
+config TARGET_UCP1020
+	bool "Support uCP1020"
+
 endchoice
 
 source "board/freescale/b4860qds/Kconfig"
@@ -194,5 +195,6 @@ source "board/stx/stxssa/Kconfig"
 source "board/xes/xpedite520x/Kconfig"
 source "board/xes/xpedite537x/Kconfig"
 source "board/xes/xpedite550x/Kconfig"
+source "board/Arcturus/ucp1020/Kconfig"
 
 endmenu
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index b93158b..65c26c0 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -114,7 +114,4 @@ endif
 obj-y	+= tlb.o
 obj-y	+= traps.o
 
-# Stub implementations of cache management functions for USB
-obj-y += cache.o
-
 endif # not minimal
diff --git a/arch/powerpc/cpu/mpc85xx/cache.c b/arch/powerpc/cpu/mpc85xx/cache.c
deleted file mode 100644
index 66384f9..0000000
--- a/arch/powerpc/cpu/mpc85xx/cache.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (C) 2012 Marek Vasut <marex@denx.de>
- *
- * This file contains stub implementation of
- *   invalidate_dcache_range()
- *   flush_dcache_range()
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 2d5ddf0..b368562 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -299,6 +299,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (has_erratum_a007798())
 		puts("Work-around for Erratum A007798 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004477
+	if (has_erratum_a004477())
+		puts("Work-around for Erratum A004477 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 	if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
 	    (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index ec3b292..3777c6f 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -249,8 +249,13 @@ void fdt_fixup_qportals(void *blob)
 #ifdef CONFIG_FSL_CORENET
 		u32 liodns[2];
 #endif
-		const int *ci = fdt_getprop(blob, off, "cell-index", NULL);
-		int i = *ci;
+		const int *ci = fdt_getprop(blob, off, "cell-index", &err);
+		int i;
+
+		if (!ci)
+			goto err;
+
+		i = *ci;
 #ifdef CONFIG_SYS_DPAA_FMAN
 		int j;
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 321ade2..d954fe2 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -73,7 +73,8 @@ void get_sys_info(sys_info_t *sys_info)
 		[14] = 4,	/* CC4 PPL / 4 */
 	};
 	uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
-#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
+#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \
+	defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
 	uint rcw_tmp;
 #endif
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
@@ -453,6 +454,48 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 #endif
 
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+#if defined(CONFIG_PPC_T2080)
+#define ESDHC_CLK_SEL	0x00000007
+#define ESDHC_CLK_SHIFT	0
+#define ESDHC_CLK_RCWSR	15
+#else	/* Support T1040 T1024 by now */
+#define ESDHC_CLK_SEL	0xe0000000
+#define ESDHC_CLK_SHIFT	29
+#define ESDHC_CLK_RCWSR	7
+#endif
+	rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]);
+	switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) {
+	case 1:
+		sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK];
+		break;
+	case 2:
+		sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2;
+		break;
+	case 3:
+		sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3;
+		break;
+#if defined(CONFIG_SYS_SDHC_CLK_2_PLL)
+	case 4:
+		sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
+		break;
+#if defined(CONFIG_PPC_T2080)
+	case 5:
+		sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
+		break;
+#endif
+	case 6:
+		sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2;
+		break;
+	case 7:
+		sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3;
+		break;
+#endif
+	default:
+		sys_info->freq_sdhc = 0;
+		printf("Error: Unknown SDHC peripheral clock select!\n");
+	}
+#endif
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
 	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
@@ -660,12 +703,16 @@ int get_clocks (void)
 	gd->arch.i2c2_clk = gd->arch.i2c1_clk;
 
 #if defined(CONFIG_FSL_ESDHC)
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+	gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
+#else
 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
        defined(CONFIG_P1014)
 	gd->arch.sdhc_clk = gd->bus_clk;
 #else
 	gd->arch.sdhc_clk = gd->bus_clk / 2;
 #endif
+#endif
 #endif /* defined(CONFIG_FSL_ESDHC) */
 
 #if defined(CONFIG_CPM2)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 28f04ee..e61d8e0 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1664,41 +1664,46 @@ clear_bss:
 	 */
 	.globl	trap_init
 trap_init:
+	mflr	r11
+	bl	_GLOBAL_OFFSET_TABLE_-4
+	mflr	r12
+
 	/* Update IVORs as per relocation */
 	mtspr	IVPR,r3
 
-	li	r4,CriticalInput@l
+	lwz	r4,CriticalInput@got(r12)
 	mtspr	IVOR0,r4	/* 0: Critical input */
-	li	r4,MachineCheck@l
+	lwz	r4,MachineCheck@got(r12)
 	mtspr	IVOR1,r4	/* 1: Machine check */
-	li	r4,DataStorage@l
+	lwz	r4,DataStorage@got(r12)
 	mtspr	IVOR2,r4	/* 2: Data storage */
-	li	r4,InstStorage@l
+	lwz	r4,InstStorage@got(r12)
 	mtspr	IVOR3,r4	/* 3: Instruction storage */
-	li	r4,ExtInterrupt@l
+	lwz	r4,ExtInterrupt@got(r12)
 	mtspr	IVOR4,r4	/* 4: External interrupt */
-	li	r4,Alignment@l
+	lwz	r4,Alignment@got(r12)
 	mtspr	IVOR5,r4	/* 5: Alignment */
-	li	r4,ProgramCheck@l
+	lwz	r4,ProgramCheck@got(r12)
 	mtspr	IVOR6,r4	/* 6: Program check */
-	li	r4,FPUnavailable@l
+	lwz	r4,FPUnavailable@got(r12)
 	mtspr	IVOR7,r4	/* 7: floating point unavailable */
-	li	r4,SystemCall@l
+	lwz	r4,SystemCall@got(r12)
 	mtspr	IVOR8,r4	/* 8: System call */
 	/* 9: Auxiliary processor unavailable(unsupported) */
-	li	r4,Decrementer@l
+	lwz	r4,Decrementer@got(r12)
 	mtspr	IVOR10,r4	/* 10: Decrementer */
-	li	r4,IntervalTimer@l
+	lwz	r4,IntervalTimer@got(r12)
 	mtspr	IVOR11,r4	/* 11: Interval timer */
-	li	r4,WatchdogTimer@l
+	lwz	r4,WatchdogTimer@got(r12)
 	mtspr	IVOR12,r4	/* 12: Watchdog timer */
-	li	r4,DataTLBError@l
+	lwz	r4,DataTLBError@got(r12)
 	mtspr	IVOR13,r4	/* 13: Data TLB error */
-	li	r4,InstructionTLBError@l
+	lwz	r4,InstructionTLBError@got(r12)
 	mtspr	IVOR14,r4	/* 14: Instruction TLB error */
-	li	r4,DebugBreakpoint@l
+	lwz	r4,DebugBreakpoint@got(r12)
 	mtspr	IVOR15,r4	/* 15: Debug */
 
+	mtlr	r11
 	blr
 
 .globl unlock_ram_in_cache
diff --git a/arch/powerpc/cpu/mpc86xx/cache.S b/arch/powerpc/cpu/mpc86xx/cache.S
index 536d9b9..34968c6 100644
--- a/arch/powerpc/cpu/mpc86xx/cache.S
+++ b/arch/powerpc/cpu/mpc86xx/cache.S
@@ -115,51 +115,6 @@ _GLOBAL(clean_dcache_range)
 	blr
 
 /*
- * Write any modified data cache blocks out to memory
- * and invalidate the corresponding instruction cache blocks.
- *
- * flush_dcache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(flush_dcache_range)
-	li	r5,CACHE_LINE_SIZE-1
-	andc	r3,r3,r5
-	subf	r4,r3,r4
-	add	r4,r4,r5
-	srwi.	r4,r4,LG_CACHE_LINE_SIZE
-	beqlr
-	mtctr	r4
-
-	sync
-1:	dcbf	0,r3
-	addi	r3,r3,CACHE_LINE_SIZE
-	bdnz	1b
-	sync				/* wait for dcbf's to get to ram */
-	blr
-
-/*
- * Like above, but invalidate the D-cache.  This is used by the 8xx
- * to invalidate the cache so the PPC core doesn't get stale data
- * from the CPM (no cache snooping here :-).
- *
- * invalidate_dcache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(invalidate_dcache_range)
-	li	r5,CACHE_LINE_SIZE-1
-	andc	r3,r3,r5
-	subf	r4,r3,r4
-	add	r4,r4,r5
-	srwi.	r4,r4,LG_CACHE_LINE_SIZE
-	beqlr
-	mtctr	r4
-
-	sync
-1:	dcbi	0,r3
-	addi	r3,r3,CACHE_LINE_SIZE
-	bdnz	1b
-	sync				/* wait for dcbi's to get to ram */
-	blr
-
-/*
  * Flush a particular page from the data cache to RAM.
  * Note: this is necessary because the instruction cache does *not*
  * snoop from the data cache.
diff --git a/arch/powerpc/cpu/ppc4xx/cache.S b/arch/powerpc/cpu/ppc4xx/cache.S
index 2714c2f..93e8366 100644
--- a/arch/powerpc/cpu/ppc4xx/cache.S
+++ b/arch/powerpc/cpu/ppc4xx/cache.S
@@ -74,49 +74,6 @@ _GLOBAL(clean_dcache_range)
 	blr
 
 /*
- * Write any modified data cache blocks out to memory and invalidate them.
- * Does not invalidate the corresponding instruction cache blocks.
- *
- * flush_dcache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(flush_dcache_range)
-	li	r5,L1_CACHE_BYTES-1
-	andc	r3,r3,r5
-	subf	r4,r3,r4
-	add	r4,r4,r5
-	srwi.	r4,r4,L1_CACHE_SHIFT
-	beqlr
-	mtctr	r4
-
-1:	dcbf	0,r3
-	addi	r3,r3,L1_CACHE_BYTES
-	bdnz	1b
-	sync				/* wait for dcbst's to get to ram */
-	blr
-
-/*
- * Like above, but invalidate the D-cache.  This is used by the 8xx
- * to invalidate the cache so the PPC core doesn't get stale data
- * from the CPM (no cache snooping here :-).
- *
- * invalidate_dcache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(invalidate_dcache_range)
-	li	r5,L1_CACHE_BYTES-1
-	andc	r3,r3,r5
-	subf	r4,r3,r4
-	add	r4,r4,r5
-	srwi.	r4,r4,L1_CACHE_SHIFT
-	beqlr
-	mtctr	r4
-
-1:	dcbi	0,r3
-	addi	r3,r3,L1_CACHE_BYTES
-	bdnz	1b
-	sync				/* wait for dcbi's to get to ram */
-	blr
-
-/*
  * 40x cores have 8K or 16K dcache and 32 byte line size.
  * 44x has a 32K dcache and 32 byte line size.
  * 8xx has 1, 2, 4, 8K variants.
diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
index 8beed30..71794a8 100644
--- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -12,4 +12,6 @@
 #ifndef __ASM_ARCH_MX85XX_GPIO_H
 #define __ASM_ARCH_MX85XX_GPIO_H
 
+#include <asm/mpc85xx_gpio.h>
+
 #endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 69e0592..9d56bc1 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -163,6 +163,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A007075
 #define CONFIG_SYS_FSL_ERRATUM_A006261
+#define CONFIG_SYS_FSL_ERRATUM_A004477
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x10
 #define CONFIG_ESDHC_HC_BLK_ADDR
 
@@ -294,6 +295,7 @@
 #define CONFIG_FSL_SATA_ERRATUM_A001
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A004477
 
 #elif defined(CONFIG_P1023)
 #define CONFIG_MAX_CPUS			2
@@ -374,6 +376,7 @@
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A004477
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 
 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
@@ -591,6 +594,7 @@
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_ERRATUM_A004477
 #define CONFIG_ESDHC_HC_BLK_ADDR
 
 #elif defined(CONFIG_BSC9132)
@@ -615,6 +619,7 @@
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_A005434
+#define CONFIG_SYS_FSL_ERRATUM_A004477
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x11
 #define CONFIG_ESDHC_HC_BLK_ADDR
@@ -723,6 +728,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A006475
 #define CONFIG_SYS_FSL_ERRATUM_A006384
 #define CONFIG_SYS_FSL_ERRATUM_A007212
+#define CONFIG_SYS_FSL_ERRATUM_A004477
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
@@ -769,7 +775,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #endif
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
-#define CONFIG_SYS_SDHC_CLOCK		0
 #define CONFIG_SYS_FSL_NUM_LAWS		16
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SEC_COMPAT	5
@@ -785,6 +790,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_FM_PLAT_CLK_DIV	1
 #define CONFIG_SYS_FM1_CLK		CONFIG_FM_PLAT_CLK_DIV
+#define CONFIG_SYS_SDHC_CLK		0/* Select SDHC CLK begining from PLL1
+					    per rcw field value */
+#define CONFIG_SYS_SDHC_CLK_2_PLL	/* Select SDHC CLK from 2 PLLs */
 #define CONFIG_SYS_FM_MURAM_SIZE	0x30000
 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
@@ -817,7 +825,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #endif
 #define CONFIG_SYS_FSL_NUM_CC_PLL	2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 1, 1 }
-#define CONFIG_SYS_SDHC_CLOCK		0
 #define CONFIG_SYS_FSL_NUM_LAWS		16
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SEC_COMPAT	5
@@ -830,6 +837,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_DDR_VER	 FSL_DDR_VER_5_0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_FM1_CLK		0
+#define CONFIG_SYS_SDHC_CLK		0/* Select SDHC CLK begining from PLL1
+					    per rcw field value */
 #define CONFIG_QBMAN_CLK_DIV		1
 #define CONFIG_SYS_FM_MURAM_SIZE	0x30000
 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
@@ -877,6 +886,9 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_PME_PLAT_CLK_DIV		1
 #define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
 #define CONFIG_SYS_FM1_CLK		0
+#define CONFIG_SYS_SDHC_CLK		1/* Select SDHC CLK begining from PLL2
+					    per rcw field value */
+#define CONFIG_SYS_SDHC_CLK_2_PLL	/* Select SDHC CLK from 2 PLLs */
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_FMAN_V3
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index 5be718b..8bee8ca 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -19,6 +19,7 @@
 #define FSL_PCI_PBFR		0x44
 
 #define FSL_PCIE_CFG_RDY	0x4b0
+#define FSL_PCIE_V3_CFG_RDY	0x1
 #define FSL_PROG_IF_AGENT	0x1
 
 #define PCI_LTSSM	0x404   /* PCIe Link Training, Status State Machine */
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index c57d9c0..4090975 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -15,6 +15,9 @@
 struct arch_global_data {
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
+#if defined(CONFIG_FSL_ESDHC_ADAPTER_IDENT)
+	u8 sdhc_adapter;
+#endif
 #endif
 #if defined(CONFIG_8xx)
 	unsigned long brg_clk;
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h
index 87bb4a0..1d0dad4 100644
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -72,9 +72,10 @@ static inline int gpio_request(unsigned gpio, const char *label)
 	return 0;
 }
 
-static inline void gpio_free(unsigned gpio)
+static inline int gpio_free(unsigned gpio)
 {
 	/* Compatibility shim */
+	return 0;
 }
 
 static inline int gpio_direction_input(unsigned gpio)
@@ -97,12 +98,13 @@ static inline int gpio_get_value(unsigned gpio)
 	return !!mpc85xx_gpio_get(1U << gpio);
 }
 
-static inline void gpio_set_value(unsigned gpio, int value)
+static inline int gpio_set_value(unsigned gpio, int value)
 {
 	if (value)
 		mpc85xx_gpio_set_high(1U << gpio);
 	else
 		mpc85xx_gpio_set_low(1U << gpio);
+	return 0;
 }
 
 static inline int gpio_is_valid(int gpio)
diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S
index 349a1c1..b96dbc6 100644
--- a/arch/powerpc/lib/ppccache.S
+++ b/arch/powerpc/lib/ppccache.S
@@ -9,6 +9,9 @@
 
 #include <config.h>
 #include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
 
 /*------------------------------------------------------------------------------- */
 /* Function:	 ppcDcbf */
@@ -54,3 +57,48 @@ ppcDcbz:
 ppcSync:
 	sync
 	blr
+
+/*
+ * Write any modified data cache blocks out to memory and invalidate them.
+ * Does not invalidate the corresponding instruction cache blocks.
+ *
+ * flush_dcache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(flush_dcache_range)
+	li	r5,L1_CACHE_BYTES-1
+	andc	r3,r3,r5
+	subf	r4,r3,r4
+	add	r4,r4,r5
+	srwi.	r4,r4,L1_CACHE_SHIFT
+	beqlr
+	mtctr	r4
+
+1:	dcbf	0,r3
+	addi	r3,r3,L1_CACHE_BYTES
+	bdnz	1b
+	sync				/* wait for dcbst's to get to ram */
+	blr
+
+/*
+ * Like above, but invalidate the D-cache.  This is used by the 8xx
+ * to invalidate the cache so the PPC core doesn't get stale data
+ * from the CPM (no cache snooping here :-).
+ *
+ * invalidate_dcache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(invalidate_dcache_range)
+	li	r5,L1_CACHE_BYTES-1
+	andc	r3,r3,r5
+	subf	r4,r3,r4
+	add	r4,r4,r5
+	srwi.	r4,r4,L1_CACHE_SHIFT
+	beqlr
+	mtctr	r4
+
+	sync
+1:	dcbi	0,r3
+	addi	r3,r3,L1_CACHE_BYTES
+	bdnz	1b
+	sync				/* wait for dcbi's to get to ram */
+	blr
+