diff options
Diffstat (limited to 'arch')
223 files changed, 3583 insertions, 1503 deletions
diff --git a/arch/arc/config.mk b/arch/arc/config.mk index 7c974f0..13676bd 100644 --- a/arch/arc/config.mk +++ b/arch/arc/config.mk @@ -31,15 +31,15 @@ CONFIG_MMU = 1 endif ifdef CONFIG_CPU_ARC750D -PLATFORM_CPPFLAGS += -marc700 +PLATFORM_CPPFLAGS += -mcpu=arc700 endif ifdef CONFIG_CPU_ARC770D -PLATFORM_CPPFLAGS += -marc700 -mlock -mswape +PLATFORM_CPPFLAGS += -mcpu=arc700 -mlock -mswape endif ifdef CONFIG_CPU_ARCEM6 -PLATFORM_CPPFLAGS += -marcem +PLATFORM_CPPFLAGS += -mcpu=arcem endif ifdef CONFIG_CPU_ARCHS34 diff --git a/arch/arc/include/asm/errno.h b/arch/arc/include/asm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/arch/arc/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5073930..38ad590 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -890,18 +890,24 @@ config TARGET_COLIBRI_PXA270 config ARCH_UNIPHIER bool "Socionext UniPhier SoCs" + select BLK select CLK_UNIPHIER - select SUPPORT_SPL - select SPL - select OF_CONTROL - select SPL_OF_CONTROL - select OF_LIBFDT select DM - select SPL_DM select DM_GPIO - select DM_SERIAL select DM_I2C select DM_MMC + select DM_SERIAL + select DM_USB + select OF_CONTROL + select OF_LIBFDT + select PINCTRL + select SPL + select SPL_DM + select SPL_LIBCOMMON_SUPPORT + select SPL_LIBGENERIC_SUPPORT + select SPL_OF_CONTROL + select SPL_PINCTRL + select SUPPORT_SPL help Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) @@ -927,6 +933,7 @@ config ARCH_ROCKCHIP select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select DM_USB if USB config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index 068d93e..5297d62 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -10,7 +10,7 @@ #include <common.h> #include <div64.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> diff --git a/arch/arm/cpu/arm1136/mx35/mx35_sdram.c b/arch/arm/cpu/arm1136/mx35/mx35_sdram.c index d358f5f..711ea76 100644 --- a/arch/arm/cpu/arm1136/mx35/mx35_sdram.c +++ b/arch/arm/cpu/arm1136/mx35/mx35_sdram.c @@ -5,7 +5,7 @@ */ #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/imx-regs.h> #include <linux/types.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/cpu/arm920t/imx/timer.c b/arch/arm/cpu/arm920t/imx/timer.c index b62558f..178422a 100644 --- a/arch/arm/cpu/arm920t/imx/timer.c +++ b/arch/arm/cpu/arm920t/imx/timer.c @@ -78,11 +78,7 @@ unsigned long long get_ticks(void) */ ulong get_tbclk (void) { - ulong tbclk; - - tbclk = CONFIG_SYS_HZ; - - return tbclk; + return CONFIG_SYS_HZ; } /* diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index 9491096..b552e43 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -11,7 +11,7 @@ */ #include <common.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> diff --git a/arch/arm/cpu/arm926ejs/mxs/iomux.c b/arch/arm/cpu/arm926ejs/mxs/iomux.c index 2e6be06..585fa8a 100644 --- a/arch/arm/cpu/arm926ejs/mxs/iomux.c +++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c @@ -8,7 +8,7 @@ */ #include <common.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/iomux.h> diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 2298620..840dd9e 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -11,7 +11,7 @@ */ #include <common.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/imx-common/dma.h> diff --git a/arch/arm/cpu/arm926ejs/spear/timer.c b/arch/arm/cpu/arm926ejs/spear/timer.c index c88e962..89fd54f 100644 --- a/arch/arm/cpu/arm926ejs/spear/timer.c +++ b/arch/arm/cpu/arm926ejs/spear/timer.c @@ -37,7 +37,7 @@ int timer_init(void) writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg); synth = MISC_GPT3SYNTH; #else -# error Incorrect config. Can only be spear{600|300|310|320} +# error Incorrect config. Can only be SPEAR{600|300|310|320} #endif writel(readl(&misc_regs_p->periph_clk_cfg) | synth, diff --git a/arch/arm/cpu/armv7/am33xx/Kconfig b/arch/arm/cpu/armv7/am33xx/Kconfig index dc51e9b..2d7d1fc 100644 --- a/arch/arm/cpu/armv7/am33xx/Kconfig +++ b/arch/arm/cpu/armv7/am33xx/Kconfig @@ -1,4 +1,14 @@ if AM43XX + +config SPL_EXT_SUPPORT + default y + +config SPL_GPIO_SUPPORT + default y + +config SPL_I2C_SUPPORT + default y + config TARGET_AM43XX_EVM bool "Support am43xx_evm" select TI_I2C_BOARD_DETECT diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index a99cbf9..68baded 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -28,7 +28,7 @@ #include <i2c.h> #include <miiphy.h> #include <cpsw.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <linux/compiler.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index 52a6824..f42eee1 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -65,9 +65,7 @@ u32 get_device_type(void) */ u32 get_sysboot_value(void) { - int mode; - mode = readl(&cstat->statusreg) & (SYSBOOT_MASK); - return mode; + return readl(&cstat->statusreg) & SYSBOOT_MASK; } #ifdef CONFIG_DISPLAY_CPUINFO diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c index 80187e3..490bc4c 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c @@ -12,7 +12,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/sysmap.h> #include <asm/kona-common/clk.h> #include "clk-core.h" diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c index d263068..4a1cc71 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/sysmap.h> #include <asm/kona-common/clk.h> #include "clk-core.h" diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c index a326dfe..79fafa0 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.c @@ -12,7 +12,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <bitfield.h> #include <asm/arch/sysmap.h> #include <asm/kona-common/clk.h> diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c index b0b92b9..f188ef0 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/sysmap.h> #include <asm/kona-common/clk.h> #include "clk-core.h" diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c index b2ce6d6..456b767 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/sysmap.h> #include <asm/kona-common/clk.h> #include "clk-core.h" diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c index 1d7c5af..908502d 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c @@ -5,7 +5,7 @@ */ #include <common.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/sysmap.h> #include "clk-core.h" diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c index 7e25255..1c28551 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c @@ -12,7 +12,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/sysmap.h> #include <asm/kona-common/clk.h> #include "clk-core.h" diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c index ba55d0a..06a7ce8 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/sysmap.h> #include <asm/kona-common/clk.h> #include "clk-core.h" diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.c b/arch/arm/cpu/armv7/bcm281xx/clk-core.c index d442583..cdc1264 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.c @@ -12,7 +12,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <bitfield.h> #include <asm/arch/sysmap.h> #include <asm/kona-common/clk.h> diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c index b0b92b9..f188ef0 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/sysmap.h> #include <asm/kona-common/clk.h> #include "clk-core.h" diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c index 49badcb..bf47672 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/sysmap.h> #include <asm/kona-common/clk.h> #include "clk-core.h" diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c index 1d7c5af..908502d 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c @@ -5,7 +5,7 @@ */ #include <common.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/sysmap.h> #include "clk-core.h" diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c index 86ace90..8e247ee 100644 --- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c +++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c @@ -7,7 +7,7 @@ #include <common.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/immap_ls102xa.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/io.h> #include "fsl_ls1_serdes.h" diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index bf52f0d..610098c 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -9,7 +9,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c index 3753c14..e6cc7cb 100644 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -12,7 +12,7 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/io.h> #include <asm/imx-common/boot_mode.h> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index b3c9dcc..9beb6f0 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -7,7 +7,7 @@ #include <common.h> #include <div64.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> diff --git a/arch/arm/cpu/armv7/mx6/mp.c b/arch/arm/cpu/armv7/mx6/mp.c index 9f034d6..e28018b 100644 --- a/arch/arm/cpu/armv7/mx6/mp.c +++ b/arch/arm/cpu/armv7/mx6/mp.c @@ -9,7 +9,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/sys_proto.h> #include <asm/arch/imx-regs.h> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 88fcfdc..5b2a051 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -8,7 +8,7 @@ */ #include <common.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> diff --git a/arch/arm/cpu/armv7/mx7/clock.c b/arch/arm/cpu/armv7/mx7/clock.c index 4d68ad2..2cfde46 100644 --- a/arch/arm/cpu/armv7/mx7/clock.c +++ b/arch/arm/cpu/armv7/mx7/clock.c @@ -10,7 +10,7 @@ #include <common.h> #include <div64.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> diff --git a/arch/arm/cpu/armv7/mx7/clock_slice.c b/arch/arm/cpu/armv7/mx7/clock_slice.c index 1665df9..68a7005 100644 --- a/arch/arm/cpu/armv7/mx7/clock_slice.c +++ b/arch/arm/cpu/armv7/mx7/clock_slice.c @@ -10,7 +10,7 @@ #include <common.h> #include <div64.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c index b71d769..e02e3ec 100644 --- a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c +++ b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c @@ -12,7 +12,7 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include "pipe3-phy.h" /* PLLCTRL Registers */ diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 99a25f9..7d884a2 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -1,5 +1,38 @@ if OMAP34XX +config SPL_EXT_SUPPORT + default y + +config SPL_FAT_SUPPORT + default y + +config SPL_GPIO_SUPPORT + default y + +config SPL_I2C_SUPPORT + default y + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBDISK_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_MMC_SUPPORT + default y + +config SPL_NAND_SUPPORT + default y + +config SPL_POWER_SUPPORT + default y + +config SPL_SERIAL_SUPPORT + default y + choice prompt "OMAP3 board select" optional diff --git a/arch/arm/cpu/armv7/omap4/Kconfig b/arch/arm/cpu/armv7/omap4/Kconfig index 49adb8e..c3dc95f 100644 --- a/arch/arm/cpu/armv7/omap4/Kconfig +++ b/arch/arm/cpu/armv7/omap4/Kconfig @@ -1,5 +1,38 @@ if OMAP44XX +config SPL_EXT_SUPPORT + default y + +config SPL_FAT_SUPPORT + default y + +config SPL_GPIO_SUPPORT + default y + +config SPL_I2C_SUPPORT + default y + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBDISK_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_MMC_SUPPORT + default y + +config SPL_NAND_SUPPORT + default y + +config SPL_POWER_SUPPORT + default y + +config SPL_SERIAL_SUPPORT + default y + choice prompt "OMAP4 board select" optional diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index a8600b1..ef68c53 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -1,5 +1,38 @@ if OMAP54XX +config SPL_EXT_SUPPORT + default y + +config SPL_FAT_SUPPORT + default y + +config SPL_GPIO_SUPPORT + default y + +config SPL_I2C_SUPPORT + default y + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBDISK_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_MMC_SUPPORT + default y + +config SPL_NAND_SUPPORT + default y + +config SPL_POWER_SUPPORT + default y + +config SPL_SERIAL_SUPPORT + default y + choice prompt "OMAP5 board select" optional diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 5fbd848..f865373 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/system.h> #include <asm/armv8/mmu.h> #include <asm/io.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c index 29cd28e..e06b063 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 9110d7a..7faa86c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> #include <fsl-mc/ldpaa_wriop.h> diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index ed3305d..1eedb39 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -1,5 +1,29 @@ if ARCH_ZYNQMP +config SPL_FAT_SUPPORT + default y + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBDISK_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_MMC_SUPPORT + default y + +config SPL_SERIAL_SUPPORT + default y + +config SPL_SPI_FLASH_SUPPORT + default y if ZYNQ_QSPI + +config SPL_SPI_SUPPORT + default y if ZYNQ_QSPI + config SYS_BOARD default "zynqmp" @@ -23,5 +47,53 @@ config ZYNQMP_USB config SYS_MALLOC_F_LEN default 0x600 +config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED + bool "Overwrite SPL bootmode" + depends on SPL + help + Overwrite bootmode selected via boot mode pins to tell SPL what should + be the next boot device. + +config SPL_ZYNQMP_ALT_BOOTMODE + hex + default 0x0 if JTAG_MODE + default 0x1 if QSPI_MODE_24BIT + default 0x2 if QSPI_MODE_32BIT + default 0x3 if SD_MODE + default 0x4 if NAND_MODE + default 0x5 if SD_MODE1 + default 0x6 if EMMC_MODE + default 0x7 if USB_MODE + +choice + prompt "Boot mode" + depends on ZYNQMP_ALT_BOOTMODE_ENABLED + default JTAG + +config JTAG_MODE + bool "JTAG_MODE" + +config QSPI_MODE_24BIT + bool "QSPI_MODE_24BIT" + +config QSPI_MODE_32BIT + bool "QSPI_MODE_32BIT" + +config SD_MODE + bool "SD_MODE" + +config SD_MODE1 + bool "SD_MODE1" + +config NAND_MODE + bool "NAND_MODE" + +config EMMC_MODE + bool "EMMC_MODE" + +config USB_MODE + bool "USB" + +endchoice endif diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index 867d2b2..04e1905 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -35,10 +35,29 @@ void board_init_f(ulong dummy) board_init_r(NULL, 0); } +static void ps_mode_reset(ulong mode) +{ + writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT, + &crlapb_base->boot_pin_ctrl); + udelay(5); + writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT | + mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT, + &crlapb_base->boot_pin_ctrl); +} + +/* + * Set default PS_MODE1 which is used for USB ULPI phy reset + * Also other resets can be connected to this certain pin + */ +#ifndef MODE_RESET +# define MODE_RESET PS_MODE1 +#endif + #ifdef CONFIG_SPL_BOARD_INIT void spl_board_init(void) { preloader_console_init(); + ps_mode_reset(MODE_RESET); board_init(); } #endif @@ -48,6 +67,13 @@ u32 spl_boot_device(void) u32 reg = 0; u8 bootmode; +#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED) + /* Change default boot mode at run-time */ + writel(BOOT_MODE_USE_ALT | + CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT, + &crlapb_base->boot_mode); +#endif + reg = readl(&crlapb_base->boot_mode); bootmode = reg & BOOT_MODES_MASK; @@ -60,6 +86,10 @@ u32 spl_boot_device(void) case SD_MODE1: return BOOT_DEVICE_MMC1; #endif +#ifdef CONFIG_SPL_DFU_SUPPORT + case USB_MODE: + return BOOT_DEVICE_DFU; +#endif default: printf("Invalid Boot Mode:0x%x\n", bootmode); break; diff --git a/arch/arm/cpu/sa1100/timer.c b/arch/arm/cpu/sa1100/timer.c index 0a0006b..90e2128 100644 --- a/arch/arm/cpu/sa1100/timer.c +++ b/arch/arm/cpu/sa1100/timer.c @@ -66,8 +66,5 @@ unsigned long long get_ticks(void) */ ulong get_tbclk (void) { - ulong tbclk; - - tbclk = CONFIG_SYS_HZ; - return tbclk; + return CONFIG_SYS_HZ; } diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 715e9bd..e89b6e80 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-375-db.dtb \ armada-388-clearfog.dtb \ armada-388-gp.dtb \ + armada-385-amc.dtb \ armada-xp-gp.dtb \ armada-xp-maxbcm.dtb \ armada-xp-synology-ds414.dtb \ @@ -263,7 +264,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h3-orangepi-pc.dtb \ sun8i-h3-orangepi-pc-plus.dtb \ sun8i-h3-orangepi-plus.dtb \ - sun8i-h3-orangepi-plus2e.dtb + sun8i-h3-orangepi-plus2e.dtb \ + sun8i-h3-nanopi-neo.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-pine64-plus.dtb \ sun50i-a64-pine64.dtb diff --git a/arch/arm/dts/armada-385-amc.dts b/arch/arm/dts/armada-385-amc.dts new file mode 100644 index 0000000..a5a8a7f --- /dev/null +++ b/arch/arm/dts/armada-385-amc.dts @@ -0,0 +1,163 @@ +/* + * Device Tree file for Marvell Armada 385 development board + * (DB-88F6820-AMC) + * + * Copyright (C) 2014 Marvell + * + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-385.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Marvell Armada 385 AMC"; + compatible = "marvell,a385-amc", "marvell,armada385", "marvell,armada380"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + spi1 = &spi1; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2 GB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; + + internal-regs { + i2c@11000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + }; + + serial@12000 { + /* + * Exported on the micro USB connector CON16 + * through an FTDI + */ + + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + ethernet@34000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; + }; + + usb@58000 { + status = "okay"; + }; + + ethernet@70000 { + pinctrl-names = "default"; + /* + * The Reference Clock 0 is used to provide a + * clock to the PHY + */ + pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + + mdio@72004 { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + + phy1: ethernet-phy@0 { + reg = <0>; + }; + }; + + flash@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + }; + }; + + pcie-controller { + status = "okay"; + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + }; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "okay"; + u-boot,dm-pre-reloc; + + spi-flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + }; +}; + +&refclk { + clock-frequency = <20000000>; +}; diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index e92a492..bd7801b 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -43,6 +43,12 @@ regulator-always-on; regulator-boot-on; }; + + vcc5v0_host: vcc5v0-host-en { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + }; }; &emmc_phy { @@ -85,6 +91,10 @@ status = "okay"; }; +&dwc3_typec0 { + status = "okay"; +}; + &usb_host1_ehci { status = "okay"; }; @@ -93,6 +103,10 @@ status = "okay"; }; +&dwc3_typec1 { + status = "okay"; +}; + &pinctrl { pmic { pmic_int_l: pmic-int-l { diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index a4c6e27..179860c 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/rockchip.h> +#define USB_CLASS_HUB 9 / { compatible = "rockchip,rk3399"; @@ -175,6 +176,8 @@ clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "ciu", "biu", "ciu-drive", "ciu-sample"; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>; fifo-depth = <0x100>; status = "disabled"; }; @@ -228,6 +231,50 @@ status = "disabled"; }; + dwc3_typec0: usb@fe800000 { + compatible = "rockchip,rk3399-xhci"; + reg = <0x0 0xfe800000 0x0 0x100000>; + status = "disabled"; + rockchip,vbus-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; + snps,dis-enblslpm-quirk; + snps,phyif-utmi-bits = <16>; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-u2-susphy-quirk; + + #address-cells = <2>; + #size-cells = <2>; + hub { + compatible = "usb-hub"; + usb,device-class = <USB_CLASS_HUB>; + }; + typec_phy0 { + compatible = "rockchip,rk3399-usb3-phy"; + reg = <0x0 0xff7c0000 0x0 0x40000>; + }; + }; + + dwc3_typec1: usb@fe900000 { + compatible = "rockchip,rk3399-xhci"; + reg = <0x0 0xfe900000 0x0 0x100000>; + status = "disabled"; + rockchip,vbus-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + snps,dis-enblslpm-quirk; + snps,phyif-utmi-bits = <16>; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-u2-susphy-quirk; + + #address-cells = <2>; + #size-cells = <2>; + hub { + compatible = "usb-hub"; + usb,device-class = <USB_CLASS_HUB>; + }; + typec_phy1 { + compatible = "rockchip,rk3399-usb3-phy"; + reg = <0x0 0xff800000 0x0 0x40000>; + }; + }; + gic: interrupt-controller@fee00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -771,6 +818,41 @@ }; }; + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 8 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 8 RK_FUNC_1 &pcfg_pull_up>, + <4 9 RK_FUNC_1 &pcfg_pull_up>, + <4 10 RK_FUNC_1 &pcfg_pull_up>, + <4 11 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 12 RK_FUNC_1 &pcfg_pull_none>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 13 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_cd: sdmcc-cd { + rockchip,pins = + <0 7 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdmmc_wp: sdmmc-wp { + rockchip,pins = + <0 8 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + spdif { spdif_bus: spdif-bus { rockchip,pins = diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/dts/sun8i-h3-nanopi-neo.dts new file mode 100644 index 0000000..3d64caf --- /dev/null +++ b/arch/arm/dts/sun8i-h3-nanopi-neo.dts @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2016 James Pettigrew <james@innovum.com.au> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "FriendlyARM NanoPi NEO"; + compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_opc>, <&leds_r_opc>; + + pwr { + label = "nanopi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + + status { + label = "nanopi:blue:status"; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ + }; + }; +}; + +&ehci3 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&pio { + leds_opc: led-pins { + allwinner,pins = "PA10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&r_pio { + leds_r_opc: led-pins { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi index b0b2b57..e441033 100644 --- a/arch/arm/dts/uniphier-common32.dtsi +++ b/arch/arm/dts/uniphier-common32.dtsi @@ -31,7 +31,7 @@ interrupts = <0 33 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart_clk>; + clocks = <&peri_clk 0>; }; serial1: serial@54006900 { @@ -41,7 +41,7 @@ interrupts = <0 35 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart_clk>; + clocks = <&peri_clk 1>; }; serial2: serial@54006a00 { @@ -51,7 +51,7 @@ interrupts = <0 37 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - clocks = <&uart_clk>; + clocks = <&peri_clk 2>; }; serial3: serial@54006b00 { @@ -61,7 +61,7 @@ interrupts = <0 177 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - clocks = <&uart_clk>; + clocks = <&peri_clk 3>; }; system_bus: system-bus@58c00000 { @@ -79,16 +79,33 @@ reg = <0x59801000 0x400>; }; - mio: mioctrl@59810000 { - /* specify compatible in each SoC DTSI */ + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; reg = <0x59810000 0x800>; - #clock-cells = <1>; + u-boot,dm-pre-reloc; + + mio_clk: clock { + #clock-cells = <1>; + }; + + mio_rst: reset { + #reset-cells = <1>; + }; }; - peri: perictrl@59820000 { - /* specify compatible in each SoC DTSI */ + perictrl@59820000 { + compatible = "socionext,uniphier-perictrl", + "simple-mfd", "syscon"; reg = <0x59820000 0x200>; - #clock-cells = <1>; + + peri_clk: clock { + #clock-cells = <1>; + }; + + peri_rst: reset { + #reset-cells = <1>; + }; }; timer@60000200 { @@ -114,7 +131,8 @@ }; soc-glue@5f800000 { - compatible = "simple-mfd", "syscon"; + compatible = "socionext,uniphier-soc-glue", + "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; u-boot,dm-pre-reloc; @@ -124,12 +142,18 @@ }; }; - sysctrl: sysctrl@61840000 { - /* specify compatible in each SoC DTSI */ + sysctrl@61840000 { + compatible = "socionext,uniphier-sysctrl", + "simple-mfd", "syscon"; reg = <0x61840000 0x4000>; - #clock-cells = <1>; - clock-names = "ref"; - clocks = <&refclk>; + + sys_clk: clock { + #clock-cells = <1>; + }; + + sys_rst: reset { + #reset-cells = <1>; + }; }; nand: nand@68000000 { diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts b/arch/arm/dts/uniphier-ph1-ld11-ref.dts index 4eb7664..ca31026 100644 --- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld11-ref.dts @@ -70,3 +70,7 @@ &pinctrl_uart0 { u-boot,dm-pre-reloc; }; + +&pinctrl_system_bus { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi b/arch/arm/dts/uniphier-ph1-ld11.dtsi index ffe04f5..0bdbbdd 100644 --- a/arch/arm/dts/uniphier-ph1-ld11.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld11.dtsi @@ -54,12 +54,6 @@ clock-frequency = <25000000>; }; - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <58820000>; - }; - i2c_clk: i2c_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -69,10 +63,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf01>, - <1 14 0xf01>, - <1 11 0xf01>, - <1 10 0xf01>; + interrupts = <1 13 4>, + <1 14 4>, + <1 11 4>, + <1 10 4>; }; soc { @@ -89,7 +83,7 @@ interrupts = <0 33 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart_clk>; + clocks = <&peri_clk 0>; clock-frequency = <58820000>; }; @@ -100,7 +94,7 @@ interrupts = <0 35 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart_clk>; + clocks = <&peri_clk 1>; clock-frequency = <58820000>; }; @@ -111,7 +105,7 @@ interrupts = <0 37 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - clocks = <&uart_clk>; + clocks = <&peri_clk 2>; clock-frequency = <58820000>; }; @@ -122,7 +116,7 @@ interrupts = <0 177 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - clocks = <&uart_clk>; + clocks = <&peri_clk 3>; clock-frequency = <58820000>; }; @@ -213,6 +207,22 @@ reg = <0x59801000 0x400>; }; + perictrl@59820000 { + compatible = "socionext,uniphier-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-ld11-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-ld11-peri-reset"; + #reset-cells = <1>; + }; + }; + usb0: usb@5a800100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; @@ -220,7 +230,7 @@ interrupts = <0 243 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio 3>, <&mio 6>; + clocks = <&mio_clk 3>, <&mio_clk 6>; }; usb1: usb@5a810100 { @@ -230,7 +240,7 @@ interrupts = <0 244 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio 4>, <&mio 6>; + clocks = <&mio_clk 4>, <&mio_clk 6>; }; usb2: usb@5a820100 { @@ -240,17 +250,29 @@ interrupts = <0 245 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio 5>, <&mio 6>; + clocks = <&mio_clk 5>, <&mio_clk 6>; }; - mio: mioctrl@5b3e0000 { - compatible = "socionext,ph1-ld11-mioctrl"; + mioctrl@5b3e0000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; reg = <0x5b3e0000 0x800>; - #clock-cells = <1>; + + mio_clk: clock { + compatible = "socionext,uniphier-ld11-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-ld11-mio-reset"; + #reset-cells = <1>; + resets = <&sys_rst 7>; + }; }; soc-glue@5f800000 { - compatible = "simple-mfd", "syscon"; + compatible = "socionext,uniphier-soc-glue", + "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; u-boot,dm-pre-reloc; @@ -273,6 +295,22 @@ #interrupt-cells = <3>; interrupts = <1 9 4>; }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-ld11-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x4000>; + + sys_clk: clock { + compatible = "socionext,uniphier-ld11-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-ld11-reset"; + #reset-cells = <1>; + }; + }; }; }; diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.dts b/arch/arm/dts/uniphier-ph1-ld20-ref.dts index 90c8705..e4e8d76 100644 --- a/arch/arm/dts/uniphier-ph1-ld20-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld20-ref.dts @@ -58,3 +58,7 @@ &pinctrl_uart0 { u-boot,dm-pre-reloc; }; + +&pinctrl_system_bus { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi b/arch/arm/dts/uniphier-ph1-ld20.dtsi index 7497539..7f97f88 100644 --- a/arch/arm/dts/uniphier-ph1-ld20.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld20.dtsi @@ -78,12 +78,6 @@ clock-frequency = <25000000>; }; - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <58820000>; - }; - i2c_clk: i2c_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -93,10 +87,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf01>, - <1 14 0xf01>, - <1 11 0xf01>, - <1 10 0xf01>; + interrupts = <1 13 4>, + <1 14 4>, + <1 11 4>, + <1 10 4>; }; soc { @@ -113,7 +107,7 @@ interrupts = <0 33 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart_clk>; + clocks = <&peri_clk 0>; clock-frequency = <58820000>; }; @@ -124,7 +118,7 @@ interrupts = <0 35 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart_clk>; + clocks = <&peri_clk 1>; clock-frequency = <58820000>; }; @@ -135,7 +129,7 @@ interrupts = <0 37 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - clocks = <&uart_clk>; + clocks = <&peri_clk 2>; clock-frequency = <58820000>; }; @@ -146,7 +140,7 @@ interrupts = <0 177 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - clocks = <&uart_clk>; + clocks = <&peri_clk 3>; clock-frequency = <58820000>; }; @@ -237,10 +231,36 @@ reg = <0x59801000 0x400>; }; - mio: mioctrl@59810000 { - compatible = "socionext,ph1-ld20-mioctrl"; + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; reg = <0x59810000 0x800>; - #clock-cells = <1>; + + mio_clk: clock { + compatible = "socionext,uniphier-ld20-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-ld20-mio-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-ld20-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-ld20-peri-reset"; + #reset-cells = <1>; + }; }; sd: sdhc@5a400000 { @@ -250,12 +270,13 @@ interrupts = <0 76 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sd>; - clocks = <&mio 0>; + clocks = <&mio_clk 0>; bus-width = <4>; }; soc-glue@5f800000 { - compatible = "simple-mfd", "syscon"; + compatible = "socionext,uniphier-soc-glue", + "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; u-boot,dm-pre-reloc; @@ -278,6 +299,22 @@ #interrupt-cells = <3>; interrupts = <1 9 4>; }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x4000>; + + sys_clk: clock { + compatible = "socionext,uniphier-ld20-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-ld20-reset"; + #reset-cells = <1>; + }; + }; }; }; diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi index 07f315a..e4884b9 100644 --- a/arch/arm/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi @@ -30,12 +30,6 @@ clock-frequency = <50000000>; }; - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <36864000>; - }; - iobus_clk: iobus_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -228,7 +222,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio 0>; + clocks = <&mio_clk 0>; bus-width = <4>; }; @@ -240,7 +234,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_emmc>; pinctrl-1 = <&pinctrl_emmc_1v8>; - clocks = <&mio 1>; + clocks = <&mio_clk 1>; bus-width = <8>; non-removable; }; @@ -252,7 +246,7 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio 3>, <&mio 6>; + clocks = <&mio_clk 3>, <&mio_clk 6>; }; usb1: usb@5a810100 { @@ -262,7 +256,7 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio 4>, <&mio 6>; + clocks = <&mio_clk 4>, <&mio_clk 6>; }; usb2: usb@5a820100 { @@ -272,7 +266,7 @@ interrupts = <0 82 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio 5>, <&mio 6>; + clocks = <&mio_clk 5>, <&mio_clk 6>; }; aidet@61830000 { @@ -302,22 +296,30 @@ clock-frequency = <36864000>; }; -&mio { - compatible = "socionext,ph1-ld4-mioctrl"; - clock-names = "stdmac", "ehci"; - clocks = <&sysctrl 10>, <&sysctrl 18>; +&mio_clk { + compatible = "socionext,uniphier-ld4-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-ld4-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-ld4-peri-clock"; }; -&peri { - compatible = "socionext,ph1-ld4-perictrl"; - clock-names = "uart", "i2c"; - clocks = <&sysctrl 3>, <&sysctrl 4>; +&peri_rst { + compatible = "socionext,uniphier-ld4-peri-reset"; }; &pinctrl { compatible = "socionext,uniphier-ld4-pinctrl"; }; -&sysctrl { - compatible = "socionext,ph1-ld4-sysctrl"; +&sys_clk { + compatible = "socionext,uniphier-ld4-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-ld4-reset"; }; diff --git a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts index 965fe08..3f178d2 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts +++ b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts @@ -89,7 +89,7 @@ u-boot,dm-pre-reloc; }; -&mio { +&mio_clk { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index e0b28b8..192ce84 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -351,7 +351,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio 0>; + clocks = <&mio_clk 0>; bus-width = <4>; }; @@ -363,7 +363,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_emmc>; pinctrl-1 = <&pinctrl_emmc_1v8>; - clocks = <&mio 1>; + clocks = <&mio_clk 1>; bus-width = <8>; non-removable; }; @@ -376,7 +376,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_sd1>; pinctrl-1 = <&pinctrl_sd1_1v8>; - clocks = <&mio 2>; + clocks = <&mio_clk 2>; bus-width = <4>; }; @@ -387,7 +387,7 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio 3>, <&mio 6>; + clocks = <&mio_clk 3>, <&mio_clk 6>; }; usb3: usb@5a810100 { @@ -397,7 +397,7 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb3>; - clocks = <&mio 4>, <&mio 6>; + clocks = <&mio_clk 4>, <&mio_clk 6>; }; aidet@5fc20000 { @@ -444,22 +444,30 @@ clock-frequency = <73728000>; }; -&mio { - compatible = "socionext,ph1-pro4-mioctrl"; - clock-names = "stdmac", "ehci"; - clocks = <&sysctrl 10>, <&sysctrl 18>; +&mio_clk { + compatible = "socionext,uniphier-pro4-mio-clock"; }; -&peri { - compatible = "socionext,ph1-pro4-perictrl"; - clock-names = "uart", "fi2c"; - clocks = <&sysctrl 3>, <&sysctrl 4>; +&mio_rst { + compatible = "socionext,uniphier-pro4-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-pro4-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-pro4-peri-reset"; }; &pinctrl { compatible = "socionext,uniphier-pro4-pinctrl"; }; -&sysctrl { - compatible = "socionext,ph1-pro4-sysctrl"; +&sys_clk { + compatible = "socionext,uniphier-pro4-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-pro4-reset"; }; diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi index 05f961f..22a70b1 100644 --- a/arch/arm/dts/uniphier-ph1-pro5.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi @@ -38,12 +38,6 @@ clock-frequency = <50000000>; }; - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <73728000>; - }; - i2c_clk: i2c_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -367,7 +361,7 @@ interrupts = <0 78 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; - clocks = <&mio 1>; + clocks = <&mio_clk 1>; bus-width = <8>; non-removable; }; @@ -380,7 +374,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio 0>; + clocks = <&mio_clk 0>; bus-width = <4>; }; @@ -423,22 +417,30 @@ clock-frequency = <73728000>; }; -&mio { - compatible = "socionext,ph1-pro5-mioctrl"; - clock-names = "stdmac"; - clocks = <&sysctrl 10>; +&mio_clk { + compatible = "socionext,uniphier-pro5-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-pro5-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-pro5-peri-clock"; }; -&peri { - compatible = "socionext,ph1-pro5-perictrl"; - clock-names = "uart", "fi2c"; - clocks = <&sysctrl 3>, <&sysctrl 4>; +&peri_rst { + compatible = "socionext,uniphier-pro5-peri-reset"; }; &pinctrl { compatible = "socionext,uniphier-pro5-pinctrl"; }; -&sysctrl { - compatible = "socionext,ph1-pro5-sysctrl"; +&sys_clk { + compatible = "socionext,uniphier-pro5-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-pro5-reset"; }; diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts index 0863588..116e571 100644 --- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts @@ -86,10 +86,14 @@ u-boot,dm-pre-reloc; }; -&mio { +&emmc { u-boot,dm-pre-reloc; }; -&emmc { - u-boot,dm-pre-reloc; +&pinctrl_uart0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_emmc { + u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi index 6a95541..a554b08 100644 --- a/arch/arm/dts/uniphier-ph1-sld3.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi @@ -42,12 +42,6 @@ clock-frequency = <50000000>; }; - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <36864000>; - }; - iobus_clk: iobus_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -90,7 +84,8 @@ status = "disabled"; reg = <0x54006800 0x40>; interrupts = <0 33 4>; - clocks = <&uart_clk>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; clock-frequency = <36864000>; }; @@ -99,7 +94,8 @@ status = "disabled"; reg = <0x54006900 0x40>; interrupts = <0 35 4>; - clocks = <&uart_clk>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; clock-frequency = <36864000>; }; @@ -108,7 +104,8 @@ status = "disabled"; reg = <0x54006a00 0x40>; interrupts = <0 37 4>; - clocks = <&uart_clk>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; clock-frequency = <36864000>; }; @@ -231,6 +228,8 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; clocks = <&iobus_clk>; clock-frequency = <100000>; }; @@ -291,12 +290,22 @@ reg = <0x59801000 0x400>; }; - mio: mioctrl@59810000 { - compatible = "socionext,ph1-sld3-mioctrl"; + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; reg = <0x59810000 0x800>; - #clock-cells = <1>; - clock-names = "stdmac", "ehci"; - clocks = <&sysctrl 10>, <&sysctrl 18>; + u-boot,dm-pre-reloc; + + mio_clk: clock { + compatible = "socionext,uniphier-sld3-mio-clock"; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-sld3-mio-reset"; + #reset-cells = <1>; + }; }; emmc: sdhc@5a400000 { @@ -304,7 +313,10 @@ status = "disabled"; reg = <0x5a400000 0x200>; interrupts = <0 78 4>; - clocks = <&mio 1>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_emmc>; + pinctrl-1 = <&pinctrl_emmc_1v8>; + clocks = <&mio_clk 1>; bus-width = <8>; non-removable; }; @@ -314,7 +326,10 @@ status = "disabled"; reg = <0x5a500000 0x200>; interrupts = <0 76 4>; - clocks = <&mio 0>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_1v8>; + clocks = <&mio_clk 0>; bus-width = <4>; }; @@ -323,7 +338,9 @@ status = "disabled"; reg = <0x5a800100 0x100>; interrupts = <0 80 4>; - clocks = <&mio 3>, <&mio 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 3>, <&mio_clk 6>; }; usb1: usb@5a810100 { @@ -331,7 +348,9 @@ status = "disabled"; reg = <0x5a810100 0x100>; interrupts = <0 81 4>; - clocks = <&mio 4>, <&mio 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 4>, <&mio_clk 6>; }; usb2: usb@5a820100 { @@ -339,7 +358,9 @@ status = "disabled"; reg = <0x5a820100 0x100>; interrupts = <0 82 4>; - clocks = <&mio 5>, <&mio 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 5>, <&mio_clk 6>; }; usb3: usb@5a830100 { @@ -347,7 +368,20 @@ status = "disabled"; reg = <0x5a830100 0x100>; interrupts = <0 83 4>; - clocks = <&mio 7>, <&mio 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + clocks = <&mio_clk 7>, <&mio_clk 6>; + }; + + soc-glue@5f800000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + u-boot,dm-pre-reloc; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-sld3-pinctrl"; + u-boot,dm-pre-reloc; + }; }; aidet@f1830000 { @@ -355,12 +389,20 @@ reg = <0xf1830000 0x200>; }; - sysctrl: sysctrl@f1840000 { - compatible = "socionext,ph1-sld3-sysctrl"; + sysctrl@f1840000 { + compatible = "socionext,uniphier-sysctrl", + "simple-mfd", "syscon"; reg = <0xf1840000 0x4000>; - #clock-cells = <1>; - clock-names = "ref"; - clocks = <&refclk>; + + sys_clk: clock { + compatible = "socionext,uniphier-sld3-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-sld3-reset"; + #reset-cells = <1>; + }; }; nand: nand@f8000000 { @@ -370,3 +412,5 @@ }; }; }; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi index e0376a1..1ecce50 100644 --- a/arch/arm/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi @@ -30,12 +30,6 @@ clock-frequency = <50000000>; }; - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <80000000>; - }; - iobus_clk: iobus_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -228,7 +222,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio 0>; + clocks = <&mio_clk 0>; bus-width = <4>; }; @@ -240,7 +234,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_emmc>; pinctrl-1 = <&pinctrl_emmc_1v8>; - clocks = <&mio 1>; + clocks = <&mio_clk 1>; bus-width = <8>; non-removable; }; @@ -252,7 +246,7 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio 3>, <&mio 6>; + clocks = <&mio_clk 3>, <&mio_clk 6>; }; usb1: usb@5a810100 { @@ -262,7 +256,7 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio 4>, <&mio 6>; + clocks = <&mio_clk 4>, <&mio_clk 6>; }; usb2: usb@5a820100 { @@ -272,7 +266,7 @@ interrupts = <0 82 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio 5>, <&mio 6>; + clocks = <&mio_clk 5>, <&mio_clk 6>; }; aidet@61830000 { @@ -302,22 +296,30 @@ clock-frequency = <80000000>; }; -&mio { - compatible = "socionext,ph1-sld8-mioctrl"; - clock-names = "stdmac", "ehci"; - clocks = <&sysctrl 10>, <&sysctrl 18>; +&mio_clk { + compatible = "socionext,uniphier-sld8-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-sld8-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-sld8-peri-clock"; }; -&peri { - compatible = "socionext,ph1-sld8-perictrl"; - clock-names = "uart", "i2c"; - clocks = <&sysctrl 3>, <&sysctrl 4>; +&peri_rst { + compatible = "socionext,uniphier-sld8-peri-reset"; }; &pinctrl { compatible = "socionext,uniphier-sld8-pinctrl"; }; -&sysctrl { - compatible = "socionext,ph1-sld8-sysctrl"; +&sys_clk { + compatible = "socionext,uniphier-sld8-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-sld8-reset"; }; diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts index 1175703..7233dc6 100644 --- a/arch/arm/dts/uniphier-proxstream2-gentil.dts +++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts @@ -69,7 +69,7 @@ u-boot,dm-pre-reloc; }; -&mio { +&mio_clk { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts index 928a092..30ea270 100644 --- a/arch/arm/dts/uniphier-proxstream2-vodka.dts +++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts @@ -54,7 +54,7 @@ u-boot,dm-pre-reloc; }; -&mio { +&mio_clk { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi index 23a6bfa..609cbaa 100644 --- a/arch/arm/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/dts/uniphier-proxstream2.dtsi @@ -52,12 +52,6 @@ clock-frequency = <50000000>; }; - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <88900000>; - }; - i2c_clk: i2c_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -366,7 +360,7 @@ interrupts = <0 78 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; - clocks = <&mio 1>; + clocks = <&mio_clk 1>; bus-width = <8>; non-removable; }; @@ -379,7 +373,7 @@ pinctrl-names = "default", "1.8v"; pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio 0>; + clocks = <&mio_clk 0>; bus-width = <4>; }; @@ -427,22 +421,30 @@ clock-frequency = <88900000>; }; -&mio { - compatible = "socionext,proxstream2-mioctrl"; - clock-names = "stdmac"; - clocks = <&sysctrl 10>; +&mio_clk { + compatible = "socionext,uniphier-pxs2-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-pxs2-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-pxs2-peri-clock"; }; -&peri { - compatible = "socionext,proxstream2-perictrl"; - clock-names = "uart", "fi2c"; - clocks = <&sysctrl 3>, <&sysctrl 4>; +&peri_rst { + compatible = "socionext,uniphier-pxs2-peri-reset"; }; &pinctrl { compatible = "socionext,uniphier-pxs2-pinctrl"; }; -&sysctrl { - compatible = "socionext,proxstream2-sysctrl"; +&sys_clk { + compatible = "socionext,uniphier-pxs2-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-pxs2-reset"; }; diff --git a/arch/arm/imx-common/cmd_bmode.c b/arch/arm/imx-common/cmd_bmode.c index 841b1d3..b0868aa 100644 --- a/arch/arm/imx-common/cmd_bmode.c +++ b/arch/arm/imx-common/cmd_bmode.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/io.h> #include <asm/imx-common/boot_mode.h> #include <malloc.h> diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 4223187..a33aa16 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -10,7 +10,7 @@ #include <bootm.h> #include <common.h> #include <netdev.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> diff --git a/arch/arm/imx-common/i2c-mxv7.c b/arch/arm/imx-common/i2c-mxv7.c index ff72b1a..ae8809c 100644 --- a/arch/arm/imx-common/i2c-mxv7.c +++ b/arch/arm/imx-common/i2c-mxv7.c @@ -7,7 +7,7 @@ #include <malloc.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/gpio.h> #include <asm/imx-common/mxc_i2c.h> #include <watchdog.h> diff --git a/arch/arm/imx-common/misc.c b/arch/arm/imx-common/misc.c index 12256a3..1b0f18d 100644 --- a/arch/arm/imx-common/misc.c +++ b/arch/arm/imx-common/misc.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/arch/sys_proto.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/io.h> #include <asm/imx-common/regs-common.h> diff --git a/arch/arm/imx-common/rdc-sema.c b/arch/arm/imx-common/rdc-sema.c index dcb5c41..5df4e02 100644 --- a/arch/arm/imx-common/rdc-sema.c +++ b/arch/arm/imx-common/rdc-sema.c @@ -8,7 +8,7 @@ #include <asm/arch/imx-regs.h> #include <asm/imx-common/rdc-sema.h> #include <asm/arch/imx-rdc.h> -#include <asm-generic/errno.h> +#include <linux/errno.h> /* * Check if the RDC Semaphore is required for this peripheral. diff --git a/arch/arm/imx-common/video.c b/arch/arm/imx-common/video.c index 46f8a1e..fdc987f 100644 --- a/arch/arm/imx-common/video.c +++ b/arch/arm/imx-common/video.c @@ -3,7 +3,7 @@ */ #include <common.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/imx-common/video.h> int board_video_skip(void) diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 21edbc2..804c77b 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -16,6 +16,7 @@ enum { ROCKCHIP_SYSCON_GRF, ROCKCHIP_SYSCON_SGRF, ROCKCHIP_SYSCON_PMU, + ROCKCHIP_SYSCON_PMUGRF, }; /* Standard Rockchip clock numbers */ diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h new file mode 100644 index 0000000..d3d1467 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -0,0 +1,321 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SOC_ROCKCHIP_RK3399_GRF_H__ +#define __SOC_ROCKCHIP_RK3399_GRF_H__ + +struct rk3399_grf_regs { + u32 reserved[0x800]; + u32 usb3_perf_con0; + u32 usb3_perf_con1; + u32 usb3_perf_con2; + u32 usb3_perf_rd_max_latency_num; + u32 usb3_perf_rd_latency_samp_num; + u32 usb3_perf_rd_latency_acc_num; + u32 usb3_perf_rd_axi_total_byte; + u32 usb3_perf_wr_axi_total_byte; + u32 usb3_perf_working_cnt; + u32 reserved1[0x103]; + u32 usb3otg0_con0; + u32 usb3otg0_con1; + u32 reserved2[2]; + u32 usb3otg1_con0; + u32 usb3otg1_con1; + u32 reserved3[2]; + u32 usb3otg0_status_lat0; + u32 usb3otg0_status_lat1; + u32 usb3otg0_status_cb; + u32 reserved4; + u32 usb3otg1_status_lat0; + u32 usb3otg1_status_lat1; + u32 usb3ogt1_status_cb; + u32 reserved5[0x6e5]; + u32 pcie_perf_con0; + u32 pcie_perf_con1; + u32 pcie_perf_con2; + u32 pcie_perf_rd_max_latency_num; + u32 pcie_perf_rd_latency_samp_num; + u32 pcie_perf_rd_laterncy_acc_num; + u32 pcie_perf_rd_axi_total_byte; + u32 pcie_perf_wr_axi_total_byte; + u32 pcie_perf_working_cnt; + u32 reserved6[0x37]; + u32 usb20_host0_con0; + u32 usb20_host0_con1; + u32 reserved7[2]; + u32 usb20_host1_con0; + u32 usb20_host1_con1; + u32 reserved8[2]; + u32 hsic_con0; + u32 hsic_con1; + u32 reserved9[6]; + u32 grf_usbhost0_status; + u32 grf_usbhost1_Status; + u32 grf_hsic_status; + u32 reserved10[0xc9]; + u32 hsicphy_con0; + u32 reserved11[3]; + u32 usbphy0_ctrl[26]; + u32 reserved12[6]; + u32 usbphy1[26]; + u32 reserved13[0x72f]; + u32 soc_con9; + u32 reserved14[0x0a]; + u32 soc_con20; + u32 soc_con21; + u32 soc_con22; + u32 soc_con23; + u32 soc_con24; + u32 soc_con25; + u32 soc_con26; + u32 reserved15[0xf65]; + u32 cpu_con[4]; + u32 reserved16[0x1c]; + u32 cpu_status[6]; + u32 reserved17[0x1a]; + u32 a53_perf_con[4]; + u32 a53_perf_rd_mon_st; + u32 a53_perf_rd_mon_end; + u32 a53_perf_wr_mon_st; + u32 a53_perf_wr_mon_end; + u32 a53_perf_rd_max_latency_num; + u32 a53_perf_rd_latency_samp_num; + u32 a53_perf_rd_laterncy_acc_num; + u32 a53_perf_rd_axi_total_byte; + u32 a53_perf_wr_axi_total_byte; + u32 a53_perf_working_cnt; + u32 a53_perf_int_status; + u32 reserved18[0x31]; + u32 a72_perf_con[4]; + u32 a72_perf_rd_mon_st; + u32 a72_perf_rd_mon_end; + u32 a72_perf_wr_mon_st; + u32 a72_perf_wr_mon_end; + u32 a72_perf_rd_max_latency_num; + u32 a72_perf_rd_latency_samp_num; + u32 a72_perf_rd_laterncy_acc_num; + u32 a72_perf_rd_axi_total_byte; + u32 a72_perf_wr_axi_total_byte; + u32 a72_perf_working_cnt; + u32 a72_perf_int_status; + u32 reserved19[0x7f6]; + u32 soc_con5; + u32 soc_con6; + u32 reserved20[0x779]; + u32 gpio2a_iomux; + union { + u32 iomux_spi2; + u32 gpio2b_iomux; + }; + union { + u32 gpio2c_iomux; + u32 iomux_spi5; + }; + u32 gpio2d_iomux; + union { + u32 gpio3a_iomux; + u32 iomux_spi0; + }; + u32 gpio3b_iomux; + u32 gpio3c_iomux; + union { + u32 iomux_i2s0; + u32 gpio3d_iomux; + }; + union { + u32 iomux_i2sclk; + u32 gpio4a_iomux; + }; + union { + u32 iomux_sdmmc; + u32 iomux_uart2a; + u32 gpio4b_iomux; + }; + union { + u32 iomux_pwm_0; + u32 iomux_pwm_1; + u32 iomux_uart2b; + u32 iomux_uart2c; + u32 iomux_edp_hotplug; + u32 gpio4c_iomux; + }; + u32 gpio4d_iomux; + u32 reserved21[4]; + u32 gpio2_p[3][4]; + u32 reserved22[4]; + u32 gpio2_sr[3][4]; + u32 reserved23[4]; + u32 gpio2_smt[3][4]; + u32 reserved24[(0xe130 - 0xe0ec)/4 - 1]; + u32 gpio4b_e01; + u32 gpio4b_e2; + u32 reserved24a[(0xe200 - 0xe134)/4 - 1]; + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5_pcie; + u32 reserved25; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9_pcie; + u32 reserved26[0x1e]; + u32 soc_status[6]; + u32 reserved27[0x32]; + u32 ddrc0_con0; + u32 ddrc0_con1; + u32 ddrc1_con0; + u32 ddrc1_con1; + u32 reserved28[0xac]; + u32 io_vsel; + u32 saradc_testbit; + u32 tsadc_testbit_l; + u32 tsadc_testbit_h; + u32 reserved29[0x6c]; + u32 chip_id_addr; + u32 reserved30[0x1f]; + u32 fast_boot_addr; + u32 reserved31[0x1df]; + u32 emmccore_con[12]; + u32 reserved32[4]; + u32 emmccore_status[4]; + u32 reserved33[0x1cc]; + u32 emmcphy_con[7]; + u32 reserved34; + u32 emmcphy_status; +}; +check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0); + +struct rk3399_pmugrf_regs { + union { + u32 iomux_pwm_3a; + u32 gpio0a_iomux; + }; + u32 gpio0b_iomux; + u32 reserved0[2]; + union { + u32 spi1_rxd; + u32 tsadc_int; + u32 gpio1a_iomux; + }; + union { + u32 spi1_csclktx; + u32 iomux_pwm_3b; + u32 iomux_i2c0_sda; + u32 gpio1b_iomux; + }; + union { + u32 iomux_pwm_2; + u32 iomux_i2c0_scl; + u32 gpio1c_iomux; + }; + u32 gpio1d_iomux; + u32 reserved1[8]; + u32 gpio0_p[2][4]; + u32 reserved3[8]; + u32 gpio0a_e; + u32 reserved4; + u32 gpio0b_e; + u32 reserved5[5]; + u32 gpio1a_e; + u32 reserved6; + u32 gpio1b_e; + u32 reserved7; + u32 gpio1c_e; + u32 reserved8; + u32 gpio1d_e; + u32 reserved9[0x11]; + u32 gpio0l_sr; + u32 reserved10; + u32 gpio1l_sr; + u32 gpio1h_sr; + u32 reserved11[4]; + u32 gpio0a_smt; + u32 gpio0b_smt; + u32 reserved12[2]; + u32 gpio1a_smt; + u32 gpio1b_smt; + u32 gpio1c_smt; + u32 gpio1d_smt; + u32 reserved13[8]; + u32 gpio0l_he; + u32 reserved14; + u32 gpio1l_he; + u32 gpio1h_he; + u32 reserved15[4]; + u32 soc_con0; + u32 reserved16[9]; + u32 soc_con10; + u32 soc_con11; + u32 reserved17[0x24]; + u32 pmupvtm_con0; + u32 pmupvtm_con1; + u32 pmupvtm_status0; + u32 pmupvtm_status1; + u32 grf_osc_e; + u32 reserved18[0x2b]; + u32 os_reg0; + u32 os_reg1; + u32 os_reg2; + u32 os_reg3; +}; +check_member(rk3399_pmugrf_regs, os_reg3, 0x30c); + +struct rk3399_pmusgrf_regs { + u32 ddr_rgn_con[35]; + u32 reserved[0x1fe5]; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 soc_con12; + u32 soc_con13; + u32 soc_con14; + u32 soc_con15; + u32 reserved1[3]; + u32 soc_con19; + u32 soc_con20; + u32 soc_con21; + u32 soc_con22; + u32 reserved2[0x29]; + u32 perilp_con[9]; + u32 reserved4[7]; + u32 perilp_status; + u32 reserved5[0xfaf]; + u32 soc_con0; + u32 soc_con1; + u32 reserved6[0x3e]; + u32 pmu_con[9]; + u32 reserved7[0x17]; + u32 fast_boot_addr; + u32 reserved8[0x1f]; + u32 efuse_prg_mask; + u32 efuse_read_mask; + u32 reserved9[0x0e]; + u32 pmu_slv_con0; + u32 pmu_slv_con1; + u32 reserved10[0x771]; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 soc_con6; + u32 soc_con7; + u32 reserved11[8]; + u32 soc_con16; + u32 soc_con17; + u32 soc_con18; + u32 reserved12[0xdd]; + u32 slv_secure_con0; + u32 slv_secure_con1; + u32 reserved13; + u32 slv_secure_con2; + u32 slv_secure_con3; + u32 slv_secure_con4; +}; +check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4); + +#endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h index e08e28f..82c3d07 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram.h +++ b/arch/arm/include/asm/arch-rockchip/sdram.h @@ -24,12 +24,16 @@ struct rk3288_sdram_channel { u8 row_3_4; u8 cs0_row; u8 cs1_row; +#if CONFIG_IS_ENABLED(OF_PLATDATA) /* * For of-platdata, which would otherwise convert this into two * byte-swapped integers. With a size of 9 bytes, this struct will * appear in of-platdata as a byte array. + * + * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) */ u8 dummy; +#endif }; struct rk3288_sdram_pctl_timing { diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h new file mode 100644 index 0000000..35423e1 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h @@ -0,0 +1,10 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co.,Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_SYS_PROTO_H +#define _ASM_ARCH_SYS_PROTO_H + +#endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/arch-sunxi/usb_phy.h b/arch/arm/include/asm/arch-sunxi/usb_phy.h index 6a14cad..cef6c98 100644 --- a/arch/arm/include/asm/arch-sunxi/usb_phy.h +++ b/arch/arm/include/asm/arch-sunxi/usb_phy.h @@ -16,7 +16,6 @@ void sunxi_usb_phy_init(int index); void sunxi_usb_phy_exit(int index); void sunxi_usb_phy_power_on(int index); void sunxi_usb_phy_power_off(int index); -int sunxi_usb_phy_power_is_on(int index); int sunxi_usb_phy_vbus_detect(int index); int sunxi_usb_phy_id_detect(int index); void sunxi_usb_phy_enable_squelch_detect(int index, int enable); diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 35964d6..456c1b0 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -25,6 +25,13 @@ #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 +#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 +#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 + +#define PS_MODE0 BIT(0) +#define PS_MODE1 BIT(1) +#define PS_MODE2 BIT(2) +#define PS_MODE3 BIT(3) struct crlapb_regs { u32 reserved0[36]; @@ -35,7 +42,9 @@ struct crlapb_regs { u32 boot_mode; /* 0x200 */ u32 reserved3[14]; u32 rst_lpd_top; /* 0x23C */ - u32 reserved4[26]; + u32 reserved4[4]; + u32 boot_pin_ctrl; /* 0x250 */ + u32 reserved5[21]; }; #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) @@ -69,7 +78,10 @@ struct iou_scntr_secure { #define SD_MODE1 0x00000005 /* sd 1 */ #define NAND_MODE 0x00000004 #define EMMC_MODE 0x00000006 +#define USB_MODE 0x00000007 #define JTAG_MODE 0x00000000 +#define BOOT_MODE_USE_ALT 0x100 +#define BOOT_MODE_ALT_SHIFT 12 #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 diff --git a/arch/arm/include/asm/errno.h b/arch/arm/include/asm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/arch/arm/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 6b9d3e4..4525287 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -26,13 +26,8 @@ #define CONFIG_FSL_CAAM #endif -#ifdef CONFIG_SPL_BUILD #define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_DM 1 -#define CONFIG_SPL_CRYPTO_SUPPORT -#define CONFIG_SPL_HASH_SUPPORT -#define CONFIG_SPL_RSA -#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#ifdef CONFIG_SPL_BUILD /* * Define the key hash for U-Boot here if public/private key pair used to * sign U-boot are different from the SRK hash put in the fuse diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 19c38f4..6f312d6 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -28,6 +28,7 @@ enum { BOOT_DEVICE_SATA, BOOT_DEVICE_I2C, BOOT_DEVICE_BOARD, + BOOT_DEVICE_DFU, BOOT_DEVICE_NONE }; #endif diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index 76fcada..2e55953 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -11,7 +11,7 @@ */ #include <common.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h> diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index 6d2a7b7..5a32bdb 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -10,7 +10,7 @@ #define __ASM_ARCH_AT91_GPIO_H #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/at91_pio.h> #include <asm/arch/hardware.h> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index c25fcf3..ce2a16f 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -61,6 +61,15 @@ endif if ARCH_EXYNOS5 +config SPL_GPIO_SUPPORT + default y + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + choice prompt "EXYNOS5 board select" diff --git a/arch/arm/mach-keystone/psc.c b/arch/arm/mach-keystone/psc.c index ff042a6..bbea74a 100644 --- a/arch/arm/mach-keystone/psc.c +++ b/arch/arm/mach-keystone/psc.c @@ -8,7 +8,7 @@ */ #include <common.h> -#include <asm-generic/errno.h> +#include <linux/errno.h> #include <asm/io.h> #include <asm/processor.h> #include <asm/arch/psc_defs.h> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 220886a..0fd71a7 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -21,7 +21,7 @@ config MV78460 bool select ARMADA_XP -config DB_88F6820_GP +config 88F6820 bool select ARMADA_38X @@ -31,7 +31,7 @@ choice config TARGET_CLEARFOG bool "Support ClearFog" - select DB_88F6820_GP + select 88F6820 config TARGET_DB_88F6720 bool "Support DB-88F6720 Armada 375" @@ -39,7 +39,11 @@ config TARGET_DB_88F6720 config TARGET_DB_88F6820_GP bool "Support DB-88F6820-GP" - select DB_88F6820_GP + select 88F6820 + +config TARGET_DB_88F6820_AMC + bool "Support DB-88F6820-AMC" + select 88F6820 config TARGET_DB_MV784MP_GP bool "Support db-mv784mp-gp" @@ -63,6 +67,7 @@ config SYS_BOARD default "clearfog" if TARGET_CLEARFOG default "db-88f6720" if TARGET_DB_88F6720 default "db-88f6820-gp" if TARGET_DB_88F6820_GP + default "db-88f6820-amc" if TARGET_DB_88F6820_AMC default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP default "ds414" if TARGET_DS414 default "maxbcm" if TARGET_MAXBCM @@ -72,6 +77,7 @@ config SYS_CONFIG_NAME default "clearfog" if TARGET_CLEARFOG default "db-88f6720" if TARGET_DB_88F6720 default "db-88f6820-gp" if TARGET_DB_88F6820_GP + default "db-88f6820-amc" if TARGET_DB_88F6820_AMC default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP default "ds414" if TARGET_DS414 default "maxbcm" if TARGET_MAXBCM @@ -81,6 +87,7 @@ config SYS_VENDOR default "Marvell" if TARGET_DB_MV784MP_GP default "Marvell" if TARGET_DB_88F6720 default "Marvell" if TARGET_DB_88F6820_GP + default "Marvell" if TARGET_DB_88F6820_AMC default "solidrun" if TARGET_CLEARFOG default "Synology" if TARGET_DS414 diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index df263bc..c4128cd 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -48,7 +48,7 @@ */ #include <common.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c index 49d704a..cc3e5e2 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c @@ -45,7 +45,7 @@ u32 g_dev_id = -1; u32 mv_board_id_get(void) { -#if defined(CONFIG_DB_88F6820_GP) +#if defined(CONFIG_TARGET_DB_88F6820_GP) return DB_GP_68XX_ID; #else /* diff --git a/arch/arm/mach-rmobile/emac.c b/arch/arm/mach-rmobile/emac.c index 0710cfd..e45244c 100644 --- a/arch/arm/mach-rmobile/emac.c +++ b/arch/arm/mach-rmobile/emac.c @@ -8,7 +8,7 @@ */ #include <common.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <netdev.h> int cpu_eth_init(bd_t *bis) diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index bec756d..6c36bf9 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -81,10 +81,6 @@ void enable_caches(void) } #endif -void lowlevel_init(void) -{ -} - #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) #include <usb.h> #include <usb/dwc2_udc.h> diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index 0804714..9263608 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -12,6 +12,9 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x400 +config SPL_SERIAL_SUPPORT + default y + source "board/rockchip/evb_rk3036/Kconfig" source "board/rockchip/kylin_rk3036/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index e0d92a6..ae509ff 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -280,7 +280,3 @@ err: /* No way to report error here */ hang(); } - -void lowlevel_init(void) -{ -} diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index b4113e0..94863a9 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -72,6 +72,21 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x0800 +config SPL_DRIVERS_MISC_SUPPORT + default y + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_MMC_SUPPORT + default y + +config SPL_SERIAL_SUPPORT + default y + source "board/chipspark/popmetal_rk3288/Kconfig" source "board/firefly/firefly-rk3288/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3288/Makefile b/arch/arm/mach-rockchip/rk3288/Makefile index 5ec3f0d..b5b28ef 100644 --- a/arch/arm/mach-rockchip/rk3288/Makefile +++ b/arch/arm/mach-rockchip/rk3288/Makefile @@ -5,5 +5,6 @@ # obj-y += clk_rk3288.o +obj-y += rk3288.o obj-y += sdram_rk3288.o obj-y += syscon_rk3288.o diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c new file mode 100644 index 0000000..92f34bb --- /dev/null +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <asm/io.h> +#include <asm/arch/hardware.h> + +#define GRF_SOC_CON2 0x24c + +int arch_cpu_init(void) +{ + /* We do some SoC one time setting here. */ + + /* Use rkpwm by default */ + rk_setreg(GRF_SOC_CON2, 1 << 0); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c index 2d81c55..2cef68b 100644 --- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c @@ -11,6 +11,7 @@ static const struct udevice_id rk3399_syscon_ids[] = { { .compatible = "rockchip,rk3399-grf", .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rk3399-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, }; U_BOOT_DRIVER(syscon_rk3399) = { diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 1a43c7b..d91b8bb 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -1,5 +1,32 @@ if ARCH_SOCFPGA +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBDISK_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_MMC_SUPPORT + default y if DM_MMC + +config SPL_NAND_SUPPORT + default y if SPL_NAND_DENALI + +config SPL_SERIAL_SUPPORT + default y + +config SPL_SPI_FLASH_SUPPORT + default y if SPL_SPI_SUPPORT + +config SPL_SPI_SUPPORT + default y if DM_SPI + +config SPL_WATCHDOG_SUPPORT + default y + config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 diff --git a/arch/arm/mach-socfpga/fpga_manager.c b/arch/arm/mach-socfpga/fpga_manager.c index 43fd2fe..f909573 100644 --- a/arch/arm/mach-socfpga/fpga_manager.c +++ b/arch/arm/mach-socfpga/fpga_manager.c @@ -10,7 +10,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/fpga_manager.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c index 2b16795..71d5d99 100644 --- a/arch/arm/mach-socfpga/freeze_controller.c +++ b/arch/arm/mach-socfpga/freeze_controller.c @@ -9,7 +9,7 @@ #include <asm/io.h> #include <asm/arch/clock_manager.h> #include <asm/arch/freeze_controller.h> -#include <asm/errno.h> +#include <linux/errno.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index f9993d2..bd1bbee 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -296,13 +296,6 @@ void sunxi_usb_phy_power_off(int index) gpio_set_value(phy->gpio_vbus, 0); } -int sunxi_usb_phy_power_is_on(int index) -{ - struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; - - return phy->power_on_count > 0; -} - int sunxi_usb_phy_vbus_detect(int index) { struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 1eaf406..76909ee 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -1,5 +1,17 @@ if TEGRA +config SPL_GPIO_SUPPORT + default y + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_SERIAL_SUPPORT + default y + config TEGRA_IVC bool "Tegra IVC protocol" help diff --git a/arch/arm/mach-tegra/tegra20/crypto.c b/arch/arm/mach-tegra/tegra20/crypto.c index ec95d7c..1b82fbb 100644 --- a/arch/arm/mach-tegra/tegra20/crypto.c +++ b/arch/arm/mach-tegra/tegra20/crypto.c @@ -6,7 +6,7 @@ */ #include <common.h> -#include <asm/errno.h> +#include <linux/errno.h> #include "crypto.h" #include "aes.h" diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 5fdc4bb..6aef6d3 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -7,7 +7,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/arch/clock.h> #include <asm/arch/emc.h> #include <asm/arch/gp_padctrl.h> diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 774ea99..ae78548 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -4,28 +4,25 @@ ifdef CONFIG_SPL_BUILD -obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ +obj-y += init/ bcu/ memconf/ obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ else -obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o -obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o obj-y += dram_init.o -obj-y += board_common.o -obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o +obj-y += board_init.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o obj-y += reset.o -obj-y += pinctrl/ clk/ - endif obj-y += boards.o obj-y += soc_info.o obj-y += boot-mode/ +obj-y += clk/ obj-y += dram/ +obj-y += pinctrl-glue.o obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/ diff --git a/arch/arm/mach-uniphier/board_common.c b/arch/arm/mach-uniphier/board_common.c deleted file mode 100644 index 330d690..0000000 --- a/arch/arm/mach-uniphier/board_common.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#include "micro-support-card.h" - -void uniphier_smp_kick_all_cpus(void); - -int board_init(void) -{ - led_puts("Uboo"); -#ifdef CONFIG_ARM64 - uniphier_smp_kick_all_cpus(); -#endif - return 0; -} diff --git a/arch/arm/mach-uniphier/board_early_init_r.c b/arch/arm/mach-uniphier/board_early_init_r.c deleted file mode 100644 index b26da36..0000000 --- a/arch/arm/mach-uniphier/board_early_init_r.c +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#include "micro-support-card.h" - -int board_early_init_r(void) -{ - support_card_late_init(); - return 0; -} diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_init.c index d35d38d..b9be52f 100644 --- a/arch/arm/mach-uniphier/board_early_init_f.c +++ b/arch/arm/mach-uniphier/board_init.c @@ -1,5 +1,7 @@ /* - * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2012-2015 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,6 +12,7 @@ #include "init.h" #include "micro-support-card.h" +#include "sg-regs.h" #include "soc-info.h" DECLARE_GLOBAL_DATA_PTR; @@ -45,71 +48,99 @@ static void uniphier_setup_xirq(void) writel(tmp, 0x55000090); } -int board_early_init_f(void) +static void uniphier_nand_pin_init(bool cs2) { +#ifdef CONFIG_NAND_DENALI + if (uniphier_pin_init(cs2 ? "nand2cs_grp" : "nand_grp")) + pr_err("failed to init NAND pins\n"); +#endif +} + +int board_init(void) +{ + const struct uniphier_board_data *bd; + led_puts("U0"); + bd = uniphier_get_board_param(); + if (!bd) + return -ENODEV; + switch (uniphier_get_soc_type()) { #if defined(CONFIG_ARCH_UNIPHIER_SLD3) case SOC_UNIPHIER_SLD3: - uniphier_sld3_pin_init(); + uniphier_nand_pin_init(true); led_puts("U1"); + uniphier_sld3_pll_init(); uniphier_ld4_clk_init(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) case SOC_UNIPHIER_LD4: - uniphier_ld4_pin_init(); + uniphier_nand_pin_init(true); led_puts("U1"); + uniphier_ld4_pll_init(); uniphier_ld4_clk_init(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO4) case SOC_UNIPHIER_PRO4: - uniphier_pro4_pin_init(); + uniphier_nand_pin_init(false); led_puts("U1"); + uniphier_pro4_pll_init(); uniphier_pro4_clk_init(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_SLD8) case SOC_UNIPHIER_SLD8: - uniphier_sld8_pin_init(); + uniphier_nand_pin_init(true); led_puts("U1"); + uniphier_ld4_pll_init(); uniphier_ld4_clk_init(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO5) case SOC_UNIPHIER_PRO5: - uniphier_pro5_pin_init(); + uniphier_nand_pin_init(true); led_puts("U1"); uniphier_pro5_clk_init(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_PXS2) case SOC_UNIPHIER_PXS2: - uniphier_pxs2_pin_init(); + uniphier_nand_pin_init(true); led_puts("U1"); uniphier_pxs2_clk_init(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_LD6B) case SOC_UNIPHIER_LD6B: - uniphier_ld6b_pin_init(); + uniphier_nand_pin_init(true); led_puts("U1"); uniphier_pxs2_clk_init(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_LD11) case SOC_UNIPHIER_LD11: - uniphier_ld20_pin_init(); + uniphier_nand_pin_init(false); + sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ + sg_set_iectrl(149); + sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ + sg_set_iectrl(153); led_puts("U1"); + uniphier_ld11_pll_init(); uniphier_ld11_clk_init(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) case SOC_UNIPHIER_LD20: - uniphier_ld20_pin_init(); + uniphier_nand_pin_init(false); + sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ + sg_set_iectrl(149); + sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ + sg_set_iectrl(153); led_puts("U1"); + uniphier_ld20_pll_init(bd); uniphier_ld20_clk_init(); cci500_init(2); break; @@ -122,5 +153,15 @@ int board_early_init_f(void) led_puts("U2"); + support_card_late_init(); + + led_puts("U3"); + +#ifdef CONFIG_ARM64 + uniphier_smp_kick_all_cpus(); +#endif + + led_puts("Uboo"); + return 0; } diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index 20093d8..79b1d20 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -184,6 +184,27 @@ static const struct uniphier_board_data uniphier_ld11_data = { #endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) +static const struct uniphier_board_data uniphier_ld20_ref_data = { + .dram_freq = 1866, + .dram_nr_ch = 3, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x40000000, + .width = 32, + }, + .dram_ch[1] = { + .base = 0xc0000000, + .size = 0x40000000, + .width = 32, + }, + .dram_ch[2] = { + .base = 0x100000000UL, + .size = 0x40000000, + .width = 32, + }, + .flags = UNIPHIER_BD_BOARD_LD20_REF, +}; + static const struct uniphier_board_data uniphier_ld20_data = { .dram_freq = 1866, .dram_nr_ch = 3, @@ -202,6 +223,7 @@ static const struct uniphier_board_data uniphier_ld20_data = { .size = 0x40000000, .width = 32, }, + .flags = UNIPHIER_BD_BOARD_LD20_GLOBAL, }; static const struct uniphier_board_data uniphier_ld21_data = { @@ -209,7 +231,7 @@ static const struct uniphier_board_data uniphier_ld21_data = { .dram_nr_ch = 2, .dram_ch[0] = { .base = 0x80000000, - .size = 0x40000000, + .size = 0x20000000, .width = 32, }, .dram_ch[1] = { @@ -217,7 +239,7 @@ static const struct uniphier_board_data uniphier_ld21_data = { .size = 0x40000000, .width = 32, }, - .flags = UNIPHIER_BD_PACKAGE_LD21, + .flags = UNIPHIER_BD_BOARD_LD21_GLOBAL, }; #endif @@ -255,6 +277,7 @@ static const struct uniphier_board_id uniphier_boards[] = { #endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) { "socionext,ph1-ld21", &uniphier_ld21_data, }, + { "socionext,ph1-ld20-ref", &uniphier_ld20_ref_data, }, { "socionext,ph1-ld20", &uniphier_ld20_data, }, #endif }; diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index 1428e0c..95f433e 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -2,12 +2,31 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o -obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o +ifdef CONFIG_SPL_BUILD + +obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-clk-ld4.o dpll-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_LD4) += early-clk-ld4.o dpll-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += early-clk-ld4.o dpll-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o dpll-sld8.o +obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o +obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o dpll-ld11.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o dpll-ld20.o + +else + +obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-ld4.o pll-sld3.o dpll-tail.o +obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o +obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o +obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-ld11.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o + +endif + +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o diff --git a/arch/arm/mach-uniphier/clk/dpll-ld11.c b/arch/arm/mach-uniphier/clk/dpll-ld11.c new file mode 100644 index 0000000..7f0677c --- /dev/null +++ b/arch/arm/mach-uniphier/clk/dpll-ld11.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "../init.h" +#include "../sc64-regs.h" +#include "pll.h" + +int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd) +{ + uniphier_ld20_sscpll_init(SC_DPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + + return 0; +} diff --git a/arch/arm/mach-uniphier/clk/dpll-ld20.c b/arch/arm/mach-uniphier/clk/dpll-ld20.c new file mode 100644 index 0000000..1132313 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/dpll-ld20.c @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "../init.h" +#include "../sc64-regs.h" +#include "pll.h" + +int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd) +{ + unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags); + unsigned int dram_freq = bd->dram_freq; + + uniphier_ld20_sscpll_init(SC_DPLL0CTRL, dram_freq, dpll_ssc_rate, 2); + uniphier_ld20_sscpll_init(SC_DPLL1CTRL, dram_freq, dpll_ssc_rate, 2); + uniphier_ld20_sscpll_init(SC_DPLL2CTRL, dram_freq, dpll_ssc_rate, 2); + + return 0; +} diff --git a/arch/arm/mach-uniphier/clk/dpll-ld4.c b/arch/arm/mach-uniphier/clk/dpll-ld4.c new file mode 100644 index 0000000..a40b30d --- /dev/null +++ b/arch/arm/mach-uniphier/clk/dpll-ld4.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2013-2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/err.h> +#include <linux/io.h> + +#include "../init.h" +#include "../sc-regs.h" + +#undef DPLL_SSC_RATE_1PER + +int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd) +{ + unsigned int dram_freq = bd->dram_freq; + u32 tmp; + + /* + * Set Frequency + * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) + * to FOUT (DPLLCTRL.bit[29:20]) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~0x000f0000; + switch (dram_freq) { + case 1333: + tmp |= 0x000d0000; + break; + case 1600: + tmp |= 0x000c0000; + break; + default: + pr_err("Unsupported frequency"); + return -EINVAL; + } + +#if defined(DPLL_SSC_RATE_1PER) + tmp &= ~SC_DPLLCTRL_SSC_RATE; +#else + tmp |= SC_DPLLCTRL_SSC_RATE; +#endif + writel(tmp, SC_DPLLCTRL); + + tmp = readl(SC_DPLLCTRL2); + tmp |= SC_DPLLCTRL2_NRSTDS; + writel(tmp, SC_DPLLCTRL2); + + /* Wait 500 usec until dpll gets stable */ + udelay(500); + + return 0; +} diff --git a/arch/arm/mach-uniphier/clk/dpll-pro4.c b/arch/arm/mach-uniphier/clk/dpll-pro4.c new file mode 100644 index 0000000..3ac48d6 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/dpll-pro4.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2013-2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/err.h> +#include <linux/io.h> + +#include "../init.h" +#include "../sc-regs.h" + +#undef DPLL_SSC_RATE_1PER + +int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd) +{ + unsigned int dram_freq = bd->dram_freq; + u32 tmp; + + /* + * Set Frequency + * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) + * to FOUT ( DPLLCTRL.bit[29:20] ) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~(0x000f0000); + switch (dram_freq) { + case 1333: + tmp |= 0x000d0000; + break; + case 1600: + tmp |= 0x000c0000; + break; + default: + pr_err("Unsupported frequency"); + return -EINVAL; + } + + /* + * Set Moduration rate + * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15]) + */ +#if defined(DPLL_SSC_RATE_1PER) + tmp &= ~0x00008000; +#else + tmp |= 0x00008000; +#endif + writel(tmp, SC_DPLLCTRL); + + tmp = readl(SC_DPLLCTRL2); + tmp |= SC_DPLLCTRL2_NRSTDS; + writel(tmp, SC_DPLLCTRL2); + + /* Wait until dpll gets stable */ + udelay(500); + + return 0; +} diff --git a/arch/arm/mach-uniphier/pll/pll-init-sld3.c b/arch/arm/mach-uniphier/clk/dpll-sld3.c index 5b4f2e3..0eb310c 100644 --- a/arch/arm/mach-uniphier/pll/pll-init-sld3.c +++ b/arch/arm/mach-uniphier/clk/dpll-sld3.c @@ -6,7 +6,7 @@ #include "../init.h" -int uniphier_sld3_pll_init(const struct uniphier_board_data *bd) +int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd) { /* add pll init code here */ return 0; diff --git a/arch/arm/mach-uniphier/clk/dpll-sld8.c b/arch/arm/mach-uniphier/clk/dpll-sld8.c new file mode 100644 index 0000000..7faa5e8 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/dpll-sld8.c @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2013-2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/io.h> + +#include "../init.h" +#include "../sc-regs.h" + +int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + /* + * Set DPLL SSC parameters for DPLLCTRL3 + * [23] DIVN_TEST 0x1 + * [22:16] DIVN 0x50 + * [10] FREFSEL_TEST 0x1 + * [9:8] FREFSEL 0x2 + * [4] ICPD_TEST 0x1 + * [3:0] ICPD 0xb + */ + tmp = readl(SC_DPLLCTRL3); + tmp &= ~0x00ff0717; + tmp |= 0x00d0061b; + writel(tmp, SC_DPLLCTRL3); + + /* + * Set DPLL SSC parameters for DPLLCTRL + * <-1%> <-2%> + * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) + * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~0x3ff07fff; +#ifdef DPLL_SSC_RATE_1PER + tmp |= 0x084018bf; +#else + tmp |= 0x084031a6; +#endif + writel(tmp, SC_DPLLCTRL); + + /* + * Set DPLL SSC parameters for DPLLCTRL2 + * [31:29] SSC_STEP 0 + * [27] SSC_REG_REF 1 + * [26:20] SSC_M 79 (0x4f) + * [19:0] SSC_K 964689 (0xeb851) + */ + tmp = readl(SC_DPLLCTRL2); + tmp &= ~0xefffffff; + tmp |= 0x0cfeb851; + writel(tmp, SC_DPLLCTRL2); + + /* Wait 500 usec until dpll gets stable */ + udelay(500); + + return 0; +} diff --git a/arch/arm/mach-uniphier/clk/dpll-tail.c b/arch/arm/mach-uniphier/clk/dpll-tail.c new file mode 100644 index 0000000..2b88490 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/dpll-tail.c @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/io.h> + +#include "../sc-regs.h" +#include "pll.h" + +void uniphier_ld4_dpll_ssc_en(void) +{ + u32 tmp; + + tmp = readl(SC_DPLLCTRL); + tmp |= SC_DPLLCTRL_SSC_EN; + writel(tmp, SC_DPLLCTRL); +} diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c b/arch/arm/mach-uniphier/clk/early-clk-ld11.c index c94d83c..c94d83c 100644 --- a/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c +++ b/arch/arm/mach-uniphier/clk/early-clk-ld11.c diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c b/arch/arm/mach-uniphier/clk/early-clk-ld20.c index 5201a55..5201a55 100644 --- a/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c +++ b/arch/arm/mach-uniphier/clk/early-clk-ld20.c diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld4.c b/arch/arm/mach-uniphier/clk/early-clk-ld4.c index b6e8b64..b6e8b64 100644 --- a/arch/arm/mach-uniphier/early-clk/early-clk-ld4.c +++ b/arch/arm/mach-uniphier/clk/early-clk-ld4.c diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-pro5.c b/arch/arm/mach-uniphier/clk/early-clk-pro5.c index c41a8ea..c41a8ea 100644 --- a/arch/arm/mach-uniphier/early-clk/early-clk-pro5.c +++ b/arch/arm/mach-uniphier/clk/early-clk-pro5.c diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-pxs2.c b/arch/arm/mach-uniphier/clk/early-clk-pxs2.c index 665ecd5..665ecd5 100644 --- a/arch/arm/mach-uniphier/early-clk/early-clk-pxs2.c +++ b/arch/arm/mach-uniphier/clk/early-clk-pxs2.c diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c new file mode 100644 index 0000000..a5027d2 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/sizes.h> + +#include "pll.h" + +/* PLL type: SSC */ +#define SC_PLLCTRL_SSC_DK_MASK GENMASK(14, 0) +#define SC_PLLCTRL_SSC_EN BIT(31) +#define SC_PLLCTRL2_NRSTDS BIT(28) +#define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0) + +/* PLL type: VPLL27 */ +#define SC_VPLL27CTRL_WP BIT(0) +#define SC_VPLL27CTRL3_K_LD BIT(28) + +/* PLL type: DSPLL */ +#define SC_DSPLLCTRL2_K_LD BIT(28) + +int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, + unsigned int ssc_rate, unsigned int divn) +{ + void __iomem *base; + u32 tmp; + + base = ioremap(reg_base, SZ_16); + if (!base) + return -ENOMEM; + + if (freq != UNIPHIER_PLL_FREQ_DEFAULT) { + tmp = readl(base); /* SSCPLLCTRL */ + tmp &= ~SC_PLLCTRL_SSC_DK_MASK; + tmp |= (487 * freq * ssc_rate / divn / 512) & + SC_PLLCTRL_SSC_DK_MASK; + writel(tmp, base); + + tmp = readl(base + 4); + tmp &= ~SC_PLLCTRL2_SSC_JK_MASK; + tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK; + + udelay(50); + } + + tmp = readl(base + 4); /* SSCPLLCTRL2 */ + tmp |= SC_PLLCTRL2_NRSTDS; + writel(tmp, base + 4); + + iounmap(base); + + return 0; +} + +int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base) +{ + void __iomem *base; + u32 tmp; + + base = ioremap(reg_base, SZ_16); + if (!base) + return -ENOMEM; + + mdelay(1); + + tmp = readl(base); /* SSCPLLCTRL */ + tmp |= SC_PLLCTRL_SSC_EN; + writel(tmp, base); + + iounmap(base); + + return 0; +} + +int uniphier_ld20_vpll27_init(unsigned long reg_base) +{ + void __iomem *base; + u32 tmp; + + base = ioremap(reg_base, SZ_16); + if (!base) + return -ENOMEM; + + tmp = readl(base); /* VPLL27CTRL */ + tmp |= SC_VPLL27CTRL_WP; /* write protect off */ + writel(tmp, base); + + tmp = readl(base + 8); /* VPLL27CTRL3 */ + tmp |= SC_VPLL27CTRL3_K_LD; + writel(tmp, base + 8); + + tmp = readl(base); /* VPLL27CTRL */ + tmp &= ~SC_VPLL27CTRL_WP; /* write protect on */ + writel(tmp, base); + + iounmap(base); + + return 0; +} + +int uniphier_ld20_dspll_init(unsigned long reg_base) +{ + void __iomem *base; + u32 tmp; + + base = ioremap(reg_base, SZ_16); + if (!base) + return -ENOMEM; + + tmp = readl(base + 8); /* DSPLLCTRL2 */ + tmp |= SC_DSPLLCTRL2_K_LD; + writel(tmp, base + 8); + + iounmap(base); + + return 0; +} diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c new file mode 100644 index 0000000..8a4a748 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/pll-ld11.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/io.h> + +#include "../init.h" +#include "../sc64-regs.h" +#include "pll.h" + +void uniphier_ld11_pll_init(void) +{ + uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2); /* 2000MHz -> 1960MHz */ + /* do nothing for SPLL */ + uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2); /* 1500MHz -> 1600MHz */ + uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + + mdelay(1); + + uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL); + + uniphier_ld20_vpll27_init(SC_VPLL27FCTRL); + uniphier_ld20_vpll27_init(SC_VPLL27ACTRL); + + writel(0, SC_CA53_GEARSET); /* Gear0: CPLL/2 */ + writel(SC_CA_GEARUPD, SC_CA53_GEARUPD); +} diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c new file mode 100644 index 0000000..5e545da --- /dev/null +++ b/arch/arm/mach-uniphier/clk/pll-ld20.c @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#include "../init.h" +#include "../sc64-regs.h" +#include "pll.h" + +int uniphier_ld20_pll_init(const struct uniphier_board_data *bd) +{ + unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags); + + uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); + /* do nothing for SPLL */ + uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); + uniphier_ld20_sscpll_init(SC_MPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); + uniphier_ld20_sscpll_init(SC_GPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + + mdelay(1); + + if (dpll_ssc_rate > 0) { + uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL); + } + + uniphier_ld20_vpll27_init(SC_VPLL27FCTRL); + uniphier_ld20_vpll27_init(SC_VPLL27ACTRL); + + uniphier_ld20_dspll_init(SC_VPLL8KCTRL); + uniphier_ld20_dspll_init(SC_A2PLLCTRL); + + return 0; +} diff --git a/arch/arm/mach-uniphier/pll/pll-init-ld4.c b/arch/arm/mach-uniphier/clk/pll-ld4.c index 57c1d9f..13257e4 100644 --- a/arch/arm/mach-uniphier/pll/pll-init-ld4.c +++ b/arch/arm/mach-uniphier/clk/pll-ld4.c @@ -1,55 +1,17 @@ /* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2013-2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> -#include <linux/err.h> #include <linux/io.h> #include "../init.h" #include "../sc-regs.h" #include "../sg-regs.h" - -#undef DPLL_SSC_RATE_1PER - -static int dpll_init(unsigned int dram_freq) -{ - u32 tmp; - - /* - * Set Frequency - * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) - * to FOUT (DPLLCTRL.bit[29:20]) - */ - tmp = readl(SC_DPLLCTRL); - tmp &= ~0x000f0000; - switch (dram_freq) { - case 1333: - tmp |= 0x000d0000; - break; - case 1600: - tmp |= 0x000c0000; - break; - default: - pr_err("Unsupported frequency"); - return -EINVAL; - } - -#if defined(DPLL_SSC_RATE_1PER) - tmp &= ~SC_DPLLCTRL_SSC_RATE; -#else - tmp |= SC_DPLLCTRL_SSC_RATE; -#endif - writel(tmp, SC_DPLLCTRL); - - tmp = readl(SC_DPLLCTRL2); - tmp |= SC_DPLLCTRL2_NRSTDS; - writel(tmp, SC_DPLLCTRL2); - - return 0; -} +#include "pll.h" static void upll_init(void) { @@ -183,22 +145,9 @@ static void vpll_init(void) writel(tmp, SC_VPLL27BCTRL); } -int uniphier_ld4_pll_init(const struct uniphier_board_data *bd) +void uniphier_ld4_pll_init(void) { - int ret; - - ret = dpll_init(bd->dram_freq); - if (ret) - return ret; upll_init(); vpll_init(); - - /* - * Wait 500 usec until dpll get stable - * We wait 10 usec in upll_init() and vpll_init() - * so 20 usec can be saved here. - */ - udelay(480); - - return 0; + uniphier_ld4_dpll_ssc_en(); } diff --git a/arch/arm/mach-uniphier/pll/pll-init-pro4.c b/arch/arm/mach-uniphier/clk/pll-pro4.c index a7e4e0e..cdd1fd4 100644 --- a/arch/arm/mach-uniphier/pll/pll-init-pro4.c +++ b/arch/arm/mach-uniphier/clk/pll-pro4.c @@ -1,59 +1,17 @@ /* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2013-2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> -#include <linux/err.h> #include <linux/io.h> #include "../init.h" #include "../sc-regs.h" #include "../sg-regs.h" - -#undef DPLL_SSC_RATE_1PER - -static int dpll_init(unsigned int dram_freq) -{ - u32 tmp; - - /* - * Set Frequency - * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) - * to FOUT ( DPLLCTRL.bit[29:20] ) - */ - tmp = readl(SC_DPLLCTRL); - tmp &= ~(0x000f0000); - switch (dram_freq) { - case 1333: - tmp |= 0x000d0000; - break; - case 1600: - tmp |= 0x000c0000; - break; - default: - pr_err("Unsupported frequency"); - return -EINVAL; - } - - /* - * Set Moduration rate - * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15]) - */ -#if defined(DPLL_SSC_RATE_1PER) - tmp &= ~0x00008000; -#else - tmp |= 0x00008000; -#endif - writel(tmp, SC_DPLLCTRL); - - tmp = readl(SC_DPLLCTRL2); - tmp |= SC_DPLLCTRL2_NRSTDS; - writel(tmp, SC_DPLLCTRL2); - - return 0; -} +#include "pll.h" static void vpll_init(void) { @@ -145,20 +103,8 @@ static void vpll_init(void) writel(tmp, SC_VPLL27BCTRL); } -int uniphier_pro4_pll_init(const struct uniphier_board_data *bd) +void uniphier_pro4_pll_init(void) { - int ret; - - ret = dpll_init(bd->dram_freq); - if (ret) - return ret; vpll_init(); - - /* - * Wait 500 usec until dpll get stable - * We wait 1 usec in vpll_init() so 1 usec can be saved here. - */ - udelay(499); - - return 0; + uniphier_ld4_dpll_ssc_en(); } diff --git a/arch/arm/mach-uniphier/clk/pll-sld3.c b/arch/arm/mach-uniphier/clk/pll-sld3.c new file mode 100644 index 0000000..37a7c12 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/pll-sld3.c @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "../init.h" +#include "pll.h" + +void uniphier_sld3_pll_init(void) +{ + uniphier_ld4_dpll_ssc_en(); +} diff --git a/arch/arm/mach-uniphier/clk/pll.h b/arch/arm/mach-uniphier/clk/pll.h new file mode 100644 index 0000000..d7e9303 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/pll.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef MACH_PLL_H +#define MACH_PLL_H + +#define UNIPHIER_PLL_FREQ_DEFAULT (0) + +void uniphier_ld4_dpll_ssc_en(void); + +int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, + unsigned int ssc_rate, unsigned int divn); +int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base); +int uniphier_ld20_vpll27_init(unsigned long reg_base); +int uniphier_ld20_dspll_init(unsigned long reg_base); + +#endif /* MACH_PLL_H */ diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h index b1b4cb0..02b3aab 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h +++ b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h @@ -1,41 +1,55 @@ /* * Copyright (C) 2016 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _DDRPHY_LD20_REGS_H #define _DDRPHY_LD20_REGS_H -#define PHY_SCL_DATA_0 0x00000104 -#define PHY_SCL_DATA_1 0x00000108 -#define PHY_SCL_LATENCY 0x0000010C -#define PHY_SCL_START 0x00000100 -#define PHY_SCL_CONFIG_1 0x00000118 -#define PHY_SCL_CONFIG_2 0x0000011C -#define PHY_PAD_CTRL 0x00000120 -#define PHY_DLL_RECALIB 0x00000124 -#define PHY_DLL_ADRCTRL 0x00000128 -#define PHY_LANE_SEL 0x0000012C -#define PHY_DLL_TRIM_1 0x00000130 -#define PHY_DLL_TRIM_2 0x00000134 -#define PHY_DLL_TRIM_3 0x00000138 -#define PHY_SCL_MAIN_CLK_DELTA 0x00000140 -#define PHY_WRLVL_AUTOINC_TRIM 0x0000014C -#define PHY_WRLVL_DYN_ODT 0x00000150 -#define PHY_WRLVL_ON_OFF 0x00000154 -#define PHY_UNQ_ANALOG_DLL_1 0x0000015C -#define PHY_DLL_INCR_TRIM_1 0x00000164 -#define PHY_DLL_INCR_TRIM_3 0x00000168 -#define PHY_SCL_CONFIG_3 0x0000016C -#define PHY_UNIQUIFY_TSMC_IO_1 0x00000170 -#define PHY_SCL_START_ADDR 0x00000188 -#define PHY_DSCL_CNT 0x0000019C -#define PHY_DLL_TRIM_CLK 0x000001A4 -#define PHY_DYNAMIC_BIT_LVL 0x000001AC -#define PHY_SCL_WINDOW_TRIM 0x000001B4 -#define PHY_DISABLE_GATING_FOR_SCL 0x000001B8 -#define PHY_SCL_CONFIG_4 0x000001BC -#define PHY_DYNAMIC_WRITE_BIT_LVL 0x000001C0 -#define PHY_VREF_TRAINING 0x000001C8 -#define PHY_SCL_GATE_TIMING 0x000001E0 +#define PHY_REG_SHIFT 2 + +#define PHY_SCL_START (0x40 << (PHY_REG_SHIFT)) +#define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT)) +#define PHY_SCL_DATA_1 (0x42 << (PHY_REG_SHIFT)) +#define PHY_SCL_LATENCY (0x43 << (PHY_REG_SHIFT)) +#define PHY_SCL_CONFIG_1 (0x46 << (PHY_REG_SHIFT)) +#define PHY_SCL_CONFIG_2 (0x47 << (PHY_REG_SHIFT)) +#define PHY_PAD_CTRL (0x48 << (PHY_REG_SHIFT)) +#define PHY_DLL_RECALIB (0x49 << (PHY_REG_SHIFT)) +#define PHY_DLL_ADRCTRL (0x4A << (PHY_REG_SHIFT)) +#define PHY_LANE_SEL (0x4B << (PHY_REG_SHIFT)) +#define PHY_DLL_TRIM_1 (0x4C << (PHY_REG_SHIFT)) +#define PHY_DLL_TRIM_2 (0x4D << (PHY_REG_SHIFT)) +#define PHY_DLL_TRIM_3 (0x4E << (PHY_REG_SHIFT)) +#define PHY_SCL_MAIN_CLK_DELTA (0x50 << (PHY_REG_SHIFT)) +#define PHY_WRLVL_AUTOINC_TRIM (0x53 << (PHY_REG_SHIFT)) +#define PHY_WRLVL_DYN_ODT (0x54 << (PHY_REG_SHIFT)) +#define PHY_WRLVL_ON_OFF (0x55 << (PHY_REG_SHIFT)) +#define PHY_UNQ_ANALOG_DLL_1 (0x57 << (PHY_REG_SHIFT)) +#define PHY_UNQ_ANALOG_DLL_2 (0x58 << (PHY_REG_SHIFT)) +#define PHY_DLL_INCR_TRIM_1 (0x59 << (PHY_REG_SHIFT)) +#define PHY_DLL_INCR_TRIM_3 (0x5A << (PHY_REG_SHIFT)) +#define PHY_SCL_CONFIG_3 (0x5B << (PHY_REG_SHIFT)) +#define PHY_UNIQUIFY_TSMC_IO_1 (0x5C << (PHY_REG_SHIFT)) +#define PHY_SCL_START_ADDR (0x62 << (PHY_REG_SHIFT)) +#define PHY_IP_DQ_DQS_BITWISE_TRIM (0x65 << (PHY_REG_SHIFT)) +#define PHY_DSCL_CNT (0x67 << (PHY_REG_SHIFT)) +#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM (0x68 << (PHY_REG_SHIFT)) +#define PHY_DLL_TRIM_CLK (0x69 << (PHY_REG_SHIFT)) +#define PHY_DYNAMIC_BIT_LVL (0x6B << (PHY_REG_SHIFT)) +#define PHY_SCL_WINDOW_TRIM (0x6D << (PHY_REG_SHIFT)) +#define PHY_DISABLE_GATING_FOR_SCL (0x6E << (PHY_REG_SHIFT)) +#define PHY_SCL_CONFIG_4 (0x6F << (PHY_REG_SHIFT)) +#define PHY_DYNAMIC_WRITE_BIT_LVL (0x70 << (PHY_REG_SHIFT)) +#define PHY_VREF_TRAINING (0x72 << (PHY_REG_SHIFT)) +#define PHY_SCL_GATE_TIMING (0x78 << (PHY_REG_SHIFT)) + +/* MASK */ +#define MSK_OP_DQ_DM_DQS_BITWISE_TRIM 0x0000007F +#define MSK_IP_DQ_DQS_BITWISE_TRIM 0x0000007F +#define MSK_OVERRIDE 0x00000080 + +#define PHY_BITLVL_DLY_WIDTH 6 #endif /* _DDRPHY_LD20_REGS_H */ diff --git a/arch/arm/mach-uniphier/dram/umc-ld20.c b/arch/arm/mach-uniphier/dram/umc-ld20.c index 186a398..1fdd119 100644 --- a/arch/arm/mach-uniphier/dram/umc-ld20.c +++ b/arch/arm/mach-uniphier/dram/umc-ld20.c @@ -1,7 +1,7 @@ /* * Copyright (C) 2016 Socionext Inc. * - * based on commit f7a4c9efe333fb1536efa86f9e96dc0ee109fedd of Diag + * based on commit a3c28918e86ad57127cf07bf8b32950cab20c03c of Diag * * SPDX-License-Identifier: GPL-2.0+ */ @@ -18,6 +18,7 @@ #include "umc64-regs.h" #define DRAM_CH_NR 3 +#define CONFIG_DDR_FREQ 1866 enum dram_freq { DRAM_FREQ_1866M, @@ -30,6 +31,268 @@ enum dram_size { DRAM_SZ_NR, }; +enum dram_board { /* board type */ + DRAM_BOARD_LD20_REF, /* LD20 reference */ + DRAM_BOARD_LD20_GLOBAL, /* LD20 TV */ + DRAM_BOARD_LD21_REF, /* LD21 reference */ + DRAM_BOARD_LD21_GLOBAL, /* LD21 TV */ + DRAM_BOARD_NR, +}; + +#define MSK_PHY_LANE_SEL 0x000000FF +#define MSK_BIT_SEL 0x00000F00 +#define MSK_DLL_MAS_DLY 0xFF000000 +#define MSK_MAS_DLY 0x7F000000 +#define MSK_DLLS_TRIM_CLK 0x000000FF + +#define PHY_DLL_MAS_DLY_WIDTH 8 +#define PHY_SLV_DLY_WIDTH 6 + +static void ddrphy_maskwritel(u32 data, u32 mask, void *addr) +{ + u32 value; + + value = (readl(addr) & ~mask) | (data & mask); + writel(value, addr); +} + +static u32 ddrphy_maskreadl(u32 mask, void *addr) +{ + return readl(addr) & mask; +} + +/* set phy_lane_sel.phy_lane_sel */ +static void ddrphy_set_phy_lane_sel(int val, void __iomem *phy_base) +{ + ddrphy_maskwritel(val, MSK_PHY_LANE_SEL, phy_base + PHY_LANE_SEL); +} + +/* set phy_lane_sel.bit_sel */ +static void ddrphy_set_bit_sel(int bit, void __iomem *phy_base) +{ + ddrphy_maskwritel(bit << 8, MSK_BIT_SEL, phy_base + PHY_LANE_SEL); +} + +/* Calculating step for PUB-byte */ +static int ddrphy_hpstep(int delay, void __iomem *phy_base) +{ + int mdl, freq; + + freq = CONFIG_DDR_FREQ; /* FIXME */ + mdl = ddrphy_maskreadl(MSK_DLL_MAS_DLY, phy_base + PHY_DLL_ADRCTRL) >> 24; + + return DIV_ROUND_CLOSEST(freq * delay * mdl, 2 * 1000000); +} + +static void ddrphy_set_dll_trim_clk(int delay_ckoffset, void __iomem *phy_base) +{ + u8 ck_step; /* ckoffset_step for clock */ + u32 ck_step_all; + + /* CK-Offset */ + if (delay_ckoffset >= 0) { + /* shift + direction */ + ck_step = min(ddrphy_hpstep(delay_ckoffset, phy_base), 127); + ck_step_all = ((0x1<<(PHY_SLV_DLY_WIDTH + 1))|ck_step); + } else{ + /* shift - direction */ + ck_step = min(ddrphy_hpstep(-1*delay_ckoffset, phy_base), 127); + ck_step_all = ck_step; + } + + ddrphy_set_phy_lane_sel(0, phy_base); + ddrphy_maskwritel(ck_step_all, MSK_DLLS_TRIM_CLK, phy_base + PHY_DLL_TRIM_CLK); +} + +static void ddrphy_set_dll_recalib(int delay_qoffset, u32 recalib_cnt, + u8 disable_recalib, u8 ctr_start_val, + void __iomem *phy_base) +{ + u8 dlls_trim_adrctrl_ma, incr_dly_adrctrl_ma; /* qoffset_step and flag for inc/dec */ + u32 recalib_all; /* all fields of register dll_recalib */ + + /* Q-Offset */ + if (delay_qoffset >= 0) { + dlls_trim_adrctrl_ma = min(ddrphy_hpstep(delay_qoffset, phy_base), 63); + incr_dly_adrctrl_ma = 0x1; + } else { + dlls_trim_adrctrl_ma = min(ddrphy_hpstep(-1*delay_qoffset, phy_base), 63); + incr_dly_adrctrl_ma = 0x0; + } + + recalib_all = ((ctr_start_val & 0xf) << 28) | + (incr_dly_adrctrl_ma << 27) | + ((disable_recalib & 0x1) << 26) | + ((recalib_cnt & 0x3ffff) << 8) | + (dlls_trim_adrctrl_ma & 0x3f); + + /* write value for all bits other than bit[7:6] */ + ddrphy_maskwritel(recalib_all, ~0xc0, phy_base + PHY_DLL_RECALIB); +} + +static void ddrphy_set_dll_adrctrl(int delay_qoffset, u8 override_adrctrl, + void __iomem *phy_base) +{ + u8 dlls_trim_adrctrl, incr_dly_adrctrl; /* qoffset_step for clock */ + u32 adrctrl_all; + + if (delay_qoffset >= 0) { + dlls_trim_adrctrl = min(ddrphy_hpstep(delay_qoffset, phy_base), 63); + incr_dly_adrctrl = 0x1; + } else { + dlls_trim_adrctrl = min(ddrphy_hpstep(-delay_qoffset, phy_base), 63); + incr_dly_adrctrl = 0x0; + } + + adrctrl_all = (incr_dly_adrctrl << 9) | + ((override_adrctrl & 0x1) << 8) | + dlls_trim_adrctrl; + + ddrphy_maskwritel(adrctrl_all, 0x33f, phy_base + PHY_DLL_ADRCTRL); +} + +/* dio */ +static int dio_adrctrl_0[DRAM_BOARD_NR][DRAM_CH_NR] = { + {268-262, 268-263, 268-378}, /* LD20 reference */ + {268-262, 268-263, 268-378}, /* LD20 TV */ + {268-212, 268-268, 0}, /* LD21 reference */ + {268-212, 268-268, 0}, /* LD21 TV */ +}; +static int dio_dlltrimclk_0[DRAM_BOARD_NR][DRAM_CH_NR] = { + {268, 268, 268}, /* LD20 reference */ + {268, 268, 268}, /* LD20 TV */ + {268, 268+252, 0}, /* LD21 reference */ + {268, 268+202, 0}, /* LD21 TV */ +}; +static int dio_dllrecalib_0[DRAM_BOARD_NR][DRAM_CH_NR] = { + {268-378, 268-263, 268-378}, /* LD20 reference */ + {268-378, 268-263, 268-378}, /* LD20 TV */ + {268-212, 268-536, 0}, /* LD21 reference */ + {268-212, 268-536, 0}, /* LD21 TV */ +}; + +static u32 dio_phy_pad_ctrl[DRAM_BOARD_NR][DRAM_CH_NR] = { + {0x50B840B1, 0x50B840B1, 0x50B840B1}, /* LD20 reference */ + {0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV */ + {0x50BB40B4, 0x50B840B1, 0x50BB40B1}, /* LD21 reference */ + {0x50BB40B4, 0x50B840B1, 0x50BB40B1}, /* LD21 TV */ +}; + +static u32 dio_scl_gate_timing[DRAM_CH_NR] = {0x00000140, 0x00000180, 0x00000140}; + +static int dio_op_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = { + { /* LD20 reference */ + { + 2, 1, 0, 1, 2, 1, 1, 1, 2, 1, 1, 2, 1, 1, 1, 1, + 1, 2, 1, 1, 1, 2, 1, 1, 2, 2, 0, 1, 1, 2, 2, 1, + }, + { + 1, 1, 0, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 2, 1, 2, 1, + }, + { + 2, 2, 0, 2, 1, 1, 2, 1, 1, 1, 0, 1, 1, -1, 1, 1, + 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 1, 2, + }, + }, + { /* LD20 TV */ + { + 2, 1, 0, 1, 2, 1, 1, 1, 2, 1, 1, 2, 1, 1, 1, 1, + 1, 2, 1, 1, 1, 2, 1, 1, 2, 2, 0, 1, 1, 2, 2, 1, + }, + { + 1, 1, 0, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 2, 1, 2, 1, + }, + { + 2, 2, 0, 2, 1, 1, 2, 1, 1, 1, 0, 1, 1, -1, 1, 1, + 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 1, 2, + }, + }, + { /* LD21 reference */ + { + 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 2, + 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, + }, + { 1, 0, 2, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, + 1, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, + }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + }, + { /* LD21 TV */ + { + 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 2, + 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, + }, + { 1, 0, 2, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, + 1, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, + }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + }, +}; +static int dio_ip_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = { + { /* LD20 reference */ + { + 3, 3, 3, 2, 3, 2, 0, 2, 2, 3, 3, 1, 2, 2, 2, 2, + 2, 2, 2, 2, 0, 1, 1, 1, 2, 2, 2, 2, 3, 0, 2, 2, + }, + { + 2, 2, 1, 1, -1, 1, 1, 1, 2, 0, 2, 2, 2, 1, 0, 2, + 2, 1, 2, 1, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, + }, + { + 2, 2, 3, 2, 1, 2, 2, 2, 2, 3, 4, 2, 3, 4, 3, 3, + 2, 2, 1, 2, 1, 1, 1, 1, 2, 2, 2, 2, 1, 2, 2, 1, + }, + }, + { /* LD20 TV */ + { + 3, 3, 3, 2, 3, 2, 0, 2, 2, 3, 3, 1, 2, 2, 2, 2, + 2, 2, 2, 2, 0, 1, 1, 1, 2, 2, 2, 2, 3, 0, 2, 2, + }, + { + 2, 2, 1, 1, -1, 1, 1, 1, 2, 0, 2, 2, 2, 1, 0, 2, + 2, 1, 2, 1, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, + }, + { + 2, 2, 3, 2, 1, 2, 2, 2, 2, 3, 4, 2, 3, 4, 3, 3, + 2, 2, 1, 2, 1, 1, 1, 1, 2, 2, 2, 2, 1, 2, 2, 1, + }, + }, + { /* LD21 reference */ + { + 2, 2, 2, 2, 1, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, + 2, 1, 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 1, 2, 2, 2, + }, + { + 3, 4, 4, 1, 0, 1, 1, 1, 1, 2, 1, 2, 2, 3, 3, 2, + 1, 0, 2, 1, 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 1, + }, + { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + }, + { /* LD21 TV */ + { + 2, 2, 2, 2, 1, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, + 2, 1, 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 1, 2, 2, 2, + }, + { + 3, 4, 4, 1, 0, 1, 1, 1, 1, 2, 1, 2, 2, 3, 3, 2, + 1, 0, 2, 1, 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 1, + }, + { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + }, +}; + /* umc */ static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11}; static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC}; @@ -37,15 +300,24 @@ static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF}; static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114}; static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0}; -static u32 umc_memconf0a[DRAM_FREQ_NR] = {0x00000801}; -static u32 umc_memconf0b[DRAM_FREQ_NR] = {0x00000130}; -static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00033803}; - +static u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = { + /* 256MB 512MB */ + {0x00000601, 0x00000801}, /* 1866 MHz */ +}; +static u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = { + /* 256MB 512MB */ + {0x00000120, 0x00000130}, /* 1866 MHz */ +}; +static u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = { + /* 256MB 512MB */ + {0x00033603, 0x00033803}, /* 1866 MHz */ +}; static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20}; static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08}; static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04}; static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = { - {0x0049071D, 0x0078071D}, + /* 256MB 512MB */ + {0x0049071D, 0x0078071D}, /* 1866 MHz */ }; static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610}; @@ -61,12 +333,22 @@ static u32 umc_directbusctrla[DRAM_CH_NR] = { 0x00000000, 0x00000001, 0x00000001 }; +/* polling function for PHY Init Complete */ +static void ddrphy_init_complete(void __iomem *dc_base) +{ + /* Wait for PHY Init Complete */ + while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0))) + cpu_relax(); +} + /* DDR PHY */ -static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq) +static void ddrphy_init(void __iomem *phy_base, void __iomem *dc_base, + enum dram_freq freq, enum dram_board board, int ch) { - writel(0x00000001, phy_base + PHY_UNIQUIFY_TSMC_IO_1); - while ((readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1))) + writel(0x0C001001, phy_base + PHY_UNIQUIFY_TSMC_IO_1); + while (!(readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1))) cpu_relax(); + writel(0x0C001000, phy_base + PHY_UNIQUIFY_TSMC_IO_1); writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3); writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1); @@ -84,14 +366,14 @@ static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq) writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM); writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1); - writel(0x50bb40b1, phy_base + PHY_PAD_CTRL); + writel(dio_phy_pad_ctrl[board][ch], phy_base + PHY_PAD_CTRL); writel(0x00000070, phy_base + PHY_VREF_TRAINING); writel(0x01000075, phy_base + PHY_SCL_CONFIG_1); writel(0x00000501, phy_base + PHY_SCL_CONFIG_2); writel(0x00000000, phy_base + PHY_SCL_CONFIG_3); writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL); writel(0x00000000, phy_base + PHY_SCL_CONFIG_4); - writel(0x000000a0, phy_base + PHY_SCL_GATE_TIMING); + writel(dio_scl_gate_timing[ch], phy_base + PHY_SCL_GATE_TIMING); writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT); writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF); writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL); @@ -99,30 +381,96 @@ static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq) writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK); writel(0xa800100d, phy_base + PHY_DLL_RECALIB); writel(0x00005076, phy_base + PHY_SCL_LATENCY); + + ddrphy_init_complete(dc_base); + + ddrphy_set_dll_adrctrl(dio_adrctrl_0[board][ch], 0, phy_base); + ddrphy_set_dll_trim_clk(dio_dlltrimclk_0[board][ch], phy_base); + ddrphy_set_dll_recalib(dio_dllrecalib_0[board][ch], 0x10, 0, 0xa, + phy_base); +} + +static void ddrphy_shift_dq(u32 reg_mask, u32 reg_addr, int shift_val, + void __iomem *phy_base) +{ + u32 reg_val; + int dq_val; + + reg_val = ddrphy_maskreadl(reg_mask, phy_base + reg_addr) & 0x7f; + dq_val = reg_val & 0x3f; + + if ((reg_val & 0x40) == 0x00) + dq_val = -1 * dq_val; + + /* value shift*/ + dq_val = dq_val + shift_val; + + if (dq_val >= 0) + reg_val = 0x40 + (dq_val & 0x3f); + else + reg_val = ((-1 * dq_val) & 0x3f); + + ddrphy_maskwritel(reg_val, reg_mask, phy_base + reg_addr); } -static int ddrphy_training(void __iomem *phy_base) +static void ddrphy_shift(void __iomem *phy_base, enum dram_board board, int ch) +{ + u32 dx, bit; + + /* set override = 1 */ + ddrphy_maskwritel(MSK_OVERRIDE, MSK_OVERRIDE, + phy_base + PHY_OP_DQ_DM_DQS_BITWISE_TRIM); + ddrphy_maskwritel(MSK_OVERRIDE, MSK_OVERRIDE, + phy_base + PHY_IP_DQ_DQS_BITWISE_TRIM); + + for (dx = 0; dx < 4; dx++) { + /* set byte to PHY_LANE_SEL.phy_lane_sel= dx * (PHY_BITLVL_DLY_WIDTH+1) */ + ddrphy_set_phy_lane_sel(dx * (PHY_BITLVL_DLY_WIDTH + 1), + phy_base); + + for (bit = 0; bit < 8; bit++) { + ddrphy_set_bit_sel(bit, phy_base); + + /* shift write reg value*/ + ddrphy_shift_dq(MSK_OP_DQ_DM_DQS_BITWISE_TRIM, + PHY_OP_DQ_DM_DQS_BITWISE_TRIM, + dio_op_dq_shift_val[board][ch][dx * 8 + bit], + phy_base); + /* shift read reg value */ + ddrphy_shift_dq(MSK_IP_DQ_DQS_BITWISE_TRIM, + PHY_IP_DQ_DQS_BITWISE_TRIM, + dio_ip_dq_shift_val[board][ch][dx * 8 + bit], + phy_base); + } + + } + ddrphy_set_phy_lane_sel(0, phy_base); + ddrphy_set_bit_sel(0, phy_base); +} + +static int ddrphy_training(void __iomem *phy_base, enum dram_board board, + int ch) { writel(0x0000000f, phy_base + PHY_WRLVL_AUTOINC_TRIM); writel(0x00010000, phy_base + PHY_DLL_TRIM_2); writel(0x50000000, phy_base + PHY_SCL_START); - while ((readl(phy_base + PHY_SCL_START) & BIT(28))) + while (readl(phy_base + PHY_SCL_START) & BIT(28)) cpu_relax(); writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL); writel(0xff00ff00, phy_base + PHY_SCL_DATA_0); writel(0xff00ff00, phy_base + PHY_SCL_DATA_1); - writel(0x00080000, phy_base + PHY_SCL_START_ADDR); + writel(0xFBF8FFFF, phy_base + PHY_SCL_START_ADDR); writel(0x11000000, phy_base + PHY_SCL_START); - while ((readl(phy_base + PHY_SCL_START) & BIT(28))) + while (readl(phy_base + PHY_SCL_START) & BIT(28)) cpu_relax(); - writel(0x00000000, phy_base + PHY_SCL_START_ADDR); + writel(0xFBF0FFFF, phy_base + PHY_SCL_START_ADDR); writel(0x30500000, phy_base + PHY_SCL_START); - while ((readl(phy_base + PHY_SCL_START) & BIT(28))) + while (readl(phy_base + PHY_SCL_START) & BIT(28)) cpu_relax(); writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL); @@ -131,16 +479,22 @@ static int ddrphy_training(void __iomem *phy_base) writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1); writel(0x11000000, phy_base + PHY_SCL_START); - while ((readl(phy_base + PHY_SCL_START) & BIT(28))) + while (readl(phy_base + PHY_SCL_START) & BIT(28)) cpu_relax(); writel(0x34000000, phy_base + PHY_SCL_START); - while ((readl(phy_base + PHY_SCL_START) & BIT(28))) + while (readl(phy_base + PHY_SCL_START) & BIT(28)) cpu_relax(); writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL); + writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL); + writel(0x00003270, phy_base + PHY_DYNAMIC_BIT_LVL); + writel(0x011BD0C4, phy_base + PHY_DSCL_CNT); + + /* shift ip_dq, op_dq trim */ + ddrphy_shift(phy_base, board, ch); return 0; } @@ -164,10 +518,6 @@ static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, return -EINVAL; } - /* Wait for PHY Init Complete */ - while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0))) - cpu_relax(); - writel(0x00000001, dc_base + UMC_DFICSOVRRD); writel(0x00000000, dc_base + UMC_DFITURNOFF); @@ -180,9 +530,9 @@ static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, writel(umc_drmmr2[freq], dc_base + UMC_DRMMR2); writel(0x00000000, dc_base + UMC_DRMMR3); - writel(umc_memconf0a[freq], dc_base + UMC_MEMCONF0A); - writel(umc_memconf0b[freq], dc_base + UMC_MEMCONF0B); - writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH); + writel(umc_memconf0a[freq][size_e], dc_base + UMC_MEMCONF0A); + writel(umc_memconf0b[freq][size_e], dc_base + UMC_MEMCONF0B); + writel(umc_memconfch[freq][size_e], dc_base + UMC_MEMCONFCH); writel(0x00000008, dc_base + UMC_MEMMAPSET); writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA); @@ -227,7 +577,8 @@ static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, } static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base, - enum dram_freq freq, unsigned long size, int ch) + enum dram_freq freq, enum dram_board board, + unsigned long size, int ch) { void __iomem *dc_base = umc_ch_base + 0x00011000; void __iomem *phy_base = phy_ch_base; @@ -240,13 +591,13 @@ static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base, writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST, dc_base + UMC_DIOCTLA); - ddrphy_init(phy_base, freq); + ddrphy_init(phy_base, dc_base, freq, board, ch); ret = umc_dc_init(dc_base, freq, size, ch); if (ret) return ret; - ret = ddrphy_training(phy_base); + ret = ddrphy_training(phy_base, board, ch); if (ret) return ret; @@ -274,6 +625,7 @@ int uniphier_ld20_umc_init(const struct uniphier_board_data *bd) void __iomem *umc_ch_base = (void __iomem *)0x5b800000; void __iomem *phy_ch_base = (void __iomem *)0x6e200000; enum dram_freq freq; + enum dram_board board; int ch, ret; switch (bd->dram_freq) { @@ -285,11 +637,30 @@ int uniphier_ld20_umc_init(const struct uniphier_board_data *bd) return -EINVAL; } + switch (UNIPHIER_BD_BOARD_GET_TYPE(bd->flags)) { + case UNIPHIER_BD_BOARD_LD20_REF: + board = DRAM_BOARD_LD20_REF; + break; + case UNIPHIER_BD_BOARD_LD20_GLOBAL: + board = DRAM_BOARD_LD20_GLOBAL; + break; + case UNIPHIER_BD_BOARD_LD21_REF: + board = DRAM_BOARD_LD21_REF; + break; + case UNIPHIER_BD_BOARD_LD21_GLOBAL: + board = DRAM_BOARD_LD21_GLOBAL; + break; + default: + pr_err("unsupported board type %d\n", + UNIPHIER_BD_BOARD_GET_TYPE(bd->flags)); + return -EINVAL; + } + for (ch = 0; ch < bd->dram_nr_ch; ch++) { unsigned long size = bd->dram_ch[ch].size; unsigned int width = bd->dram_ch[ch].width; - ret = umc_ch_init(umc_ch_base, phy_ch_base, freq, + ret = umc_ch_init(umc_ch_base, phy_ch_base, freq, board, size / (width / 16), ch); if (ret) { pr_err("failed to initialize UMC ch%d\n", ch); diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile deleted file mode 100644 index 755a361..0000000 --- a/arch/arm/mach-uniphier/early-clk/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-clk-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_LD4) += early-clk-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += early-clk-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o -obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile b/arch/arm/mach-uniphier/early-pinctrl/Makefile deleted file mode 100644 index 7177a8c..0000000 --- a/arch/arm/mach-uniphier/early-pinctrl/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-pinctrl-sld3.o -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-pinctrl-ld20.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-pinctrl-ld20.o diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c deleted file mode 100644 index 537deaf..0000000 --- a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include "../init.h" -#include "../sg-regs.h" - -int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd) -{ - /* Comment format: PAD Name -> Function Name */ - sg_set_pinsel(0, 0, 8, 4); /* XECS1 -> XECS1 */ - sg_set_pinsel(1, 0, 8, 4); /* ERXW -> ERXW */ - sg_set_pinsel(2, 0, 8, 4); /* XERWE1 -> XERWE1 */ - sg_set_pinsel(6, 2, 8, 4); /* XNFRE -> XERWE0 */ - sg_set_pinsel(7, 2, 8, 4); /* XNFWE -> ES0 */ - sg_set_pinsel(8, 2, 8, 4); /* NFALE -> ES1 */ - sg_set_pinsel(9, 2, 8, 4); /* NFCLE -> ES2 */ - sg_set_pinsel(10, 2, 8, 4); /* NFD0 -> ED0 */ - sg_set_pinsel(11, 2, 8, 4); /* NFD1 -> ED1 */ - sg_set_pinsel(12, 2, 8, 4); /* NFD2 -> ED2 */ - sg_set_pinsel(13, 2, 8, 4); /* NFD3 -> ED3 */ - sg_set_pinsel(14, 2, 8, 4); /* NFD4 -> ED4 */ - sg_set_pinsel(15, 2, 8, 4); /* NFD5 -> ED5 */ - sg_set_pinsel(16, 2, 8, 4); /* NFD6 -> ED6 */ - sg_set_pinsel(17, 2, 8, 4); /* NFD7 -> ED7 */ - sg_set_iectrl_range(0, 2); - sg_set_iectrl_range(6, 17); - - return 0; -} diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c deleted file mode 100644 index 6c5d58f..0000000 --- a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include "../init.h" -#include "../sg-regs.h" - -int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_UNIPHIER_SERIAL - sg_set_pinsel(63, 0, 4, 4); /* RXD0 */ - sg_set_pinsel(64, 1, 4, 4); /* TXD0 */ - - sg_set_pinsel(65, 0, 4, 4); /* RXD1 */ - sg_set_pinsel(66, 1, 4, 4); /* TXD1 */ - - sg_set_pinsel(96, 2, 4, 4); /* RXD2 */ - sg_set_pinsel(102, 2, 4, 4); /* TXD2 */ -#endif - - sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */ - - return 0; -} diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index db80074..4e3bee1 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -23,9 +23,17 @@ struct uniphier_board_data { unsigned int dram_nr_ch; struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH]; unsigned int flags; -#define UNIPHIER_BD_DDR3PLUS BIT(2) -#define UNIPHIER_BD_PACKAGE_LD21 1 -#define UNIPHIER_BD_PACKAGE_TYPE(f) ((f) & 0x3) + +#define UNIPHIER_BD_DPLL_SSC_GET_RATE(f) (((f) >> 8) & 0x3) +#define UNIPHIER_BD_DPLL_SSC_RATE(r) (((r) & 0x3) << 8) + +#define UNIPHIER_BD_DDR3PLUS BIT(2) + +#define UNIPHIER_BD_BOARD_GET_TYPE(f) ((f) & 0x3) +#define UNIPHIER_BD_BOARD_LD20_REF 0 /* LD20 reference */ +#define UNIPHIER_BD_BOARD_LD20_GLOBAL 1 /* LD20 TV Set */ +#define UNIPHIER_BD_BOARD_LD21_REF 2 /* LD21 reference */ +#define UNIPHIER_BD_BOARD_LD21_GLOBAL 3 /* LD21 TV Set */ }; const struct uniphier_board_data *uniphier_get_board_param(void); @@ -75,13 +83,12 @@ int memconf_init(const struct uniphier_board_data *bd); int uniphier_sld3_memconf_init(const struct uniphier_board_data *bd); int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd); -int uniphier_sld3_pll_init(const struct uniphier_board_data *bd); -int uniphier_ld4_pll_init(const struct uniphier_board_data *bd); -int uniphier_pro4_pll_init(const struct uniphier_board_data *bd); -int uniphier_sld8_pll_init(const struct uniphier_board_data *bd); - -int uniphier_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd); -int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd); +int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd); +int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd); +int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd); +int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd); +int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd); +int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd); int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd); int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd); @@ -89,9 +96,6 @@ int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd); int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd); int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd); -int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd); -int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd); - int uniphier_ld4_umc_init(const struct uniphier_board_data *bd); int uniphier_pro4_umc_init(const struct uniphier_board_data *bd); int uniphier_sld8_umc_init(const struct uniphier_board_data *bd); @@ -99,14 +103,11 @@ int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd); int uniphier_ld20_umc_init(const struct uniphier_board_data *bd); int uniphier_ld11_umc_init(const struct uniphier_board_data *bd); -void uniphier_sld3_pin_init(void); -void uniphier_ld4_pin_init(void); -void uniphier_pro4_pin_init(void); -void uniphier_sld8_pin_init(void); -void uniphier_pro5_pin_init(void); -void uniphier_pxs2_pin_init(void); -void uniphier_ld6b_pin_init(void); -void uniphier_ld20_pin_init(void); +void uniphier_sld3_pll_init(void); +void uniphier_ld4_pll_init(void); +void uniphier_pro4_pll_init(void); +void uniphier_ld11_pll_init(void); +int uniphier_ld20_pll_init(const struct uniphier_board_data *bd); void uniphier_ld4_clk_init(void); void uniphier_pro4_clk_init(void); @@ -115,6 +116,8 @@ void uniphier_pxs2_clk_init(void); void uniphier_ld11_clk_init(void); void uniphier_ld20_clk_init(void); +int uniphier_pin_init(const char *pinconfig_name); +void uniphier_smp_kick_all_cpus(void); void cci500_init(int nr_slaves); #define pr_err(fmt, args...) printf(fmt, ##args) diff --git a/arch/arm/mach-uniphier/init/init-ld11.c b/arch/arm/mach-uniphier/init/init-ld11.c index de2dc62..e324c94 100644 --- a/arch/arm/mach-uniphier/init/init-ld11.c +++ b/arch/arm/mach-uniphier/init/init-ld11.c @@ -15,7 +15,7 @@ int uniphier_ld11_init(const struct uniphier_board_data *bd) { uniphier_sbc_init_savepin(bd); uniphier_pxs2_sbc_init(bd); - uniphier_ld20_early_pin_init(bd); + uniphier_pin_init("system_bus_grp"); support_card_reset(); @@ -31,12 +31,14 @@ int uniphier_ld11_init(const struct uniphier_board_data *bd) led_puts("L2"); - led_puts("L3"); - #ifdef CONFIG_SPL_SERIAL_SUPPORT preloader_console_init(); #endif + led_puts("L3"); + + uniphier_ld11_dpll_init(bd); + led_puts("L4"); { diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c index 7f66053..cb05421 100644 --- a/arch/arm/mach-uniphier/init/init-ld20.c +++ b/arch/arm/mach-uniphier/init/init-ld20.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -14,7 +15,7 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd) { uniphier_sbc_init_savepin(bd); uniphier_pxs2_sbc_init(bd); - uniphier_ld20_early_pin_init(bd); + uniphier_pin_init("system_bus_grp"); support_card_reset(); @@ -31,12 +32,14 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd) led_puts("L2"); - led_puts("L3"); - #ifdef CONFIG_SPL_SERIAL_SUPPORT preloader_console_init(); #endif + led_puts("L3"); + + uniphier_ld20_dpll_init(bd); + led_puts("L4"); { diff --git a/arch/arm/mach-uniphier/init/init-ld4.c b/arch/arm/mach-uniphier/init/init-ld4.c index b1c9b5d..2f4c60d 100644 --- a/arch/arm/mach-uniphier/init/init-ld4.c +++ b/arch/arm/mach-uniphier/init/init-ld4.c @@ -1,5 +1,7 @@ /* - * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2013-2015 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -19,7 +21,7 @@ int uniphier_ld4_init(const struct uniphier_board_data *bd) support_card_reset(); - uniphier_ld4_pll_init(bd); + uniphier_ld4_dpll_init(bd); support_card_init(); @@ -53,9 +55,5 @@ int uniphier_ld4_init(const struct uniphier_board_data *bd) led_puts("L5"); - uniphier_ld4_enable_dpll_ssc(bd); - - led_puts("L6"); - return 0; } diff --git a/arch/arm/mach-uniphier/init/init-pro4.c b/arch/arm/mach-uniphier/init/init-pro4.c index 3528d84..2825150 100644 --- a/arch/arm/mach-uniphier/init/init-pro4.c +++ b/arch/arm/mach-uniphier/init/init-pro4.c @@ -1,5 +1,7 @@ /* - * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2013-2015 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -16,7 +18,7 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd) support_card_reset(); - uniphier_pro4_pll_init(bd); + uniphier_pro4_dpll_init(bd); support_card_init(); @@ -50,9 +52,5 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd) led_puts("L5"); - uniphier_ld4_enable_dpll_ssc(bd); - - led_puts("L6"); - return 0; } diff --git a/arch/arm/mach-uniphier/init/init-sld3.c b/arch/arm/mach-uniphier/init/init-sld3.c index 50fcbb0..ee3245c 100644 --- a/arch/arm/mach-uniphier/init/init-sld3.c +++ b/arch/arm/mach-uniphier/init/init-sld3.c @@ -1,5 +1,7 @@ /* - * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2013-2015 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -16,11 +18,9 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd) uniphier_sbc_init_admulti(bd); - uniphier_sld3_early_pin_init(bd); - support_card_reset(); - uniphier_sld3_pll_init(bd); + uniphier_sld3_dpll_init(bd); support_card_init(); @@ -45,9 +45,5 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd) led_puts("L5"); - uniphier_sld3_enable_dpll_ssc(bd); - - led_puts("L6"); - return 0; } diff --git a/arch/arm/mach-uniphier/init/init-sld8.c b/arch/arm/mach-uniphier/init/init-sld8.c index 07c6d60..82d036b 100644 --- a/arch/arm/mach-uniphier/init/init-sld8.c +++ b/arch/arm/mach-uniphier/init/init-sld8.c @@ -1,5 +1,7 @@ /* - * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2013-2015 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -19,7 +21,7 @@ int uniphier_sld8_init(const struct uniphier_board_data *bd) support_card_reset(); - uniphier_sld8_pll_init(bd); + uniphier_sld8_dpll_init(bd); support_card_init(); @@ -53,9 +55,5 @@ int uniphier_sld8_init(const struct uniphier_board_data *bd) led_puts("L5"); - uniphier_ld4_enable_dpll_ssc(bd); - - led_puts("L6"); - return 0; } diff --git a/arch/arm/mach-uniphier/micro-support-card.c b/arch/arm/mach-uniphier/micro-support-card.c index 6987d1e..04e6558 100644 --- a/arch/arm/mach-uniphier/micro-support-card.c +++ b/arch/arm/mach-uniphier/micro-support-card.c @@ -49,7 +49,7 @@ static int support_card_show_revision(void) return 0; } -int check_support_card(void) +int checkboard(void) { printf("SC: Micro Support Card "); return support_card_show_revision(); diff --git a/arch/arm/mach-uniphier/micro-support-card.h b/arch/arm/mach-uniphier/micro-support-card.h index 5da0ada..4dae603 100644 --- a/arch/arm/mach-uniphier/micro-support-card.h +++ b/arch/arm/mach-uniphier/micro-support-card.h @@ -1,17 +1,18 @@ /* - * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2012-2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef ARCH_BOARD_H -#define ARCH_BOARD_H +#ifndef MICRO_SUPPORT_CARD_H +#define MICRO_SUPPORT_CARD_H #if defined(CONFIG_MICRO_SUPPORT_CARD) void support_card_reset(void); void support_card_init(void); void support_card_late_init(void); -int check_support_card(void); void led_puts(const char *s); #else static inline void support_card_reset(void) @@ -26,14 +27,9 @@ static inline void support_card_late_init(void) { } -static inline int check_support_card(void) -{ - return 0; -} - static inline void led_puts(const char *s) { } #endif -#endif /* ARCH_BOARD_H */ +#endif /* MICRO_SUPPORT_CARD_H */ diff --git a/arch/arm/mach-uniphier/pinctrl-glue.c b/arch/arm/mach-uniphier/pinctrl-glue.c new file mode 100644 index 0000000..48549e3 --- /dev/null +++ b/arch/arm/mach-uniphier/pinctrl-glue.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/err.h> +#include <dm/device.h> +#include <dm/pinctrl.h> +#include <dm/uclass.h> + +#include "init.h" + +int uniphier_pin_init(const char *pinconfig_name) +{ + struct udevice *pctldev, *config, *next; + int ret; + + ret = uclass_first_device(UCLASS_PINCTRL, &pctldev); + if (ret) + return ret; + + device_foreach_child_safe(config, next, pctldev) { + if (strcmp(config->name, pinconfig_name)) + continue; + + return pinctrl_generic_set_state(pctldev, config); + } + + return -ENODEV; +} diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile deleted file mode 100644 index 7f4d9f7..0000000 --- a/arch/arm/mach-uniphier/pinctrl/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += pinctrl-sld3.o -obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pinctrl-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += pinctrl-pro4.o -obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pinctrl-sld8.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += pinctrl-pro5.o -obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += pinctrl-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += pinctrl-ld6b.o -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pinctrl-ld20.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pinctrl-ld20.o diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c deleted file mode 100644 index 645b901..0000000 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sg-regs.h" - -void uniphier_ld20_pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(3, 0, 8, 4); /* XNFWP -> XNFWP */ - sg_set_pinsel(4, 0, 8, 4); /* XNFCE0 -> XNFCE0 */ - sg_set_pinsel(5, 0, 8, 4); /* NFRYBY0 -> NFRYBY0 */ - sg_set_pinsel(6, 0, 8, 4); /* XNFRE -> XNFRE */ - sg_set_pinsel(7, 0, 8, 4); /* XNFWE -> XNFWE */ - sg_set_pinsel(8, 0, 8, 4); /* NFALE -> NFALE */ - sg_set_pinsel(9, 0, 8, 4); /* NFCLE -> NFCLE */ - sg_set_pinsel(10, 0, 8, 4); /* NFD0 -> NFD0 */ - sg_set_pinsel(11, 0, 8, 4); /* NFD1 -> NFD1 */ - sg_set_pinsel(12, 0, 8, 4); /* NFD2 -> NFD2 */ - sg_set_pinsel(13, 0, 8, 4); /* NFD3 -> NFD3 */ - sg_set_pinsel(14, 0, 8, 4); /* NFD4 -> NFD4 */ - sg_set_pinsel(15, 0, 8, 4); /* NFD5 -> NFD5 */ - sg_set_pinsel(16, 0, 8, 4); /* NFD6 -> NFD6 */ - sg_set_pinsel(17, 0, 8, 4); /* NFD7 -> NFD7 */ - sg_set_iectrl_range(3, 17); -#endif - -#ifdef CONFIG_USB_XHCI_UNIPHIER - sg_set_pinsel(46, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(47, 0, 8, 4); /* USB0OD -> USB0OD */ - sg_set_pinsel(48, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(49, 0, 8, 4); /* USB1OD -> USB1OD */ - sg_set_pinsel(50, 0, 8, 4); /* USB2VBUS -> USB2VBUS */ - sg_set_pinsel(51, 0, 8, 4); /* USB2OD -> USB2OD */ - sg_set_pinsel(52, 0, 8, 4); /* USB3VBUS -> USB3VBUS */ - sg_set_pinsel(53, 0, 8, 4); /* USB3OD -> USB3OD */ - sg_set_iectrl_range(46, 53); -#endif - - sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ - sg_set_iectrl(149); - sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ - sg_set_iectrl(153); -} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c deleted file mode 100644 index 625d40c..0000000 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sg-regs.h" - -void uniphier_ld4_pin_init(void) -{ - u32 tmp; - - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(158, 0, 8, 4); /* XNFRE -> XNFRE_GB */ - sg_set_pinsel(159, 0, 8, 4); /* XNFWE -> XNFWE_GB */ - sg_set_pinsel(160, 0, 8, 4); /* XFALE -> NFALE_GB */ - sg_set_pinsel(161, 0, 8, 4); /* XFCLE -> NFCLE_GB */ - sg_set_pinsel(162, 0, 8, 4); /* XNFWP -> XFNWP_GB */ - sg_set_pinsel(163, 0, 8, 4); /* XNFCE0 -> XNFCE0_GB */ - sg_set_pinsel(164, 0, 8, 4); /* NANDRYBY0 -> NANDRYBY0_GB */ - sg_set_pinsel(22, 0, 8, 4); /* MMCCLK -> XFNCE1_GB */ - sg_set_pinsel(23, 0, 8, 4); /* MMCCMD -> NANDRYBY1_GB */ - sg_set_pinsel(24, 0, 8, 4); /* MMCDAT0 -> NFD0_GB */ - sg_set_pinsel(25, 0, 8, 4); /* MMCDAT1 -> NFD1_GB */ - sg_set_pinsel(26, 0, 8, 4); /* MMCDAT2 -> NFD2_GB */ - sg_set_pinsel(27, 0, 8, 4); /* MMCDAT3 -> NFD3_GB */ - sg_set_pinsel(28, 0, 8, 4); /* MMCDAT4 -> NFD4_GB */ - sg_set_pinsel(29, 0, 8, 4); /* MMCDAT5 -> NFD5_GB */ - sg_set_pinsel(30, 0, 8, 4); /* MMCDAT6 -> NFD6_GB */ - sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */ -#endif - - tmp = readl(SG_IECTRL); - tmp |= 0x41; - writel(tmp, SG_IECTRL); -} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c deleted file mode 100644 index 913722b..0000000 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sg-regs.h" - -void uniphier_ld6b_pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(30, 0, 8, 4); /* XNFRE -> XNFRE */ - sg_set_pinsel(31, 0, 8, 4); /* XNFWE -> XNFWE */ - sg_set_pinsel(32, 0, 8, 4); /* NFALE -> NFALE */ - sg_set_pinsel(33, 0, 8, 4); /* NFCLE -> NFCLE */ - sg_set_pinsel(34, 0, 8, 4); /* XNFWP -> XNFWP */ - sg_set_pinsel(35, 0, 8, 4); /* XNFCE0 -> XNFCE0 */ - sg_set_pinsel(36, 0, 8, 4); /* NRYBY0 -> NRYBY0 */ - sg_set_pinsel(37, 0, 8, 4); /* XNFCE1 -> NRYBY1 */ - sg_set_pinsel(38, 0, 8, 4); /* NRYBY1 -> XNFCE1 */ - sg_set_pinsel(39, 0, 8, 4); /* NFD0 -> NFD0 */ - sg_set_pinsel(40, 0, 8, 4); /* NFD1 -> NFD1 */ - sg_set_pinsel(41, 0, 8, 4); /* NFD2 -> NFD2 */ - sg_set_pinsel(42, 0, 8, 4); /* NFD3 -> NFD3 */ - sg_set_pinsel(43, 0, 8, 4); /* NFD4 -> NFD4 */ - sg_set_pinsel(44, 0, 8, 4); /* NFD5 -> NFD5 */ - sg_set_pinsel(45, 0, 8, 4); /* NFD6 -> NFD6 */ - sg_set_pinsel(46, 0, 8, 4); /* NFD7 -> NFD7 */ -#endif - -#ifdef CONFIG_USB_XHCI_UNIPHIER - sg_set_pinsel(56, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(57, 0, 8, 4); /* USB0OD -> USB0OD */ - sg_set_pinsel(58, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(59, 0, 8, 4); /* USB1OD -> USB1OD */ - sg_set_pinsel(60, 0, 8, 4); /* USB2VBUS -> USB2VBUS */ - sg_set_pinsel(61, 0, 8, 4); /* USB2OD -> USB2OD */ - sg_set_pinsel(62, 0, 8, 4); /* USB3VBUS -> USB3VBUS */ - sg_set_pinsel(63, 0, 8, 4); /* USB3OD -> USB3OD */ -#endif -} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c deleted file mode 100644 index 3796491..0000000 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sg-regs.h" - -void uniphier_pro4_pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(40, 0, 4, 8); /* NFD0 -> NFD0 */ - sg_set_pinsel(41, 0, 4, 8); /* NFD1 -> NFD1 */ - sg_set_pinsel(42, 0, 4, 8); /* NFD2 -> NFD2 */ - sg_set_pinsel(43, 0, 4, 8); /* NFD3 -> NFD3 */ - sg_set_pinsel(44, 0, 4, 8); /* NFD4 -> NFD4 */ - sg_set_pinsel(45, 0, 4, 8); /* NFD5 -> NFD5 */ - sg_set_pinsel(46, 0, 4, 8); /* NFD6 -> NFD6 */ - sg_set_pinsel(47, 0, 4, 8); /* NFD7 -> NFD7 */ - sg_set_pinsel(48, 0, 4, 8); /* NFALE -> NFALE */ - sg_set_pinsel(49, 0, 4, 8); /* NFCLE -> NFCLE */ - sg_set_pinsel(50, 0, 4, 8); /* XNFRE -> XNFRE */ - sg_set_pinsel(51, 0, 4, 8); /* XNFWE -> XNFWE */ - sg_set_pinsel(52, 0, 4, 8); /* XNFWP -> XNFWP */ - sg_set_pinsel(53, 0, 4, 8); /* XNFCE0 -> XNFCE0 */ - sg_set_pinsel(54, 0, 4, 8); /* NRYBY0 -> NRYBY0 */ - /* sg_set_pinsel(131, 1, 4, 8); */ /* RXD2 -> NRYBY1 */ - /* sg_set_pinsel(132, 1, 4, 8); */ /* TXD2 -> XNFCE1 */ -#endif - -#ifdef CONFIG_USB_XHCI_UNIPHIER - sg_set_pinsel(180, 0, 4, 8); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(181, 0, 4, 8); /* USB0OD -> USB0OD */ - sg_set_pinsel(182, 0, 4, 8); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */ -#endif - - writel(1, SG_LOADPINCTRL); -} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c deleted file mode 100644 index 32ba923..0000000 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sg-regs.h" - -void uniphier_pro5_pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(19, 0, 4, 8); /* XNFRE -> XNFRE */ - sg_set_pinsel(20, 0, 4, 8); /* XNFWE -> XNFWE */ - sg_set_pinsel(21, 0, 4, 8); /* NFALE -> NFALE */ - sg_set_pinsel(22, 0, 4, 8); /* NFCLE -> NFCLE */ - sg_set_pinsel(23, 0, 4, 8); /* XNFWP -> XNFWP */ - sg_set_pinsel(24, 0, 4, 8); /* XNFCE0 -> XNFCE0 */ - sg_set_pinsel(25, 0, 4, 8); /* NRYBY0 -> NRYBY0 */ - sg_set_pinsel(26, 0, 4, 8); /* XNFCE1 -> XNFCE1 */ - sg_set_pinsel(27, 0, 4, 8); /* NRYBY1 -> NRYBY1 */ - sg_set_pinsel(28, 0, 4, 8); /* NFD0 -> NFD0 */ - sg_set_pinsel(29, 0, 4, 8); /* NFD1 -> NFD1 */ - sg_set_pinsel(30, 0, 4, 8); /* NFD2 -> NFD2 */ - sg_set_pinsel(31, 0, 4, 8); /* NFD3 -> NFD3 */ - sg_set_pinsel(32, 0, 4, 8); /* NFD4 -> NFD4 */ - sg_set_pinsel(33, 0, 4, 8); /* NFD5 -> NFD5 */ - sg_set_pinsel(34, 0, 4, 8); /* NFD6 -> NFD6 */ - sg_set_pinsel(35, 0, 4, 8); /* NFD7 -> NFD7 */ -#endif - -#ifdef CONFIG_USB_XHCI_UNIPHIER - sg_set_pinsel(124, 0, 4, 8); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(125, 0, 4, 8); /* USB0OD -> USB0OD */ - sg_set_pinsel(126, 0, 4, 8); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(127, 0, 4, 8); /* USB1OD -> USB1OD */ -#endif - - writel(1, SG_LOADPINCTRL); -} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c deleted file mode 100644 index 2d62ab3..0000000 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sg-regs.h" - -void uniphier_pxs2_pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(30, 8, 8, 4); /* XNFRE -> XNFRE */ - sg_set_pinsel(31, 8, 8, 4); /* XNFWE -> XNFWE */ - sg_set_pinsel(32, 8, 8, 4); /* NFALE -> NFALE */ - sg_set_pinsel(33, 8, 8, 4); /* NFCLE -> NFCLE */ - sg_set_pinsel(34, 8, 8, 4); /* XNFWP -> XNFWP */ - sg_set_pinsel(35, 8, 8, 4); /* XNFCE0 -> XNFCE0 */ - sg_set_pinsel(36, 8, 8, 4); /* NRYBY0 -> NRYBY0 */ - sg_set_pinsel(37, 8, 8, 4); /* XNFCE1 -> NRYBY1 */ - sg_set_pinsel(38, 8, 8, 4); /* NRYBY1 -> XNFCE1 */ - sg_set_pinsel(39, 8, 8, 4); /* NFD0 -> NFD0 */ - sg_set_pinsel(40, 8, 8, 4); /* NFD1 -> NFD1 */ - sg_set_pinsel(41, 8, 8, 4); /* NFD2 -> NFD2 */ - sg_set_pinsel(42, 8, 8, 4); /* NFD3 -> NFD3 */ - sg_set_pinsel(43, 8, 8, 4); /* NFD4 -> NFD4 */ - sg_set_pinsel(44, 8, 8, 4); /* NFD5 -> NFD5 */ - sg_set_pinsel(45, 8, 8, 4); /* NFD6 -> NFD6 */ - sg_set_pinsel(46, 8, 8, 4); /* NFD7 -> NFD7 */ -#endif - -#ifdef CONFIG_USB_XHCI_UNIPHIER - sg_set_pinsel(56, 8, 8, 4); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(57, 8, 8, 4); /* USB0OD -> USB0OD */ - sg_set_pinsel(58, 8, 8, 4); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(59, 8, 8, 4); /* USB1OD -> USB1OD */ - sg_set_pinsel(60, 8, 8, 4); /* USB2VBUS -> USB2VBUS */ - sg_set_pinsel(61, 8, 8, 4); /* USB2OD -> USB2OD */ - sg_set_pinsel(62, 8, 8, 4); /* USB3VBUS -> USB3VBUS */ - sg_set_pinsel(63, 8, 8, 4); /* USB3OD -> USB3OD */ -#endif -} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c deleted file mode 100644 index 62edc49..0000000 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include "../init.h" -#include "../sg-regs.h" - -void uniphier_sld3_pin_init(void) -{ -#ifdef CONFIG_USB_EHCI - sg_set_pinsel(13, 0, 4, 4); /* USB0OC */ - sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */ - - sg_set_pinsel(15, 0, 4, 4); /* USB1OC */ - sg_set_pinsel(16, 1, 4, 4); /* USB1VBUS */ - - sg_set_pinsel(17, 0, 4, 4); /* USB2OC */ - sg_set_pinsel(18, 1, 4, 4); /* USB2VBUS */ - - sg_set_pinsel(19, 0, 4, 4); /* USB3OC */ - sg_set_pinsel(20, 1, 4, 4); /* USB3VBUS */ -#endif - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(38, 1, 4, 4); /* NFALE_GB, NFCLE_GB */ - sg_set_pinsel(39, 1, 4, 4); /* XNFRYBY0_GB */ - sg_set_pinsel(40, 1, 4, 4); /* XNFCE0_GB, XNFRE_GB, XNFWE_GB, XNFWP_GB */ - sg_set_pinsel(41, 1, 4, 4); /* XNFRYBY1_GB, XNFCE1_GB */ - sg_set_pinsel(58, 1, 4, 4); /* NFD[0-3]_GB */ - sg_set_pinsel(59, 1, 4, 4); /* NFD[4-7]_GB */ -#endif - -#ifdef CONFIG_MMC_UNIPHIER - /* eMMC */ - sg_set_pinsel(55, 1, 4, 4); /* XERST */ - sg_set_pinsel(56, 1, 4, 4); /* MMCDAT[0-3] */ - sg_set_pinsel(57, 1, 4, 4); /* MMCDAT[4-7] */ - sg_set_pinsel(60, 1, 4, 4); /* MMCCLK, MMCCMD */ - - /* SD card */ - sg_set_pinsel(42, 1, 4, 4); /* SD1CLK, SD1CMD, SD1DAT[0-3] */ - sg_set_pinsel(43, 1, 4, 4); /* SD1CD */ - sg_set_pinsel(44, 1, 4, 4); /* SD1WP */ - sg_set_pinsel(45, 1, 4, 4); /* SDVTCG */ -#endif -} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-sld8.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-sld8.c deleted file mode 100644 index 1c97c8b..0000000 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-sld8.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sg-regs.h" - -void uniphier_sld8_pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(15, 0, 8, 4); /* XNFRE_GB -> XNFRE_GB */ - sg_set_pinsel(16, 0, 8, 4); /* XNFWE_GB -> XNFWE_GB */ - sg_set_pinsel(17, 0, 8, 4); /* XFALE_GB -> NFALE_GB */ - sg_set_pinsel(18, 0, 8, 4); /* XFCLE_GB -> NFCLE_GB */ - sg_set_pinsel(19, 0, 8, 4); /* XNFWP_GB -> XFNWP_GB */ - sg_set_pinsel(20, 0, 8, 4); /* XNFCE0_GB -> XNFCE0_GB */ - sg_set_pinsel(21, 0, 8, 4); /* NANDRYBY0_GB -> NANDRYBY0_GB */ - sg_set_pinsel(22, 0, 8, 4); /* XFNCE1_GB -> XFNCE1_GB */ - sg_set_pinsel(23, 0, 8, 4); /* NANDRYBY1_GB -> NANDRYBY1_GB */ - sg_set_pinsel(24, 0, 8, 4); /* NFD0_GB -> NFD0_GB */ - sg_set_pinsel(25, 0, 8, 4); /* NFD1_GB -> NFD1_GB */ - sg_set_pinsel(26, 0, 8, 4); /* NFD2_GB -> NFD2_GB */ - sg_set_pinsel(27, 0, 8, 4); /* NFD3_GB -> NFD3_GB */ - sg_set_pinsel(28, 0, 8, 4); /* NFD4_GB -> NFD4_GB */ - sg_set_pinsel(29, 0, 8, 4); /* NFD5_GB -> NFD5_GB */ - sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */ - sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */ -#endif -} diff --git a/arch/arm/mach-uniphier/pll/Makefile b/arch/arm/mach-uniphier/pll/Makefile deleted file mode 100644 index 63f169c..0000000 --- a/arch/arm/mach-uniphier/pll/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += pll-init-sld3.o pll-spectrum-sld3.o -obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pll-init-ld4.o pll-spectrum-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += pll-init-pro4.o pll-spectrum-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pll-init-sld8.o pll-spectrum-ld4.o diff --git a/arch/arm/mach-uniphier/pll/pll-init-sld8.c b/arch/arm/mach-uniphier/pll/pll-init-sld8.c deleted file mode 100644 index b26106e..0000000 --- a/arch/arm/mach-uniphier/pll/pll-init-sld8.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/io.h> - -#include "../init.h" -#include "../sc-regs.h" -#include "../sg-regs.h" - -static void dpll_init(void) -{ - u32 tmp; - /* - * Set DPLL SSC parameters for DPLLCTRL3 - * [23] DIVN_TEST 0x1 - * [22:16] DIVN 0x50 - * [10] FREFSEL_TEST 0x1 - * [9:8] FREFSEL 0x2 - * [4] ICPD_TEST 0x1 - * [3:0] ICPD 0xb - */ - tmp = readl(SC_DPLLCTRL3); - tmp &= ~0x00ff0717; - tmp |= 0x00d0061b; - writel(tmp, SC_DPLLCTRL3); - - /* - * Set DPLL SSC parameters for DPLLCTRL - * <-1%> <-2%> - * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) - * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) - */ - tmp = readl(SC_DPLLCTRL); - tmp &= ~0x3ff07fff; -#ifdef CONFIG_DPLL_SSC_RATE_1PER - tmp |= 0x084018bf; -#else - tmp |= 0x084031a6; -#endif - writel(tmp, SC_DPLLCTRL); - - /* - * Set DPLL SSC parameters for DPLLCTRL2 - * [31:29] SSC_STEP 0 - * [27] SSC_REG_REF 1 - * [26:20] SSC_M 79 (0x4f) - * [19:0] SSC_K 964689 (0xeb851) - */ - tmp = readl(SC_DPLLCTRL2); - tmp &= ~0xefffffff; - tmp |= 0x0cfeb851; - writel(tmp, SC_DPLLCTRL2); -} - -static void upll_init(void) -{ - u32 tmp, clk_mode_upll, clk_mode_axosel; - - tmp = readl(SG_PINMON0); - clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; - clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; - - /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ - tmp = readl(SC_UPLLCTRL); - tmp &= ~0x18000000; - writel(tmp, SC_UPLLCTRL); - - if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { - if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || - clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { - /* AXO: 25MHz */ - tmp &= ~0x07ffffff; - tmp |= 0x0228f5c0; - } else { - /* AXO: default 24.576MHz */ - tmp &= ~0x07ffffff; - tmp |= 0x02328000; - } - } - - writel(tmp, SC_UPLLCTRL); - - /* set 1 to K_LD(UPLLCTRL.bit[27]) */ - tmp |= 0x08000000; - writel(tmp, SC_UPLLCTRL); - - /* wait 10 usec */ - udelay(10); - - /* set 1 to SNRT(UPLLCTRL.bit[28]) */ - tmp |= 0x10000000; - writel(tmp, SC_UPLLCTRL); -} - -static void vpll_init(void) -{ - u32 tmp, clk_mode_axosel; - - tmp = readl(SG_PINMON0); - clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; - - /* set 1 to VPLA27WP and VPLA27WP */ - tmp = readl(SC_VPLL27ACTRL); - tmp |= 0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); - tmp |= 0x00000001; - writel(tmp, SC_VPLL27BCTRL); - - /* Set 0 to VPLA_K_LD and VPLB_K_LD */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL3); - - /* Set 0 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL2); - - /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); - tmp &= ~0x0000007f; - tmp |= 0x00000020; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp &= ~0x0000007f; - tmp |= 0x00000020; - writel(tmp, SC_VPLL27BCTRL2); - - if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || - clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { - /* AXO: 25MHz */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x000fffff; - tmp |= 0x00066664; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x000fffff; - tmp |= 0x00066664; - writel(tmp, SC_VPLL27BCTRL3); - } else { - /* AXO: default 24.576MHz */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x000fffff; - tmp |= 0x000f5800; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x000fffff; - tmp |= 0x000f5800; - writel(tmp, SC_VPLL27BCTRL3); - } - - /* Set 1 to VPLA_K_LD and VPLB_K_LD */ - tmp = readl(SC_VPLL27ACTRL3); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL3); - - /* wait 10 usec */ - udelay(10); - - /* Set 0 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL2); - - /* set 0 to VPLA27WP and VPLA27WP */ - tmp = readl(SC_VPLL27ACTRL); - tmp &= ~0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); - tmp |= ~0x00000001; - writel(tmp, SC_VPLL27BCTRL); -} - -int uniphier_sld8_pll_init(const struct uniphier_board_data *bd) -{ - dpll_init(); - upll_init(); - vpll_init(); - - /* - * Wait 500 usec until dpll get stable - * We wait 10 usec in upll_init() and vpll_init() - * so 20 usec can be saved here. - */ - udelay(480); - - return 0; -} diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-ld4.c b/arch/arm/mach-uniphier/pll/pll-spectrum-ld4.c deleted file mode 100644 index dc97697..0000000 --- a/arch/arm/mach-uniphier/pll/pll-spectrum-ld4.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sc-regs.h" - -int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd) -{ - u32 tmp; - - tmp = readl(SC_DPLLCTRL); - tmp |= SC_DPLLCTRL_SSC_EN; - writel(tmp, SC_DPLLCTRL); - - return 0; -} diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-sld3.c b/arch/arm/mach-uniphier/pll/pll-spectrum-sld3.c deleted file mode 100644 index ff09a92..0000000 --- a/arch/arm/mach-uniphier/pll/pll-spectrum-sld3.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/io.h> - -#include "../init.h" -#include "../sc-regs.h" - -int uniphier_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd) -{ - u32 tmp; - - tmp = readl(SC_DPLLCTRL); - tmp |= SC_DPLLCTRL_SSC_EN; - writel(tmp, SC_DPLLCTRL); - - return 0; -} diff --git a/arch/arm/mach-uniphier/print_misc_info.c b/arch/arm/mach-uniphier/print_misc_info.c deleted file mode 100644 index 695b7ae..0000000 --- a/arch/arm/mach-uniphier/print_misc_info.c +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include "micro-support-card.h" - -int misc_init_f(void) -{ - return check_support_card(); -} diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h index ef02830..780fdd1 100644 --- a/arch/arm/mach-uniphier/sc64-regs.h +++ b/arch/arm/mach-uniphier/sc64-regs.h @@ -1,7 +1,8 @@ /* * UniPhier SC (System Control) block registers for ARMv8 SoCs * - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -11,6 +12,27 @@ #define SC_BASE_ADDR 0x61840000 +/* PLL type: SSC */ +#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* LD11/20: CPU/ARM */ +#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* LD11/20: misc */ +#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* LD20: IPP */ +#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* LD11/20: Video codec */ +#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD11 */ +#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD20: VPE etc. */ +#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* LD20: GPU/Mali */ +#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* LD11: DDR memory */ +#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* LD20: DDR memory 0 */ +#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* LD20: DDR memory 1 */ +#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* LD20: DDR memory 2 */ + +/* PLL type: VPLL27 */ +#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) + +/* PLL type: DSPLL */ +#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) +#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0) + #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) @@ -41,4 +63,12 @@ #define SC_CLKCTRL7_UMC31 (1 << 1) #define SC_CLKCTRL7_UMC30 (1 << 0) +#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8080) +#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8084) +#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8088) +#define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080) +#define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084) +#define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088) +#define SC_CA_GEARUPD (1 << 0) + #endif /* SC64_REGS_H */ diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index a982320..a1175ee 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -1,5 +1,29 @@ if ARCH_ZYNQ +config SPL_FAT_SUPPORT + default y + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBDISK_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_MMC_SUPPORT + default y if ZYNQ_SDHCI + +config SPL_SERIAL_SUPPORT + default y + +config SPL_SPI_FLASH_SUPPORT + default y if ZYNQ_QSPI + +config SPL_SPI_SUPPORT + default y if ZYNQ_QSPI + config SYS_BOARD default "zynq" diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index 914b1fe..ba9171e 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -43,12 +43,8 @@ int arch_cpu_init(void) unsigned int zynq_get_silicon_version(void) { - unsigned int ver; - - ver = (readl(&devcfg_base->mctrl) & - ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT; - - return ver; + return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK) + >> ZYNQ_SILICON_VER_SHIFT; } void reset_cpu(ulong addr) diff --git a/arch/avr32/cpu/interrupts.c b/arch/avr32/cpu/interrupts.c index 4a03e19..de20220 100644 --- a/arch/avr32/cpu/interrupts.c +++ b/arch/avr32/cpu/interrupts.c @@ -6,7 +6,7 @@ #include <common.h> #include <div64.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/io.h> #include <asm/processor.h> #include <asm/sysreg.h> diff --git a/arch/avr32/include/asm/errno.h b/arch/avr32/include/asm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/arch/avr32/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c index 4b4cf93..81b7090 100644 --- a/arch/blackfin/cpu/gpio.c +++ b/arch/blackfin/cpu/gpio.c @@ -8,7 +8,7 @@ */ #include <common.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/gpio.h> #include <asm/portmux.h> diff --git a/arch/blackfin/cpu/interrupts.c b/arch/blackfin/cpu/interrupts.c index 45c92c3..abb7dc1 100644 --- a/arch/blackfin/cpu/interrupts.c +++ b/arch/blackfin/cpu/interrupts.c @@ -47,10 +47,7 @@ unsigned long long get_ticks(void) */ ulong get_tbclk(void) { - ulong tbclk; - - tbclk = CONFIG_SYS_HZ; - return tbclk; + return CONFIG_SYS_HZ; } void enable_interrupts(void) diff --git a/arch/blackfin/include/asm/errno.h b/arch/blackfin/include/asm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/arch/blackfin/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S index b5d51bd..1bd914e 100644 --- a/arch/m68k/cpu/mcf5227x/start.S +++ b/arch/m68k/cpu/mcf5227x/start.S @@ -10,10 +10,6 @@ #include "version.h" #include <asm/cache.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - #define _START _start #define _FAULT _fault diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S index c4f6082..8533108 100644 --- a/arch/m68k/cpu/mcf523x/start.S +++ b/arch/m68k/cpu/mcf523x/start.S @@ -10,10 +10,6 @@ #include "version.h" #include <asm/cache.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - #define _START _start #define _FAULT _fault diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S index 9837c41..ab199b1 100644 --- a/arch/m68k/cpu/mcf52x2/start.S +++ b/arch/m68k/cpu/mcf52x2/start.S @@ -10,10 +10,6 @@ #include "version.h" #include <asm/cache.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - #define _START _start #define _FAULT _fault diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S index da41c9a..536daa4 100644 --- a/arch/m68k/cpu/mcf530x/start.S +++ b/arch/m68k/cpu/mcf530x/start.S @@ -10,10 +10,6 @@ #include "version.h" #include <asm/cache.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - #define _START _start #define _FAULT _fault diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S index 302fca5..4678643 100644 --- a/arch/m68k/cpu/mcf532x/start.S +++ b/arch/m68k/cpu/mcf532x/start.S @@ -13,10 +13,6 @@ #include "version.h" #include <asm/cache.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - #define _START _start #define _FAULT _fault diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index bc48ca0..0487d84 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -15,10 +15,6 @@ #include "version.h" #include <asm/cache.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - #define _START _start #define _FAULT _fault diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S index fecf253..2296f9a 100644 --- a/arch/m68k/cpu/mcf547x_8x/start.S +++ b/arch/m68k/cpu/mcf547x_8x/start.S @@ -10,10 +10,6 @@ #include "version.h" #include <asm/cache.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - #define _START _start #define _FAULT _fault diff --git a/arch/m68k/include/asm/errno.h b/arch/m68k/include/asm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/arch/m68k/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c index 3163354..cb90c83 100644 --- a/arch/m68k/lib/time.c +++ b/arch/m68k/lib/time.c @@ -192,7 +192,5 @@ unsigned long usec2ticks(unsigned long usec) */ ulong get_tbclk(void) { - ulong tbclk; - tbclk = CONFIG_SYS_HZ; - return tbclk; + return CONFIG_SYS_HZ; } diff --git a/arch/microblaze/include/asm/errno.h b/arch/microblaze/include/asm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/arch/microblaze/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 21066f0..097ad58 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -26,6 +26,8 @@ config TARGET_MALTA select DM select DM_SERIAL select DYNAMIC_IO_PORT_BASE + select MIPS_CM + select MIPS_L2_CACHE select OF_CONTROL select OF_ISA_BUS select SUPPORTS_BIG_ENDIAN @@ -73,10 +75,43 @@ config MACH_PIC32 select OF_CONTROL select DM +config TARGET_BOSTON + bool "Support Boston" + select DM + select DM_SERIAL + select OF_CONTROL + select MIPS_CM + select MIPS_L1_CACHE_SHIFT_6 + select MIPS_L2_CACHE + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_LITTLE_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_CPU_MIPS32_R6 + select SUPPORTS_CPU_MIPS64_R1 + select SUPPORTS_CPU_MIPS64_R2 + select SUPPORTS_CPU_MIPS64_R6 + +config TARGET_XILFPGA + bool "Support Imagination Xilfpga" + select OF_CONTROL + select DM + select DM_SERIAL + select DM_GPIO + select DM_ETH + select SUPPORTS_LITTLE_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select MIPS_L1_CACHE_SHIFT_4 + help + This supports IMGTEC MIPSfpga platform + endchoice source "board/dbau1x00/Kconfig" +source "board/imgtec/boston/Kconfig" source "board/imgtec/malta/Kconfig" +source "board/imgtec/xilfpga/Kconfig" source "board/micronas/vct/Kconfig" source "board/pb1x00/Kconfig" source "board/qemu-mips/Kconfig" @@ -300,9 +335,31 @@ config MIPS_L1_CACHE_SHIFT default "4" if MIPS_L1_CACHE_SHIFT_4 default "5" +config MIPS_L2_CACHE + bool + help + Select this if your system includes an L2 cache and you want U-Boot + to initialise & maintain it. + config DYNAMIC_IO_PORT_BASE bool +config MIPS_CM + bool + help + Select this if your system contains a MIPS Coherence Manager and you + wish U-Boot to configure it or make use of it to retrieve system + information such as cache configuration. + +config MIPS_CM_BASE + hex + default 0x1fbf8000 + help + The physical base address at which to map the MIPS Coherence Manager + Global Configuration Registers (GCRs). This should be set such that + the GCRs occupy a region of the physical address space which is + otherwise unused, or at minimum that software doesn't need to access. + endif endmenu diff --git a/arch/mips/cpu/Makefile b/arch/mips/cpu/Makefile index fc6b455..429fd3a 100644 --- a/arch/mips/cpu/Makefile +++ b/arch/mips/cpu/Makefile @@ -7,3 +7,5 @@ extra-y = start.o obj-y += time.o obj-y += interrupts.o obj-y += cpu.o + +obj-$(CONFIG_MIPS_CM) += cm_init.o diff --git a/arch/mips/cpu/cm_init.S b/arch/mips/cpu/cm_init.S new file mode 100644 index 0000000..ddcaa49 --- /dev/null +++ b/arch/mips/cpu/cm_init.S @@ -0,0 +1,45 @@ +/* + * MIPS Coherence Manager (CM) Initialisation + * + * Copyright (c) 2016 Imagination Technologies Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/addrspace.h> +#include <asm/asm.h> +#include <asm/cm.h> +#include <asm/mipsregs.h> +#include <asm/regdef.h> + +LEAF(mips_cm_map) + /* Config3 must exist for a CM to be present */ + mfc0 t0, CP0_CONFIG, 1 + bgez t0, 2f + mfc0 t0, CP0_CONFIG, 2 + bgez t0, 2f + + /* Check Config3.CMGCR to determine CM presence */ + mfc0 t0, CP0_CONFIG, 3 + and t0, t0, MIPS_CONF3_CMGCR + beqz t0, 2f + + /* Find the current physical GCR base address */ +1: MFC0 t0, CP0_CMGCRBASE + PTR_SLL t0, t0, 4 + + /* If the GCRs are where we want, we're done */ + PTR_LI t1, CONFIG_MIPS_CM_BASE + beq t0, t1, 2f + + /* Move the GCRs to our configured base address */ + PTR_LI t2, CKSEG1 + PTR_ADDU t0, t0, t2 + sw zero, GCR_BASE_UPPER(t0) + sw t1, GCR_BASE(t0) + + /* Re-check the GCR base */ + b 1b + +2: jr ra + END(mips_cm_map) diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c index 391feb3..1b919ed 100644 --- a/arch/mips/cpu/cpu.c +++ b/arch/mips/cpu/cpu.c @@ -8,6 +8,7 @@ #include <common.h> #include <command.h> #include <linux/compiler.h> +#include <asm/cache.h> #include <asm/mipsregs.h> #include <asm/reboot.h> @@ -35,3 +36,9 @@ void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) write_c0_index(index); tlb_write_indexed(); } + +int arch_cpu_init(void) +{ + mips_cache_probe(); + return 0; +} diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index fc6dd66..3f0fc12 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -12,10 +12,6 @@ #include <asm/regdef.h> #include <asm/mipsregs.h> -#ifndef CONFIG_SYS_MIPS_CACHE_MODE -#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT -#endif - #ifndef CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_INIT_SP_OFFSET) @@ -112,9 +108,28 @@ ENTRY(_start) .align 4 reset: +#if __mips_isa_rev >= 6 + mfc0 t0, CP0_CONFIG, 5 + and t0, t0, MIPS_CONF5_VP + beqz t0, 1f + nop + + b 2f + mfc0 t0, CP0_GLOBALNUMBER +#endif + +1: mfc0 t0, CP0_EBASE + and t0, t0, EBASE_CPUNUM + + /* Hang if this isn't the first CPU in the system */ +2: beqz t0, 4f + nop +3: wait + b 3b + nop /* Clear watch registers */ - MTC0 zero, CP0_WATCHLO +4: MTC0 zero, CP0_WATCHLO mtc0 zero, CP0_WATCHHI /* WP(Watch Pending), SW0/1 should be cleared */ @@ -127,9 +142,11 @@ reset: mtc0 zero, CP0_COMPARE #ifndef CONFIG_SKIP_LOWLEVEL_INIT - /* CONFIG0 register */ - li t0, CONF_CM_UNCACHED + mfc0 t0, CP0_CONFIG + and t0, t0, MIPS_CONF_IMPL + or t0, t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG + ehb #endif /* @@ -144,20 +161,31 @@ reset: 1: PTR_L gp, 0(ra) +#ifdef CONFIG_MIPS_CM + PTR_LA t9, mips_cm_map + jalr t9 + nop +#endif + #ifndef CONFIG_SKIP_LOWLEVEL_INIT +# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD /* Initialize any external memory */ PTR_LA t9, lowlevel_init jalr t9 nop +# endif /* Initialize caches... */ PTR_LA t9, mips_cache_reset jalr t9 nop - /* ... and enable them */ - li t0, CONFIG_SYS_MIPS_CACHE_MODE - mtc0 t0, CP0_CONFIG +# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD + /* Initialize any external memory */ + PTR_LA t9, lowlevel_init + jalr t9 + nop +# endif #endif /* Set up temporary stack */ @@ -214,12 +242,9 @@ ENTRY(relocate_code) PTR_LI t0, CONFIG_SYS_MONITOR_BASE PTR_SUB s1, s2, t0 # s1 <-- relocation offset - PTR_LA t3, in_ram - PTR_L t2, -(3 * PTRSIZE)(t3) # t2 <-- __image_copy_end + PTR_LA t2, __image_copy_end move t1, a2 - PTR_ADD gp, s1 # adjust gp - /* * t0 = source address * t1 = target address @@ -232,32 +257,14 @@ ENTRY(relocate_code) blt t0, t2, 1b PTR_ADDU t1, PTRSIZE - /* If caches were enabled, we would have to flush them here. */ - PTR_SUB a1, t1, s2 # a1 <-- size - PTR_LA t9, flush_cache - jalr t9 - move a0, s2 # a0 <-- destination address - - /* Jump to where we've relocated ourselves */ - PTR_ADDIU t0, s2, in_ram - _start - jr t0 - nop - - PTR __rel_dyn_end - PTR __rel_dyn_start - PTR __image_copy_end - PTR _GLOBAL_OFFSET_TABLE_ - PTR num_got_entries - -in_ram: /* * Now we want to update GOT. * * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object * generated by GNU ld. Skip these reserved entries from relocation. */ - PTR_L t3, -(1 * PTRSIZE)(t0) # t3 <-- num_got_entries - PTR_L t8, -(2 * PTRSIZE)(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ + PTR_LA t3, num_got_entries + PTR_LA t8, _GLOBAL_OFFSET_TABLE_ PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_ PTR_ADDIU t8, t8, 2 * PTRSIZE # skipping first two entries PTR_LI t2, 2 @@ -272,8 +279,8 @@ in_ram: PTR_ADDIU t8, PTRSIZE /* Update dynamic relocations */ - PTR_L t1, -(4 * PTRSIZE)(t0) # t1 <-- __rel_dyn_start - PTR_L t2, -(5 * PTRSIZE)(t0) # t2 <-- __rel_dyn_end + PTR_LA t1, __rel_dyn_start + PTR_LA t2, __rel_dyn_end b 2f # skip first reserved entry PTR_ADDIU t1, 2 * PTRSIZE @@ -298,6 +305,20 @@ in_ram: PTR_ADDIU t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes /* + * Flush caches to ensure our newly modified instructions are visible + * to the instruction cache. We're still running with the old GOT, so + * apply the reloc offset to the start address. + */ + PTR_LA a0, __text_start + PTR_LA a1, __text_end + PTR_SUB a1, a1, a0 + PTR_LA t9, flush_cache + jalr t9 + PTR_ADD a0, s1 + + PTR_ADD gp, s1 # adjust gp + + /* * Clear BSS * * GOT is now relocated. Thus __bss_start and __bss_end can be diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds index 7d71c11..0129c99 100644 --- a/arch/mips/cpu/u-boot.lds +++ b/arch/mips/cpu/u-boot.lds @@ -19,7 +19,9 @@ SECTIONS . = ALIGN(4); .text : { + __text_start = .; *(.text*) + __text_end = .; } . = ALIGN(4); diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 2f04d73..30fcc2b 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -4,8 +4,10 @@ dtb-$(CONFIG_TARGET_AP121) += ap121.dtb dtb-$(CONFIG_TARGET_AP143) += ap143.dtb +dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb +dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/img,boston.dts b/arch/mips/dts/img,boston.dts new file mode 100644 index 0000000..1d4eeda --- /dev/null +++ b/arch/mips/dts/img,boston.dts @@ -0,0 +1,222 @@ +/dts-v1/; + +#include <dt-bindings/clock/boston-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/mips-gic.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "img,boston"; + + chosen { + stdout-path = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "img,mips"; + reg = <0>; + clocks = <&clk_boston BOSTON_CLK_CPU>; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + gic: interrupt-controller { + compatible = "mti,gic"; + + interrupt-controller; + #interrupt-cells = <3>; + + timer { + compatible = "mti,gic-timer"; + interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; + clocks = <&clk_boston BOSTON_CLK_CPU>; + }; + }; + + pci0: pci@10000000 { + status = "disabled"; + compatible = "xlnx,axi-pcie-host-1.00.a"; + device_type = "pci"; + reg = <0x10000000 0x2000000>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; + + ranges = <0x02000000 0 0x40000000 + 0x40000000 0 0x40000000>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pci0_intc 0>, + <0 0 0 2 &pci0_intc 1>, + <0 0 0 3 &pci0_intc 2>, + <0 0 0 4 &pci0_intc 3>; + + pci0_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pci1: pci@12000000 { + status = "disabled"; + compatible = "xlnx,axi-pcie-host-1.00.a"; + device_type = "pci"; + reg = <0x12000000 0x2000000>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>; + + ranges = <0x02000000 0 0x20000000 + 0x20000000 0 0x20000000>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pci1_intc 0>, + <0 0 0 2 &pci1_intc 1>, + <0 0 0 3 &pci1_intc 2>, + <0 0 0 4 &pci1_intc 3>; + + pci1_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pci2: pci@14000000 { + compatible = "xlnx,axi-pcie-host-1.00.a"; + device_type = "pci"; + reg = <0x14000000 0x2000000>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; + + ranges = <0x02000000 0 0x16000000 + 0x16000000 0 0x100000>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pci2_intc 0>, + <0 0 0 2 &pci2_intc 1>, + <0 0 0 3 &pci2_intc 2>, + <0 0 0 4 &pci2_intc 3>; + + pci2_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + pci2_root@0,0,0 { + compatible = "pci10ee,7021"; + reg = <0x00000000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + eg20t_bridge@1,0,0 { + compatible = "pci8086,8800"; + reg = <0x00010000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + eg20t_mac@2,0,1 { + compatible = "pci8086,8802"; + reg = <0x00020100 0 0 0 0>; + phy-reset-gpios = <&eg20t_gpio 6 GPIO_ACTIVE_LOW>; + }; + + eg20t_gpio: eg20t_gpio@2,0,2 { + compatible = "pci8086,8803"; + reg = <0x00020200 0 0 0 0>; + + gpio-controller; + #gpio-cells = <2>; + }; + + eg20t_i2c@2,12,2 { + compatible = "pci8086,8817"; + reg = <0x00026200 0 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + rtc@0x68 { + compatible = "st,m41t81s"; + reg = <0x68>; + }; + }; + }; + }; + }; + + plat_regs: system-controller@17ffd000 { + compatible = "img,boston-platform-regs", "syscon"; + reg = <0x17ffd000 0x1000>; + u-boot,dm-pre-reloc; + }; + + clk_boston: clock { + compatible = "img,boston-clock"; + #clock-cells = <1>; + regmap = <&plat_regs>; + u-boot,dm-pre-reloc; + }; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&plat_regs>; + offset = <0x10>; + mask = <0x10>; + }; + + uart0: uart@17ffe000 { + compatible = "ns16550a"; + reg = <0x17ffe000 0x1000>; + reg-shift = <2>; + reg-io-width = <4>; + + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&clk_boston BOSTON_CLK_SYS>; + + u-boot,dm-pre-reloc; + }; + + lcd: lcd@17fff000 { + compatible = "img,boston-lcd"; + reg = <0x17fff000 0x8>; + }; + + flash@18000000 { + compatible = "cfi-flash"; + reg = <0x18000000 0x8000000>; + bank-width = <2>; + }; +}; diff --git a/arch/mips/dts/microAptiv.dtsi b/arch/mips/dts/microAptiv.dtsi new file mode 100644 index 0000000..81d518e --- /dev/null +++ b/arch/mips/dts/microAptiv.dtsi @@ -0,0 +1,21 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "img,xilfpga"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "mips,m14Kc"; + clocks = <&ext>; + reg = <0>; + }; + }; + + ext: ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; +}; diff --git a/arch/mips/dts/nexys4ddr.dts b/arch/mips/dts/nexys4ddr.dts new file mode 100644 index 0000000..e254ab1 --- /dev/null +++ b/arch/mips/dts/nexys4ddr.dts @@ -0,0 +1,62 @@ +/dts-v1/; + +#include "microAptiv.dtsi" + +/ { + compatible = "digilent,nexys4ddr"; + + memory { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + + cpuintc: interrupt-controller@0 { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + aliases { + console = &axi_uart16550; + }; + + axi_ethernetlite: ethernet@10e00000 { + compatible = "xlnx,xps-ethernetlite-1.00.a"; + device_type = "network"; + local-mac-address = [08 86 4C 0D F7 09]; + phy-handle = <&phy0>; + reg = <0x10e00000 0x10000>; + xlnx,duplex = <0x1>; + xlnx,include-global-buffers = <0x1>; + xlnx,include-internal-loopback = <0x0>; + xlnx,include-mdio = <0x1>; + xlnx,instance = "axi_ethernetlite_inst"; + xlnx,rx-ping-pong = <0x1>; + xlnx,s-axi-id-width = <0x1>; + xlnx,tx-ping-pong = <0x1>; + xlnx,use-internal = <0x0>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: phy@1 { + compatible = <0x0007c0f0 0xfffffff0>; + device_type = "ethernet-phy"; + reg = <1>; + } ; + } ; + } ; + + + axi_uart16550: serial@10400000 { + compatible = "ns16550a"; + reg = <0x10400000 0x10000>; + + reg-shift = <2>; + reg-offset = <0x1000>; + + clock-frequency = <50000000>; + + }; +}; + diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 0cea581..669c362 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -19,4 +19,13 @@ */ #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN +/** + * mips_cache_probe() - Probe the properties of the caches + * + * Call this to probe the properties such as line sizes of the caches + * present in the system, if any. This must be done before cache maintenance + * functions such as flush_cache may be called. + */ +void mips_cache_probe(void); + #endif /* __MIPS_CACHE_H__ */ diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h new file mode 100644 index 0000000..b9ab0c6 --- /dev/null +++ b/arch/mips/include/asm/cm.h @@ -0,0 +1,62 @@ +/* + * MIPS Coherence Manager (CM) Register Definitions + * + * Copyright (c) 2016 Imagination Technologies Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MIPS_ASM_CM_H__ +#define __MIPS_ASM_CM_H__ + +/* Global Control Register (GCR) offsets */ +#define GCR_BASE 0x0008 +#define GCR_BASE_UPPER 0x000c +#define GCR_REV 0x0030 +#define GCR_L2_CONFIG 0x0130 +#define GCR_L2_TAG_ADDR 0x0600 +#define GCR_L2_TAG_ADDR_UPPER 0x0604 +#define GCR_L2_TAG_STATE 0x0608 +#define GCR_L2_TAG_STATE_UPPER 0x060c +#define GCR_L2_DATA 0x0610 +#define GCR_L2_DATA_UPPER 0x0614 +#define GCR_Cx_COHERENCE 0x2008 + +/* GCR_REV CM versions */ +#define GCR_REV_CM3 0x0800 + +/* GCR_L2_CONFIG fields */ +#define GCR_L2_CONFIG_ASSOC_SHIFT 0 +#define GCR_L2_CONFIG_ASSOC_BITS 8 +#define GCR_L2_CONFIG_LINESZ_SHIFT 8 +#define GCR_L2_CONFIG_LINESZ_BITS 4 +#define GCR_L2_CONFIG_SETSZ_SHIFT 12 +#define GCR_L2_CONFIG_SETSZ_BITS 4 +#define GCR_L2_CONFIG_BYPASS (1 << 20) + +/* GCR_Cx_COHERENCE */ +#define GCR_Cx_COHERENCE_DOM_EN (0xff << 0) +#define GCR_Cx_COHERENCE_EN (0x1 << 0) + +#ifndef __ASSEMBLY__ + +#include <asm/io.h> + +static inline void *mips_cm_base(void) +{ + return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE); +} + +static inline unsigned long mips_cm_l2_line_size(void) +{ + unsigned long l2conf, line_sz; + + l2conf = __raw_readl(mips_cm_base() + GCR_L2_CONFIG); + + line_sz = l2conf >> GCR_L2_CONFIG_LINESZ_SHIFT; + line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0); + return line_sz ? (2 << line_sz) : 0; +} + +#endif /* !__ASSEMBLY__ */ + +#endif /* __MIPS_ASM_CM_H__ */ diff --git a/arch/mips/include/asm/errno.h b/arch/mips/include/asm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/arch/mips/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h index 37f8ed5..0078bbe 100644 --- a/arch/mips/include/asm/global_data.h +++ b/arch/mips/include/asm/global_data.h @@ -21,6 +21,13 @@ struct arch_global_data { unsigned long rev; unsigned long ver; #endif +#ifdef CONFIG_SYS_CACHE_SIZE_AUTO + unsigned short l1i_line_size; + unsigned short l1d_line_size; +#endif +#ifdef CONFIG_MIPS_L2_CACHE + unsigned short l2_line_size; +#endif }; #include <asm-generic/global_data.h> diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 3185dc7..9ab5063 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -39,6 +39,7 @@ #define CP0_ENTRYLO0 $2 #define CP0_ENTRYLO1 $3 #define CP0_CONF $3 +#define CP0_GLOBALNUMBER $3, 1 #define CP0_CONTEXT $4 #define CP0_PAGEMASK $5 #define CP0_WIRED $6 @@ -361,6 +362,11 @@ #define CAUSEF_BD (_ULCAST_(1) << 31) /* + * Bits in the coprocessor 0 EBase register. + */ +#define EBASE_CPUNUM 0x3ff + +/* * Bits in the coprocessor 0 config register. */ /* Generic bits. */ @@ -450,6 +456,7 @@ #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7) #define MIPS_CONF_AR (_ULCAST_(7) << 10) #define MIPS_CONF_AT (_ULCAST_(3) << 13) +#define MIPS_CONF_IMPL (_ULCAST_(0x1ff) << 16) #define MIPS_CONF_M (_ULCAST_(1) << 31) /* @@ -484,9 +491,13 @@ #define MIPS_CONF1_TLBS_SIZE (6) #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT) +#define MIPS_CONF2_SA_SHF 0 #define MIPS_CONF2_SA (_ULCAST_(15) << 0) +#define MIPS_CONF2_SL_SHF 4 #define MIPS_CONF2_SL (_ULCAST_(15) << 4) +#define MIPS_CONF2_SS_SHF 8 #define MIPS_CONF2_SS (_ULCAST_(15) << 8) +#define MIPS_CONF2_L2B (_ULCAST_(1) << 12) #define MIPS_CONF2_SU (_ULCAST_(15) << 12) #define MIPS_CONF2_TA (_ULCAST_(15) << 16) #define MIPS_CONF2_TL (_ULCAST_(15) << 20) @@ -548,8 +559,10 @@ #define MIPS_CONF5_MRP (_ULCAST_(1) << 3) #define MIPS_CONF5_LLB (_ULCAST_(1) << 4) #define MIPS_CONF5_MVH (_ULCAST_(1) << 5) +#define MIPS_CONF5_VP (_ULCAST_(1) << 7) #define MIPS_CONF5_FRE (_ULCAST_(1) << 8) #define MIPS_CONF5_UFE (_ULCAST_(1) << 9) +#define MIPS_CONF5_L2C (_ULCAST_(1) << 10) #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) #define MIPS_CONF5_EVA (_ULCAST_(1) << 28) #define MIPS_CONF5_CV (_ULCAST_(1) << 29) diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index db81953..bd14ba6 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -7,34 +7,85 @@ #include <common.h> #include <asm/cacheops.h> +#include <asm/cm.h> #include <asm/mipsregs.h> -static inline unsigned long icache_line_size(void) +DECLARE_GLOBAL_DATA_PTR; + +static void probe_l2(void) { - unsigned long conf1, il; +#ifdef CONFIG_MIPS_L2_CACHE + unsigned long conf2, sl; + bool l2c = false; + + if (!(read_c0_config1() & MIPS_CONF_M)) + return; - if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO)) - return CONFIG_SYS_ICACHE_LINE_SIZE; + conf2 = read_c0_config2(); + + if (__mips_isa_rev >= 6) { + l2c = conf2 & MIPS_CONF_M; + if (l2c) + l2c = read_c0_config3() & MIPS_CONF_M; + if (l2c) + l2c = read_c0_config4() & MIPS_CONF_M; + if (l2c) + l2c = read_c0_config5() & MIPS_CONF5_L2C; + } + + if (l2c && config_enabled(CONFIG_MIPS_CM)) { + gd->arch.l2_line_size = mips_cm_l2_line_size(); + } else if (l2c) { + /* We don't know how to retrieve L2 config on this system */ + BUG(); + } else { + sl = (conf2 & MIPS_CONF2_SL) >> MIPS_CONF2_SL_SHF; + gd->arch.l2_line_size = sl ? (2 << sl) : 0; + } +#endif +} + +void mips_cache_probe(void) +{ +#ifdef CONFIG_SYS_CACHE_SIZE_AUTO + unsigned long conf1, il, dl; conf1 = read_c0_config1(); + il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF; - if (!il) - return 0; - return 2 << il; + dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF; + + gd->arch.l1i_line_size = il ? (2 << il) : 0; + gd->arch.l1d_line_size = dl ? (2 << dl) : 0; +#endif + probe_l2(); } -static inline unsigned long dcache_line_size(void) +static inline unsigned long icache_line_size(void) { - unsigned long conf1, dl; +#ifdef CONFIG_SYS_CACHE_SIZE_AUTO + return gd->arch.l1i_line_size; +#else + return CONFIG_SYS_ICACHE_LINE_SIZE; +#endif +} - if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO)) - return CONFIG_SYS_DCACHE_LINE_SIZE; +static inline unsigned long dcache_line_size(void) +{ +#ifdef CONFIG_SYS_CACHE_SIZE_AUTO + return gd->arch.l1d_line_size; +#else + return CONFIG_SYS_DCACHE_LINE_SIZE; +#endif +} - conf1 = read_c0_config1(); - dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF; - if (!dl) - return 0; - return 2 << dl; +static inline unsigned long scache_line_size(void) +{ +#ifdef CONFIG_MIPS_L2_CACHE + return gd->arch.l2_line_size; +#else + return 0; +#endif } #define cache_loop(start, end, lsize, ops...) do { \ @@ -53,12 +104,13 @@ void flush_cache(ulong start_addr, ulong size) { unsigned long ilsize = icache_line_size(); unsigned long dlsize = dcache_line_size(); + unsigned long slsize = scache_line_size(); /* aend will be miscalculated when size is zero, so we return here */ if (size == 0) return; - if (ilsize == dlsize) { + if ((ilsize == dlsize) && !slsize) { /* flush I-cache & D-cache simultaneously */ cache_loop(start_addr, start_addr + size, ilsize, HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I); @@ -68,6 +120,11 @@ void flush_cache(ulong start_addr, ulong size) /* flush D-cache */ cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D); + /* flush L2 cache */ + if (slsize) + cache_loop(start_addr, start_addr + size, slsize, + HIT_WRITEBACK_INV_SD); + /* flush I-cache */ cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I); } @@ -75,21 +132,31 @@ void flush_cache(ulong start_addr, ulong size) void flush_dcache_range(ulong start_addr, ulong stop) { unsigned long lsize = dcache_line_size(); + unsigned long slsize = scache_line_size(); /* aend will be miscalculated when size is zero, so we return here */ if (start_addr == stop) return; cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D); + + /* flush L2 cache */ + if (slsize) + cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD); } void invalidate_dcache_range(ulong start_addr, ulong stop) { unsigned long lsize = dcache_line_size(); + unsigned long slsize = scache_line_size(); /* aend will be miscalculated when size is zero, so we return here */ if (start_addr == stop) return; + /* invalidate L2 cache */ + if (slsize) + cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD); + cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D); } diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index bc8ab27..698a5af 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -13,6 +13,7 @@ #include <asm/mipsregs.h> #include <asm/addrspace.h> #include <asm/cacheops.h> +#include <asm/cm.h> #ifndef CONFIG_SYS_MIPS_CACHE_MODE #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT @@ -95,22 +96,147 @@ * with good parity is available. This routine will initialise an area of * memory starting at location zero to be used as a source of parity. * + * Note that this function does not follow the standard calling convention & + * may clobber typically callee-saved registers. + * * RETURNS: N/A * */ +#define R_RETURN s0 +#define R_IC_SIZE s1 +#define R_IC_LINE s2 +#define R_DC_SIZE s3 +#define R_DC_LINE s4 +#define R_L2_SIZE s5 +#define R_L2_LINE s6 +#define R_L2_BYPASSED s7 +#define R_L2_L2C t8 LEAF(mips_cache_reset) + move R_RETURN, ra + +#ifdef CONFIG_MIPS_L2_CACHE + /* + * For there to be an L2 present, Config2 must be present. If it isn't + * then we proceed knowing there's no L2 cache. + */ + move R_L2_SIZE, zero + move R_L2_LINE, zero + move R_L2_BYPASSED, zero + move R_L2_L2C, zero + mfc0 t0, CP0_CONFIG, 1 + bgez t0, l2_probe_done + + /* + * From MIPSr6 onwards the L2 cache configuration might not be reported + * by Config2. The Config5.L2C bit indicates whether this is the case, + * and if it is then we need knowledge of where else to look. For cores + * from Imagination Technologies this is a CM GCR. + */ +# if __mips_isa_rev >= 6 + /* Check that Config5 exists */ + mfc0 t0, CP0_CONFIG, 2 + bgez t0, l2_probe_cop0 + mfc0 t0, CP0_CONFIG, 3 + bgez t0, l2_probe_cop0 + mfc0 t0, CP0_CONFIG, 4 + bgez t0, l2_probe_cop0 + + /* Check Config5.L2C is set */ + mfc0 t0, CP0_CONFIG, 5 + and R_L2_L2C, t0, MIPS_CONF5_L2C + beqz R_L2_L2C, l2_probe_cop0 + + /* Config5.L2C is set */ +# ifdef CONFIG_MIPS_CM + /* The CM will provide L2 configuration */ + PTR_LI t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE) + lw t1, GCR_L2_CONFIG(t0) + bgez t1, l2_probe_done + + ext R_L2_LINE, t1, \ + GCR_L2_CONFIG_LINESZ_SHIFT, GCR_L2_CONFIG_LINESZ_BITS + beqz R_L2_LINE, l2_probe_done + li t2, 2 + sllv R_L2_LINE, t2, R_L2_LINE + + ext t2, t1, GCR_L2_CONFIG_ASSOC_SHIFT, GCR_L2_CONFIG_ASSOC_BITS + addiu t2, t2, 1 + mul R_L2_SIZE, R_L2_LINE, t2 + + ext t2, t1, GCR_L2_CONFIG_SETSZ_SHIFT, GCR_L2_CONFIG_SETSZ_BITS + sllv R_L2_SIZE, R_L2_SIZE, t2 + li t2, 64 + mul R_L2_SIZE, R_L2_SIZE, t2 + + /* Bypass the L2 cache so that we can init the L1s early */ + or t1, t1, GCR_L2_CONFIG_BYPASS + sw t1, GCR_L2_CONFIG(t0) + sync + li R_L2_BYPASSED, 1 + + /* Zero the L2 tag registers */ + sw zero, GCR_L2_TAG_ADDR(t0) + sw zero, GCR_L2_TAG_ADDR_UPPER(t0) + sw zero, GCR_L2_TAG_STATE(t0) + sw zero, GCR_L2_TAG_STATE_UPPER(t0) + sw zero, GCR_L2_DATA(t0) + sw zero, GCR_L2_DATA_UPPER(t0) + sync +# else + /* We don't know how to retrieve L2 configuration on this system */ +# endif + b l2_probe_done +# endif + + /* + * For pre-r6 systems, or r6 systems with Config5.L2C==0, probe the L2 + * cache configuration from the cop0 Config2 register. + */ +l2_probe_cop0: + mfc0 t0, CP0_CONFIG, 2 + + srl R_L2_LINE, t0, MIPS_CONF2_SL_SHF + andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF + beqz R_L2_LINE, l2_probe_done + li t1, 2 + sllv R_L2_LINE, t1, R_L2_LINE + + srl t1, t0, MIPS_CONF2_SA_SHF + andi t1, t1, MIPS_CONF2_SA >> MIPS_CONF2_SA_SHF + addiu t1, t1, 1 + mul R_L2_SIZE, R_L2_LINE, t1 + + srl t1, t0, MIPS_CONF2_SS_SHF + andi t1, t1, MIPS_CONF2_SS >> MIPS_CONF2_SS_SHF + sllv R_L2_SIZE, R_L2_SIZE, t1 + li t1, 64 + mul R_L2_SIZE, R_L2_SIZE, t1 + + /* Attempt to bypass the L2 so that we can init the L1s early */ + or t0, t0, MIPS_CONF2_L2B + mtc0 t0, CP0_CONFIG, 2 + ehb + mfc0 t0, CP0_CONFIG, 2 + and R_L2_BYPASSED, t0, MIPS_CONF2_L2B + + /* Zero the L2 tag registers */ + mtc0 zero, CP0_TAGLO, 4 + ehb +l2_probe_done: +#endif + #ifndef CONFIG_SYS_CACHE_SIZE_AUTO - li t2, CONFIG_SYS_ICACHE_SIZE - li t8, CONFIG_SYS_ICACHE_LINE_SIZE + li R_IC_SIZE, CONFIG_SYS_ICACHE_SIZE + li R_IC_LINE, CONFIG_SYS_ICACHE_LINE_SIZE #else - l1_info t2, t8, MIPS_CONF1_IA_SHF + l1_info R_IC_SIZE, R_IC_LINE, MIPS_CONF1_IA_SHF #endif #ifndef CONFIG_SYS_CACHE_SIZE_AUTO - li t3, CONFIG_SYS_DCACHE_SIZE - li t9, CONFIG_SYS_DCACHE_LINE_SIZE + li R_DC_SIZE, CONFIG_SYS_DCACHE_SIZE + li R_DC_LINE, CONFIG_SYS_DCACHE_LINE_SIZE #else - l1_info t3, t9, MIPS_CONF1_DA_SHF + l1_info R_DC_SIZE, R_DC_LINE, MIPS_CONF1_DA_SHF #endif #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD @@ -123,9 +249,9 @@ LEAF(mips_cache_reset) li v0, CONFIG_SYS_DCACHE_SIZE #endif #else - move v0, t2 - sltu t1, t2, t3 - movn v0, t3, t1 + move v0, R_IC_SIZE + sltu t1, R_IC_SIZE, R_DC_SIZE + movn v0, R_DC_SIZE, t1 #endif /* * Now clear that much memory starting from zero. @@ -138,13 +264,36 @@ LEAF(mips_cache_reset) #endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */ +#ifdef CONFIG_MIPS_L2_CACHE + /* + * If the L2 is bypassed, init the L1 first so that we can execute the + * rest of the cache initialisation using the L1 instruction cache. + */ + bnez R_L2_BYPASSED, l1_init + +l2_init: + PTR_LI t0, INDEX_BASE + PTR_ADDU t1, t0, R_L2_SIZE +1: cache INDEX_STORE_TAG_SD, 0(t0) + PTR_ADDU t0, t0, R_L2_LINE + bne t0, t1, 1b + + /* + * If the L2 was bypassed then we already initialised the L1s before + * the L2, so we are now done. + */ + bnez R_L2_BYPASSED, l2_unbypass +#endif + /* * The TagLo registers used depend upon the CPU implementation, but the * architecture requires that it is safe for software to write to both * TagLo selects 0 & 2 covering supported cases. */ +l1_init: mtc0 zero, CP0_TAGLO mtc0 zero, CP0_TAGLO, 2 + ehb /* * The caches are probably in an indeterminate state, so we force good @@ -158,40 +307,122 @@ LEAF(mips_cache_reset) /* * Initialize the I-cache first, */ - blez t2, 1f + blez R_IC_SIZE, 1f PTR_LI t0, INDEX_BASE - PTR_ADDU t1, t0, t2 + PTR_ADDU t1, t0, R_IC_SIZE /* clear tag to invalidate */ - cache_loop t0, t1, t8, INDEX_STORE_TAG_I + cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD /* fill once, so data field parity is correct */ PTR_LI t0, INDEX_BASE - cache_loop t0, t1, t8, FILL + cache_loop t0, t1, R_IC_LINE, FILL /* invalidate again - prudent but not strictly neccessary */ PTR_LI t0, INDEX_BASE - cache_loop t0, t1, t8, INDEX_STORE_TAG_I + cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I +#endif + + /* Enable use of the I-cache by setting Config.K0 */ + sync + mfc0 t0, CP0_CONFIG + li t1, CONFIG_SYS_MIPS_CACHE_MODE +#if __mips_isa_rev >= 2 + ins t0, t1, 0, 3 +#else + ori t0, t0, CONF_CM_CMASK + xori t0, t0, CONF_CM_CMASK + or t0, t0, t1 #endif + mtc0 t0, CP0_CONFIG /* * then initialize D-cache. */ -1: blez t3, 3f +1: blez R_DC_SIZE, 3f PTR_LI t0, INDEX_BASE - PTR_ADDU t1, t0, t3 + PTR_ADDU t1, t0, R_DC_SIZE /* clear all tags */ - cache_loop t0, t1, t9, INDEX_STORE_TAG_D + cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD /* load from each line (in cached space) */ PTR_LI t0, INDEX_BASE 2: LONG_L zero, 0(t0) - PTR_ADDU t0, t9 + PTR_ADDU t0, R_DC_LINE bne t0, t1, 2b /* clear all tags */ PTR_LI t0, INDEX_BASE - cache_loop t0, t1, t9, INDEX_STORE_TAG_D + cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D #endif +3: + +#ifdef CONFIG_MIPS_L2_CACHE + /* If the L2 isn't bypassed then we're done */ + beqz R_L2_BYPASSED, return + + /* The L2 is bypassed - go initialise it */ + b l2_init -3: jr ra +l2_unbypass: +# if __mips_isa_rev >= 6 + beqz R_L2_L2C, 1f + + li t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE) + lw t1, GCR_L2_CONFIG(t0) + xor t1, t1, GCR_L2_CONFIG_BYPASS + sw t1, GCR_L2_CONFIG(t0) + sync + ehb + b 2f +# endif +1: mfc0 t0, CP0_CONFIG, 2 + xor t0, t0, MIPS_CONF2_L2B + mtc0 t0, CP0_CONFIG, 2 + ehb + +2: +# ifdef CONFIG_MIPS_CM + /* Config3 must exist for a CM to be present */ + mfc0 t0, CP0_CONFIG, 1 + bgez t0, 2f + mfc0 t0, CP0_CONFIG, 2 + bgez t0, 2f + + /* Check Config3.CMGCR to determine CM presence */ + mfc0 t0, CP0_CONFIG, 3 + and t0, t0, MIPS_CONF3_CMGCR + beqz t0, 2f + + /* Change Config.K0 to a coherent CCA */ + mfc0 t0, CP0_CONFIG + li t1, CONF_CM_CACHABLE_COW +#if __mips_isa_rev >= 2 + ins t0, t1, 0, 3 +#else + ori t0, t0, CONF_CM_CMASK + xori t0, t0, CONF_CM_CMASK + or t0, t0, t1 +#endif + mtc0 t0, CP0_CONFIG + + /* + * Join the coherent domain such that the caches of this core are kept + * coherent with those of other cores. + */ + PTR_LI t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE) + lw t1, GCR_REV(t0) + li t2, GCR_REV_CM3 + li t3, GCR_Cx_COHERENCE_EN + bge t1, t2, 1f + li t3, GCR_Cx_COHERENCE_DOM_EN +1: sw t3, GCR_Cx_COHERENCE(t0) + ehb +2: +# endif +#endif + +return: + /* Ensure all cache operations complete before returning */ + sync + jr ra END(mips_cache_reset) /* diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c index 5756a06..4ef5092 100644 --- a/arch/mips/mach-ath79/cpu.c +++ b/arch/mips/mach-ath79/cpu.c @@ -46,7 +46,7 @@ static const struct ath79_soc_desc desc[] = { {ATH79_SOC_QCA9561, "9561", REV_ID_MAJOR_QCA9561, 0}, }; -int arch_cpu_init(void) +int mach_cpu_init(void) { void __iomem *base; enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c index 073a179..0593ec4 100644 --- a/arch/mips/mach-ath79/reset.c +++ b/arch/mips/mach-ath79/reset.c @@ -5,7 +5,7 @@ */ #include <common.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/io.h> #include <asm/addrspace.h> #include <asm/types.h> diff --git a/arch/nds32/include/asm/errno.h b/arch/nds32/include/asm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/arch/nds32/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/arch/nios2/include/asm/errno.h b/arch/nios2/include/asm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/arch/nios2/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/arch/openrisc/include/asm/errno.h b/arch/openrisc/include/asm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/arch/openrisc/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/arch/powerpc/cpu/mpc512x/cpu.c b/arch/powerpc/cpu/mpc512x/cpu.c index 8508e8d..4ee91e1 100644 --- a/arch/powerpc/cpu/mpc512x/cpu.c +++ b/arch/powerpc/cpu/mpc512x/cpu.c @@ -95,11 +95,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) */ unsigned long get_tbclk (void) { - ulong tbclk; - - tbclk = (gd->bus_clk + 3L) / 4L; - - return tbclk; + return (gd->bus_clk + 3L) / 4L; } diff --git a/arch/powerpc/cpu/mpc512x/start.S b/arch/powerpc/cpu/mpc512x/start.S index 6c331d1..471d401 100644 --- a/arch/powerpc/cpu/mpc512x/start.S +++ b/arch/powerpc/cpu/mpc512x/start.S @@ -15,9 +15,6 @@ #include <asm-offsets.h> #include <config.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "MPC512X" -#endif #include <version.h> #define CONFIG_521X 1 /* needed for Linux kernel header files*/ diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index 3809309..c87f0fd 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -173,11 +173,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) unsigned long get_tbclk(void) { - ulong tbclk; - - tbclk = (gd->bus_clk + 3L) / 4L; - - return tbclk; + return (gd->bus_clk + 3L) / 4L; } diff --git a/arch/powerpc/cpu/mpc83xx/qe_io.c b/arch/powerpc/cpu/mpc83xx/qe_io.c index 106704d..14406af 100644 --- a/arch/powerpc/cpu/mpc83xx/qe_io.c +++ b/arch/powerpc/cpu/mpc83xx/qe_io.c @@ -7,10 +7,10 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "common.h" -#include "asm/errno.h" -#include "asm/io.h" -#include "asm/immap_83xx.h" +#include <common.h> +#include <linux/errno.h> +#include <asm/io.h> +#include <asm/immap_83xx.h> #define NUM_OF_PINS 32 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 9bd86d8..0001687 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -14,9 +14,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc83xx.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "MPC83XX" -#endif #include <version.h> #define CONFIG_83XX 1 /* needed for Linux kernel header files*/ diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index ebc9b81..810ddb0 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -10,7 +10,7 @@ #include <asm/io.h> #include <asm/processor.h> #include <asm/fsl_law.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <fsl_errata.h> #include "fsl_corenet2_serdes.h" diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 85739e9..72d5e30 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -13,7 +13,7 @@ #include <asm/io.h> #include <asm/processor.h> #include <asm/fsl_law.h> -#include <asm/errno.h> +#include <linux/errno.h> #include "fsl_corenet_serdes.h" /* diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c index d2825ec..49e82a2 100644 --- a/arch/powerpc/cpu/mpc85xx/qe_io.c +++ b/arch/powerpc/cpu/mpc85xx/qe_io.c @@ -7,10 +7,10 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "common.h" -#include "asm/errno.h" -#include "asm/io.h" -#include "asm/immap_85xx.h" +#include <common.h> +#include <linux/errno.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) #define NUM_OF_PINS 32 diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index 0ab9aac..e17e201 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -9,7 +9,7 @@ #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include <asm/fsl_srio.h> -#include <asm/errno.h> +#include <linux/errno.h> #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER #define SRIO_PORT_ACCEPT_ALL 0x10000001 diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pci.c b/arch/powerpc/cpu/ppc4xx/4xx_pci.c index 30e6c65..bfe48a2 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_pci.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_pci.c @@ -118,7 +118,8 @@ void pci_405gp_init(struct pci_controller *hose) #endif unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA}; unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS}; -#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405) +#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \ + || defined(CONFIG_TARGET_MIP405T) unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0}; unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0}; unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0}; @@ -408,7 +409,8 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); } -#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) +#if !(defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \ + || defined(CONFIG_TARGET_MIP405T)) /* *As is these functs get called out of flash Not a horrible diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c index f0f3462..a616365 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c @@ -18,7 +18,7 @@ #include <asm/ppc4xx.h> #include <asm/processor.h> #include <asm/io.h> -#include <asm/errno.h> +#include <linux/errno.h> #if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \ diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 92a330d..a6066ef 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -104,6 +104,9 @@ config TARGET_ICON config TARGET_MIP405 bool "Support MIP405" +config TARGET_MIP405T + bool "Support MIP405T" + config TARGET_PIP405 bool "Support PIP405" diff --git a/arch/powerpc/cpu/ppc4xx/resetvec.S b/arch/powerpc/cpu/ppc4xx/resetvec.S index b3308bd..a42d91f 100644 --- a/arch/powerpc/cpu/ppc4xx/resetvec.S +++ b/arch/powerpc/cpu/ppc4xx/resetvec.S @@ -4,7 +4,8 @@ #if defined(CONFIG_440) b _start_440 #else -#if defined(CONFIG_BOOT_PCI) && defined(CONFIG_MIP405) +#if defined(CONFIG_BOOT_PCI) && (defined(CONFIG_TARGET_MIP405) \ + || defined(CONFIG_TARGET_MIP405T)) b _start_pci #else b _start diff --git a/arch/powerpc/include/asm/errno.h b/arch/powerpc/include/asm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/arch/powerpc/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 2e937f0..f9154d3 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -79,13 +79,7 @@ #endif /* #ifdef CONFIG_SECURE_BOOT */ #ifdef CONFIG_CHAIN_OF_TRUST - #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_DM 1 -#define CONFIG_SPL_CRYPTO_SUPPORT -#define CONFIG_SPL_HASH_SUPPORT -#define CONFIG_SPL_RSA -#define CONFIG_SPL_DRIVERS_MISC_SUPPORT /* * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init * due to space crunch on CPC and thus malloc will not work. diff --git a/arch/powerpc/lib/ppcstring.S b/arch/powerpc/lib/ppcstring.S index 56bb3b8..4f60108 100644 --- a/arch/powerpc/lib/ppcstring.S +++ b/arch/powerpc/lib/ppcstring.S @@ -6,7 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <ppc_asm.tmpl> -#include <asm/errno.h> +#include <linux/errno.h> .globl strcpy strcpy: diff --git a/arch/sandbox/include/asm/errno.h b/arch/sandbox/include/asm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/arch/sandbox/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/arch/sh/include/asm/errno.h b/arch/sh/include/asm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/arch/sh/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/arch/sparc/include/asm/errno.h b/arch/sparc/include/asm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/arch/sparc/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index b31f24e..b312d9f 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -25,15 +25,9 @@ int cpu_mmc_init(bd_t *bis) #ifndef CONFIG_EFI_APP int arch_cpu_init(void) { - int ret; - post_code(POST_CPU_INIT); - ret = x86_cpu_init_f(); - if (ret) - return ret; - - return 0; + return x86_cpu_init_f(); } int arch_misc_init(void) diff --git a/arch/x86/cpu/ivybridge/ivybridge.c b/arch/x86/cpu/ivybridge/ivybridge.c index c770b53..e817eb9 100644 --- a/arch/x86/cpu/ivybridge/ivybridge.c +++ b/arch/x86/cpu/ivybridge/ivybridge.c @@ -10,13 +10,7 @@ int arch_cpu_init(void) { - int ret; - post_code(POST_CPU_INIT); - ret = x86_cpu_init_f(); - if (ret) - return ret; - - return 0; + return x86_cpu_init_f(); } diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 680e558..c3092f2 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -139,15 +139,9 @@ static void qemu_chipset_init(void) int arch_cpu_init(void) { - int ret; - post_code(POST_CPU_INIT); - ret = x86_cpu_init_f(); - if (ret) - return ret; - - return 0; + return x86_cpu_init_f(); } #ifndef CONFIG_EFI_STUB diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index b226e4c..f307c62 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -94,15 +94,9 @@ static int __maybe_unused disable_igd(void) int arch_cpu_init(void) { - int ret; - post_code(POST_CPU_INIT); - ret = x86_cpu_init_f(); - if (ret) - return ret; - - return 0; + return x86_cpu_init_f(); } int arch_early_init_r(void) diff --git a/arch/x86/include/asm/errno.h b/arch/x86/include/asm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/arch/x86/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index c480920..8e8d443 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -22,7 +22,7 @@ #ifdef __KERNEL__ -#include <asm/errno.h> +#include <linux/errno.h> struct msr { union { diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 82fd5c3..bac671d 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -6,7 +6,7 @@ */ #include <common.h> -#include <asm/errno.h> +#include <linux/errno.h> #include <asm/mtrr.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/xtensa/include/asm/errno.h b/arch/xtensa/include/asm/errno.h deleted file mode 100644 index 4c82b50..0000000 --- a/arch/xtensa/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/arch/xtensa/lib/time.c b/arch/xtensa/lib/time.c index 1332072..915eb51 100644 --- a/arch/xtensa/lib/time.c +++ b/arch/xtensa/lib/time.c @@ -104,10 +104,7 @@ unsigned long long get_ticks(void) */ ulong get_tbclk(void) { - ulong tbclk; - - tbclk = CONFIG_SYS_HZ; - return tbclk; + return CONFIG_SYS_HZ; } #if XCHAL_HAVE_CCOUNT |