diff options
Diffstat (limited to 'arch')
51 files changed, 1996 insertions, 63 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5ab0254..6542c38 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -419,6 +419,7 @@ config ARCH_EXYNOS select DM_SERIAL select DM_SPI select DM_GPIO + select DM_KEYBOARD config ARCH_S5PC1XX bool "Samsung S5PC1XX" diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index bd14326..1633ddc 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -273,12 +273,6 @@ void s_init(void) set_uart_mux_conf(); setup_clocks_for_console(); uart_soft_reset(); -#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT) - /* TODO: This does not work, gd is not available yet */ - gd->baudrate = CONFIG_BAUDRATE; - serial_init(); - gd->have_console = 1; -#endif #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) /* Enable RTC32K clock */ rtc32k_enable(); diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 459d5d8..33c76ef 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -49,5 +49,6 @@ obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o +obj-$(CONFIG_MACH_SUN8I_H3) += dram_sun8i_h3.o obj-y += fel_utils.o endif diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 794b829..0f26cb0 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -72,6 +72,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3) + sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); + sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index 3ab3b31..916ee48 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -34,9 +34,11 @@ void clock_init_safe(void) clock_set_pll1(408000000); - writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); - writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); + while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK)) + ; + + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c index 05fef32..1e73332 100644 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -69,6 +69,8 @@ int print_cpuinfo(void) puts("CPU: Allwinner A23 (SUN8I)\n"); #elif defined CONFIG_MACH_SUN8I_A33 puts("CPU: Allwinner A33 (SUN8I)\n"); +#elif defined CONFIG_MACH_SUN8I_H3 + puts("CPU: Allwinner H3 (SUN8I)\n"); #elif defined CONFIG_MACH_SUN9I puts("CPU: Allwinner A80 (SUN9I)\n"); #else diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c new file mode 100644 index 0000000..b721d60 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c @@ -0,0 +1,469 @@ +/* + * sun8i H3 platform dram controller init + * + * (C) Copyright 2007-2015 Allwinner Technology Co. + * Jerry Wang <wangflord@allwinnertech.com> + * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> + * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> + * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/dram.h> +#include <linux/kconfig.h> + +struct dram_para { + u32 read_delays; + u32 write_delays; + u16 page_size; + u8 bus_width; + u8 dual_rank; + u8 row_bits; +}; + +static inline int ns_to_t(int nanoseconds) +{ + const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; + + return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); +} + +static u32 bin_to_mgray(int val) +{ + static const u8 lookup_table[32] = { + 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, + 0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, + 0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d, + 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11, + }; + + return lookup_table[clamp(val, 0, 31)]; +} + +static int mgray_to_bin(u32 val) +{ + static const u8 lookup_table[32] = { + 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, + 0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b, + 0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b, + 0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15, + }; + + return lookup_table[val & 0x1f]; +} + +static void mctl_phy_init(u32 val) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + writel(val | PIR_INIT, &mctl_ctl->pir); + mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1); +} + +static void mctl_dq_delay(u32 read, u32 write) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + int i, j; + u32 val; + + for (i = 0; i < 4; i++) { + val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) | + DATX_IOCR_READ_DELAY((read >> (i * 4)) & 0xf); + + for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++) + setbits_le32(&mctl_ctl->datx[i].iocr[j], val); + } + + clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26); + + for (i = 0; i < 4; i++) { + val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) | + DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf); + + setbits_le32(&mctl_ctl->datx[i].iocr[DATX_IOCR_DQS], val); + setbits_le32(&mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN], val); + } + + setbits_le32(&mctl_ctl->pgcr[0], 1 << 26); + + udelay(1); +} + +static void mctl_set_master_priority(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + + /* enable bandwidth limit windows and set windows size 1us */ + writel(0x00010190, &mctl_com->bwcr); + + /* set cpu high priority */ + writel(0x00000001, &mctl_com->mapr); + + writel(0x0200000d, &mctl_com->mcr[0][0]); + writel(0x00800100, &mctl_com->mcr[0][1]); + writel(0x06000009, &mctl_com->mcr[1][0]); + writel(0x01000400, &mctl_com->mcr[1][1]); + writel(0x0200000d, &mctl_com->mcr[2][0]); + writel(0x00600100, &mctl_com->mcr[2][1]); + writel(0x0100000d, &mctl_com->mcr[3][0]); + writel(0x00200080, &mctl_com->mcr[3][1]); + writel(0x07000009, &mctl_com->mcr[4][0]); + writel(0x01000640, &mctl_com->mcr[4][1]); + writel(0x0100000d, &mctl_com->mcr[5][0]); + writel(0x00200080, &mctl_com->mcr[5][1]); + writel(0x01000009, &mctl_com->mcr[6][0]); + writel(0x00400080, &mctl_com->mcr[6][1]); + writel(0x0100000d, &mctl_com->mcr[7][0]); + writel(0x00400080, &mctl_com->mcr[7][1]); + writel(0x0100000d, &mctl_com->mcr[8][0]); + writel(0x00400080, &mctl_com->mcr[8][1]); + writel(0x04000009, &mctl_com->mcr[9][0]); + writel(0x00400100, &mctl_com->mcr[9][1]); + writel(0x2000030d, &mctl_com->mcr[10][0]); + writel(0x04001800, &mctl_com->mcr[10][1]); + writel(0x04000009, &mctl_com->mcr[11][0]); + writel(0x00400120, &mctl_com->mcr[11][1]); +} + +static void mctl_set_timing_params(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + u8 tccd = 2; + u8 tfaw = ns_to_t(50); + u8 trrd = max(ns_to_t(10), 4); + u8 trcd = ns_to_t(15); + u8 trc = ns_to_t(53); + u8 txp = max(ns_to_t(8), 3); + u8 twtr = max(ns_to_t(8), 4); + u8 trtp = max(ns_to_t(8), 4); + u8 twr = max(ns_to_t(15), 3); + u8 trp = ns_to_t(15); + u8 tras = ns_to_t(38); + u16 trefi = ns_to_t(7800) / 32; + u16 trfc = ns_to_t(350); + + u8 tmrw = 0; + u8 tmrd = 4; + u8 tmod = 12; + u8 tcke = 3; + u8 tcksrx = 5; + u8 tcksre = 5; + u8 tckesr = 4; + u8 trasmax = 24; + + u8 tcl = 6; /* CL 12 */ + u8 tcwl = 4; /* CWL 8 */ + u8 t_rdata_en = 4; + u8 wr_latency = 2; + + u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ + u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ + u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ + + u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ + u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ + u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ + + /* set mode register */ + writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ + writel(0x40, &mctl_ctl->mr[1]); + writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */ + writel(0x0, &mctl_ctl->mr[3]); + + /* set DRAM timing */ + writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | + DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), + &mctl_ctl->dramtmg[0]); + writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc), + &mctl_ctl->dramtmg[1]); + writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | + DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), + &mctl_ctl->dramtmg[2]); + writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), + &mctl_ctl->dramtmg[3]); + writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | + DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); + writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | + DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), + &mctl_ctl->dramtmg[5]); + + /* set two rank timing */ + clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), + (0x66 << 8) | (0x10 << 0)); + + /* set PHY interface timing, write latency and read latency configure */ + writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | + (wr_latency << 0), &mctl_ctl->pitmg[0]); + + /* set PHY timing, PTR0-2 use default */ + writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); + writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]); + + /* set refresh timing */ + writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg); +} + +static void mctl_zq_calibration(struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + int i; + u16 zq_val[6]; + u8 val; + + writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); + + for (i = 0; i < 6; i++) { + u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; + + writel((zq << 20) | (zq << 16) | (zq << 12) | + (zq << 8) | (zq << 4) | (zq << 0), + &mctl_ctl->zqcr); + + writel(PIR_CLRSR, &mctl_ctl->pir); + mctl_phy_init(PIR_ZCAL); + + zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff; + writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]); + + writel(PIR_CLRSR, &mctl_ctl->pir); + mctl_phy_init(PIR_ZCAL); + + val = readl(&mctl_ctl->zqdr[0]) >> 24; + zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8; + } + + writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); + writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); + writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]); +} + +static void mctl_set_cr(struct dram_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + + writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED | + MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) | + (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | + MCTL_CR_PAGE_SIZE(para->page_size) | + MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr); +} + +static void mctl_sys_init(struct dram_para *para) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); + clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); + clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); + clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); + udelay(10); + + clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); + udelay(1000); + + clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false); + clrsetbits_le32(&ccm->dram_clk_cfg, + CCM_DRAMCLK_CFG_DIV_MASK | CCM_DRAMCLK_CFG_SRC_MASK, + CCM_DRAMCLK_CFG_DIV(1) | CCM_DRAMCLK_CFG_SRC_PLL5 | + CCM_DRAMCLK_CFG_UPD); + mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); + + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); + setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); + setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); + + setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); + udelay(10); + + writel(0xc00e, &mctl_ctl->clken); + udelay(500); +} + +static int mctl_channel_init(struct dram_para *para) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + unsigned int i; + + mctl_set_cr(para); + mctl_set_timing_params(para); + mctl_set_master_priority(); + + /* setting VTC, default disable all VT */ + clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f); + clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26); + + /* increase DFI_PHY_UPD clock */ + writel(PROTECT_MAGIC, &mctl_com->protect); + udelay(100); + clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16); + writel(0x0, &mctl_com->protect); + udelay(100); + + /* set dramc odt */ + for (i = 0; i < 4; i++) + clrsetbits_le32(&mctl_ctl->datx[i].gcr, (0x3 << 4) | + (0x1 << 1) | (0x3 << 2) | (0x3 << 12) | + (0x3 << 14), + IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2); + + /* AC PDR should always ON */ + setbits_le32(&mctl_ctl->aciocr, 0x1 << 1); + + /* set DQS auto gating PD mode */ + setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6); + + /* dx ddr_clk & hdr_clk dynamic mode */ + clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12)); + + /* dphy & aphy phase select 270 degree */ + clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), + (0x1 << 10) | (0x2 << 8)); + + /* set half DQ */ + if (para->bus_width != 32) { + writel(0x0, &mctl_ctl->datx[2].gcr); + writel(0x0, &mctl_ctl->datx[3].gcr); + } + + /* data training configuration */ + clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, + (para->dual_rank ? 0x3 : 0x1) << 24); + + + if (para->read_delays || para->write_delays) { + mctl_dq_delay(para->read_delays, para->write_delays); + udelay(50); + } + + mctl_zq_calibration(para); + + mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST | + PIR_DRAMINIT | PIR_QSGATE); + + /* detect ranks and bus width */ + if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) { + /* only one rank */ + if (((readl(&mctl_ctl->datx[0].gsr[0]) >> 24) & 0x2) || + ((readl(&mctl_ctl->datx[1].gsr[0]) >> 24) & 0x2)) { + clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24); + para->dual_rank = 0; + } + + /* only half DQ width */ + if (((readl(&mctl_ctl->datx[2].gsr[0]) >> 24) & 0x1) || + ((readl(&mctl_ctl->datx[3].gsr[0]) >> 24) & 0x1)) { + writel(0x0, &mctl_ctl->datx[2].gcr); + writel(0x0, &mctl_ctl->datx[3].gcr); + para->bus_width = 16; + } + + mctl_set_cr(para); + udelay(20); + + /* re-train */ + mctl_phy_init(PIR_QSGATE); + if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) + return 1; + } + + /* check the dramc status */ + mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1); + + /* liuke added for refresh debug */ + setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31); + udelay(10); + clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31); + udelay(10); + + /* set PGCR3, CKE polarity */ + writel(0x00aa0060, &mctl_ctl->pgcr[3]); + + /* power down zq calibration module for power save */ + setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN); + + /* enable master access */ + writel(0xffffffff, &mctl_com->maer); + + return 0; +} + +static void mctl_auto_detect_dram_size(struct dram_para *para) +{ + /* detect row address bits */ + para->page_size = 512; + para->row_bits = 16; + mctl_set_cr(para); + + for (para->row_bits = 11; para->row_bits < 16; para->row_bits++) + if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size)) + break; + + /* detect page size */ + para->page_size = 8192; + mctl_set_cr(para); + + for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2) + if (mctl_mem_matches(para->page_size)) + break; +} + +unsigned long sunxi_dram_init(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + struct dram_para para = { + .read_delays = 0x00007979, + .write_delays = 0x6aaa0000, + .dual_rank = 0, + .bus_width = 32, + .row_bits = 15, + .page_size = 4096, + }; + + mctl_sys_init(¶); + if (mctl_channel_init(¶)) + return 0; + + if (para.dual_rank) + writel(0x00000303, &mctl_ctl->odtmap); + else + writel(0x00000201, &mctl_ctl->odtmap); + udelay(1); + + /* odt delay */ + writel(0x0c000400, &mctl_ctl->odtcfg); + + /* clear credit value */ + setbits_le32(&mctl_com->cccr, 1 << 31); + udelay(10); + + mctl_auto_detect_dram_size(¶); + mctl_set_cr(¶); + + return (1 << (para.row_bits + 3)) * para.page_size * + (para.dual_rank ? 2 : 1); +} diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c index dcb80b5..58312a7 100644 --- a/arch/arm/cpu/armv8/zynqmp/mp.c +++ b/arch/arm/cpu/armv8/zynqmp/mp.c @@ -183,6 +183,29 @@ static void set_r5_start(u8 high) writel(tmp, &rpu_base->rpu1_cfg); } +static void write_tcm_boot_trampoline(u32 boot_addr) +{ + if (boot_addr) { + /* + * Boot trampoline is simple ASM code below. + * + * b over; + * label: + * .word 0 + * over: ldr r0, =label + * ldr r1, [r0] + * bx r1 + */ + debug("Write boot trampoline for %x\n", boot_addr); + writel(0xea000000, ZYNQMP_TCM_START_ADDRESS); + writel(boot_addr, ZYNQMP_TCM_START_ADDRESS + 0x4); + writel(0xe59f0004, ZYNQMP_TCM_START_ADDRESS + 0x8); + writel(0xe5901000, ZYNQMP_TCM_START_ADDRESS + 0xc); + writel(0xe12fff11, ZYNQMP_TCM_START_ADDRESS + 0x10); + writel(0x00000004, ZYNQMP_TCM_START_ADDRESS + 0x14); // address for + } +} + int cpu_release(int nr, int argc, char * const argv[]) { if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { @@ -205,11 +228,18 @@ int cpu_release(int nr, int argc, char * const argv[]) } u32 boot_addr = simple_strtoul(argv[0], NULL, 16); + u32 boot_addr_uniq = 0; if (!(boot_addr == ZYNQMP_R5_LOVEC_ADDR || boot_addr == ZYNQMP_R5_HIVEC_ADDR)) { - printf("Invalid starting address 0x%x\n", boot_addr); - printf("0 or 0xffff0000 are permitted\n"); - return 1; + printf("Using TCM jump trampoline for address 0x%x\n", + boot_addr); + /* Save boot address for later usage */ + boot_addr_uniq = boot_addr; + /* + * R5 needs to start from LOVEC at TCM + * OCM will be probably occupied by ATF + */ + boot_addr = ZYNQMP_R5_LOVEC_ADDR; } if (!strncmp(argv[1], "lockstep", 8)) { @@ -219,6 +249,7 @@ int cpu_release(int nr, int argc, char * const argv[]) set_r5_start(boot_addr); enable_clock_r5(); release_r5_reset(LOCK); + write_tcm_boot_trampoline(boot_addr_uniq); set_r5_halt_mode(RELEASE, LOCK); } else if (!strncmp(argv[1], "split", 5)) { printf("R5 split mode\n"); @@ -226,6 +257,7 @@ int cpu_release(int nr, int argc, char * const argv[]) set_r5_halt_mode(HALT, SPLIT); enable_clock_r5(); release_r5_reset(SPLIT); + write_tcm_boot_trampoline(boot_addr_uniq); set_r5_halt_mode(RELEASE, SPLIT); } else { printf("Unsupported mode\n"); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9542fff..65e76ac 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -147,6 +147,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-cubietruck.dtb \ sun7i-a20-hummingbird.dtb \ sun7i-a20-i12-tvbox.dtb \ + sun7i-a20-lamobo-r1.dtb \ sun7i-a20-m3.dtb \ sun7i-a20-m5.dtb \ sun7i-a20-mk808c.dtb \ @@ -170,6 +171,9 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \ sun8i-a33-ga10h-v1.1.dtb \ sun8i-a33-q8-tablet.dtb \ sun8i-a33-sinlinx-sina33.dtb +dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-plus.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 0f49709..ac367f8 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -324,6 +324,7 @@ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; + clock-frequency = <24000000>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -337,6 +338,7 @@ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; + clock-frequency = <24000000>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -350,6 +352,7 @@ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; + clock-frequency = <24000000>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -362,6 +365,7 @@ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; + clock-frequency = <24000000>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -375,6 +379,7 @@ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; + clock-frequency = <24000000>; clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; diff --git a/arch/arm/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/dts/sun7i-a20-lamobo-r1.dts new file mode 100644 index 0000000..975b0b2 --- /dev/null +++ b/arch/arm/dts/sun7i-a20-lamobo-r1.dts @@ -0,0 +1,297 @@ +/* + * Copyright 2015 Jelle de Jong <jelledejong@powercraft.nl> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Lamobo R1"; + compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + serial1 = &uart3; + serial2 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_lamobo_r1>; + + green { + label = "lamobo_r1:green:usr"; + gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_power_pin_lamobo_r1>; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + }; +}; + +&ahci_pwr_pin_a { + allwinner,pins = "PB3"; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; + operating-points = < + /* kHz uV */ + 960000 1400000 + 912000 1400000 + 864000 1350000 + 720000 1250000 + 528000 1150000 + 312000 1100000 + 144000 1050000 + >; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_gmac_3v3>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&ir0 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_rx_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo_r1>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + mmc0_cd_pin_lamobo_r1: mmc0_cd_pin@0 { + allwinner,pins = "PH10"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + gmac_power_pin_lamobo_r1: gmac_power_pin@0 { + allwinner,pins = "PH23"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + led_pins_lamobo_r1: led_pins@0 { + allwinner,pins = "PH24"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +#include "axp209.dtsi" + +®_ahci_5v { + gpio = <&pio 1 3 0>; /* PB3 */ + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_a>, + <&spi0_cs0_pins_a>, + <&spi0_cs1_pins_a>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_b>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts new file mode 100644 index 0000000..4b25dcc --- /dev/null +++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2015 Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Xunlong Orange Pi PC"; + compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-plus.dts new file mode 100644 index 0000000..1cb6c66 --- /dev/null +++ b/arch/arm/dts/sun8i-h3-orangepi-plus.dts @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Xunlong Orange Pi Plus"; + compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_usb3_vbus: usb3-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_vbus_pin_a>; + regulator-name = "usb3-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&pio { + usb3_vbus_pin_a: usb3_vbus_pin@0 { + allwinner,pins = "PG11"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +®_usb1_vbus { + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb1_vbus_pin_a { + allwinner,pins = "PG13"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb3_vbus-supply = <®_usb3_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi new file mode 100644 index 0000000..0faa38a --- /dev/null +++ b/arch/arm/dts/sun8i-h3.dtsi @@ -0,0 +1,595 @@ +/* + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <24000000>; + arm,cpu-registers-not-fw-configured; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + pll1: clk@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + /* dummy clock until actually implemented */ + pll5: pll5_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "pll5"; + }; + + pll6: clk@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6", "pll6x2", "pll6d2"; + }; + + pll8: clk@01c20044 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20044 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll8", "pll8x2"; + }; + + cpu: cpu_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20050 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; + clock-output-names = "cpu"; + }; + + axi: axi_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-axi-clk"; + reg = <0x01c20050 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + ahb1: ahb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-ahb1-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; + clock-output-names = "ahb1"; + }; + + ahb2: ahb2_clk@01c2005c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-h3-ahb2-clk"; + reg = <0x01c2005c 0x4>; + clocks = <&ahb1>, <&pll6 2>; + clock-output-names = "ahb2"; + }; + + apb1: apb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb1>; + clock-output-names = "apb1"; + }; + + apb2: apb2_clk@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; + clock-output-names = "apb2"; + }; + + bus_gates: clk@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-h3-bus-gates-clk"; + reg = <0x01c20060 0x14>; + clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; + clock-names = "ahb1", "ahb2", "apb1", "apb2"; + clock-indices = <5>, <6>, <8>, + <9>, <10>, <13>, + <14>, <17>, <18>, + <19>, <20>, + <21>, <23>, + <24>, <25>, + <26>, <27>, + <28>, <29>, + <30>, <31>, <32>, + <35>, <36>, <37>, + <40>, <41>, <43>, + <44>, <52>, <53>, + <54>, <64>, + <65>, <69>, <72>, + <76>, <77>, <78>, + <96>, <97>, <98>, + <112>, <113>, + <114>, <115>, <116>, + <128>, <135>; + clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0", + "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand", + "ahb1_sdram", "ahb2_gmac", "ahb1_ts", + "ahb1_hstimer", "ahb1_spi0", + "ahb1_spi1", "ahb1_otg", + "ahb1_otg_ehci0", "ahb1_ehic1", + "ahb1_ehic2", "ahb1_ehic3", + "ahb1_otg_ohci0", "ahb2_ohic1", + "ahb2_ohic2", "ahb2_ohic3", "ahb1_ve", + "ahb1_lcd0", "ahb1_lcd1", "ahb1_deint", + "ahb1_csi", "ahb1_tve", "ahb1_hdmi", + "ahb1_de", "ahb1_gpu", "ahb1_msgbox", + "ahb1_spinlock", "apb1_codec", + "apb1_spdif", "apb1_pio", "apb1_ths", + "apb1_i2s0", "apb1_i2s1", "apb1_i2s2", + "apb2_i2c0", "apb2_i2c1", "apb2_i2c2", + "apb2_uart0", "apb2_uart1", + "apb2_uart2", "apb2_uart3", "apb2_scr", + "ahb1_ephy", "ahb1_dbg"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; + clock-output-names = "mmc0", + "mmc0_output", + "mmc0_sample"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; + clock-output-names = "mmc1", + "mmc1_output", + "mmc1_sample"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-a10-mmc-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; + clock-output-names = "mmc2", + "mmc2_output", + "mmc2_sample"; + }; + + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun8i-h3-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&osc24M>; + clock-output-names = "usb_phy0", "usb_phy1", + "usb_phy2", "usb_phy3", + "usb_ohci0", "usb_ohci1", + "usb_ohci2", "usb_ohci3"; + }; + + mbus_clk: clk@01c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-mbus-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5>; + clock-output-names = "mbus"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dma: dma-controller@01c02000 { + compatible = "allwinner,sun8i-h3-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 6>; + resets = <&bus_rst 6>; + #dma-cells = <1>; + }; + + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&bus_gates 8>, + <&mmc0_clk 0>, + <&mmc0_clk 1>, + <&mmc0_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&bus_rst 8>; + reset-names = "ahb"; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&bus_gates 9>, + <&mmc1_clk 0>, + <&mmc1_clk 1>, + <&mmc1_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&bus_rst 9>; + reset-names = "ahb"; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&bus_gates 10>, + <&mmc2_clk 0>, + <&mmc2_clk 1>, + <&mmc2_clk 2>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&bus_rst 10>; + reset-names = "ahb"; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbphy: phy@01c19400 { + compatible = "allwinner,sun8i-h3-usb-phy"; + reg = <0x01c19400 0x2c>, + <0x01c1a800 0x4>, + <0x01c1b800 0x4>, + <0x01c1c800 0x4>, + <0x01c1d800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2", + "pmu3"; + clocks = <&usb_clk 8>, + <&usb_clk 9>, + <&usb_clk 10>, + <&usb_clk 11>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy", + "usb3_phy"; + resets = <&usb_clk 0>, + <&usb_clk 1>, + <&usb_clk 2>, + <&usb_clk 3>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset", + "usb3_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci1: usb@01c1b000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1b000 0x100>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 25>, <&bus_gates 29>; + resets = <&bus_rst 25>, <&bus_rst 29>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@01c1b400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1b400 0x100>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 29>, <&bus_gates 25>, + <&usb_clk 17>; + resets = <&bus_rst 29>, <&bus_rst 25>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@01c1c000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 26>, <&bus_gates 30>; + resets = <&bus_rst 26>, <&bus_rst 30>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@01c1c400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 30>, <&bus_gates 26>, + <&usb_clk 18>; + resets = <&bus_rst 30>, <&bus_rst 26>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci3: usb@01c1d000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1d000 0x100>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 27>, <&bus_gates 31>; + resets = <&bus_rst 27>, <&bus_rst 31>; + phys = <&usbphy 3>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci3: usb@01c1d400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1d400 0x100>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 31>, <&bus_gates 27>, + <&usb_clk 19>; + resets = <&bus_rst 31>, <&bus_rst 27>; + phys = <&usbphy 3>; + phy-names = "usb"; + status = "disabled"; + }; + + pio: pinctrl@01c20800 { + compatible = "allwinner,sun8i-h3-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 69>; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <2>; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PA4", "PA5"; + allwinner,function = "uart0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_cd_pin: mmc0_cd_pin@0 { + allwinner,pins = "PF6"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + mmc1_pins_a: mmc1@0 { + allwinner,pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + allwinner,function = "mmc1"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + }; + + bus_rst: reset@01c202c0 { + #reset-cells = <1>; + compatible = "allwinner,sun8i-h3-bus-reset"; + reg = <0x01c202c0 0x1c>; + }; + + timer@01c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; + }; + + wdt0: watchdog@01c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 112>; + resets = <&bus_rst 144>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 113>; + resets = <&bus_rst 145>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 114>; + resets = <&bus_rst 146>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&bus_gates 115>; + resets = <&bus_rst 147>; + dmas = <&dma 9>, <&dma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + rtc: rtc@01f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +}; diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 479893e..a7da6b5 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -98,4 +98,7 @@ #define NUM_CRYSTAL_FREQ 0x4 +/* EDMA3 Base Address */ +#define EDMA3_BASE 0x49000000 + #endif /* __AM43XX_HARDWARE_AM43XX_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 845ba4f..d76514e 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -27,7 +27,6 @@ #endif #if defined(CONFIG_SYS_NS16550_SERIAL) -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_CLK get_serial_clock() diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 9b7b90c..09337a1 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -201,6 +201,7 @@ struct sunxi_ccm_reg { #define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) #define CCM_PLL6_CTRL_K_SHIFT 4 #define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) +#define CCM_PLL6_CTRL_LOCK (1 << 28) #define CCM_MIPI_PLL_CTRL_M_SHIFT 0 #define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT) @@ -219,7 +220,11 @@ struct sunxi_ccm_reg { #define CCM_PLL11_CTRL_UPD (0x1 << 30) #define CCM_PLL11_CTRL_EN (0x1 << 31) -#define AHB1_ABP1_DIV_DEFAULT 0x00002020 +#if defined CONFIG_MACH_SUN8I_H3 +#define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ +#else +#define AHB1_ABP1_DIV_DEFAULT 0x00002020 /* AHB1=AXI/4, APB1=AHB1/2 */ +#endif #define AXI_GATE_OFFSET_DRAM 0 @@ -282,6 +287,9 @@ struct sunxi_ccm_reg { #define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0) #define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) #define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8) +#define CCM_DRAMCLK_CFG_SRC_PLL5 (0x0 << 20) +#define CCM_DRAMCLK_CFG_SRC_PLL6x2 (0x1 << 20) +#define CCM_DRAMCLK_CFG_SRC_MASK (0x3 << 20) #define CCM_DRAMCLK_CFG_UPD (0x1 << 16) #define CCM_DRAMCLK_CFG_RST (0x1 << 31) diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index 273f80f..b3c1688 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -22,6 +22,8 @@ #include <asm/arch/dram_sun8i_a23.h> #elif defined(CONFIG_MACH_SUN8I_A33) #include <asm/arch/dram_sun8i_a33.h> +#elif defined(CONFIG_MACH_SUN8I_H3) +#include <asm/arch/dram_sun8i_h3.h> #else #include <asm/arch/dram_sun4i.h> #endif diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h new file mode 100644 index 0000000..d0f2b8a --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h @@ -0,0 +1,185 @@ +/* + * sun8i H3 platform dram controller register and constant defines + * + * (C) Copyright 2007-2015 Allwinner Technology Co. + * Jerry Wang <wangflord@allwinnertech.com> + * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> + * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> + * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DRAM_SUN8I_H3_H +#define _SUNXI_DRAM_SUN8I_H3_H + +struct sunxi_mctl_com_reg { + u32 cr; /* 0x00 control register */ + u8 res0[0xc]; /* 0x04 */ + u32 mcr[16][2]; /* 0x10 */ + u32 bwcr; /* 0x90 bandwidth control register */ + u32 maer; /* 0x94 master enable register */ + u32 mapr; /* 0x98 master priority register */ + u32 mcgcr; /* 0x9c */ + u32 cpu_bwcr; /* 0xa0 */ + u32 gpu_bwcr; /* 0xa4 */ + u32 ve_bwcr; /* 0xa8 */ + u32 disp_bwcr; /* 0xac */ + u32 other_bwcr; /* 0xb0 */ + u32 total_bwcr; /* 0xb4 */ + u8 res1[0x8]; /* 0xb8 */ + u32 swonr; /* 0xc0 */ + u32 swoffr; /* 0xc4 */ + u8 res2[0x8]; /* 0xc8 */ + u32 cccr; /* 0xd0 */ + u8 res3[0x72c]; /* 0xd4 */ + u32 protect; /* 0x800 */ +}; + +#define MCTL_CR_BL8 (0x4 << 20) + +#define MCTL_CR_1T (0x1 << 19) +#define MCTL_CR_2T (0x0 << 19) + +#define MCTL_CR_LPDDR3 (0x7 << 16) +#define MCTL_CR_LPDDR2 (0x6 << 16) +#define MCTL_CR_DDR3 (0x3 << 16) +#define MCTL_CR_DDR2 (0x2 << 16) + +#define MCTL_CR_SEQUENTIAL (0x1 << 15) +#define MCTL_CR_INTERLEAVED (0x0 << 15) + +#define MCTL_CR_32BIT (0x1 << 12) +#define MCTL_CR_16BIT (0x0 << 12) +#define MCTL_CR_BUS_WIDTH(x) ((x) == 32 ? MCTL_CR_32BIT : MCTL_CR_16BIT) + +#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) +#define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4) +#define MCTL_CR_EIGHT_BANKS (0x1 << 2) +#define MCTL_CR_FOUR_BANKS (0x0 << 2) +#define MCTL_CR_DUAL_RANK (0x1 << 0) +#define MCTL_CR_SINGLE_RANK (0x0 << 0) + +#define PROTECT_MAGIC (0x94be6fa3) + +struct sunxi_mctl_ctl_reg { + u32 pir; /* 0x00 PHY initialization register */ + u32 pwrctl; /* 0x04 */ + u32 mrctrl; /* 0x08 */ + u32 clken; /* 0x0c */ + u32 pgsr[2]; /* 0x10 PHY general status registers */ + u32 statr; /* 0x18 */ + u8 res1[0x14]; /* 0x1c */ + u32 mr[4]; /* 0x30 mode registers */ + u32 pllgcr; /* 0x40 */ + u32 ptr[5]; /* 0x44 PHY timing registers */ + u32 dramtmg[9]; /* 0x58 DRAM timing registers */ + u32 odtcfg; /* 0x7c */ + u32 pitmg[2]; /* 0x80 PHY interface timing registers */ + u8 res2[0x4]; /* 0x88 */ + u32 rfshctl0; /* 0x8c */ + u32 rfshtmg; /* 0x90 refresh timing */ + u32 rfshctl1; /* 0x94 */ + u32 pwrtmg; /* 0x98 */ + u8 res3[0x20]; /* 0x9c */ + u32 dqsgmr; /* 0xbc */ + u32 dtcr; /* 0xc0 */ + u32 dtar[4]; /* 0xc4 */ + u32 dtdr[2]; /* 0xd4 */ + u32 dtmr[2]; /* 0xdc */ + u32 dtbmr; /* 0xe4 */ + u32 catr[2]; /* 0xe8 */ + u32 dtedr[2]; /* 0xf0 */ + u8 res4[0x8]; /* 0xf8 */ + u32 pgcr[4]; /* 0x100 PHY general configuration registers */ + u32 iovcr[2]; /* 0x110 */ + u32 dqsdr; /* 0x118 */ + u32 dxccr; /* 0x11c */ + u32 odtmap; /* 0x120 */ + u32 zqctl[2]; /* 0x124 */ + u8 res6[0x14]; /* 0x12c */ + u32 zqcr; /* 0x140 ZQ control register */ + u32 zqsr; /* 0x144 ZQ status register */ + u32 zqdr[3]; /* 0x148 ZQ data registers */ + u8 res7[0x6c]; /* 0x154 */ + u32 sched; /* 0x1c0 */ + u32 perfhpr[2]; /* 0x1c4 */ + u32 perflpr[2]; /* 0x1cc */ + u32 perfwr[2]; /* 0x1d4 */ + u8 res8[0x2c]; /* 0x1dc */ + u32 aciocr; /* 0x208 */ + u8 res9[0xf4]; /* 0x20c */ + struct { /* 0x300 DATX8 modules*/ + u32 mdlr; /* 0x00 */ + u32 lcdlr[3]; /* 0x04 */ + u32 iocr[11]; /* 0x10 IO configuration register */ + u32 bdlr6; /* 0x3c */ + u32 gtr; /* 0x40 */ + u32 gcr; /* 0x44 */ + u32 gsr[3]; /* 0x48 */ + u8 res0[0x2c]; /* 0x54 */ + } datx[4]; + u8 res10[0x388]; /* 0x500 */ + u32 upd2; /* 0x888 */ +}; + +#define PTR3_TDINIT1(x) ((x) << 20) +#define PTR3_TDINIT0(x) ((x) << 0) + +#define PTR4_TDINIT3(x) ((x) << 20) +#define PTR4_TDINIT2(x) ((x) << 0) + +#define DRAMTMG0_TWTP(x) ((x) << 24) +#define DRAMTMG0_TFAW(x) ((x) << 16) +#define DRAMTMG0_TRAS_MAX(x) ((x) << 8) +#define DRAMTMG0_TRAS(x) ((x) << 0) + +#define DRAMTMG1_TXP(x) ((x) << 16) +#define DRAMTMG1_TRTP(x) ((x) << 8) +#define DRAMTMG1_TRC(x) ((x) << 0) + +#define DRAMTMG2_TCWL(x) ((x) << 24) +#define DRAMTMG2_TCL(x) ((x) << 16) +#define DRAMTMG2_TRD2WR(x) ((x) << 8) +#define DRAMTMG2_TWR2RD(x) ((x) << 0) + +#define DRAMTMG3_TMRW(x) ((x) << 16) +#define DRAMTMG3_TMRD(x) ((x) << 12) +#define DRAMTMG3_TMOD(x) ((x) << 0) + +#define DRAMTMG4_TRCD(x) ((x) << 24) +#define DRAMTMG4_TCCD(x) ((x) << 16) +#define DRAMTMG4_TRRD(x) ((x) << 8) +#define DRAMTMG4_TRP(x) ((x) << 0) + +#define DRAMTMG5_TCKSRX(x) ((x) << 24) +#define DRAMTMG5_TCKSRE(x) ((x) << 16) +#define DRAMTMG5_TCKESR(x) ((x) << 8) +#define DRAMTMG5_TCKE(x) ((x) << 0) + +#define RFSHTMG_TREFI(x) ((x) << 16) +#define RFSHTMG_TRFC(x) ((x) << 0) + +#define PIR_CLRSR (0x1 << 27) /* clear status registers */ +#define PIR_QSGATE (0x1 << 10) /* Read DQS gate training */ +#define PIR_DRAMINIT (0x1 << 8) /* DRAM initialization */ +#define PIR_DRAMRST (0x1 << 7) /* DRAM reset */ +#define PIR_PHYRST (0x1 << 6) /* PHY reset */ +#define PIR_DCAL (0x1 << 5) /* DDL calibration */ +#define PIR_PLLINIT (0x1 << 4) /* PLL initialization */ +#define PIR_ZCAL (0x1 << 1) /* ZQ calibration */ +#define PIR_INIT (0x1 << 0) /* PHY initialization trigger */ + +#define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */ + +#define ZQCR_PWRDOWN (0x1 << 31) /* ZQ power down */ + +#define DATX_IOCR_DQ(x) (x) /* DQ0-7 IOCR index */ +#define DATX_IOCR_DM (8) /* DM IOCR index */ +#define DATX_IOCR_DQS (9) /* DQS IOCR index */ +#define DATX_IOCR_DQSN (10) /* DQSN IOCR index */ + +#define DATX_IOCR_WRITE_DELAY(x) ((x) << 8) +#define DATX_IOCR_READ_DELAY(x) ((x) << 0) + +#endif /* _SUNXI_DRAM_SUN8I_H3_H */ diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 8382101..7af5e29 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -147,6 +147,7 @@ enum sunxi_gpio_number { #define SUN7I_GPA_GMAC 5 #define SUN6I_GPA_SDC2 5 #define SUN6I_GPA_SDC3 4 +#define SUN8I_H3_GPA_UART0 2 #define SUN4I_GPB_TWI0 2 #define SUN4I_GPB_TWI1 2 diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index f7737bf..9205b1e 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -49,6 +49,9 @@ config TARGET_GOFLEXHOME config TARGET_NAS220 bool "BlackArmor NAS220" +config TARGET_NSA310S + bool "Zyxel NSA310S" + endchoice config SYS_SOC @@ -69,5 +72,6 @@ source "board/raidsonic/ib62x0/Kconfig" source "board/Seagate/dockstar/Kconfig" source "board/Seagate/goflexhome/Kconfig" source "board/Seagate/nas220/Kconfig" +source "board/zyxel/nsa310s/Kconfig" endif diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 9dde710..1d49cab 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -70,6 +70,8 @@ #define CONFIG_PHYLIB #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ #define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ +#define CONFIG_ARP_TIMEOUT 200 +#define CONFIG_NET_RETRY_COUNT 50 #endif /* CONFIG_CMD_NET */ /* diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index ab50f4e..3f7dc8e 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -33,9 +33,6 @@ config DM_I2C config DM_GPIO default y -config ROCKCHIP_SERIAL - default y - source "arch/arm/mach-rockchip/rk3288/Kconfig" endif diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index a5b7e0d..de2454e 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -12,6 +12,7 @@ config TEGRA_ARMV7_COMMON select DM_I2C select DM_SPI select DM_GPIO + select DM_KEYBOARD choice prompt "Tegra SoC select" diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index b00e4b5..8c8927d 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -6,6 +6,8 @@ */ #include <common.h> +#include <dm.h> +#include <ns16550.h> #include <spl.h> #include <asm/io.h> #include <asm/arch/clock.h> @@ -212,6 +214,18 @@ void board_init_uart_f(void) setup_uarts(uart_ids); } +#if CONFIG_IS_ENABLED(DM_SERIAL) && !CONFIG_IS_ENABLED(OF_CONTROL) +static struct ns16550_platdata ns16550_com1_pdata = { + .base = CONFIG_SYS_NS16550_COM1, + .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, +}; + +U_BOOT_DEVICE(ns16550_com1) = { + "ns16550_serial", &ns16550_com1_pdata +}; +#endif + #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) void enable_caches(void) { diff --git a/arch/blackfin/lib/cmd_cache_dump.c b/arch/blackfin/lib/cmd_cache_dump.c index 412e019..f9f9097 100644 --- a/arch/blackfin/lib/cmd_cache_dump.c +++ b/arch/blackfin/lib/cmd_cache_dump.c @@ -9,6 +9,7 @@ #include <config.h> #include <common.h> #include <command.h> +#include <console.h> #include <asm/blackfin.h> #include <asm/mach-common/bits/mpu.h> diff --git a/arch/microblaze/include/asm/bitops.h b/arch/microblaze/include/asm/bitops.h index d24f2cf..2cab2ac 100644 --- a/arch/microblaze/include/asm/bitops.h +++ b/arch/microblaze/include/asm/bitops.h @@ -14,38 +14,14 @@ #ifdef __KERNEL__ /* - * Function prototypes to keep gcc -Wall happy - */ - -/* * The __ functions are not atomic */ -extern void set_bit(int nr, volatile void * addr); -extern void __set_bit(int nr, volatile void * addr); - -extern void clear_bit(int nr, volatile void * addr); -#define __clear_bit(nr, addr) clear_bit(nr, addr) -#define PLATFORM__CLEAR_BIT - -extern void change_bit(int nr, volatile void * addr); -extern void __change_bit(int nr, volatile void * addr); -extern int test_and_set_bit(int nr, volatile void * addr); -extern int __test_and_set_bit(int nr, volatile void * addr); -extern int test_and_clear_bit(int nr, volatile void * addr); -extern int __test_and_clear_bit(int nr, volatile void * addr); -extern int test_and_change_bit(int nr, volatile void * addr); -extern int __test_and_change_bit(int nr, volatile void * addr); -extern int __constant_test_bit(int nr, const volatile void * addr); -extern int __test_bit(int nr, volatile void * addr); -extern int find_first_zero_bit(void * addr, unsigned size); -extern int find_next_zero_bit (void * addr, int size, int offset); - /* * ffz = Find First Zero in word. Undefined if no zero exists, * so code should check against ~0UL first.. */ -extern __inline__ unsigned long ffz(unsigned long word) +static inline unsigned long ffz(unsigned long word) { unsigned long result = 0; @@ -57,7 +33,7 @@ extern __inline__ unsigned long ffz(unsigned long word) } -extern __inline__ void set_bit(int nr, volatile void * addr) +static inline void set_bit(int nr, volatile void *addr) { int * a = (int *) addr; int mask; @@ -70,7 +46,7 @@ extern __inline__ void set_bit(int nr, volatile void * addr) restore_flags(flags); } -extern __inline__ void __set_bit(int nr, volatile void * addr) +static inline void __set_bit(int nr, volatile void *addr) { int * a = (int *) addr; int mask; @@ -87,7 +63,7 @@ extern __inline__ void __set_bit(int nr, volatile void * addr) #define smp_mb__before_clear_bit() barrier() #define smp_mb__after_clear_bit() barrier() -extern __inline__ void clear_bit(int nr, volatile void * addr) +static inline void clear_bit(int nr, volatile void *addr) { int * a = (int *) addr; int mask; @@ -100,7 +76,10 @@ extern __inline__ void clear_bit(int nr, volatile void * addr) restore_flags(flags); } -extern __inline__ void change_bit(int nr, volatile void * addr) +#define __clear_bit(nr, addr) clear_bit(nr, addr) +#define PLATFORM__CLEAR_BIT + +static inline void change_bit(int nr, volatile void *addr) { int mask; unsigned long flags; @@ -113,7 +92,7 @@ extern __inline__ void change_bit(int nr, volatile void * addr) restore_flags(flags); } -extern __inline__ void __change_bit(int nr, volatile void * addr) +static inline void __change_bit(int nr, volatile void *addr) { int mask; unsigned long *ADDR = (unsigned long *) addr; @@ -123,7 +102,7 @@ extern __inline__ void __change_bit(int nr, volatile void * addr) *ADDR ^= mask; } -extern __inline__ int test_and_set_bit(int nr, volatile void * addr) +static inline int test_and_set_bit(int nr, volatile void *addr) { int mask, retval; volatile unsigned int *a = (volatile unsigned int *) addr; @@ -139,7 +118,7 @@ extern __inline__ int test_and_set_bit(int nr, volatile void * addr) return retval; } -extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) +static inline int __test_and_set_bit(int nr, volatile void *addr) { int mask, retval; volatile unsigned int *a = (volatile unsigned int *) addr; @@ -151,7 +130,7 @@ extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) return retval; } -extern __inline__ int test_and_clear_bit(int nr, volatile void * addr) +static inline int test_and_clear_bit(int nr, volatile void *addr) { int mask, retval; volatile unsigned int *a = (volatile unsigned int *) addr; @@ -167,7 +146,7 @@ extern __inline__ int test_and_clear_bit(int nr, volatile void * addr) return retval; } -extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) +static inline int __test_and_clear_bit(int nr, volatile void *addr) { int mask, retval; volatile unsigned int *a = (volatile unsigned int *) addr; @@ -179,7 +158,7 @@ extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) return retval; } -extern __inline__ int test_and_change_bit(int nr, volatile void * addr) +static inline int test_and_change_bit(int nr, volatile void *addr) { int mask, retval; volatile unsigned int *a = (volatile unsigned int *) addr; @@ -195,7 +174,7 @@ extern __inline__ int test_and_change_bit(int nr, volatile void * addr) return retval; } -extern __inline__ int __test_and_change_bit(int nr, volatile void * addr) +static inline int __test_and_change_bit(int nr, volatile void *addr) { int mask, retval; volatile unsigned int *a = (volatile unsigned int *) addr; @@ -210,12 +189,12 @@ extern __inline__ int __test_and_change_bit(int nr, volatile void * addr) /* * This routine doesn't need to be atomic. */ -extern __inline__ int __constant_test_bit(int nr, const volatile void * addr) +static inline int __constant_test_bit(int nr, const volatile void *addr) { return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0; } -extern __inline__ int __test_bit(int nr, volatile void * addr) +static inline int __test_bit(int nr, volatile void *addr) { int * a = (int *) addr; int mask; @@ -233,7 +212,7 @@ extern __inline__ int __test_bit(int nr, volatile void * addr) #define find_first_zero_bit(addr, size) \ find_next_zero_bit((addr), (size), 0) -extern __inline__ int find_next_zero_bit (void * addr, int size, int offset) +static inline int find_next_zero_bit(void *addr, int size, int offset) { unsigned long *p = ((unsigned long *) addr) + (offset >> 5); unsigned long result = offset & ~31UL; @@ -279,7 +258,7 @@ found_middle: #define hweight8(x) generic_hweight8(x) -extern __inline__ int ext2_set_bit(int nr, volatile void * addr) +static inline int ext2_set_bit(int nr, volatile void *addr) { int mask, retval; unsigned long flags; @@ -294,7 +273,7 @@ extern __inline__ int ext2_set_bit(int nr, volatile void * addr) return retval; } -extern __inline__ int ext2_clear_bit(int nr, volatile void * addr) +static inline int ext2_clear_bit(int nr, volatile void *addr) { int mask, retval; unsigned long flags; @@ -309,7 +288,7 @@ extern __inline__ int ext2_clear_bit(int nr, volatile void * addr) return retval; } -extern __inline__ int ext2_test_bit(int nr, const volatile void * addr) +static inline int ext2_test_bit(int nr, const volatile void *addr) { int mask; const volatile unsigned char *ADDR = (const unsigned char *) addr; diff --git a/arch/microblaze/include/asm/system.h b/arch/microblaze/include/asm/system.h index 0297a11..3107748 100644 --- a/arch/microblaze/include/asm/system.h +++ b/arch/microblaze/include/asm/system.h @@ -131,7 +131,7 @@ extern void *switch_thread (struct thread_struct *last, ((__typeof__ (*(ptr)))__xchg ((unsigned long)(with), (ptr), sizeof (*(ptr)))) #define tas(ptr) (xchg ((ptr), 1)) -extern inline unsigned long __xchg (unsigned long with, +static inline unsigned long __xchg(unsigned long with, __volatile__ void *ptr, int size) { unsigned long tmp, flags; diff --git a/arch/nios2/dts/10m50_devboard.dts b/arch/nios2/dts/10m50_devboard.dts index e89dbb2..05eac30 100644 --- a/arch/nios2/dts/10m50_devboard.dts +++ b/arch/nios2/dts/10m50_devboard.dts @@ -262,6 +262,6 @@ chosen { bootargs = "debug console=ttyS0,115200"; - stdout-path = &uart_0; + stdout-path = &a_16550_uart_0; }; }; diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c index 30ea3de..9bb395e 100644 --- a/arch/powerpc/cpu/mpc8260/ether_fcc.c +++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c @@ -24,6 +24,7 @@ */ #include <common.h> +#include <console.h> #include <malloc.h> #include <asm/cpm_8260.h> #include <mpc8260.h> diff --git a/arch/powerpc/cpu/mpc8260/i2c.c b/arch/powerpc/cpu/mpc8260/i2c.c index 8658ebd..a0de101 100644 --- a/arch/powerpc/cpu/mpc8260/i2c.c +++ b/arch/powerpc/cpu/mpc8260/i2c.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <console.h> #if defined(CONFIG_HARD_I2C) diff --git a/arch/powerpc/cpu/mpc8xx/i2c.c b/arch/powerpc/cpu/mpc8xx/i2c.c index 6146de3..3dff4ab 100644 --- a/arch/powerpc/cpu/mpc8xx/i2c.c +++ b/arch/powerpc/cpu/mpc8xx/i2c.c @@ -12,6 +12,7 @@ */ #include <common.h> +#include <console.h> #ifdef CONFIG_HARD_I2C diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 65496d0..bb23756 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -104,4 +104,12 @@ /* All PPC boards must swap IDE bytes */ #define CONFIG_IDE_SWAP_IO +#if defined(CONFIG_DM_SERIAL) +/* + * TODO: Convert this to a clock driver exists that can give us the UART + * clock here. + */ +#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif + #endif /* _ASM_CONFIG_H_ */ diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index f078c9e..25e316c 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -17,4 +17,7 @@ config PCI used on some devices to allow the CPU to communicate with its peripherals. +config DM_KEYBOARD + default y + endmenu diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 3a7f5a0..196f3e1 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -37,7 +37,10 @@ void sandbox_exit(void) /* delay x useconds */ void __udelay(unsigned long usec) { - os_usleep(usec); + struct sandbox_state *state = state_get_current(); + + if (!state->skip_delays) + os_usleep(usec); } int cleanup_before_linux(void) diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 4c38fab..0dda4fc 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -257,6 +257,14 @@ static int sandbox_cmdline_cb_terminal(struct sandbox_state *state, SANDBOX_CMDLINE_OPT_SHORT(terminal, 't', 1, "Set terminal to raw/cooked mode"); +static int sandbox_cmdline_cb_verbose(struct sandbox_state *state, + const char *arg) +{ + state->show_test_output = true; + return 0; +} +SANDBOX_CMDLINE_OPT_SHORT(verbose, 'v', 0, "Show test output"); + int main(int argc, char *argv[]) { struct sandbox_state *state; diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index 7e5d03e..d2a7dc9 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -337,6 +337,20 @@ struct sandbox_state *state_get_current(void) return state; } +void state_set_skip_delays(bool skip_delays) +{ + struct sandbox_state *state = state_get_current(); + + state->skip_delays = skip_delays; +} + +bool state_get_skip_delays(void) +{ + struct sandbox_state *state = state_get_current(); + + return state->skip_delays; +} + int state_init(void) { state = &main_state; diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 08f72ac..720ef93 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -177,6 +177,10 @@ sides = <4>; }; + timer { + compatible = "sandbox,timer"; + }; + tpm { compatible = "google,sandbox-tpm"; }; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index e2c4971..b6d9a15 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -307,12 +307,29 @@ compatible = "sandbox,usb-hub"; #address-cells = <1>; #size-cells = <0>; - flash-stick { + flash-stick@0 { reg = <0>; compatible = "sandbox,usb-flash"; sandbox,filepath = "testflash.bin"; }; + flash-stick@1 { + reg = <1>; + compatible = "sandbox,usb-flash"; + sandbox,filepath = "testflash1.bin"; + }; + + flash-stick@2 { + reg = <2>; + compatible = "sandbox,usb-flash"; + sandbox,filepath = "testflash2.bin"; + }; + + keyb@3 { + reg = <3>; + compatible = "sandbox,usb-keyb"; + }; + }; }; }; diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index 2bd28f6..11856c2 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -63,6 +63,8 @@ struct sandbox_state { enum reset_t last_reset; /* Last reset type */ bool reset_allowed[RESET_COUNT]; /* Allowed reset types */ enum state_terminal_raw term_raw; /* Terminal raw/cooked */ + bool skip_delays; /* Ignore any time delays (for test) */ + bool show_test_output; /* Don't suppress stdout in tests */ /* Pointer to information for each SPI bus/cs */ struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS] @@ -185,6 +187,24 @@ int sandbox_write_state(struct sandbox_state *state, const char *fname); int state_setprop(int node, const char *prop_name, const void *data, int size); /** + * Control skipping of time delays + * + * Some tests have unnecessay time delays (e.g. USB). Allow these to be + * skipped to speed up testing + * + * @param skip_delays true to skip delays from now on, false to honour delay + * requests + */ +void state_set_skip_delays(bool skip_delays); + +/** + * See if delays should be skipped + * + * @return true if delays should be skipped, false if they should be honoured + */ +bool state_get_skip_delays(void); + +/** * Initialize the test system state */ int state_init(void); diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index d3c7851..224b0eb 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -86,4 +86,6 @@ long sandbox_i2c_rtc_set_offset(struct udevice *dev, bool use_system_time, */ long sandbox_i2c_rtc_get_set_base_time(struct udevice *dev, long base_time); +int sandbox_usb_keyb_add_string(struct udevice *dev, const char *str); + #endif diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index 6dad3c7..69cdca3 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -7,6 +7,7 @@ #include <common.h> #include <command.h> +#include <console.h> #include <malloc.h> #include <stdio_dev.h> #include <version.h> diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c index d2ac6bc..10475d1 100644 --- a/arch/sparc/lib/board.c +++ b/arch/sparc/lib/board.c @@ -11,6 +11,7 @@ #include <common.h> #include <command.h> +#include <console.h> #include <malloc.h> #include <stdio_dev.h> #include <config.h> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 8914be3..14ab98e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -435,6 +435,12 @@ config I8254_TIMER Intel 8254 timer contains three counters which have fixed uses. Include this to have U-Boot set up the timer correctly. +config I8042_KEYB + default y + +config DM_KEYBOARD + default y + source "arch/x86/lib/efi/Kconfig" endmenu diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 52d0999..aa86387 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -10,6 +10,7 @@ #include <dt-bindings/interrupt-router/intel-irq.h> /include/ "skeleton.dtsi" +/include/ "keyboard.dtsi" /include/ "serial.dtsi" /include/ "rtc.dtsi" diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index f27263a..7870bb1 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -1,6 +1,7 @@ /dts-v1/; /include/ "skeleton.dtsi" +/include/ "keyboard.dtsi" /include/ "serial.dtsi" /include/ "rtc.dtsi" @@ -41,6 +42,10 @@ stdout-path = "/serial"; }; + keyboard { + intel,duplicate-por; + }; + spd { compatible = "memory-spd"; #address-cells = <1>; diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 3e354c4..eb8421c 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "keyboard.dtsi" /include/ "rtc.dtsi" / { diff --git a/arch/x86/dts/keyboard.dtsi b/arch/x86/dts/keyboard.dtsi new file mode 100644 index 0000000..000751b --- /dev/null +++ b/arch/x86/dts/keyboard.dtsi @@ -0,0 +1,5 @@ +/ { + keyboard { + compatible = "intel,i8042-keyboard"; + }; +}; diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index fc74cd0..8da7e52 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "keyboard.dtsi" /include/ "rtc.dtsi" / { diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index 7f16971..df30c89 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -20,6 +20,7 @@ /include/ "skeleton.dtsi" /include/ "serial.dtsi" +/include/ "keyboard.dtsi" /include/ "rtc.dtsi" / { diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi index 6865eed..54c3faf 100644 --- a/arch/x86/dts/serial.dtsi +++ b/arch/x86/dts/serial.dtsi @@ -1,6 +1,6 @@ / { serial: serial { - compatible = "x86-uart"; + compatible = "ns16550"; reg = <0x3f8 8>; reg-shift = <0>; clock-frequency = <1843200>; |