diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 16 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 9 |
2 files changed, 16 insertions, 9 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 0524172..d151f49 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -330,6 +330,7 @@ endchoice config ARCH_B4420 bool select E500MC + select E6500 select FSL_LAW select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004477 @@ -350,6 +351,7 @@ config ARCH_B4420 config ARCH_B4860 bool select E500MC + select E6500 select FSL_LAW select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004477 @@ -806,6 +808,7 @@ config ARCH_T1042 config ARCH_T2080 bool select E500MC + select E6500 select FSL_LAW select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 @@ -822,6 +825,7 @@ config ARCH_T2080 config ARCH_T2081 bool select E500MC + select E6500 select FSL_LAW select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 @@ -838,6 +842,7 @@ config ARCH_T2081 config ARCH_T4160 bool select E500MC + select E6500 select FSL_LAW select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004468 @@ -855,6 +860,7 @@ config ARCH_T4160 config ARCH_T4240 bool select E500MC + select E6500 select FSL_LAW select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004468 @@ -885,6 +891,11 @@ config E500MC help Enble PowerPC E500MC core +config E6500 + bool + help + Enable PowerPC E6500 core + config FSL_LAW bool help @@ -1165,6 +1176,11 @@ config SYS_FSL_NUM_LAWS Number of local access windows. This is fixed per SoC. If not sure, do not change. +config SYS_FSL_THREADS_PER_CORE + int + default 2 if E6500 + default 1 + config SYS_NUM_TLBCAMS int "Number of TLB CAM entries" default 64 if E500MC diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 2a826fe..92c96d7 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -238,7 +238,6 @@ #define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) -#define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ @@ -284,7 +283,6 @@ #define CONFIG_SYS_FSL_PCI_VER_3_X #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) -#define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ @@ -399,7 +397,6 @@ #define CONFIG_SYS_FSL_SFP_VER_3_0 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) -#define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ @@ -451,12 +448,6 @@ #endif -#ifdef CONFIG_E6500 -#define CONFIG_SYS_FSL_THREADS_PER_CORE 2 -#else -#define CONFIG_SYS_FSL_THREADS_PER_CORE 1 -#endif - #if !defined(CONFIG_ARCH_C29X) #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #endif |