diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 33 |
1 files changed, 31 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index a334f49..56f8aa5 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -1385,7 +1385,30 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -#ifndef CONFIG_MX6SX +static void pre_misc_setting(void) +{ + /* Bypass IPU1 QoS generator */ + writel(0x00000002, 0x00bb048c); + /* Bypass IPU2 QoS generator */ + writel(0x00000002, 0x00bb050c); + /* Bandwidth THR for of PRE0 */ + writel(0x00000200, 0x00bb0690); + /* Bandwidth THR for of PRE1 */ + writel(0x00000200, 0x00bb0710); + /* Bandwidth THR for of PRE2 */ + writel(0x00000200, 0x00bb0790); + /* Bandwidth THR for of PRE3 */ + writel(0x00000200, 0x00bb0810); + /* Saturation THR for of PRE0 */ + writel(0x00000020, 0x00bb0694); + /* Saturation THR for of PRE1 */ + writel(0x00000020, 0x00bb0714); + /* Saturation THR for of PRE2 */ + writel(0x00000020, 0x00bb0794); + /* Saturation THR for of PRE */ + writel(0x00000020, 0x00bb0814); +} + void enable_ipu_clock(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -1397,9 +1420,15 @@ void enable_ipu_clock(void) if (is_mx6dqp()) { setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); + + /* + * Since CONFIG_VIDEO_IPUV3 is always set in mx6sabre_common.h and + * this misc setting is a must for mx6qp, this position is ok + * to do such settings. + */ + pre_misc_setting(); } } -#endif #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \ defined(CONFIG_MX6S) |