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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/cpu/armv7/socfpga/freeze_controller.c6
-rw-r--r--arch/arm/cpu/armv7/socfpga/reset_manager.c4
-rw-r--r--arch/arm/cpu/armv7/uniphier/init_page_table.c4
-rw-r--r--arch/arm/dts/socfpga.dtsi56
-rw-r--r--arch/arm/dts/socfpga_cyclone5.dtsi13
-rw-r--r--arch/arm/dts/socfpga_cyclone5_socrates.dts39
-rw-r--r--arch/arm/dts/uniphier-ph1-ld4-ref.dts8
-rw-r--r--arch/arm/dts/uniphier-ph1-pro4-ref.dts8
-rw-r--r--arch/arm/dts/uniphier-ph1-sld3-ref.dts6
-rw-r--r--arch/arm/dts/uniphier-ph1-sld8-ref.dts8
-rw-r--r--arch/arm/include/asm/arch-socfpga/clock_manager.h1
-rw-r--r--arch/arm/include/asm/arch-socfpga/freeze_controller.h1
-rw-r--r--arch/arm/include/asm/arch-socfpga/scan_manager.h1
-rw-r--r--arch/powerpc/cpu/mpc85xx/p5040_ids.c24
-rw-r--r--arch/powerpc/cpu/mpc85xx/portals.c43
-rw-r--r--arch/powerpc/cpu/mpc85xx/tlb.c12
17 files changed, 157 insertions, 78 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2b0d2c9..5eb1d03 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -800,6 +800,7 @@ config ARCH_UNIPHIER
bool "Panasonic UniPhier platform"
select CPU_V7
select SUPPORT_SPL
+ select SPL
select OF_CONTROL if !SPL_BUILD
endchoice
diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/arch/arm/cpu/armv7/socfpga/freeze_controller.c
index b8c9bce..0be643c 100644
--- a/arch/arm/cpu/armv7/socfpga/freeze_controller.c
+++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c
@@ -38,8 +38,7 @@ void sys_mgr_frzctrl_freeze_req(void)
/* Freeze channel 0 to 2 */
for (channel_id = 0; channel_id <= 2; channel_id++) {
ioctrl_reg_offset = (u32)(
- &freeze_controller_base->vioctrl +
- (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
+ &freeze_controller_base->vioctrl + channel_id);
/*
* Assert active low enrnsl, plniotri
@@ -120,8 +119,7 @@ void sys_mgr_frzctrl_thaw_req(void)
/* Thaw channel 0 to 2 */
for (channel_id = 0; channel_id <= 2; channel_id++) {
ioctrl_reg_offset
- = (u32)(&freeze_controller_base->vioctrl
- + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
+ = (u32)(&freeze_controller_base->vioctrl + channel_id);
/*
* Assert active low bhniotri signal and
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index af9db85..25921e7 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -110,6 +110,6 @@ void socfpga_spim_enable(void)
{
const void *reset = &reset_manager_base->per_mod_reset;
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);
+ clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) |
+ (1 << RSTMGR_PERMODRST_SPIM1_LSB));
}
diff --git a/arch/arm/cpu/armv7/uniphier/init_page_table.c b/arch/arm/cpu/armv7/uniphier/init_page_table.c
index a0d10a9..febb3c8 100644
--- a/arch/arm/cpu/armv7/uniphier/init_page_table.c
+++ b/arch/arm/cpu/armv7/uniphier/init_page_table.c
@@ -17,11 +17,7 @@
#define REG DEVICE /* IO Register: Device */
#define DDR DEVICE /* DDR SDRAM: Device */
-#ifdef CONFIG_SPL_BUILD
#define IS_SPL_TEXT_AREA(x) ((x) == ((CONFIG_SPL_TEXT_BASE) >> 20))
-#else
-#define IS_SPL_TEXT_AREA(x) ((x) == ((CONFIG_SYS_TEXT_BASE) >> 20))
-#endif
#define IS_INIT_STACK_AREA(x) ((x) == ((CONFIG_SYS_INIT_SP_ADDR) >> 20))
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 4472fd9..969e5ad 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -1,18 +1,7 @@
/*
* Copyright (C) 2012 Altera <www.altera.com>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include "skeleton.dtsi"
@@ -639,6 +628,49 @@
clock-names = "biu", "ciu";
};
+ qspi: spi@ff705000 {
+ compatible = "cadence,qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff705000 0x1000>,
+ <0xffa00000 0x1000>;
+ interrupts = <0 151 4>;
+ clocks = <&qspi_clk>;
+ ext-decoder = <0>; /* external decoder */
+ num-chipselect = <4>;
+ fifo-depth = <128>;
+ bus-num = <2>;
+ status = "disabled";
+ };
+
+ spi0: spi@fff00000 {
+ compatible = "snps,dw-spi-mmio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfff00000 0x1000>;
+ interrupts = <0 154 4>;
+ num-chipselect = <4>;
+ bus-num = <0>;
+ tx-dma-channel = <&pdma 16>;
+ rx-dma-channel = <&pdma 17>;
+ clocks = <&per_base_clk>;
+ status = "disabled";
+ };
+
+ spi1: spi@fff01000 {
+ compatible = "snps,dw-spi-mmio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfff01000 0x1000>;
+ interrupts = <0 156 4>;
+ num-chipselect = <4>;
+ bus-num = <1>;
+ tx-dma-channel = <&pdma 20>;
+ rx-dma-channel = <&pdma 21>;
+ clocks = <&per_base_clk>;
+ status = "disabled";
+ };
+
/* Local timer */
timer@fffec600 {
compatible = "arm,cortex-a9-twd-timer";
diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi
index 28c05e7..234a901 100644
--- a/arch/arm/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5.dtsi
@@ -1,18 +1,7 @@
/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index a1814b4..ea30483 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -1,18 +1,7 @@
/*
* Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include "socfpga_cyclone5.dtsi"
@@ -25,6 +14,12 @@
bootargs = "console=ttyS0,115200";
};
+ aliases {
+ spi0 = "/spi@ff705000"; /* QSPI */
+ spi1 = "/spi@fff00000";
+ spi2 = "/spi@fff01000";
+ };
+
memory {
name = "memory";
device_type = "memory";
@@ -48,3 +43,23 @@
&mmc {
status = "okay";
};
+
+&qspi {
+ status = "okay";
+
+ flash0: n25q00@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00";
+ reg = <0>; /* chip select */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ page-size = <256>;
+ block-size = <16>; /* 2^16, 64KB */
+ read-delay = <4>; /* delay value in read data capture register */
+ tshsl-ns = <50>;
+ tsd2d-ns = <50>;
+ tchsh-ns = <4>;
+ tslch-ns = <4>;
+ };
+};
diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
index 08bbd03..6855878 100644
--- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
@@ -25,10 +25,10 @@
};
aliases {
- uart0 = &uart0;
- uart1 = &uart1;
- uart2 = &uart2;
- uart3 = &uart3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
index 23add7c..1227b62 100644
--- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
@@ -25,10 +25,10 @@
};
aliases {
- uart0 = &uart0;
- uart1 = &uart1;
- uart2 = &uart2;
- uart3 = &uart3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
index 91b4dbe..fefc592 100644
--- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
@@ -25,9 +25,9 @@
};
aliases {
- uart0 = &uart0;
- uart1 = &uart1;
- uart2 = &uart2;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
index a8ce049..9b6d95c 100644
--- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
@@ -25,10 +25,10 @@
};
aliases {
- uart0 = &uart0;
- uart1 = &uart1;
- uart2 = &uart2;
- uart3 = &uart3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h
index fa49f6a..5449726 100644
--- a/arch/arm/include/asm/arch-socfpga/clock_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h
@@ -14,6 +14,7 @@ unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
#endif
typedef struct {
diff --git a/arch/arm/include/asm/arch-socfpga/freeze_controller.h b/arch/arm/include/asm/arch-socfpga/freeze_controller.h
index 120f20e..f19ad87 100644
--- a/arch/arm/include/asm/arch-socfpga/freeze_controller.h
+++ b/arch/arm/include/asm/arch-socfpga/freeze_controller.h
@@ -42,7 +42,6 @@ typedef enum {
#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
-#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2
void sys_mgr_frzctrl_freeze_req(void);
void sys_mgr_frzctrl_thaw_req(void);
diff --git a/arch/arm/include/asm/arch-socfpga/scan_manager.h b/arch/arm/include/asm/arch-socfpga/scan_manager.h
index b2686d3..1155fd3 100644
--- a/arch/arm/include/asm/arch-socfpga/scan_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/scan_manager.h
@@ -13,6 +13,7 @@ struct socfpga_scan_manager {
u32 padding[2];
u32 fifo_single_byte;
u32 fifo_double_byte;
+ u32 fifo_triple_byte;
u32 fifo_quad_byte;
};
diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
index d4343ef..98a568f 100644
--- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
@@ -49,23 +49,23 @@ int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
#ifdef CONFIG_SYS_DPAA_FMAN
struct liodn_id_table fman1_liodn_tbl[] = {
- SET_FMAN_RX_1G_LIODN(1, 0, 6),
- SET_FMAN_RX_1G_LIODN(1, 1, 7),
- SET_FMAN_RX_1G_LIODN(1, 2, 8),
- SET_FMAN_RX_1G_LIODN(1, 3, 9),
- SET_FMAN_RX_1G_LIODN(1, 4, 10),
- SET_FMAN_RX_10G_LIODN(1, 0, 11),
+ SET_FMAN_RX_1G_LIODN(1, 0, 11),
+ SET_FMAN_RX_1G_LIODN(1, 1, 12),
+ SET_FMAN_RX_1G_LIODN(1, 2, 13),
+ SET_FMAN_RX_1G_LIODN(1, 3, 14),
+ SET_FMAN_RX_1G_LIODN(1, 4, 15),
+ SET_FMAN_RX_10G_LIODN(1, 0, 16),
};
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
#if (CONFIG_SYS_NUM_FMAN == 2)
struct liodn_id_table fman2_liodn_tbl[] = {
- SET_FMAN_RX_1G_LIODN(2, 0, 12),
- SET_FMAN_RX_1G_LIODN(2, 1, 13),
- SET_FMAN_RX_1G_LIODN(2, 2, 14),
- SET_FMAN_RX_1G_LIODN(2, 3, 15),
- SET_FMAN_RX_1G_LIODN(2, 4, 16),
- SET_FMAN_RX_10G_LIODN(2, 0, 17),
+ SET_FMAN_RX_1G_LIODN(2, 0, 17),
+ SET_FMAN_RX_1G_LIODN(2, 1, 18),
+ SET_FMAN_RX_1G_LIODN(2, 2, 19),
+ SET_FMAN_RX_1G_LIODN(2, 3, 20),
+ SET_FMAN_RX_1G_LIODN(2, 4, 21),
+ SET_FMAN_RX_10G_LIODN(2, 0, 22),
};
int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index 98815f8..ec3b292 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -14,9 +14,46 @@
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
+#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
+#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
+static void inhibit_portals(void __iomem *addr, int max_portals,
+ int arch_max_portals, int portal_cinh_size)
+{
+ uint32_t val;
+ int i;
+
+ /* arch_max_portals is the maximum based on memory size. This includes
+ * the reserved memory in the SoC. max_portals the number of physical
+ * portals in the SoC */
+ if (max_portals > arch_max_portals) {
+ printf("ERROR: portal config error\n");
+ max_portals = arch_max_portals;
+ }
+
+ for (i = 0; i < max_portals; i++) {
+ out_be32(addr, -1);
+ val = in_be32(addr);
+ if (!val) {
+ printf("ERROR: Stopped after %d portals\n", i);
+ goto done;
+ }
+ addr += portal_cinh_size;
+ }
+#ifdef DEBUG
+ printf("Cleared %d portals\n", i);
+#endif
+done:
+
+ return;
+}
+
void setup_portals(void)
{
ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
+ void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
+ CONFIG_SYS_BMAN_SWP_ISDR_REG;
+ void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
+ CONFIG_SYS_QMAN_SWP_ISDR_REG;
#ifdef CONFIG_FSL_CORENET
int i;
@@ -38,6 +75,12 @@ void setup_portals(void)
out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
#endif
out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
+
+ /* Change default state of BMan ISDR portals to all 1s */
+ inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
+ CONFIG_SYS_BMAN_SP_CINH_SIZE);
+ inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
+ CONFIG_SYS_QMAN_SP_CINH_SIZE);
}
/* Update portal containter to match LAW setup of portal in phy map */
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 4adba95..8e0508f 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -299,12 +299,16 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
{
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
u64 memsize = (u64)memsize_in_meg << 20;
+ u64 size;
- memsize = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED);
- memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM);
+ size = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED);
+ size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM);
- if (memsize)
- print_size(memsize, " left unmapped\n");
+ if (size || memsize > CONFIG_MAX_MEM_MAPPED) {
+ print_size(memsize > CONFIG_MAX_MEM_MAPPED ?
+ memsize - CONFIG_MAX_MEM_MAPPED + size : size,
+ " left unmapped\n");
+ }
return memsize_in_meg;
}
generated by cgit v1.1 at 2024-12-28 22:00:49 +0000