diff options
Diffstat (limited to 'arch')
35 files changed, 465 insertions, 391 deletions
diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index a3baae4..f354aae 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -71,10 +71,12 @@ config SPL_ZYNQMP_ALT_BOOTMODE default 0x5 if SD_MODE1 default 0x6 if EMMC_MODE default 0x7 if USB_MODE + default 0xa if SW_USBHOST_MODE + default 0xb if SW_SATA_MODE choice prompt "Boot mode" - depends on ZYNQMP_ALT_BOOTMODE_ENABLED + depends on SPL_ZYNQMP_ALT_BOOTMODE_ENABLED default JTAG config JTAG_MODE @@ -101,6 +103,12 @@ config EMMC_MODE config USB_MODE bool "USB" +config SW_USBHOST_MODE + bool "SW USBHOST_MODE" + +config SW_SATA_MODE + bool "SW SATA_MODE" + endchoice endif diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index bdbd613..f5f550f 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -92,6 +92,10 @@ u32 spl_boot_device(void) case USB_MODE: return BOOT_DEVICE_DFU; #endif +#ifdef CONFIG_SPL_SATA_SUPPORT + case SW_SATA_MODE: + return BOOT_DEVICE_SATA; +#endif default: printf("Invalid Boot Mode:0x%x\n", bootmode); break; diff --git a/arch/arm/dts/zynq-picozed.dts b/arch/arm/dts/zynq-picozed.dts index fea04ab..e15667c 100644 --- a/arch/arm/dts/zynq-picozed.dts +++ b/arch/arm/dts/zynq-picozed.dts @@ -14,6 +14,8 @@ aliases { serial0 = &uart1; + spi0 = &qspi; + mmc0 = &sdhci1; }; memory@0 { @@ -26,3 +28,13 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&qspi { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&sdhci1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 551c927..f6ea1df 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -348,7 +348,7 @@ */ #define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219 -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) +#if defined(CONFIG_DRA7XX) #define V_OSCK 20000000 /* Clock output from T2 */ #else #define V_OSCK 19200000 /* Clock output from T2 */ diff --git a/arch/arm/include/asm/arch-omap5/hardware.h b/arch/arm/include/asm/arch-omap5/hardware.h index a5bd600..d24d645 100644 --- a/arch/arm/include/asm/arch-omap5/hardware.h +++ b/arch/arm/include/asm/arch-omap5/hardware.h @@ -24,7 +24,7 @@ #define GPMC_BASE 0x50000000 /* EDMA3 Base address for DRA7XX and AM57XX */ -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) +#if defined(CONFIG_DRA7XX) #define EDMA3_BASE 0x43300000 #endif diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index ef8e975..b5e5519 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -29,13 +29,13 @@ #define CONTROL_CORE_ID_CODE 0x4A002204 #define CONTROL_WKUP_ID_CODE 0x4AE0C204 -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) +#if defined(CONFIG_DRA7XX) #define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE #else #define CONTROL_ID_CODE CONTROL_CORE_ID_CODE #endif -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) +#if defined(CONFIG_DRA7XX) #define DRA7_USB_OTG_SS1_BASE 0x48890000 #define DRA7_USB_OTG_SS1_GLUE_BASE 0x48880000 #define DRA7_USB3_PHY1_PLL_CTRL 0x4A084C00 @@ -185,7 +185,7 @@ struct s32ktimer { * much larger) and do not, at this time, make use of the additional * space. */ -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) +#if defined(CONFIG_DRA7XX) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ #define NON_SECURE_SRAM_IMG_END 0x4037E000 diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index e7738fa..5908c50 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -83,6 +83,9 @@ struct iou_scntr_secure { #define JTAG_MODE 0x00000000 #define BOOT_MODE_USE_ALT 0x100 #define BOOT_MODE_ALT_SHIFT 12 +/* SW secondary boot modes 0xa - 0xd */ +#define SW_USBHOST_MODE 0x0000000A +#define SW_SATA_MODE 0x0000000B #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 605c549..290a190 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -632,6 +632,7 @@ void omap_smc1(u32 service, u32 val); * security (HS) device variants by doing a specially-formed smc entry. */ u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params); +u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params); void enable_edma3_clocks(void); void disable_edma3_clocks(void); diff --git a/arch/arm/include/asm/omap_sec_common.h b/arch/arm/include/asm/omap_sec_common.h index 4bde93f..79f1fbd 100644 --- a/arch/arm/include/asm/omap_sec_common.h +++ b/arch/arm/include/asm/omap_sec_common.h @@ -51,4 +51,10 @@ int secure_emif_reserve(void); */ int secure_emif_firewall_lock(void); +/* + * Invoke a secure HAL API to authenticate and install a Trusted Execution + * Environment (TEE) image. + */ +int secure_tee_install(u32 tee_image); + #endif /* _OMAP_SEC_COMMON_H_ */ diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 5d1c5c5..c593dad 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -7,10 +7,14 @@ choice config TARGET_IPAM390 bool "IPAM390 board" select SUPPORT_SPL + select SYS_DA850_PLL_INIT + select SYS_DA850_DDR_INIT config TARGET_DA850EVM bool "DA850 EVM board" select SUPPORT_SPL + select SYS_DA850_PLL_INIT + select SYS_DA850_DDR_INIT config TARGET_EA20 bool "EA20 board" @@ -18,18 +22,30 @@ config TARGET_EA20 config TARGET_OMAPL138_LCDK bool "OMAPL138 LCDK" select SUPPORT_SPL + select SYS_DA850_PLL_INIT + select SYS_DA850_DDR_INIT config TARGET_CALIMAIN bool "Calimain board" + select SYS_DA850_PLL_INIT + select SYS_DA850_DDR_INIT config TARGET_LEGOEV3 bool "LEGO MINDSTORMS EV3" + select SYS_DA850_PLL_INIT + select SYS_DA850_DDR_INIT endchoice config SYS_SOC default "davinci" +config SYS_DA850_PLL_INIT + bool + +config SYS_DA850_DDR_INIT + bool + source "board/Barix/ipam390/Kconfig" source "board/davinci/da8xxevm/Kconfig" source "board/davinci/ea20/Kconfig" diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index 6b92530..ee8e12e 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -138,7 +138,10 @@ static void ddr3_reset_data(u32 base, u32 ddr3_size) puts("\nClear entire DDR3 memory to enable ECC\n"); /* save the SES MPAX regs */ - msmc_get_ses_mpax(8, 0, mpax); + if (cpu_is_k2g()) + msmc_get_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax); + else + msmc_get_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax); /* setup edma slot 1 configuration */ slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB | @@ -169,8 +172,17 @@ static void ddr3_reset_data(u32 base, u32 ddr3_size) for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) { /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF access slave interface so that edma driver can access */ - msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT, - KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G); + if (cpu_is_k2g()) { + msmc_map_ses_segment(K2G_MSMC_SEGMENT_ARM, 0, + base >> KS2_MSMC_SEG_SIZE_SHIFT, + KS2_MSMC_DST_SEG_BASE + seg, + MPAX_SEG_2G); + } else { + msmc_map_ses_segment(K2HKLE_MSMC_SEGMENT_ARM, 0, + base >> KS2_MSMC_SEG_SIZE_SHIFT, + KS2_MSMC_DST_SEG_BASE + seg, + MPAX_SEG_2G); + } if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM) edma_blks = KS2_MSMC_MAP_SEG_NUM << @@ -197,7 +209,10 @@ static void ddr3_reset_data(u32 base, u32 ddr3_size) qedma3_stop(KS2_EDMA0_BASE, &edma_channel); /* restore the SES MPAX regs */ - msmc_set_ses_mpax(8, 0, mpax); + if (cpu_is_k2g()) + msmc_set_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax); + else + msmc_set_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax); } static void ddr3_ecc_init_range(u32 base) diff --git a/arch/arm/mach-omap2/omap5/Makefile b/arch/arm/mach-omap2/omap5/Makefile index 0212df7..af17a3d 100644 --- a/arch/arm/mach-omap2/omap5/Makefile +++ b/arch/arm/mach-omap2/omap5/Makefile @@ -15,3 +15,4 @@ obj-y += abb.o obj-y += fdt.o obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o obj-$(CONFIG_TI_SECURE_DEVICE) += sec-fxns.o +obj-$(CONFIG_DRA7XX) += sec_entry_cpu1.o diff --git a/arch/arm/mach-omap2/omap5/boot.c b/arch/arm/mach-omap2/omap5/boot.c index 583becc..18750b8 100644 --- a/arch/arm/mach-omap2/omap5/boot.c +++ b/arch/arm/mach-omap2/omap5/boot.c @@ -12,7 +12,7 @@ #include <spl.h> static u32 boot_devices[] = { -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) +#if defined(CONFIG_DRA7XX) BOOT_DEVICE_MMC2, BOOT_DEVICE_NAND, BOOT_DEVICE_MMC1, diff --git a/arch/arm/mach-omap2/omap5/fdt.c b/arch/arm/mach-omap2/omap5/fdt.c index da8d59b..afa0037 100644 --- a/arch/arm/mach-omap2/omap5/fdt.c +++ b/arch/arm/mach-omap2/omap5/fdt.c @@ -212,6 +212,38 @@ static int ft_hs_fixup_dram(void *fdt, bd_t *bd) static int ft_hs_fixup_dram(void *fdt, bd_t *bd) { return 0; } #endif +static int ft_hs_add_tee(void *fdt, bd_t *bd) +{ + const char *path, *subpath; + int offs; + + extern int tee_loaded; + if (!tee_loaded) + return 0; + + path = "/"; + offs = fdt_path_offset(fdt, path); + + subpath = "firmware"; + offs = fdt_add_subnode(fdt, offs, subpath); + if (offs < 0) { + printf("Could not create %s node.\n", subpath); + return 1; + } + + subpath = "optee"; + offs = fdt_add_subnode(fdt, offs, subpath); + if (offs < 0) { + printf("Could not create %s node.\n", subpath); + return 1; + } + + fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz"); + fdt_setprop_string(fdt, offs, "method", "smc"); + + return 0; +} + static void ft_hs_fixups(void *fdt, bd_t *bd) { /* Check we are running on an HS/EMU device type */ @@ -219,7 +251,8 @@ static void ft_hs_fixups(void *fdt, bd_t *bd) if ((ft_hs_fixup_crossbar(fdt, bd) == 0) && (ft_hs_disable_rng(fdt, bd) == 0) && (ft_hs_fixup_sram(fdt, bd) == 0) && - (ft_hs_fixup_dram(fdt, bd) == 0)) + (ft_hs_fixup_dram(fdt, bd) == 0) && + (ft_hs_add_tee(fdt, bd) == 0)) return; } else { printf("ERROR: Incorrect device type (GP) detected!"); diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index fc99135..02f086b 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -456,7 +456,7 @@ void enable_basic_clocks(void) void enable_basic_uboot_clocks(void) { u32 const clk_domains_essential[] = { -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) +#if defined(CONFIG_DRA7XX) (*prcm)->cm_ipu_clkstctrl, #endif 0 @@ -472,7 +472,7 @@ void enable_basic_uboot_clocks(void) (*prcm)->cm_l4per_i2c2_clkctrl, (*prcm)->cm_l4per_i2c3_clkctrl, (*prcm)->cm_l4per_i2c4_clkctrl, -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) +#if defined(CONFIG_DRA7XX) (*prcm)->cm_ipu_i2c5_clkctrl, #else (*prcm)->cm_l4per_i2c5_clkctrl, diff --git a/arch/arm/mach-omap2/omap5/sec-fxns.c b/arch/arm/mach-omap2/omap5/sec-fxns.c index 33d4ea4..7fab575 100644 --- a/arch/arm/mach-omap2/omap5/sec-fxns.c +++ b/arch/arm/mach-omap2/omap5/sec-fxns.c @@ -19,13 +19,30 @@ #include <asm/omap_sec_common.h> #include <asm/spl.h> #include <spl.h> +#include <asm/cache.h> +#include <mapmem.h> +#include <tee/optee.h> /* Index for signature PPA-based TI HAL APIs */ #define PPA_HAL_SERVICES_START_INDEX (0x200) +#define PPA_SERV_HAL_TEE_LOAD_MASTER (PPA_HAL_SERVICES_START_INDEX + 23) +#define PPA_SERV_HAL_TEE_LOAD_SLAVE (PPA_HAL_SERVICES_START_INDEX + 24) #define PPA_SERV_HAL_SETUP_SEC_RESVD_REGION (PPA_HAL_SERVICES_START_INDEX + 25) #define PPA_SERV_HAL_SETUP_EMIF_FW_REGION (PPA_HAL_SERVICES_START_INDEX + 26) #define PPA_SERV_HAL_LOCK_EMIF_FW (PPA_HAL_SERVICES_START_INDEX + 27) +int tee_loaded = 0; + +/* Argument for PPA_SERV_HAL_TEE_LOAD_MASTER */ +struct ppa_tee_load_info { + u32 tee_sec_mem_start; /* Physical start address reserved for TEE */ + u32 tee_sec_mem_size; /* Size of the memory reserved for TEE */ + u32 tee_cert_start; /* Address where signed TEE binary is loaded */ + u32 tee_cert_size; /* Size of TEE certificate (signed binary) */ + u32 tee_jump_addr; /* Address to jump to start TEE execution */ + u32 tee_arg0; /* argument to TEE jump function, in r0 */ +}; + static u32 get_sec_mem_start(void) { u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START; @@ -124,3 +141,94 @@ int secure_emif_firewall_lock(void) return result; } + +static struct ppa_tee_load_info tee_info __aligned(ARCH_DMA_MINALIGN); + +int secure_tee_install(u32 addr) +{ + struct optee_header *hdr; + void *loadptr; + u32 tee_file_size; + u32 sec_mem_start = get_sec_mem_start(); + const u32 size = CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE; + u32 *smc_cpu1_params; + u32 ret; + + /* If there is no protected region, there is no place to put the TEE */ + if (size == 0) { + printf("Error loading TEE, no protected memory region available\n"); + return -ENOBUFS; + } + + hdr = (struct optee_header *)map_sysmem(addr, sizeof(struct optee_header)); + /* 280 bytes = size of signature */ + tee_file_size = hdr->init_size + hdr->paged_size + + sizeof(struct optee_header) + 280; + + if ((hdr->magic != OPTEE_MAGIC) || + (hdr->version != OPTEE_VERSION) || + (hdr->init_load_addr_hi != 0) || + (hdr->init_load_addr_lo < (sec_mem_start + sizeof(struct optee_header))) || + (tee_file_size > size) || + ((hdr->init_load_addr_lo + tee_file_size - 1) > + (sec_mem_start + size - 1))) { + printf("Error in TEE header. Check load address and sizes\n"); + unmap_sysmem(hdr); + return CMD_RET_FAILURE; + } + + tee_info.tee_sec_mem_start = sec_mem_start; + tee_info.tee_sec_mem_size = size; + tee_info.tee_jump_addr = hdr->init_load_addr_lo; + tee_info.tee_cert_start = addr; + tee_info.tee_cert_size = tee_file_size; + tee_info.tee_arg0 = hdr->init_size + tee_info.tee_jump_addr; + unmap_sysmem(hdr); + loadptr = map_sysmem(addr, tee_file_size); + + debug("tee_info.tee_sec_mem_start= %08X\n", tee_info.tee_sec_mem_start); + debug("tee_info.tee_sec_mem_size = %08X\n", tee_info.tee_sec_mem_size); + debug("tee_info.tee_jump_addr = %08X\n", tee_info.tee_jump_addr); + debug("tee_info.tee_cert_start = %08X\n", tee_info.tee_cert_start); + debug("tee_info.tee_cert_size = %08X\n", tee_info.tee_cert_size); + debug("tee_info.tee_arg0 = %08X\n", tee_info.tee_arg0); + debug("tee_file_size = %d\n", tee_file_size); + +#if !defined(CONFIG_SYS_DCACHE_OFF) + flush_dcache_range( + rounddown((u32)loadptr, ARCH_DMA_MINALIGN), + roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN)); + + flush_dcache_range((u32)&tee_info, (u32)&tee_info + + roundup(sizeof(tee_info), ARCH_DMA_MINALIGN)); +#endif + unmap_sysmem(loadptr); + + ret = secure_rom_call(PPA_SERV_HAL_TEE_LOAD_MASTER, 0, 0, 1, &tee_info); + if (ret) { + printf("TEE_LOAD_MASTER Failed\n"); + return ret; + } + printf("TEE_LOAD_MASTER Done\n"); + + if (!is_dra72x()) { + /* Reuse the tee_info buffer for SMC params */ + smc_cpu1_params = (u32 *)&tee_info; + smc_cpu1_params[0] = 0; +#if !defined(CONFIG_SYS_DCACHE_OFF) + flush_dcache_range((u32)smc_cpu1_params, (u32)smc_cpu1_params + + roundup(sizeof(u32), ARCH_DMA_MINALIGN)); +#endif + ret = omap_smc_sec_cpu1(PPA_SERV_HAL_TEE_LOAD_SLAVE, 0, 0, + smc_cpu1_params); + if (ret) { + printf("TEE_LOAD_SLAVE Failed\n"); + return ret; + } + printf("TEE_LOAD_SLAVE Done\n"); + } + + tee_loaded = 1; + + return 0; +} diff --git a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S new file mode 100644 index 0000000..c2a35ee --- /dev/null +++ b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S @@ -0,0 +1,123 @@ +/* + * Secure entry function for CPU Core #1 + * + * (C) Copyright 2016 + * Texas Instruments, <www.ti.com> + * + * Author : + * Harinarayan Bhatta <harinarayan@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/arch/omap.h> +#include <asm/omap_common.h> +#include <linux/linkage.h> + +.arch_extension sec + +#if !defined(CONFIG_SYS_DCACHE_OFF) +.global flush_dcache_range +#endif + +#define AUX_CORE_BOOT_0 0x48281800 +#define AUX_CORE_BOOT_1 0x48281804 + +#ifdef CONFIG_DRA7XX +/* DRA7xx ROM code function "startup_BootSlave". This function is where CPU1 + * waits on WFE, polling on AUX_CORE_BOOT_x registers. + * This address is same for J6 and J6 Eco. + */ +#define ROM_FXN_STARTUP_BOOTSLAVE 0x00038a64 +#endif + +/* Assembly core where CPU1 is woken up into + * No need to save-restore registers, does not use stack. + */ +LENTRY(cpu1_entry) + ldr r4, =omap_smc_sec_cpu1_args + ldm r4, {r0,r1,r2,r3} @ Retrieve args + + mov r6, #0xFF @ Indicate new Task call + mov r12, #0x00 @ Secure Service ID in R12 + + dsb + dmb + smc 0 @ SMC #0 to enter monitor mode + + b .Lend @ exit at end of the service execution + nop + + @ In case of IRQ happening in Secure, then ARM will branch here. + @ At that moment, IRQ will be pending and ARM will jump to Non Secure + @ IRQ handler + mov r12, #0xFE + + dsb + dmb + smc 0 @ SMC #0 to enter monitor mode + +.Lend: + ldr r4, =omap_smc_sec_cpu1_args + str r0, [r4, #0x10] @ save return value + ldr r4, =AUX_CORE_BOOT_0 + mov r5, #0x0 + str r5, [r4] + ldr r4, =ROM_FXN_STARTUP_BOOTSLAVE + sev @ Tell CPU0 we are done + bx r4 @ Jump back to ROM +END(cpu1_entry) + +/* + * u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params); + * + * Makes a secure ROM/PPA call on CPU Core #1 on supported platforms. + * Assumes that CPU #1 is waiting in ROM code and not yet woken up or used by + * u-boot. + */ +ENTRY(omap_smc_sec_cpu1) + push {r4, r5, lr} + ldr r4, =omap_smc_sec_cpu1_args + stm r4, {r0,r1,r2,r3} @ Save args to memory +#if !defined(CONFIG_SYS_DCACHE_OFF) + mov r0, r4 + mov r1, #CONFIG_SYS_CACHELINE_SIZE + add r1, r0, r1 @ dcache is not enabled on CPU1, so + blx flush_dcache_range @ flush the cache on args buffer +#endif + ldr r4, =AUX_CORE_BOOT_1 + ldr r5, =cpu1_entry + str r5, [r4] @ Setup CPU1 entry function + ldr r4, =AUX_CORE_BOOT_0 + mov r5, #0x10 + str r5, [r4] @ Tell ROM to exit while loop + sev @ Wake up CPU1 +.Lwait: + wfe @ Wait for CPU1 to finish + nop + ldr r5, [r4] @ Check if CPU1 is done + cmp r5, #0 + bne .Lwait + + ldr r4, =omap_smc_sec_cpu1_args + ldr r0, [r4, #0x10] @ Retrieve return value + pop {r4, r5, pc} +ENDPROC(omap_smc_sec_cpu1) + +/* + * Buffer to save function arguments and return value for omap_smc_sec_cpu1 + */ +.section .data +omap_smc_sec_cpu1_args: +#if !defined(CONFIG_SYS_DCACHE_OFF) + .balign CONFIG_SYS_CACHELINE_SIZE + .rept CONFIG_SYS_CACHELINE_SIZE/4 + .word 0 + .endr +#else + .rept 5 + .word 0 + .endr +#endif +END(omap_smc_sec_cpu1_args) diff --git a/arch/sh/Makefile b/arch/sh/Makefile index ca55fac..14e0b66 100644 --- a/arch/sh/Makefile +++ b/arch/sh/Makefile @@ -2,7 +2,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -head-y := arch/sh/cpu/$(CPU)/start.o +head-y := arch/sh/lib/start.o libs-y += arch/sh/cpu/$(CPU)/ libs-y += arch/sh/lib/ diff --git a/arch/sh/config.mk b/arch/sh/config.mk index 0578fa3..71540c8 100644 --- a/arch/sh/config.mk +++ b/arch/sh/config.mk @@ -15,6 +15,6 @@ CONFIG_STANDALONE_LOAD_ADDR += -EB endif PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ -PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE) +PLATFORM_RELFLAGS += -fpic LDFLAGS_FINAL = --gc-sections PLATFORM_RELFLAGS += -ffixed-r13 diff --git a/arch/sh/cpu/sh2/Makefile b/arch/sh/cpu/sh2/Makefile index a19ed5e..80fff49 100644 --- a/arch/sh/cpu/sh2/Makefile +++ b/arch/sh/cpu/sh2/Makefile @@ -8,5 +8,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -extra-y = start.o obj-y = cpu.o interrupts.o watchdog.o diff --git a/arch/sh/cpu/sh2/cpu.c b/arch/sh/cpu/sh2/cpu.c index 9a93cf5..a2f856f 100644 --- a/arch/sh/cpu/sh2/cpu.c +++ b/arch/sh/cpu/sh2/cpu.c @@ -83,9 +83,3 @@ int dcache_status(void) { return 0; } - -void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr) -{ - /* TODO(sh maintainer): Implement this */ - while (1); -} diff --git a/arch/sh/cpu/sh3/Makefile b/arch/sh/cpu/sh3/Makefile index 1dccaf9..cddc15b 100644 --- a/arch/sh/cpu/sh3/Makefile +++ b/arch/sh/cpu/sh3/Makefile @@ -11,5 +11,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -extra-y = start.o -obj-y = cpu.o interrupts.o watchdog.o cache.o +obj-y = cpu.o interrupts.o watchdog.o diff --git a/arch/sh/cpu/sh3/cache.c b/arch/sh/cpu/sh3/cache.c deleted file mode 100644 index 34cbbff..0000000 --- a/arch/sh/cpu/sh3/cache.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2007 - * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * (C) Copyright 2007 - * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> - -/* - * Jump to P2 area. - * When handling TLB or caches, we need to do it from P2 area. - */ -#define jump_to_P2() \ - do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "mov.l 1f, %0\n\t" \ - "or %1, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy) \ - : "r" (0x20000000)); \ - } while (0) - -/* - * Back to P1 area. - */ -#define back_to_P1() \ - do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "nop;nop;nop;nop;nop;nop;nop\n\t" \ - "mov.l 1f, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy)); \ - } while (0) - -#define CACHE_VALID 1 -#define CACHE_UPDATED 2 - -static inline void cache_wback_all(void) -{ - unsigned long addr, data, i, j; - - jump_to_P2(); - for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) { - for (j = 0; j < CACHE_OC_NUM_WAYS; j++) { - addr = CACHE_OC_ADDRESS_ARRAY - | (j << CACHE_OC_WAY_SHIFT) - | (i << CACHE_OC_ENTRY_SHIFT); - data = inl(addr); - if (data & CACHE_UPDATED) { - data &= ~CACHE_UPDATED; - outl(data, addr); - } - } - } - back_to_P1(); -} - - -#define CACHE_ENABLE 0 -#define CACHE_DISABLE 1 - -int cache_control(unsigned int cmd) -{ - unsigned long ccr; - - jump_to_P2(); - ccr = inl(CCR); - - if (ccr & CCR_CACHE_ENABLE) - cache_wback_all(); - - if (cmd == CACHE_DISABLE) - outl(CCR_CACHE_STOP, CCR); - else - outl(CCR_CACHE_INIT, CCR); - back_to_P1(); - - return 0; -} diff --git a/arch/sh/cpu/sh3/cpu.c b/arch/sh/cpu/sh3/cpu.c index 494f908..ea0006a 100644 --- a/arch/sh/cpu/sh3/cpu.c +++ b/arch/sh/cpu/sh3/cpu.c @@ -66,9 +66,3 @@ int dcache_status(void) { return 0; } - -void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr) -{ - /* TODO(sh maintainer): Implement this */ - while (1); -} diff --git a/arch/sh/cpu/sh3/start.S b/arch/sh/cpu/sh3/start.S deleted file mode 100644 index 9ed7198..0000000 --- a/arch/sh/cpu/sh3/start.S +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2007 - * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * (C) Copyright 2007 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <config.h> - - .text - .align 2 - - .global _start -_sh_start: - mov.l ._lowlevel_init, r0 -100: bsrf r0 - nop - - bsr 1f - nop -1: sts pr, r5 - mov.l ._reloc_dst, r4 - add #(_sh_start-1b), r5 - mov.l ._reloc_dst_end, r6 - -2: mov.l @r5+, r1 - mov.l r1, @r4 - add #4, r4 - cmp/hs r6, r4 - bf 2b - - mov.l ._bss_start, r4 - mov.l ._bss_end, r5 - mov #0, r1 - -3: mov.l r1, @r4 /* bss clear */ - add #4, r4 - cmp/hs r5, r4 - bf 3b - - mov.l ._gd_init, r13 /* global data */ - mov.l ._stack_init, r15 /* stack */ - - #TODO(sh maintainer): Fix this up to call the correct code - #mov.l ._sh_generic_init, r0 - #jsr @r0 - nop - -loop: - bra loop - - .align 2 - -._lowlevel_init: .long (lowlevel_init - (100b + 4)) -._reloc_dst: .long reloc_dst -._reloc_dst_end: .long reloc_dst_end -._bss_start: .long bss_start -._bss_end: .long bss_end -._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE) -._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16) -#._sh_generic_init: .long sh_generic_init diff --git a/arch/sh/cpu/sh4/Makefile b/arch/sh/cpu/sh4/Makefile index 38c6188..976994b 100644 --- a/arch/sh/cpu/sh4/Makefile +++ b/arch/sh/cpu/sh4/Makefile @@ -8,5 +8,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -extra-y = start.o obj-y = cpu.o interrupts.o watchdog.o cache.o diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c index e1ee970..6175c67 100644 --- a/arch/sh/cpu/sh4/cache.c +++ b/arch/sh/cpu/sh4/cache.c @@ -1,50 +1,15 @@ /* - * (C) Copyright 2007 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * (C) Copyright 2016 Vladimir Zapolskiy <vz@mleia.com> + * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <command.h> -#include <asm/processor.h> #include <asm/io.h> - -/* - * Jump to P2 area. - * When handling TLB or caches, we need to do it from P2 area. - */ -#define jump_to_P2() \ - do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "mov.l 1f, %0\n\t" \ - "or %1, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy) \ - : "r" (0x20000000)); \ - } while (0) - -/* - * Back to P1 area. - */ -#define back_to_P1() \ - do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "nop;nop;nop;nop;nop;nop;nop\n\t" \ - "mov.l 1f, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy)); \ - } while (0) +#include <asm/processor.h> +#include <asm/system.h> #define CACHE_VALID 1 #define CACHE_UPDATED 2 @@ -53,10 +18,10 @@ static inline void cache_wback_all(void) { unsigned long addr, data, i, j; - jump_to_P2(); - for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++){ + for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) { for (j = 0; j < CACHE_OC_NUM_WAYS; j++) { - addr = CACHE_OC_ADDRESS_ARRAY | (j << CACHE_OC_WAY_SHIFT) + addr = CACHE_OC_ADDRESS_ARRAY + | (j << CACHE_OC_WAY_SHIFT) | (i << CACHE_OC_ENTRY_SHIFT); data = inl(addr); if (data & CACHE_UPDATED) { @@ -65,14 +30,12 @@ static inline void cache_wback_all(void) } } } - back_to_P1(); } - #define CACHE_ENABLE 0 #define CACHE_DISABLE 1 -int cache_control(unsigned int cmd) +static int cache_control(unsigned int cmd) { unsigned long ccr; @@ -97,7 +60,7 @@ void flush_dcache_range(unsigned long start, unsigned long end) start &= ~(L1_CACHE_BYTES - 1); for (v = start; v < end; v += L1_CACHE_BYTES) { - asm volatile ("ocbwb %0" : /* no output */ + asm volatile ("ocbp %0" : /* no output */ : "m" (__m(v))); } } @@ -112,3 +75,36 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) : "m" (__m(v))); } } + +void flush_cache(unsigned long addr, unsigned long size) +{ + flush_dcache_range(addr , addr + size); +} + +void icache_enable(void) +{ + cache_control(CACHE_ENABLE); +} + +void icache_disable(void) +{ + cache_control(CACHE_DISABLE); +} + +int icache_status(void) +{ + return 0; +} + +void dcache_enable(void) +{ +} + +void dcache_disable(void) +{ +} + +int dcache_status(void) +{ + return 0; +} diff --git a/arch/sh/cpu/sh4/cpu.c b/arch/sh/cpu/sh4/cpu.c index de90ca7..aa8d4df 100644 --- a/arch/sh/cpu/sh4/cpu.c +++ b/arch/sh/cpu/sh4/cpu.c @@ -9,7 +9,6 @@ #include <command.h> #include <netdev.h> #include <asm/processor.h> -#include <asm/cache.h> int checkcpu(void) { @@ -35,39 +34,6 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -void flush_cache (unsigned long addr, unsigned long size) -{ - invalidate_dcache_range(addr , addr + size); -} - -void icache_enable (void) -{ - cache_control(0); -} - -void icache_disable (void) -{ - cache_control(1); -} - -int icache_status (void) -{ - return 0; -} - -void dcache_enable (void) -{ -} - -void dcache_disable (void) -{ -} - -int dcache_status (void) -{ - return 0; -} - int cpu_eth_init(bd_t *bis) { #ifdef CONFIG_SH_ETHER @@ -75,9 +41,3 @@ int cpu_eth_init(bd_t *bis) #endif return 0; } - -void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr) -{ - /* TODO(sh maintainer): Implement this */ - while (1); -} diff --git a/arch/sh/cpu/sh4/start.S b/arch/sh/cpu/sh4/start.S deleted file mode 100644 index 77fc221..0000000 --- a/arch/sh/cpu/sh4/start.S +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2007, 2010 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <config.h> - - .text - .align 2 - - .global _start -_sh_start: - mov.l ._lowlevel_init, r0 -100: bsrf r0 - nop - - bsr 1f - nop -1: sts pr, r5 - mov.l ._reloc_dst, r4 - add #(_sh_start-1b), r5 - mov.l ._reloc_dst_end, r6 - -2: mov.l @r5+, r1 - mov.l r1, @r4 - add #4, r4 - cmp/hs r6, r4 - bf 2b - - mov.l ._bss_start, r4 - mov.l ._bss_end, r5 - mov #0, r1 - -3: mov.l r1, @r4 /* bss clear */ - add #4, r4 - cmp/hs r5, r4 - bf 3b - - mov.l ._gd_init, r13 /* global data */ - mov.l ._stack_init, r15 /* stack */ - - #TODO(sh maintainer): Fix this up to call the correct code - #mov.l ._sh_generic_init, r0 - #jsr @r0 - nop - -loop: - bra loop - - .align 2 - -._lowlevel_init: .long (lowlevel_init - (100b + 4)) -._reloc_dst: .long reloc_dst -._reloc_dst_end: .long reloc_dst_end -._bss_start: .long bss_start -._bss_end: .long bss_end -._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE) -._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16) -#._sh_generic_init: .long sh_generic_init diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds index 78611c2..bbf9ff4 100644 --- a/arch/sh/cpu/u-boot.lds +++ b/arch/sh/cpu/u-boot.lds @@ -1,26 +1,27 @@ /* - * Copyright (C) 2007 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * Copyright (C) 2008-2009 - * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * Copyright (C) 2008 - * Mark Jonas <mark.jonas@de.bosch.com> + * Copyright (C) 2016 Vladimir Zapolskiy <vz@mleia.com> + * Copyright (C) 2008-2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * Copyright (C) 2008 Mark Jonas <mark.jonas@de.bosch.com> + * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * * SPDX-License-Identifier: GPL-2.0+ */ +#include "config.h" + OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") OUTPUT_ARCH(sh) + +MEMORY +{ + ram : ORIGIN = CONFIG_SYS_SDRAM_BASE, LENGTH = CONFIG_SYS_SDRAM_SIZE +} + ENTRY(_start) SECTIONS { - /* - * entry and reloct_dst will be provided via ldflags - */ - . = .; + reloc_dst = .; PROVIDE (_ftext = .); PROVIDE (_fcode = .); @@ -29,6 +30,8 @@ SECTIONS .text : { KEEP(*/start.o (.text)) + KEEP(CONFIG_BOARDDIR/lowlevel_init.o (.text .spiboot1.text)) + KEEP(*(.spiboot2.text)) . = ALIGN(8192); common/env_embedded.o (.ppcenv) . = ALIGN(8192); @@ -36,13 +39,13 @@ SECTIONS . = ALIGN(8192); *(.text) . = ALIGN(4); - } =0xFF + } >ram =0xFF PROVIDE (_ecode = .); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) . = ALIGN(4); - } + } >ram PROVIDE (_etext = .); @@ -51,25 +54,23 @@ SECTIONS { *(.data) . = ALIGN(4); - } + } >ram PROVIDE (_edata = .); PROVIDE (_fgot = .); .got : { - *(.got) + *(.got.plt) *(.got) . = ALIGN(4); - } + } >ram PROVIDE (_egot = .); - .u_boot_list : { KEEP(*(SORT(.u_boot_list*))); - } + } >ram PROVIDE (__init_end = .); PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ PROVIDE (bss_start = .); PROVIDE (__bss_start = .); @@ -77,8 +78,7 @@ SECTIONS { *(.bss) . = ALIGN(4); - } + } >ram PROVIDE (bss_end = .); - PROVIDE (__bss_end = .); } diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h index abaf405..b548a35 100644 --- a/arch/sh/include/asm/cache.h +++ b/arch/sh/include/asm/cache.h @@ -3,8 +3,6 @@ #if defined(CONFIG_CPU_SH4) -int cache_control(unsigned int cmd); - #define L1_CACHE_BYTES 32 struct __large_struct { unsigned long buf[100]; }; diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h index 5dc27be..5cb000c 100644 --- a/arch/sh/include/asm/io.h +++ b/arch/sh/include/asm/io.h @@ -68,13 +68,6 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen); #define __raw_base_readl(base, off) __arch_base_getl(base, off) /* - * Now, pick up the machine-defined IO definitions - */ -#if 0 /* XXX###XXX */ -#include <asm/arch/io.h> -#endif /* XXX###XXX */ - -/* * IO port access primitives * ------------------------- * @@ -82,9 +75,6 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen); * mapped. Note that these are defined to perform little endian accesses * only. Their primary purpose is to access PCI and ISA peripherals. * - * The machine specific io.h include defines __io to translate an "IO" - * address to a memory address. - * * Note that we prevent GCC re-ordering or caching values in expressions * by introducing sequence points into the in*() definitions. Note that * __raw_* do not guarantee this behaviour. diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile index c5cf89f..473cf0d 100644 --- a/arch/sh/lib/Makefile +++ b/arch/sh/lib/Makefile @@ -5,7 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # +extra-y += start.o +obj-y += board.o obj-$(CONFIG_CMD_BOOTM) += bootm.o ifeq ($(CONFIG_CPU_SH2),y) obj-y += time_sh2.o diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c new file mode 100644 index 0000000..aa967c0 --- /dev/null +++ b/arch/sh/lib/board.c @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2016 Vladimir Zapolskiy <vz@mleia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + return 0; +} + +void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaddr) +{ + void (*reloc_board_init_r)(gd_t *gd, ulong dest) = board_init_r; + + if (new_gd->reloc_off) { + memcpy((void *)new_gd->relocaddr, + (void *)(new_gd->relocaddr - new_gd->reloc_off), + new_gd->mon_len); + + reloc_board_init_r += new_gd->reloc_off; + } + + __asm__ __volatile__("mov.l %0, r15\n" : : "m" (new_gd->start_addr_sp)); + + while (1) + reloc_board_init_r(new_gd, 0x0); +} diff --git a/arch/sh/cpu/sh2/start.S b/arch/sh/lib/start.S index 6171edc..37d38d5 100644 --- a/arch/sh/cpu/sh2/start.S +++ b/arch/sh/lib/start.S @@ -1,7 +1,7 @@ /* - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * Copyright (C) 2008 Renesas Solutions Corp. - + * Copyright (C) 2016 Vladimir Zapolskiy <vz@mleia.com> + * Copyright (C) 2007, 2010 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -12,20 +12,22 @@ .align 2 .global _start -_sh_start: - .long 0x00000010 /* Ppower ON reset PC*/ +_start: +#ifdef CONFIG_CPU_SH2 + .long 0x00000010 /* Ppower ON reset PC*/ .long 0x00000000 - .long 0x00000010 /* Manual reset PC */ + .long 0x00000010 /* Manual reset PC */ .long 0x00000000 -_init: +#endif mov.l ._lowlevel_init, r0 100: bsrf r0 nop + bsr 1f nop 1: sts pr, r5 mov.l ._reloc_dst, r4 - add #(_sh_start-1b), r5 + add #(_start-1b), r5 mov.l ._reloc_dst_end, r6 2: mov.l @r5+, r1 @@ -46,10 +48,9 @@ _init: mov.l ._gd_init, r13 /* global data */ mov.l ._stack_init, r15 /* stack */ - #TODO(sh maintainer): Fix this up to call the correct code - #mov.l ._sh_generic_init, r0 - #jsr @r0 - nop + mov.l ._sh_generic_init, r0 + jsr @r0 + mov #0, r4 loop: bra loop @@ -57,10 +58,10 @@ loop: .align 2 ._lowlevel_init: .long (lowlevel_init - (100b + 4)) -._reloc_dst: .long reloc_dst +._reloc_dst: .long _start ._reloc_dst_end: .long reloc_dst_end ._bss_start: .long bss_start ._bss_end: .long bss_end -._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE) -._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16) -#._sh_generic_init: .long sh_generic_init +._gd_init: .long (_start - GENERATED_GBL_DATA_SIZE) +._stack_init: .long (_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16) +._sh_generic_init: .long board_init_f |