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-rw-r--r--arch/powerpc/cpu/mpc85xx/cmd_errata.c6
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c29
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c26
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c148
-rw-r--r--arch/powerpc/cpu/mpc85xx/t1040_ids.c1
-rw-r--r--arch/powerpc/cpu/mpc85xx/t2080_serdes.c27
-rw-r--r--arch/powerpc/cpu/mpc85xx/t4240_serdes.c172
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h24
-rw-r--r--arch/powerpc/include/asm/fsl_law.h1
-rw-r--r--arch/powerpc/include/asm/fsl_liodn.h4
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h37
11 files changed, 469 insertions, 6 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 3d37a76..3a04a89 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -231,6 +231,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
puts("Work-around for Erratum NMG ETSEC129 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
+ puts("Work-around for Erratum A004508 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
puts("Work-around for Erratum A004510 enabled\n");
#endif
@@ -266,6 +269,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
puts("Work-around for Erratum USB14 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+ puts("Work-around for Erratum A007186 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
puts("Work-around for Erratum A006593 enabled\n");
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index d6cf885..78316a6 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -225,6 +225,32 @@ static void disable_cpc_sram(void)
}
#endif
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#ifdef CONFIG_POST
+#error POST memory test cannot be enabled with TDM
+#endif
+static void enable_tdm_law(void)
+{
+ int ret;
+ char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+ int tdm_hwconfig_enabled = 0;
+
+ /*
+ * Extract hwconfig from environment since environment
+ * is not setup properly yet. Search for tdm entry in
+ * hwconfig.
+ */
+ ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+ if (ret > 0) {
+ tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
+ /* If tdm is defined in hwconfig, set law for tdm workaround */
+ if (tdm_hwconfig_enabled)
+ set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
+ LAW_TRGT_IF_CCSR);
+ }
+}
+#endif
+
static void enable_cpc(void)
{
int i;
@@ -729,6 +755,9 @@ skip_l2:
disable_cpc_sram();
#endif
enable_cpc();
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+ enable_tdm_law();
+#endif
#ifndef CONFIG_SYS_FSL_NO_SERDES
/* needs to be in ram since code uses global static vars */
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index ed80a84..85dfa5b 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -14,6 +14,7 @@
#include <linux/ctype.h>
#include <asm/io.h>
#include <asm/fsl_portals.h>
+#include <hwconfig.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
@@ -35,6 +36,11 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
u32 bootpg = determine_mp_bootpg(NULL);
u32 id = get_my_id();
const char *enable_method;
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+ int ret;
+ int tdm_hwconfig_enabled = 0;
+ char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+#endif
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
@@ -77,6 +83,26 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
"device_type", "cpu", 4);
}
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#define CONFIG_MEM_HOLE_16M 0x1000000
+ /*
+ * Extract hwconfig from environment.
+ * Search for tdm entry in hwconfig.
+ */
+ ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+ if (ret > 0)
+ tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
+
+ /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
+ if (tdm_hwconfig_enabled) {
+ off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
+ CONFIG_MEM_HOLE_16M);
+ if (off < 0)
+ printf("Failed to reserve memory for tdm: %s\n",
+ fdt_strerror(off));
+ }
+#endif
+
/* Reserve the boot page so OSes dont use it */
if ((u64)bootpg < memory_limit) {
off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 70e09ea..d1fc76a 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -147,12 +147,43 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
return -ENODEV;
}
+#define BC3_SHIFT 9
+#define DC3_SHIFT 6
+#define FC3_SHIFT 0
+#define BC2_SHIFT 19
+#define DC2_SHIFT 16
+#define FC2_SHIFT 10
+#define BC1_SHIFT 29
+#define DC1_SHIFT 26
+#define FC1_SHIFT 20
+#define BC_MASK 0x1
+#define DC_MASK 0x7
+#define FC_MASK 0x3F
+
+#define FUSE_VAL_MASK 0x00000003
+#define FUSE_VAL_SHIFT 30
+#define CR0_DCBIAS_SHIFT 5
+#define CR1_FCAP_SHIFT 15
+#define CR1_BCAP_SHIFT 29
+#define FCAP_MASK 0x001F8000
+#define BCAP_MASK 0x20000000
+#define BCAP_OVD_MASK 0x10000000
+#define BYP_CAL_MASK 0x02000000
+
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u64 serdes_prtcl_map = 0;
u32 cfg;
int lane;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+ struct ccsr_sfp_regs __iomem *sfp_regs =
+ (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
+ u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
+ u32 bc_status, fc_status, dc_status, pll_sr2;
+ serdes_corenet_t __iomem *srds_regs = (void *)sd_addr;
+ u32 sfp_spfr0, sel;
+#endif
cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
/* Is serdes enabled at all? */
@@ -161,6 +192,123 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
return 0;
}
+/* Erratum A-007186
+ * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
+ * The workaround requires factory pre-set SerDes calibration values to be
+ * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0)
+ * These values have been shown to work across the
+ * entire temperature range for all SerDes. These values are then written into
+ * the SerDes registers to calibrate the SerDes PLL.
+ *
+ * This workaround for the protocols and rates that only have the Ring VCO.
+ */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+ sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
+ debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
+
+ sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
+
+ if (sel == 0x01 || sel == 0x02) {
+ for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
+ pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ debug("A007186: pll_num=%x pllcr0=%x\n",
+ pll_num, pll_status);
+ /* STEP 1 */
+ /* Read factory pre-set SerDes calibration values
+ * from fuse block(SFP scratch register-sfp_spfr0)
+ */
+ switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
+ case SRDS_PLLCR0_FRATE_SEL_3_0:
+ case SRDS_PLLCR0_FRATE_SEL_3_072:
+ debug("A007186: 3.0/3.072 protocol rate\n");
+ bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+ dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+ fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+ break;
+ case SRDS_PLLCR0_FRATE_SEL_3_125:
+ debug("A007186: 3.125 protocol rate\n");
+ bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
+ dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
+ fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
+ break;
+ case SRDS_PLLCR0_FRATE_SEL_3_75:
+ debug("A007186: 3.75 protocol rate\n");
+ bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+ dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+ fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+ break;
+ default:
+ continue;
+ }
+
+ /* STEP 2 */
+ /* Write SRDSxPLLnCR1[11:16] = FC
+ * Write SRDSxPLLnCR1[2] = BC
+ */
+ pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
+ pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) |
+ ((fc << CR1_FCAP_SHIFT) & FCAP_MASK));
+ out_be32(&srds_regs->bank[pll_num].pllcr1,
+ (pll_cr_upd | pll_cr1));
+ debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+ pll_num, (pll_cr_upd | pll_cr1));
+ /* Write SRDSxPLLnCR0[24:26] = DC
+ */
+ pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ out_be32(&srds_regs->bank[pll_num].pllcr0,
+ pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
+ debug("A007186: pll_num=%x, Updated PLLCR0=%x\n",
+ pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
+ /* Write SRDSxPLLnCR1[3] = 1
+ * Write SRDSxPLLnCR1[6] = 1
+ */
+ pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
+ pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
+ out_be32(&srds_regs->bank[pll_num].pllcr1,
+ (pll_cr_upd | pll_cr1));
+ debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+ pll_num, (pll_cr_upd | pll_cr1));
+
+ /* STEP 3 */
+ /* Read the status Registers */
+ /* Verify SRDSxPLLnSR2[8] = BC */
+ pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
+ debug("A007186: pll_num=%x pllsr2=%x\n",
+ pll_num, pll_sr2);
+ bc_status = (pll_sr2 >> 23) & BC_MASK;
+ if (bc_status != bc)
+ debug("BC mismatch\n");
+ fc_status = (pll_sr2 >> 16) & FC_MASK;
+ if (fc_status != fc)
+ debug("FC mismatch\n");
+ pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 |
+ 0x02000000);
+ pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
+ dc_status = (pll_sr2 >> 17) & DC_MASK;
+ if (dc_status != dc)
+ debug("DC mismatch\n");
+ pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 &
+ 0xfdffffff);
+
+ /* STEP 4 */
+ /* Wait 750us to verify the PLL is locked
+ * by checking SRDSxPLLnCR0[8] = 1.
+ */
+ udelay(750);
+ pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ debug("A007186: pll_num=%x pllcr0=%x\n",
+ pll_num, pll_status);
+
+ if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
+ printf("A007186 Serdes PLL not locked\n");
+ else
+ debug("A007186 Serdes PLL locked\n");
+ }
+ }
+#endif
+
cfg >>= sd_prctl_shift;
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
if (!is_serdes_prtcl_valid(sd, cfg))
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
index 1034cd4..a5dfb81 100644
--- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
@@ -47,6 +47,7 @@ struct liodn_id_table liodn_tbl[] = {
/* SET_NEXUS_LIODN(557), -- not yet implemented */
SET_QE_LIODN(559),
+ SET_TDM_LIODN(560),
};
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
index 07e27de..7138bb4 100644
--- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
@@ -43,6 +43,10 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
{0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE4, PCIE4, PCIE4, PCIE4} },
+ {0x1B, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
@@ -59,18 +63,34 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x50, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
XAUI_FM1_MAC9, XAUI_FM1_MAC9,
PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x5E, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x64, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x6A, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ XFI_FM1_MAC1, XFI_FM1_MAC2,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
XFI_FM1_MAC1, XFI_FM1_MAC2,
PCIE4, SGMII_FM1_DTSEC4,
@@ -115,6 +135,9 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
{0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0xD2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
@@ -127,8 +150,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
{0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
XFI_FM1_MAC1, XFI_FM1_MAC2,
PCIE4, PCIE4, PCIE4, PCIE4} },
-
-#if defined(CONFIG_PPC_T2081)
{0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
PCIE4, PCIE4, PCIE4, PCIE4} },
{0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
@@ -137,7 +158,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
{0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
-#endif
{}
};
@@ -150,6 +170,7 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
{0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
{0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
{0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
+ {0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SATA1, SATA2} },
{0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
{0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
{0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index 1f99a0a..74c4c81 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -30,22 +30,41 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+ {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+ {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+ {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{38, {NONE, NONE, QSGMII_FM1_B, NONE,
NONE, NONE, QSGMII_FM1_A, NONE}},
+ {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
+ {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
+ {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
@@ -65,10 +84,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+ {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -77,10 +104,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -89,6 +124,10 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -97,34 +136,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {37, {NONE, NONE, QSGMII_FM2_B, NONE,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{38, {NONE, NONE, QSGMII_FM2_B, NONE,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {55, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ XFI_FM2_MAC10, XFI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
XFI_FM2_MAC10, XFI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -137,22 +208,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
};
static const struct serdes_config serdes3_cfg_tbl[] = {
/* SerDes 3 */
+ {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
+ {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
+ {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
+ {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+ {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2} },
{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2}},
+ {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2} },
{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2}},
+ {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1}},
{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1}},
+ {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1}},
{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -161,13 +244,21 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
};
static const struct serdes_config serdes4_cfg_tbl[] = {
/* SerDes 4 */
+ {1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} },
{2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
+ {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
+ {5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
{6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+ {7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
{8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+ {9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
{10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
+ {11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
{12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
+ {13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
{14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+ {15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
{16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
{}
@@ -187,36 +278,66 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
+ {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+ {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+ {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{38, {NONE, NONE, QSGMII_FM1_B, NONE,
NONE, NONE, QSGMII_FM1_A, NONE} },
{}
};
static const struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
+ {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -225,34 +346,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
NONE, NONE} },
+ {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {37, {NONE, NONE, QSGMII_FM2_B, NONE,
+ NONE, QSGMII_FM1_A, NONE, NONE} },
{38, {NONE, NONE, QSGMII_FM2_B, NONE,
NONE, QSGMII_FM1_A, NONE, NONE} },
+ {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, QSGMII_FM1_A, NONE, NONE} },
{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, QSGMII_FM1_A, NONE, NONE} },
+ {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, QSGMII_FM1_A, NONE, NONE} },
{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, QSGMII_FM1_A, NONE, NONE} },
+ {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, QSGMII_FM1_A, NONE, NONE} },
{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, QSGMII_FM1_A, NONE, NONE} },
+ {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ NONE, NONE, NONE, NONE} },
{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
NONE, NONE, NONE, NONE} },
+ {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, NONE, NONE} },
{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
NONE, NONE, NONE, NONE} },
+ {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, NONE, NONE} },
{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
NONE, NONE, NONE, NONE} },
+ {55, {NONE, XFI_FM1_MAC10,
+ XFI_FM2_MAC10, NONE,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{56, {NONE, XFI_FM1_MAC10,
XFI_FM2_MAC10, NONE,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -265,22 +418,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
};
static const struct serdes_config serdes3_cfg_tbl[] = {
/* SerDes 3 */
+ {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
+ {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
+ {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+ {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
+ {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2} },
{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2} },
+ {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2} },
{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2} },
+ {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1} },
{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1} },
+ {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1} },
{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -289,12 +454,19 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
};
static const struct serdes_config serdes4_cfg_tbl[] = {
/* SerDes 4 */
+ {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
+ {5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
{6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
{8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
{10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
+ {11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
{12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
+ {13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
{14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
{16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
{18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
{}
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 34fc8fb..712f2ef 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -38,6 +38,7 @@
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_MPC8540)
@@ -122,6 +123,7 @@
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_MPC8572)
@@ -132,6 +134,7 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_DDR_115
#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1010)
@@ -154,6 +157,7 @@
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
@@ -171,6 +175,7 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1012 is single core version of P1021 */
@@ -188,6 +193,7 @@
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1013 is single core version of P1022 */
@@ -202,6 +208,7 @@
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_FSL_SATA_ERRATUM_A001
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1014)
@@ -219,6 +226,7 @@
#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#define CONFIG_SYS_FSL_ERRATUM_A004508
/* P1017 is single core version of P1023 */
#elif defined(CONFIG_P1017)
@@ -234,6 +242,7 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1020)
@@ -246,6 +255,7 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
@@ -264,6 +274,7 @@
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
@@ -278,6 +289,7 @@
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_FSL_SATA_ERRATUM_A001
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1023)
@@ -293,6 +305,7 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
@@ -309,6 +322,7 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1025 is lower end variant of P1021 */
@@ -326,6 +340,7 @@
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P2010 is single core version of P2020 */
@@ -338,6 +353,7 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P2020)
@@ -353,8 +369,10 @@
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
@@ -657,8 +675,10 @@
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_PCI_VER_3_X
#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
@@ -684,12 +704,14 @@
#define CONFIG_SYS_FSL_ERRATUM_A_004934
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_ERRATUM_A006475
#define CONFIG_SYS_FSL_ERRATUM_A006384
#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#define CONFIG_SYS_FSL_SFP_VER_3_0
#ifdef CONFIG_PPC_B4860
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
@@ -809,8 +831,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006379
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define CONFIG_SYS_FSL_SFP_VER_3_0
#elif defined(CONFIG_PPC_C29X)
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index 37d3a22..3b50487 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -68,6 +68,7 @@ enum law_trgt_if {
LAW_TRGT_IF_DDR_INTLV_1234 = 0x16,
LAW_TRGT_IF_BMAN = 0x18,
LAW_TRGT_IF_DCSR = 0x1d,
+ LAW_TRGT_IF_CCSR = 0x1e,
LAW_TRGT_IF_LBC = 0x1f,
LAW_TRGT_IF_QMAN = 0x3c,
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index f658bcb..adfbb66 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -103,6 +103,10 @@ extern void fdt_fixup_liodn(void *blob);
SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
CONFIG_SYS_MPC85xx_QE_OFFSET)
+#define SET_TDM_LIODN(liodn) \
+ SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
+ CONFIG_SYS_MPC85xx_TDM_OFFSET)
+
#define SET_QMAN_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
CONFIG_SYS_FSL_QMAN_OFFSET, \
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index eff573b..8258ab3 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1899,7 +1899,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
u32 sata2liodnr; /* SATA 2 LIODN */
u32 sata3liodnr; /* SATA 3 LIODN */
u32 sata4liodnr; /* SATA 4 LIODN */
- u8 res22[24];
+ u8 res22[20];
+ u32 tdmliodnr; /* TDM LIODN */
u32 qeliodnr; /* QE LIODN */
u8 res_57c[4];
u32 dma1liodnr; /* DMA 1 LIODN */
@@ -2521,14 +2522,17 @@ typedef struct serdes_corenet {
#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
+#define SRDS_PLLCR0_PLL_LCK 0x00800000
#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000
#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_4_9152 0x00030000
#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
-#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
-#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
+#define SRDS_PLLCR0_FRATE_SEL_3_125 0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000
+#define SRDS_PLLCR0_FRATE_SEL_3_072 0x000c0000
#define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0
#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
u32 pllcr1; /* PLL Control Register 1 */
@@ -2863,6 +2867,21 @@ struct ccsr_pman {
u8 res_f4[0xf0c];
};
#endif
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
+struct ccsr_sfp_regs {
+ u32 ospr; /* 0x200 */
+ u32 reserved0[14];
+ u32 srk_hash[8]; /* 0x23c Super Root Key Hash */
+ u32 oem_uid; /* 0x9c OEM Unique ID */
+ u8 reserved2[0x04];
+ u32 ovpr; /* 0xA4 Intent To Secure */
+ u8 reserved4[0x08];
+ u32 fsl_uid; /* 0xB0 FSL Unique ID */
+ u8 reserved5[0x04];
+ u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */
+ u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */
+};
+#endif
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
@@ -2876,6 +2895,14 @@ struct ccsr_pman {
#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
+/* In SFPv3, OSPR register is now at offset 0x200.
+ * * So directly mapping sfp register map to this address */
+#define CONFIG_SYS_OSPR_OFFSET 0x200
+#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
+#else
+#define CONFIG_SYS_SFP_OFFSET 0xE8000
+#endif
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
@@ -2889,6 +2916,7 @@ struct ccsr_pman {
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
+#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
@@ -3094,6 +3122,9 @@ struct ccsr_pman {
#define CONFIG_SYS_PCIE4_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
+#define CONFIG_SYS_SFP_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
+
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
generated by cgit v1.1 at 2024-11-06 05:36:57 +0000