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-rw-r--r--arch/arm/cpu/armv7/Makefile (renamed from arch/arm/cpu/arm_cortexa8/Makefile)0
-rw-r--r--arch/arm/cpu/armv7/config.mk (renamed from arch/arm/cpu/arm_cortexa8/config.mk)0
-rw-r--r--arch/arm/cpu/armv7/cpu.c (renamed from arch/arm/cpu/arm_cortexa8/cpu.c)0
-rw-r--r--arch/arm/cpu/armv7/mx51/Makefile (renamed from arch/arm/cpu/arm_cortexa8/mx51/Makefile)0
-rw-r--r--arch/arm/cpu/armv7/mx51/clock.c (renamed from arch/arm/cpu/arm_cortexa8/mx51/clock.c)0
-rw-r--r--arch/arm/cpu/armv7/mx51/iomux.c (renamed from arch/arm/cpu/arm_cortexa8/mx51/iomux.c)0
-rw-r--r--arch/arm/cpu/armv7/mx51/lowlevel_init.S (renamed from arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S)0
-rw-r--r--arch/arm/cpu/armv7/mx51/soc.c (renamed from arch/arm/cpu/arm_cortexa8/mx51/soc.c)0
-rw-r--r--arch/arm/cpu/armv7/mx51/speed.c (renamed from arch/arm/cpu/arm_cortexa8/mx51/speed.c)0
-rw-r--r--arch/arm/cpu/armv7/mx51/timer.c (renamed from arch/arm/cpu/arm_cortexa8/mx51/timer.c)0
-rw-r--r--arch/arm/cpu/armv7/mx51/u-boot.lds (renamed from arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds)2
-rw-r--r--arch/arm/cpu/armv7/omap-common/Makefile46
-rw-r--r--arch/arm/cpu/armv7/omap-common/config.mk33
-rw-r--r--arch/arm/cpu/armv7/omap-common/reset.S (renamed from arch/arm/cpu/arm_cortexa8/omap3/reset.S)0
-rw-r--r--arch/arm/cpu/armv7/omap-common/timer.c (renamed from arch/arm/cpu/arm_cortexa8/omap3/timer.c)5
-rw-r--r--arch/arm/cpu/armv7/omap3/Makefile (renamed from arch/arm/cpu/arm_cortexa8/omap3/Makefile)2
-rw-r--r--arch/arm/cpu/armv7/omap3/board.c (renamed from arch/arm/cpu/arm_cortexa8/omap3/board.c)0
-rw-r--r--arch/arm/cpu/armv7/omap3/cache.S (renamed from arch/arm/cpu/arm_cortexa8/omap3/cache.S)0
-rw-r--r--arch/arm/cpu/armv7/omap3/clock.c (renamed from arch/arm/cpu/arm_cortexa8/omap3/clock.c)0
-rw-r--r--arch/arm/cpu/armv7/omap3/emif4.c (renamed from arch/arm/cpu/arm_cortexa8/omap3/emif4.c)0
-rw-r--r--arch/arm/cpu/armv7/omap3/gpio.c (renamed from arch/arm/cpu/arm_cortexa8/omap3/gpio.c)0
-rw-r--r--arch/arm/cpu/armv7/omap3/lowlevel_init.S (renamed from arch/arm/cpu/arm_cortexa8/omap3/lowlevel_init.S)0
-rw-r--r--arch/arm/cpu/armv7/omap3/mem.c (renamed from arch/arm/cpu/arm_cortexa8/omap3/mem.c)0
-rw-r--r--arch/arm/cpu/armv7/omap3/sdrc.c (renamed from arch/arm/cpu/arm_cortexa8/omap3/sdrc.c)0
-rw-r--r--arch/arm/cpu/armv7/omap3/sys_info.c (renamed from arch/arm/cpu/arm_cortexa8/omap3/sys_info.c)0
-rw-r--r--arch/arm/cpu/armv7/omap3/syslib.c (renamed from arch/arm/cpu/arm_cortexa8/omap3/syslib.c)0
-rw-r--r--arch/arm/cpu/armv7/omap4/Makefile48
-rw-r--r--arch/arm/cpu/armv7/omap4/board.c90
-rw-r--r--arch/arm/cpu/armv7/omap4/lowlevel_init.S48
-rw-r--r--arch/arm/cpu/armv7/omap4/sys_info.c54
-rw-r--r--arch/arm/cpu/armv7/s5pc1xx/Makefile (renamed from arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile)0
-rw-r--r--arch/arm/cpu/armv7/s5pc1xx/cache.S (renamed from arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S)2
-rw-r--r--arch/arm/cpu/armv7/s5pc1xx/clock.c (renamed from arch/arm/cpu/arm_cortexa8/s5pc1xx/clock.c)0
-rw-r--r--arch/arm/cpu/armv7/s5pc1xx/cpu_info.c (renamed from arch/arm/cpu/arm_cortexa8/s5pc1xx/cpu_info.c)0
-rw-r--r--arch/arm/cpu/armv7/s5pc1xx/reset.S (renamed from arch/arm/cpu/arm_cortexa8/s5pc1xx/reset.S)0
-rw-r--r--arch/arm/cpu/armv7/s5pc1xx/sromc.c (renamed from arch/arm/cpu/arm_cortexa8/s5pc1xx/sromc.c)0
-rw-r--r--arch/arm/cpu/armv7/s5pc1xx/timer.c (renamed from arch/arm/cpu/arm_cortexa8/s5pc1xx/timer.c)0
-rw-r--r--arch/arm/cpu/armv7/start.S (renamed from arch/arm/cpu/arm_cortexa8/start.S)0
-rw-r--r--arch/arm/cpu/armv7/u-boot.lds (renamed from arch/arm/cpu/arm_cortexa8/u-boot.lds)2
-rw-r--r--arch/arm/cpu/pxa/pxafb.c76
-rw-r--r--arch/arm/cpu/pxa/start.S48
-rw-r--r--arch/arm/include/asm/arch-mx51/asm-offsets.h2
-rw-r--r--arch/arm/include/asm/arch-omap3/i2c.h149
-rw-r--r--arch/arm/include/asm/arch-omap3/mmc.h242
-rw-r--r--arch/arm/include/asm/arch-omap3/mmc_host_def.h15
-rw-r--r--arch/arm/include/asm/arch-omap4/cpu.h94
-rw-r--r--arch/arm/include/asm/arch-omap4/i2c.h74
-rw-r--r--arch/arm/include/asm/arch-omap4/mmc_host_def.h171
-rw-r--r--arch/arm/include/asm/arch-omap4/omap4.h118
-rw-r--r--arch/arm/include/asm/arch-omap4/sys_proto.h37
-rw-r--r--arch/arm/include/asm/arch-pxa/macro.h324
-rw-r--r--arch/arm/include/asm/arch-pxa/pxa-regs.h10
52 files changed, 1289 insertions, 403 deletions
diff --git a/arch/arm/cpu/arm_cortexa8/Makefile b/arch/arm/cpu/armv7/Makefile
index ae20299..ae20299 100644
--- a/arch/arm/cpu/arm_cortexa8/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
diff --git a/arch/arm/cpu/arm_cortexa8/config.mk b/arch/arm/cpu/armv7/config.mk
index 49ac9c7..49ac9c7 100644
--- a/arch/arm/cpu/arm_cortexa8/config.mk
+++ b/arch/arm/cpu/armv7/config.mk
diff --git a/arch/arm/cpu/arm_cortexa8/cpu.c b/arch/arm/cpu/armv7/cpu.c
index a01e0d6..a01e0d6 100644
--- a/arch/arm/cpu/arm_cortexa8/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/Makefile b/arch/arm/cpu/armv7/mx51/Makefile
index 7cfaa2c..7cfaa2c 100644
--- a/arch/arm/cpu/arm_cortexa8/mx51/Makefile
+++ b/arch/arm/cpu/armv7/mx51/Makefile
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/clock.c b/arch/arm/cpu/armv7/mx51/clock.c
index a27227d..a27227d 100644
--- a/arch/arm/cpu/arm_cortexa8/mx51/clock.c
+++ b/arch/arm/cpu/armv7/mx51/clock.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/iomux.c b/arch/arm/cpu/armv7/mx51/iomux.c
index 62b2954..62b2954 100644
--- a/arch/arm/cpu/arm_cortexa8/mx51/iomux.c
+++ b/arch/arm/cpu/armv7/mx51/iomux.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S b/arch/arm/cpu/armv7/mx51/lowlevel_init.S
index 783c81f..783c81f 100644
--- a/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx51/lowlevel_init.S
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/soc.c b/arch/arm/cpu/armv7/mx51/soc.c
index f22ebe9..f22ebe9 100644
--- a/arch/arm/cpu/arm_cortexa8/mx51/soc.c
+++ b/arch/arm/cpu/armv7/mx51/soc.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/speed.c b/arch/arm/cpu/armv7/mx51/speed.c
index a444def..a444def 100644
--- a/arch/arm/cpu/arm_cortexa8/mx51/speed.c
+++ b/arch/arm/cpu/armv7/mx51/speed.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/timer.c b/arch/arm/cpu/armv7/mx51/timer.c
index 81c4a06..81c4a06 100644
--- a/arch/arm/cpu/arm_cortexa8/mx51/timer.c
+++ b/arch/arm/cpu/armv7/mx51/timer.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds b/arch/arm/cpu/armv7/mx51/u-boot.lds
index 2953b93..d66434c 100644
--- a/arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds
+++ b/arch/arm/cpu/armv7/mx51/u-boot.lds
@@ -36,7 +36,7 @@ SECTIONS
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm_cortexa8/start.o
+ arch/arm/cpu/armv7/start.o
*(.text)
}
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
new file mode 100644
index 0000000..3a4a304
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)libomap-common.a
+
+SOBJS := reset.o
+COBJS := timer.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/omap-common/config.mk b/arch/arm/cpu/armv7/omap-common/config.mk
new file mode 100644
index 0000000..49ac9c7
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
+
+# Make ARMv5 to allow more compilers to work, even though its v7a.
+PLATFORM_CPPFLAGS += -march=armv5
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
+ $(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/reset.S b/arch/arm/cpu/armv7/omap-common/reset.S
index a53c408..a53c408 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/reset.S
+++ b/arch/arm/cpu/armv7/omap-common/reset.S
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c
index 401bfe6..69e285f 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/timer.c
+++ b/arch/arm/cpu/armv7/omap-common/timer.c
@@ -84,6 +84,11 @@ void set_timer(ulong t)
/* delay x useconds */
void __udelay(unsigned long usec)
{
+#if defined(CONFIG_OMAP44XX)
+ /* TODO temporary hack until OMAP4 clock setup routines are present */
+ if (usec > 1000)
+ usec = usec/1000;
+#endif
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
unsigned long now, last = readl(&timer_base->tcrr);
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile
index 7d63c6b..79ae267 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
+++ b/arch/arm/cpu/armv7/omap3/Makefile
@@ -27,7 +27,6 @@ LIB = $(obj)lib$(SOC).a
SOBJS := lowlevel_init.o
SOBJS += cache.o
-SOBJS += reset.o
COBJS += board.o
COBJS += clock.o
@@ -35,7 +34,6 @@ COBJS += gpio.o
COBJS += mem.o
COBJS += syslib.o
COBJS += sys_info.o
-COBJS += timer.o
COBJS-$(CONFIG_EMIF4) += emif4.o
COBJS-$(CONFIG_SDRC) += sdrc.o
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 69e56f5..69e56f5 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/cache.S b/arch/arm/cpu/armv7/omap3/cache.S
index 4b65ac5..4b65ac5 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/cache.S
+++ b/arch/arm/cpu/armv7/omap3/cache.S
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 6330c9e..6330c9e 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c
index fae5b11..fae5b11 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/emif4.c
+++ b/arch/arm/cpu/armv7/omap3/emif4.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/gpio.c b/arch/arm/cpu/armv7/omap3/gpio.c
index aeb6066..aeb6066 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/gpio.c
+++ b/arch/arm/cpu/armv7/omap3/gpio.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index 73063ec..73063ec 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
index bd914b0..bd914b0 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/mem.c
+++ b/arch/arm/cpu/armv7/omap3/mem.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index 96fd990c..96fd990c 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
index 1df4401..1df4401 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c
+++ b/arch/arm/cpu/armv7/omap3/sys_info.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/syslib.c b/arch/arm/cpu/armv7/omap3/syslib.c
index 9ced495..9ced495 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/syslib.c
+++ b/arch/arm/cpu/armv7/omap3/syslib.c
diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
new file mode 100644
index 0000000..ecf64f9
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+SOBJS += lowlevel_init.o
+
+COBJS += board.o
+COBJS += sys_info.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
new file mode 100644
index 0000000..5bf7173
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -0,0 +1,90 @@
+/*
+ *
+ * Common functions for OMAP4 based boards
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called path is with SRAM stack.
+ */
+void s_init(void)
+{
+ watchdog_init();
+}
+
+/*
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ */
+void wait_for_command_complete(struct watchdog *wd_base)
+{
+ int pending = 1;
+ do {
+ pending = readl(&wd_base->wwps);
+ } while (pending);
+}
+
+/*
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ */
+void watchdog_init(void)
+{
+ struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
+
+ writel(WD_UNLOCK1, &wd2_base->wspr);
+ wait_for_command_complete(wd2_base);
+ writel(WD_UNLOCK2, &wd2_base->wspr);
+}
+
+/*
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = 0x80000000;
+ gd->bd->bi_dram[0].size = 512 << 20;
+ return 0;
+}
+
+/*
+ * Print board information
+ */
+int checkboard(void)
+{
+ puts(sysinfo.board_string);
+ return 0;
+}
+
diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
new file mode 100644
index 0000000..9a181eb
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
@@ -0,0 +1,48 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/omap4.h>
+
+.globl lowlevel_init
+lowlevel_init:
+ /*
+ * Setup a temporary stack
+ */
+ ldr sp, =LOW_LEVEL_SRAM_STACK
+
+ /*
+ * Save the old lr(passed in ip) and the current lr to stack
+ */
+ push {ip, lr}
+
+ /*
+ * go setup pll, mux, memory
+ */
+ bl s_init
+ pop {ip, pc}
+
diff --git a/arch/arm/cpu/armv7/omap4/sys_info.c b/arch/arm/cpu/armv7/omap4/sys_info.c
new file mode 100644
index 0000000..3b73191
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/sys_info.c
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * get_device_type(): tell if GP/HS/EMU/TST
+ */
+u32 get_device_type(void)
+{
+ return 0;
+}
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev(void)
+{
+ return 0x20;
+}
+
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+
+ puts("CPU : OMAP4430\n");
+
+ return 0;
+}
+
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile b/arch/arm/cpu/armv7/s5pc1xx/Makefile
index 3785593..3785593 100644
--- a/arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile
+++ b/arch/arm/cpu/armv7/s5pc1xx/Makefile
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S
index 906118d..7734b32 100644
--- a/arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S
+++ b/arch/arm/cpu/armv7/s5pc1xx/cache.S
@@ -2,7 +2,7 @@
* Copyright (C) 2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
*
- * based on arch/arm/cpu/arm_cortexa8/omap3/cache.S
+ * based on arch/arm/cpu/armv7/omap3/cache.S
*
* See file CREDITS for list of people who contributed to this
* project.
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/clock.c b/arch/arm/cpu/armv7/s5pc1xx/clock.c
index 19619f9..19619f9 100644
--- a/arch/arm/cpu/arm_cortexa8/s5pc1xx/clock.c
+++ b/arch/arm/cpu/armv7/s5pc1xx/clock.c
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/cpu_info.c b/arch/arm/cpu/armv7/s5pc1xx/cpu_info.c
index f16c0ff..f16c0ff 100644
--- a/arch/arm/cpu/arm_cortexa8/s5pc1xx/cpu_info.c
+++ b/arch/arm/cpu/armv7/s5pc1xx/cpu_info.c
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/reset.S b/arch/arm/cpu/armv7/s5pc1xx/reset.S
index 7f6ff9c..7f6ff9c 100644
--- a/arch/arm/cpu/arm_cortexa8/s5pc1xx/reset.S
+++ b/arch/arm/cpu/armv7/s5pc1xx/reset.S
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/sromc.c b/arch/arm/cpu/armv7/s5pc1xx/sromc.c
index 380be81..380be81 100644
--- a/arch/arm/cpu/arm_cortexa8/s5pc1xx/sromc.c
+++ b/arch/arm/cpu/armv7/s5pc1xx/sromc.c
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/timer.c b/arch/arm/cpu/armv7/s5pc1xx/timer.c
index c5df5c5..c5df5c5 100644
--- a/arch/arm/cpu/arm_cortexa8/s5pc1xx/timer.c
+++ b/arch/arm/cpu/armv7/s5pc1xx/timer.c
diff --git a/arch/arm/cpu/arm_cortexa8/start.S b/arch/arm/cpu/armv7/start.S
index 1e0a150..1e0a150 100644
--- a/arch/arm/cpu/arm_cortexa8/start.S
+++ b/arch/arm/cpu/armv7/start.S
diff --git a/arch/arm/cpu/arm_cortexa8/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
index 820e3a1..9e5b5a9 100644
--- a/arch/arm/cpu/arm_cortexa8/u-boot.lds
+++ b/arch/arm/cpu/armv7/u-boot.lds
@@ -34,7 +34,7 @@ SECTIONS
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm_cortexa8/start.o (.text)
+ arch/arm/cpu/armv7/start.o (.text)
*(.text)
}
diff --git a/arch/arm/cpu/pxa/pxafb.c b/arch/arm/cpu/pxa/pxafb.c
index d56c5f0..524a03b 100644
--- a/arch/arm/cpu/pxa/pxafb.c
+++ b/arch/arm/cpu/pxa/pxafb.c
@@ -112,6 +112,39 @@ vidinfo_t panel_info = {
vl_efw: 0,
};
#endif /* CONFIG_SHARP_LM8V31 */
+/*----------------------------------------------------------------------*/
+#ifdef CONFIG_VOIPAC_LCD
+
+# define LCD_BPP LCD_COLOR8
+# define LCD_INVERT_COLORS
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x043008f8
+# define REG_LCCR3 0x0340FF08
+
+vidinfo_t panel_info = {
+ vl_col: 640,
+ vl_row: 480,
+ vl_width: 157,
+ vl_height: 118,
+ vl_clkp: CONFIG_SYS_HIGH,
+ vl_oep: CONFIG_SYS_HIGH,
+ vl_hsp: CONFIG_SYS_HIGH,
+ vl_vsp: CONFIG_SYS_HIGH,
+ vl_dp: CONFIG_SYS_HIGH,
+ vl_bpix: LCD_BPP,
+ vl_lbw: 0,
+ vl_splt: 1,
+ vl_clor: 1,
+ vl_tft: 1,
+ vl_hpw: 32,
+ vl_blw: 144,
+ vl_elw: 32,
+ vl_vpw: 2,
+ vl_bfw: 13,
+ vl_efw: 30,
+};
+#endif /* CONFIG_VOIPAC_LCD */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_HITACHI_SX14
@@ -147,6 +180,40 @@ vidinfo_t panel_info = {
#endif /* CONFIG_HITACHI_SX14 */
/*----------------------------------------------------------------------*/
+#ifdef CONFIG_LMS283GF05
+
+# define LCD_BPP LCD_COLOR8
+//# define LCD_INVERT_COLORS
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x043008f8
+# define REG_LCCR3 0x03b00009
+
+vidinfo_t panel_info = {
+ vl_col: 240,
+ vl_row: 320,
+ vl_width: 240,
+ vl_height: 320,
+ vl_clkp: CONFIG_SYS_HIGH,
+ vl_oep: CONFIG_SYS_LOW,
+ vl_hsp: CONFIG_SYS_LOW,
+ vl_vsp: CONFIG_SYS_LOW,
+ vl_dp: CONFIG_SYS_HIGH,
+ vl_bpix: LCD_BPP,
+ vl_lbw: 0,
+ vl_splt: 1,
+ vl_clor: 1,
+ vl_tft: 1,
+ vl_hpw: 4,
+ vl_blw: 4,
+ vl_elw: 8,
+ vl_vpw: 4,
+ vl_bfw: 4,
+ vl_efw: 8,
+};
+#endif /* CONFIG_LMS283GF05 */
+
+/*----------------------------------------------------------------------*/
#if LCD_BPP == LCD_COLOR8
void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
@@ -292,7 +359,9 @@ static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
return 0;
}
-
+#ifdef CONFIG_CPU_MONAHANS
+static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
+#else
static void pxafb_setup_gpio (vidinfo_t *vid)
{
u_long lccr0;
@@ -349,6 +418,7 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
}
}
+#endif
static void pxafb_enable_controller (vidinfo_t *vid)
{
@@ -363,7 +433,11 @@ static void pxafb_enable_controller (vidinfo_t *vid)
FDADR1 = vid->pxa.fdadr1;
LCCR0 |= LCCR0_ENB;
+#ifdef CONFIG_CPU_MONAHANS
+ CKENA |= CKENA_1_LCD;
+#else
CKEN |= CKEN16_LCD;
+#endif
debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index e07c8c2..8010b0e 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -34,6 +34,25 @@
.globl _start
_start: b reset
+#ifdef CONFIG_PRELOADER
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+
+_hang:
+ .word do_hang
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678 /* now 16*4=64 */
+#else
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@@ -49,6 +68,7 @@ _data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
+#endif /* CONFIG_PRELOADER */
.balignl 16,0xdeadbeef
@@ -117,8 +137,10 @@ reset:
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
+#ifndef CONFIG_PRELOADER
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
+#endif
ldr r2, _armboot_start
ldr r3, _bss_start
@@ -135,28 +157,37 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
+#ifdef CONFIG_PRELOADER
+ sub sp, r0, #128 /* leave 32 words for abort-stack */
+#else
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif /* CONFIG_USE_IRQ */
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+#endif
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
+#ifndef CONFIG_PRELOADER
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
ble clbss_l
+#endif
ldr pc, _start_armboot
+#ifdef CONFIG_ONENAND_IPL
+_start_armboot: .word start_oneboot
+#else
_start_armboot: .word start_armboot
-
+#endif
/****************************************************************************/
/* */
@@ -296,7 +327,7 @@ setspeed_done:
*/
mov pc, lr
-
+#ifndef CONFIG_PRELOADER
/****************************************************************************/
/* */
/* Interrupt handling */
@@ -394,6 +425,7 @@ setspeed_done:
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
+#endif /* CONFIG_PRELOADER */
/****************************************************************************/
@@ -402,6 +434,12 @@ setspeed_done:
/* */
/****************************************************************************/
+#ifdef CONFIG_PRELOADER
+ .align 5
+do_hang:
+ ldr sp, _TEXT_BASE /* use 32 words abort stack */
+ bl hang /* hang and never return */
+#else /* !CONFIG_PRELOADER */
.align 5
undefined_instruction:
get_bad_stack
@@ -461,7 +499,7 @@ fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
-
+#endif /* CONFIG_PRELOADER */
#endif /* CONFIG_USE_IRQ */
/****************************************************************************/
diff --git a/arch/arm/include/asm/arch-mx51/asm-offsets.h b/arch/arm/include/asm/arch-mx51/asm-offsets.h
index fbba412..afd2728 100644
--- a/arch/arm/include/asm/arch-mx51/asm-offsets.h
+++ b/arch/arm/include/asm/arch-mx51/asm-offsets.h
@@ -1,5 +1,5 @@
/*
- * needed for arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S
+ * needed for arch/arm/cpu/armv7/mx51/lowlevel_init.S
*
* These should be auto-generated
*/
diff --git a/arch/arm/include/asm/arch-omap3/i2c.h b/arch/arm/include/asm/arch-omap3/i2c.h
index 490e03b..7a4a73a 100644
--- a/arch/arm/include/asm/arch-omap3/i2c.h
+++ b/arch/arm/include/asm/arch-omap3/i2c.h
@@ -20,9 +20,10 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#ifndef _I2C_H_
-#define _I2C_H_
+#ifndef _OMAP3_I2C_H_
+#define _OMAP3_I2C_H_
+#define I2C_BUS_MAX 3
#define I2C_DEFAULT_BASE I2C_BASE1
struct i2c {
@@ -58,146 +59,4 @@ struct i2c {
unsigned short res15;
};
-#define I2C_BUS_MAX 3
-
-/* I2C masks */
-
-/* I2C Interrupt Enable Register (I2C_IE): */
-#define I2C_IE_GC_IE (1 << 5)
-#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
-#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
-#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
-#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
-#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
-
-/* I2C Status Register (I2C_STAT): */
-
-#define I2C_STAT_SBD (1 << 15) /* Single byte data */
-#define I2C_STAT_BB (1 << 12) /* Bus busy */
-#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
-#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
-#define I2C_STAT_AAS (1 << 9) /* Address as slave */
-#define I2C_STAT_GC (1 << 5)
-#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
-#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
-#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
-#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
-#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
-
-/* I2C Interrupt Code Register (I2C_INTCODE): */
-
-#define I2C_INTCODE_MASK 7
-#define I2C_INTCODE_NONE 0
-#define I2C_INTCODE_AL 1 /* Arbitration lost */
-#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
-#define I2C_INTCODE_ARDY 3 /* Register access ready */
-#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
-#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
-
-/* I2C Buffer Configuration Register (I2C_BUF): */
-
-#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
-#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
-
-/* I2C Configuration Register (I2C_CON): */
-
-#define I2C_CON_EN (1 << 15) /* I2C module enable */
-#define I2C_CON_BE (1 << 14) /* Big endian mode */
-#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
-#define I2C_CON_MST (1 << 10) /* Master/slave mode */
-#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */
- /* (master mode only) */
-#define I2C_CON_XA (1 << 8) /* Expand address */
-#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
-#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
-
-/* I2C System Test Register (I2C_SYSTEST): */
-
-#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
-#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */
-#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
-#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
-#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
-#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
-#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
-#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
-
-#define I2C_SCLL_SCLL 0
-#define I2C_SCLL_SCLL_M 0xFF
-#define I2C_SCLL_HSSCLL 8
-#define I2C_SCLH_HSSCLL_M 0xFF
-#define I2C_SCLH_SCLH 0
-#define I2C_SCLH_SCLH_M 0xFF
-#define I2C_SCLH_HSSCLH 8
-#define I2C_SCLH_HSSCLH_M 0xFF
-
-#define OMAP_I2C_STANDARD 100000
-#define OMAP_I2C_FAST_MODE 400000
-#define OMAP_I2C_HIGH_SPEED 3400000
-
-#define SYSTEM_CLOCK_12 12000000
-#define SYSTEM_CLOCK_13 13000000
-#define SYSTEM_CLOCK_192 19200000
-#define SYSTEM_CLOCK_96 96000000
-
-/* Use the reference value of 96MHz if not explicitly set by the board */
-#ifndef I2C_IP_CLK
-#define I2C_IP_CLK SYSTEM_CLOCK_96
-#endif
-
-/*
- * The reference minimum clock for high speed is 19.2MHz.
- * The linux 2.6.30 kernel uses this value.
- * The reference minimum clock for fast mode is 9.6MHz
- * The reference minimum clock for standard mode is 4MHz
- * In TRM, the value of 12MHz is used.
- */
-#ifndef I2C_INTERNAL_SAMPLING_CLK
-#define I2C_INTERNAL_SAMPLING_CLK 19200000
-#endif
-
-/*
- * The equation for the low and high time is
- * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
- * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
- *
- * If the duty cycle is 50%
- *
- * tlow = scll + scll_trim = sampling clock / (2 * speed)
- * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
- *
- * In TRM
- * scll_trim = 7
- * sclh_trim = 5
- *
- * The linux 2.6.30 kernel uses
- * scll_trim = 6
- * sclh_trim = 6
- *
- * These are the trim values for standard and fast speed
- */
-#ifndef I2C_FASTSPEED_SCLL_TRIM
-#define I2C_FASTSPEED_SCLL_TRIM 6
-#endif
-#ifndef I2C_FASTSPEED_SCLH_TRIM
-#define I2C_FASTSPEED_SCLH_TRIM 6
-#endif
-
-/* These are the trim values for high speed */
-#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
-#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
-#endif
-#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
-#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
-#endif
-#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
-#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
-#endif
-#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
-#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
-#endif
-
-#define I2C_PSC_MAX 0x0f
-#define I2C_PSC_MIN 0x00
-
-#endif /* _I2C_H_ */
+#endif /* _OMAP3_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/mmc.h b/arch/arm/include/asm/arch-omap3/mmc.h
deleted file mode 100644
index 196ffdc..0000000
--- a/arch/arm/include/asm/arch-omap3/mmc.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation's version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef MMC_H
-#define MMC_H
-
-#include "mmc_host_def.h"
-
-/* Responses */
-#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
-#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
-#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK)
-#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK)
-#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK)
-#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK)
-#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
-#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
-#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
-
-/* All supported commands */
-#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
-#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD7_DESELECT (INDEX(7)| RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
-#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
-#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
-#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE)
-#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
-#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE)
-#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
-#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
-
-#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16)
-#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16)
-#define MMC_DSR_DEFAULT 0x0404
-#define SD_CMD8_CHECK_PATTERN 0xAA
-#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8)
-
-/* Clock Configurations and Macros */
-
-#define MMC_CLOCK_REFERENCE 96
-#define MMC_RELATIVE_CARD_ADDRESS 0x1234
-#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80)
-#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400)
-#define CLKDR(r, f, u) ((((r)*100) / ((f)*(u))) + 1)
-#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u))
-
-#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29)
-#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29)
-#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29)
-
-#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30)
-#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30)
-#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30)
-
-#define MMC_SD2_CSD_C_SIZE_LSB_MASK 0xFFFF
-#define MMC_SD2_CSD_C_SIZE_MSB_MASK 0x003F
-#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET 16
-#define MMC_CSD_C_SIZE_LSB_MASK 0x0003
-#define MMC_CSD_C_SIZE_MSB_MASK 0x03FF
-#define MMC_CSD_C_SIZE_MSB_OFFSET 2
-
-#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0)
-#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3)
-#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0)
-#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3)
-#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3)
-
-typedef struct {
- unsigned not_used:1;
- unsigned crc:7;
- unsigned ecc:2;
- unsigned file_format:2;
- unsigned tmp_write_protect:1;
- unsigned perm_write_protect:1;
- unsigned copy:1;
- unsigned file_format_grp:1;
- unsigned content_prot_app:1;
- unsigned reserved_1:4;
- unsigned write_bl_partial:1;
- unsigned write_bl_len:4;
- unsigned r2w_factor:3;
- unsigned default_ecc:2;
- unsigned wp_grp_enable:1;
- unsigned wp_grp_size:5;
- unsigned erase_grp_mult:5;
- unsigned erase_grp_size:5;
- unsigned c_size_mult:3;
- unsigned vdd_w_curr_max:3;
- unsigned vdd_w_curr_min:3;
- unsigned vdd_r_curr_max:3;
- unsigned vdd_r_curr_min:3;
- unsigned c_size_lsb:2;
- unsigned c_size_msb:10;
- unsigned reserved_2:2;
- unsigned dsr_imp:1;
- unsigned read_blk_misalign:1;
- unsigned write_blk_misalign:1;
- unsigned read_bl_partial:1;
- unsigned read_bl_len:4;
- unsigned ccc:12;
- unsigned tran_speed:8;
- unsigned nsac:8;
- unsigned taac:8;
- unsigned reserved_3:2;
- unsigned spec_vers:4;
- unsigned csd_structure:2;
-} mmc_csd_reg_t;
-
-/* csd for sd2.0 */
-typedef struct {
- unsigned not_used:1;
- unsigned crc:7;
- unsigned reserved_1:2;
- unsigned file_format:2;
- unsigned tmp_write_protect:1;
- unsigned perm_write_protect:1;
- unsigned copy:1;
- unsigned file_format_grp:1;
- unsigned reserved_2:5;
- unsigned write_bl_partial:1;
- unsigned write_bl_len:4;
- unsigned r2w_factor:3;
- unsigned reserved_3:2;
- unsigned wp_grp_enable:1;
- unsigned wp_grp_size:7;
- unsigned sector_size:7;
- unsigned erase_blk_len:1;
- unsigned reserved_4:1;
- unsigned c_size_lsb:16;
- unsigned c_size_msb:6;
- unsigned reserved_5:6;
- unsigned dsr_imp:1;
- unsigned read_blk_misalign:1;
- unsigned write_blk_misalign:1;
- unsigned read_bl_partial:1;
- unsigned read_bl_len:4;
- unsigned ccc:12;
- unsigned tran_speed:8;
- unsigned nsac:8;
- unsigned taac:8;
- unsigned reserved_6:6;
- unsigned csd_structure:2;
-} mmc_sd2_csd_reg_t;
-
-/* extended csd - 512 bytes long */
-typedef struct {
- unsigned char reserved_1[181];
- unsigned char erasedmemorycontent;
- unsigned char reserved_2;
- unsigned char buswidthmode;
- unsigned char reserved_3;
- unsigned char highspeedinterfacetiming;
- unsigned char reserved_4;
- unsigned char powerclass;
- unsigned char reserved_5;
- unsigned char commandsetrevision;
- unsigned char reserved_6;
- unsigned char commandset;
- unsigned char extendedcsdrevision;
- unsigned char reserved_7;
- unsigned char csdstructureversion;
- unsigned char reserved_8;
- unsigned char cardtype;
- unsigned char reserved_9[3];
- unsigned char powerclass_52mhz_1_95v;
- unsigned char powerclass_26mhz_1_95v;
- unsigned char powerclass_52mhz_3_6v;
- unsigned char powerclass_26mhz_3_6v;
- unsigned char reserved_10;
- unsigned char minreadperf_4b_26mhz;
- unsigned char minwriteperf_4b_26mhz;
- unsigned char minreadperf_8b_26mhz_4b_52mhz;
- unsigned char minwriteperf_8b_26mhz_4b_52mhz;
- unsigned char minreadperf_8b_52mhz;
- unsigned char minwriteperf_8b_52mhz;
- unsigned char reserved_11;
- unsigned int sectorcount;
- unsigned char reserved_12[288];
- unsigned char supportedcommandsets;
- unsigned char reserved_13[7];
-} mmc_extended_csd_reg_t;
-
-/* mmc sd responce */
-typedef struct {
- unsigned int ocr;
-} mmc_resp_r3;
-
-typedef struct {
- unsigned short cardstatus;
- unsigned short newpublishedrca;
-} mmc_resp_r6;
-
-typedef union {
- unsigned int resp[4];
- mmc_resp_r3 r3;
- mmc_resp_r6 r6;
- mmc_csd_reg_t Card_CSD;
-} mmc_resp_t;
-
-extern mmc_card_data mmc_dev;
-
-unsigned char mmc_lowlevel_init(void);
-unsigned char mmc_send_command(unsigned int cmd, unsigned int arg,
- unsigned int *response);
-unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd);
-unsigned char mmc_set_opendrain(unsigned char state);
-unsigned char mmc_read_data(unsigned int *output_buf);
-
-#endif /* MMC_H */
diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
index aa751c9..43dd705 100644
--- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
@@ -29,13 +29,20 @@
#define T2_BASE 0x48002000
typedef struct t2 {
- unsigned char res1[0x274];
+ unsigned char res1[0x274]; /* 0x000 */
unsigned int devconf0; /* 0x274 */
- unsigned char res2[0x2A8];
+ unsigned char res2[0x060]; /* 0x278 */
+ unsigned int devconf1; /* 0x2D8 */
+ unsigned char res3[0x244]; /* 0x2DC */
unsigned int pbias_lite; /* 0x520 */
} t2_t;
#define MMCSDIO1ADPCLKISEL (1 << 24)
+#define MMCSDIO2ADPCLKISEL (1 << 6)
+
+#define EN_MMC1 (1 << 24)
+#define EN_MMC2 (1 << 25)
+#define EN_MMC3 (1 << 30)
#define PBIASLITEPWRDNZ0 (1 << 1)
#define PBIASSPEEDCTRL0 (1 << 2)
@@ -44,7 +51,9 @@ typedef struct t2 {
/*
* OMAP HSMMC register definitions
*/
-#define OMAP_HSMMC_BASE 0x4809C000
+#define OMAP_HSMMC1_BASE 0x4809C000
+#define OMAP_HSMMC2_BASE 0x480B4000
+#define OMAP_HSMMC3_BASE 0x480AD000
typedef struct hsmmc {
unsigned char res1[0x10];
diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
new file mode 100644
index 0000000..7d8aa20
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2006-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct gptimer {
+ u32 tidr; /* 0x00 r */
+ u8 res[0xc];
+ u32 tiocp_cfg; /* 0x10 rw */
+ u32 tistat; /* 0x14 r */
+ u32 tisr; /* 0x18 rw */
+ u32 tier; /* 0x1c rw */
+ u32 twer; /* 0x20 rw */
+ u32 tclr; /* 0x24 rw */
+ u32 tcrr; /* 0x28 rw */
+ u32 tldr; /* 0x2c rw */
+ u32 ttgr; /* 0x30 rw */
+ u32 twpc; /* 0x34 r */
+ u32 tmar; /* 0x38 rw */
+ u32 tcar1; /* 0x3c r */
+ u32 tcicr; /* 0x40 rw */
+ u32 tcar2; /* 0x44 r */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* enable sys_clk NO-prescale /1 */
+#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
+
+/* Watchdog */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct watchdog {
+ u8 res1[0x34];
+ u32 wwps; /* 0x34 r */
+ u8 res2[0x10];
+ u32 wspr; /* 0x48 rw */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define WD_UNLOCK1 0xAAAA
+#define WD_UNLOCK2 0x5555
+
+#define SYSCLKDIV_1 (0x1 << 6)
+#define SYSCLKDIV_2 (0x1 << 7)
+
+#define CLKSEL_GPT1 (0x1 << 0)
+
+#define EN_GPT1 (0x1 << 0)
+#define EN_32KSYNC (0x1 << 2)
+
+#define ST_WDT2 (0x1 << 5)
+
+#define RESETDONE (0x1 << 0)
+
+#define TCLR_ST (0x1 << 0)
+#define TCLR_AR (0x1 << 1)
+#define TCLR_PRE (0x1 << 5)
+
+/* I2C base */
+#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000)
+#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000)
+#define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000)
+
+#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap4/i2c.h b/arch/arm/include/asm/arch-omap4/i2c.h
new file mode 100644
index 0000000..a91b4c2
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/i2c.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2004-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP4_I2C_H_
+#define _OMAP4_I2C_H_
+
+#define I2C_BUS_MAX 3
+#define I2C_DEFAULT_BASE I2C_BASE1
+
+struct i2c {
+ unsigned short revnb_lo; /* 0x00 */
+ unsigned short res1;
+ unsigned short revnb_hi; /* 0x04 */
+ unsigned short res2[13];
+ unsigned short sysc; /* 0x20 */
+ unsigned short res3;
+ unsigned short irqstatus_raw; /* 0x24 */
+ unsigned short res4;
+ unsigned short stat; /* 0x28 */
+ unsigned short res5;
+ unsigned short ie; /* 0x2C */
+ unsigned short res6;
+ unsigned short irqenable_clr; /* 0x30 */
+ unsigned short res7;
+ unsigned short iv; /* 0x34 */
+ unsigned short res8[45];
+ unsigned short syss; /* 0x90 */
+ unsigned short res9;
+ unsigned short buf; /* 0x94 */
+ unsigned short res10;
+ unsigned short cnt; /* 0x98 */
+ unsigned short res11;
+ unsigned short data; /* 0x9C */
+ unsigned short res13;
+ unsigned short res14; /* 0xA0 */
+ unsigned short res15;
+ unsigned short con; /* 0xA4 */
+ unsigned short res16;
+ unsigned short oa; /* 0xA8 */
+ unsigned short res17;
+ unsigned short sa; /* 0xAC */
+ unsigned short res18;
+ unsigned short psc; /* 0xB0 */
+ unsigned short res19;
+ unsigned short scll; /* 0xB4 */
+ unsigned short res20;
+ unsigned short sclh; /* 0xB8 */
+ unsigned short res21;
+ unsigned short systest; /* 0xBC */
+ unsigned short res22;
+ unsigned short bufstat; /* 0xC0 */
+ unsigned short res23;
+};
+
+#endif /* _OMAP4_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
new file mode 100644
index 0000000..e5d8b53
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+/*
+ * OMAP HSMMC register definitions
+ */
+
+#define OMAP_HSMMC1_BASE 0x4809C100
+#define OMAP_HSMMC2_BASE 0x480B4100
+#define OMAP_HSMMC3_BASE 0x480AD100
+
+typedef struct hsmmc {
+ unsigned char res1[0x10];
+ unsigned int sysconfig; /* 0x10 */
+ unsigned int sysstatus; /* 0x14 */
+ unsigned char res2[0x14];
+ unsigned int con; /* 0x2C */
+ unsigned char res3[0xD4];
+ unsigned int blk; /* 0x104 */
+ unsigned int arg; /* 0x108 */
+ unsigned int cmd; /* 0x10C */
+ unsigned int rsp10; /* 0x110 */
+ unsigned int rsp32; /* 0x114 */
+ unsigned int rsp54; /* 0x118 */
+ unsigned int rsp76; /* 0x11C */
+ unsigned int data; /* 0x120 */
+ unsigned int pstate; /* 0x124 */
+ unsigned int hctl; /* 0x128 */
+ unsigned int sysctl; /* 0x12C */
+ unsigned int stat; /* 0x130 */
+ unsigned int ie; /* 0x134 */
+ unsigned char res4[0x8];
+ unsigned int capa; /* 0x140 */
+} hsmmc_t;
+
+/*
+ * OMAP HS MMC Bit definitions
+ */
+#define MMC_SOFTRESET (0x1 << 1)
+#define RESETDONE (0x1 << 0)
+#define NOOPENDRAIN (0x0 << 0)
+#define OPENDRAIN (0x1 << 0)
+#define OD (0x1 << 0)
+#define INIT_NOINIT (0x0 << 1)
+#define INIT_INITSTREAM (0x1 << 1)
+#define HR_NOHOSTRESP (0x0 << 2)
+#define STR_BLOCK (0x0 << 3)
+#define MODE_FUNC (0x0 << 4)
+#define DW8_1_4BITMODE (0x0 << 5)
+#define MIT_CTO (0x0 << 6)
+#define CDP_ACTIVEHIGH (0x0 << 7)
+#define WPP_ACTIVEHIGH (0x0 << 8)
+#define RESERVED_MASK (0x3 << 9)
+#define CTPL_MMC_SD (0x0 << 11)
+#define BLEN_512BYTESLEN (0x200 << 0)
+#define NBLK_STPCNT (0x0 << 16)
+#define DE_DISABLE (0x0 << 0)
+#define BCE_DISABLE (0x0 << 1)
+#define ACEN_DISABLE (0x0 << 2)
+#define DDIR_OFFSET (4)
+#define DDIR_MASK (0x1 << 4)
+#define DDIR_WRITE (0x0 << 4)
+#define DDIR_READ (0x1 << 4)
+#define MSBS_SGLEBLK (0x0 << 5)
+#define RSP_TYPE_OFFSET (16)
+#define RSP_TYPE_MASK (0x3 << 16)
+#define RSP_TYPE_NORSP (0x0 << 16)
+#define RSP_TYPE_LGHT136 (0x1 << 16)
+#define RSP_TYPE_LGHT48 (0x2 << 16)
+#define RSP_TYPE_LGHT48B (0x3 << 16)
+#define CCCE_NOCHECK (0x0 << 19)
+#define CCCE_CHECK (0x1 << 19)
+#define CICE_NOCHECK (0x0 << 20)
+#define CICE_CHECK (0x1 << 20)
+#define DP_OFFSET (21)
+#define DP_MASK (0x1 << 21)
+#define DP_NO_DATA (0x0 << 21)
+#define DP_DATA (0x1 << 21)
+#define CMD_TYPE_NORMAL (0x0 << 22)
+#define INDEX_OFFSET (24)
+#define INDEX_MASK (0x3f << 24)
+#define INDEX(i) (i << 24)
+#define DATI_MASK (0x1 << 1)
+#define DATI_CMDDIS (0x1 << 1)
+#define DTW_1_BITMODE (0x0 << 1)
+#define DTW_4_BITMODE (0x1 << 1)
+#define SDBP_PWROFF (0x0 << 8)
+#define SDBP_PWRON (0x1 << 8)
+#define SDVS_1V8 (0x5 << 9)
+#define SDVS_3V0 (0x6 << 9)
+#define ICE_MASK (0x1 << 0)
+#define ICE_STOP (0x0 << 0)
+#define ICS_MASK (0x1 << 1)
+#define ICS_NOTREADY (0x0 << 1)
+#define ICE_OSCILLATE (0x1 << 0)
+#define CEN_MASK (0x1 << 2)
+#define CEN_DISABLE (0x0 << 2)
+#define CEN_ENABLE (0x1 << 2)
+#define CLKD_OFFSET (6)
+#define CLKD_MASK (0x3FF << 6)
+#define DTO_MASK (0xF << 16)
+#define DTO_15THDTO (0xE << 16)
+#define SOFTRESETALL (0x1 << 24)
+#define CC_MASK (0x1 << 0)
+#define TC_MASK (0x1 << 1)
+#define BWR_MASK (0x1 << 4)
+#define BRR_MASK (0x1 << 5)
+#define ERRI_MASK (0x1 << 15)
+#define IE_CC (0x01 << 0)
+#define IE_TC (0x01 << 1)
+#define IE_BWR (0x01 << 4)
+#define IE_BRR (0x01 << 5)
+#define IE_CTO (0x01 << 16)
+#define IE_CCRC (0x01 << 17)
+#define IE_CEB (0x01 << 18)
+#define IE_CIE (0x01 << 19)
+#define IE_DTO (0x01 << 20)
+#define IE_DCRC (0x01 << 21)
+#define IE_DEB (0x01 << 22)
+#define IE_CERR (0x01 << 28)
+#define IE_BADA (0x01 << 29)
+
+#define VS30_3V0SUP (1 << 25)
+#define VS18_1V8SUP (1 << 26)
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE 512
+#define MMC_CARD 0
+#define SD_CARD 1
+#define BYTE_MODE 0
+#define SECTOR_MODE 1
+#define CLK_INITSEQ 0
+#define CLK_400KHZ 1
+#define CLK_MISC 2
+
+typedef struct {
+ unsigned int card_type;
+ unsigned int version;
+ unsigned int mode;
+ unsigned int size;
+ unsigned int RCA;
+} mmc_card_data;
+
+#define mmc_reg_out(addr, mask, val)\
+ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
new file mode 100644
index 0000000..d123d6a
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Authors:
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Derived from OMAP3 work by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP4_H_
+#define _OMAP4_H_
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP44XX_L4_CORE_BASE 0x4A000000
+#define OMAP44XX_L4_WKUP_BASE 0x4A300000
+#define OMAP44XX_L4_PER_BASE 0x48000000
+
+/* CONTROL */
+#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
+
+/* UART */
+#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
+#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
+#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000)
+
+/* General Purpose Timers */
+#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000)
+#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000)
+#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000)
+
+/* Watchdog Timer2 - MPU watchdog */
+#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
+
+/* 32KTIMER */
+#define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
+
+/* GPMC */
+#define GPMC_BASE 0x50000000
+
+/*
+ * Hardware Register Details
+ */
+
+/* Watchdog Timer */
+#define WD_UNLOCK1 0xAAAA
+#define WD_UNLOCK2 0x5555
+
+/* GP Timer */
+#define TCLR_ST (0x1 << 0)
+#define TCLR_AR (0x1 << 1)
+#define TCLR_PRE (0x1 << 5)
+
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE 0x4A306000
+#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL PRM_DEVICE_BASE
+
+#ifndef __ASSEMBLY__
+
+struct s32ktimer {
+ unsigned char res[0x10];
+ unsigned int s32k_cr; /* 0x10 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Non-secure SRAM Addresses
+ * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
+ * at 0x40304000(EMU base) so that our code works for both EMU and GP
+ */
+#define NON_SECURE_SRAM_START 0x40304000
+#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_ROM_VECT_BASE 0x4030D000
+/* Temporary SRAM stack used while low level init is done */
+#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
+
+/*
+ * OMAP4 real hardware:
+ * TODO: Change this to the IDCODE in the hw regsiter
+ */
+#define CPU_OMAP4430_ES10 1
+#define CPU_OMAP4430_ES20 2
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
new file mode 100644
index 0000000..6f4d3d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <asm/arch/omap4.h>
+#include <asm/io.h>
+
+struct omap_sysinfo {
+ char *board_string;
+};
+
+void watchdog_init(void);
+u32 get_device_type(void);
+void invalidate_dcache(u32);
+
+extern const struct omap_sysinfo sysinfo;
+
+#endif
diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h
new file mode 100644
index 0000000..035a57e
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa/macro.h
@@ -0,0 +1,324 @@
+/*
+ * arch/arm/include/asm/arch-pxa/macro.h
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_PXA_MACRO_H__
+#define __ASM_ARCH_PXA_MACRO_H__
+#ifdef __ASSEMBLY__
+
+#include <asm/macro.h>
+#include <asm/arch/pxa-regs.h>
+
+/*
+ * This macro performs a 32bit write to a memory location and makes sure the
+ * write operation really happened by performing a read back.
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro write32rb addr, data
+ ldr r4, =\addr
+ ldr r5, =\data
+ str r5, [r4]
+ ldr r5, [r4]
+.endm
+
+/*
+ * This macro waits according to OSCR incrementation
+ *
+ * Clobbered regs: r4, r5, r6
+ */
+.macro pxa_wait_ticks ticks
+ ldr r4, =OSCR
+ mov r5, #0
+ str r5, [r4]
+ ldr r5, =\ticks
+1:
+ ldr r6, [r4]
+ cmp r5, r6
+ bgt 1b
+.endm
+
+/*
+ * This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro pxa_gpio_setup
+ write32 GPSR0, CONFIG_SYS_GPSR0_VAL
+ write32 GPSR1, CONFIG_SYS_GPSR1_VAL
+ write32 GPSR2, CONFIG_SYS_GPSR2_VAL
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ write32 GPSR3, CONFIG_SYS_GPSR3_VAL
+#endif
+
+ write32 GPCR0, CONFIG_SYS_GPCR0_VAL
+ write32 GPCR1, CONFIG_SYS_GPCR1_VAL
+ write32 GPCR2, CONFIG_SYS_GPCR2_VAL
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ write32 GPCR3, CONFIG_SYS_GPCR3_VAL
+#endif
+
+ write32 GPDR0, CONFIG_SYS_GPDR0_VAL
+ write32 GPDR1, CONFIG_SYS_GPDR1_VAL
+ write32 GPDR2, CONFIG_SYS_GPDR2_VAL
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ write32 GPDR3, CONFIG_SYS_GPDR3_VAL
+#endif
+
+ write32 GAFR0_L, CONFIG_SYS_GAFR0_L_VAL
+ write32 GAFR0_U, CONFIG_SYS_GAFR0_U_VAL
+ write32 GAFR1_L, CONFIG_SYS_GAFR1_L_VAL
+ write32 GAFR1_U, CONFIG_SYS_GAFR1_U_VAL
+ write32 GAFR2_L, CONFIG_SYS_GAFR2_L_VAL
+ write32 GAFR2_U, CONFIG_SYS_GAFR2_U_VAL
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ write32 GAFR3_L, CONFIG_SYS_GAFR3_L_VAL
+ write32 GAFR3_U, CONFIG_SYS_GAFR3_U_VAL
+#endif
+
+ write32 PSSR, CONFIG_SYS_PSSR_VAL
+.endm
+
+/*
+ * This macro sets up the Memory controller of the PXA2xx CPU
+ *
+ * Clobbered regs: r3, r4, r5
+ */
+.macro pxa_mem_setup
+ /* This comes handy when setting MDREFR */
+ ldr r3, =MEMC_BASE
+
+ /*
+ * 1) Initialize Asynchronous static memory controller
+ */
+
+ /* MSC0: nCS(0,1) */
+ write32rb (MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL
+ /* MSC1: nCS(2,3) */
+ write32rb (MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL
+ /* MSC2: nCS(4,5) */
+ write32rb (MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL
+
+ /*
+ * 2) Initialize Card Interface
+ */
+
+ /* MECR: Memory Expansion Card Register */
+ write32rb (MEMC_BASE + MECR_OFFSET), CONFIG_SYS_MECR_VAL
+ /* MCMEM0: Card Interface slot 0 timing */
+ write32rb (MEMC_BASE + MCMEM0_OFFSET), CONFIG_SYS_MCMEM0_VAL
+ /* MCMEM1: Card Interface slot 1 timing */
+ write32rb (MEMC_BASE + MCMEM1_OFFSET), CONFIG_SYS_MCMEM1_VAL
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ write32rb (MEMC_BASE + MCATT0_OFFSET), CONFIG_SYS_MCATT0_VAL
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ write32rb (MEMC_BASE + MCATT1_OFFSET), CONFIG_SYS_MCATT1_VAL
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ write32rb (MEMC_BASE + MCIO0_OFFSET), CONFIG_SYS_MCIO0_VAL
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ write32rb (MEMC_BASE + MCIO1_OFFSET), CONFIG_SYS_MCIO1_VAL
+
+ /*
+ * 3) Configure Fly-By DMA register
+ */
+
+ write32rb (MEMC_BASE + FLYCNFG_OFFSET), CONFIG_SYS_FLYCNFG_VAL
+
+ /*
+ * 4) Initialize Timing for Sync Memory (SDCLK0)
+ */
+
+ /*
+ * Before accessing MDREFR we need a valid DRI field, so we set
+ * this to power on defaults + DRI field.
+ */
+ ldr r5, [r3, #MDREFR_OFFSET]
+ bic r5, r5, #0x0ff
+ bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */
+
+ ldr r4, =CONFIG_SYS_MDREFR_VAL
+ mov r6, r4
+ lsl r4, #20
+ lsr r4, #20 /* Get a valid DRI field */
+
+ orr r5, r5, r4 /* MDREFR user config with correct DRI */
+
+ orr r5, #MDREFR_K0RUN
+ orr r5, #MDREFR_SLFRSH
+ bic r5, #MDREFR_APD
+ bic r5, #MDREFR_E1PIN
+
+ str r5, [r3, #MDREFR_OFFSET]
+ ldr r4, [r3, #MDREFR_OFFSET]
+
+ /*
+ * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
+ */
+
+ /* Initialize SXCNFG register. Assert the enable bits.
+ *
+ * Write SXMRS to cause an MRS command to all enabled banks of
+ * synchronous static memory. Note that SXLCR need not be written
+ * at this time.
+ */
+ write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL
+
+ /*
+ * 6) Initialize SDRAM
+ */
+
+ bic r6, #MDREFR_SLFRSH
+ str r6, [r3, #MDREFR_OFFSET]
+ ldr r4, [r3, #MDREFR_OFFSET]
+
+ orr r6, #MDREFR_E1PIN
+ str r6, [r3, #MDREFR_OFFSET]
+ ldr r4, [r3, #MDREFR_OFFSET]
+
+ /*
+ * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
+ * but not enable each SDRAM partition pair.
+ */
+
+ /* Fetch platform value of MDCNFG */
+ ldr r4, =CONFIG_SYS_MDCNFG_VAL
+ /* Disable all sdram banks */
+ bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
+ bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
+ /* Write initial value of MDCNFG, w/o enabling sdram banks */
+ str r4, [r3, #MDCNFG_OFFSET]
+ ldr r4, [r3, #MDCNFG_OFFSET]
+
+ /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
+ pxa_wait_ticks 0x300
+
+ /*
+ * 8) Trigger a number (usually 8) refresh cycles by attempting
+ * non-burst read or write accesses to disabled SDRAM, as commonly
+ * specified in the power up sequence documented in SDRAM data
+ * sheets. The address(es) used for this purpose must not be
+ * cacheable.
+ */
+
+ ldr r4, =CONFIG_SYS_DRAM_BASE
+.rept 9
+ str r5, [r4]
+.endr
+
+ /*
+ * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
+ */
+
+ ldr r5, =CONFIG_SYS_MDCNFG_VAL
+ ldr r4, =(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3)
+ and r5, r5, r4
+ ldr r4, [r3, #MDCNFG_OFFSET]
+ orr r4, r4, r5
+ str r4, [r3, #MDCNFG_OFFSET]
+ ldr r4, [r3, #MDCNFG_OFFSET]
+
+ /*
+ * 10) Write MDMRS.
+ */
+
+ ldr r4, =CONFIG_SYS_MDMRS_VAL
+ str r4, [r3, #MDMRS_OFFSET]
+ ldr r4, [r3, #MDMRS_OFFSET]
+
+ /*
+ * 11) Enable APD
+ */
+
+ ldr r4, [r3, #MDREFR_OFFSET]
+ and r6, r6, #MDREFR_APD
+ orr r4, r4, r6
+ str r4, [r3, #MDREFR_OFFSET]
+ ldr r4, [r3, #MDREFR_OFFSET]
+.endm
+
+/*
+ * This macro tests if the CPU woke up from sleep and eventually resumes
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro pxa_wakeup
+ ldr r4, =RCSR
+ ldr r5, [r4]
+ and r5, r5, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+ str r5, [r4]
+ teq r5, #RCSR_SMR
+
+ bne pxa_wakeup_exit
+
+ ldr r4, =PSSR
+ mov r5, #PSSR_PH
+ str r5, [r4]
+
+ ldr r4, =PSPR
+ ldr pc, [r4]
+pxa_wakeup_exit:
+.endm
+
+/*
+ * This macro disables all interupts on PXA2xx/PXA3xx CPU
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro pxa_intr_setup
+ write32 ICLR, 0
+ write32 ICMR, 0
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ write32 ICLR2, 0
+ write32 ICMR2, 0
+#endif
+.endm
+
+/*
+ * This macro configures clock on PXA2xx/PXA3xx CPU
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro pxa_clock_setup
+ /* Disable the peripheral clocks, and set the core clock frequency */
+
+ /* Turn Off ALL on-chip peripheral clocks for re-configuration */
+ write32 CKEN, CONFIG_SYS_CKEN
+
+ /* Write CCCR */
+ write32 CCCR, CONFIG_SYS_CCCR
+
+#ifdef CONFIG_RTC
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+ write32 OSCC, #OSCC_OON
+ ldr r4, =OSCC
+
+ /* Spin here until OSCC.OOK get set, meaning the PLL has settled. */
+2:
+ ldr r5, [r4]
+ ands r5, r5, #1
+ beq 2b
+#endif
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_PXA_MACRO_H__ */
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h
index cd7b7f9..d442fb0 100644
--- a/arch/arm/include/asm/arch-pxa/pxa-regs.h
+++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h
@@ -1132,10 +1132,18 @@ typedef void (*ExcpHndlr) (void) ;
#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
-#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
+#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1 Control Register */
#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
+#define PWM_CTRL2 __REG(0x40B00010) /* PWM 2 Control Register */
+#define PWM_PWDUTY2 __REG(0x40B00014) /* PWM 2 Duty Cycle Register */
+#define PWM_PERVAL2 __REG(0x40B00018) /* PWM 2 Period Control Register */
+
+#define PWM_CTRL3 __REG(0x40C00010) /* PWM 3 Control Register */
+#define PWM_PWDUTY3 __REG(0x40C00014) /* PWM 3 Duty Cycle Register */
+#define PWM_PERVAL3 __REG(0x40C00018) /* PWM 3 Period Control Register */
+
/*
* Interrupt Controller
*/