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-rw-r--r--arch/arm/cpu/armv7/zynq/cpu.c13
-rw-r--r--arch/arm/cpu/armv7/zynq/ddrc.c5
-rw-r--r--arch/arm/cpu/armv7/zynq/slcr.c87
-rw-r--r--arch/arm/cpu/armv7/zynq/spl.c15
-rw-r--r--arch/arm/dts/zynq-7000.dtsi194
-rw-r--r--arch/arm/dts/zynq-microzed.dts9
-rw-r--r--arch/arm/dts/zynq-zc702.dts9
-rw-r--r--arch/arm/dts/zynq-zc706.dts9
-rw-r--r--arch/arm/dts/zynq-zc770-xm010.dts9
-rw-r--r--arch/arm/dts/zynq-zc770-xm012.dts9
-rw-r--r--arch/arm/dts/zynq-zc770-xm013.dts9
-rw-r--r--arch/arm/dts/zynq-zed.dts9
-rw-r--r--arch/arm/include/asm/arch-tegra/usb.h2
-rw-r--r--arch/arm/include/asm/arch-zynq/hardware.h13
-rw-r--r--arch/arm/include/asm/arch-zynq/sys_proto.h2
15 files changed, 385 insertions, 9 deletions
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 7626b5c..816d0c5 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -14,6 +14,9 @@ void lowlevel_init(void)
{
}
+#define ZYNQ_SILICON_VER_MASK 0xF0000000
+#define ZYNQ_SILICON_VER_SHIFT 28
+
int arch_cpu_init(void)
{
zynq_slcr_unlock();
@@ -42,6 +45,16 @@ int arch_cpu_init(void)
return 0;
}
+unsigned int zynq_get_silicon_version(void)
+{
+ unsigned int ver;
+
+ ver = (readl(&devcfg_base->mctrl) &
+ ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT;
+
+ return ver;
+}
+
void reset_cpu(ulong addr)
{
zynq_slcr_cpu_reset();
diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c
index ba6a6ae..e0ed3bf 100644
--- a/arch/arm/cpu/armv7/zynq/ddrc.c
+++ b/arch/arm/cpu/armv7/zynq/ddrc.c
@@ -40,11 +40,8 @@ void zynq_ddrc_init(void)
* first stage bootloader. To get ECC to work all memory has
* been initialized by writing any value.
*/
- memset(0, 0, 1 * 1024 * 1024);
+ memset((void *)0, 0, 1 * 1024 * 1024);
} else {
puts("Memory: ECC disabled\n");
}
-
- if (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)
- gd->ram_size /= 2;
}
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index d7c1882..934ccc3 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -8,26 +8,75 @@
#include <asm/io.h>
#include <malloc.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
#include <asm/arch/clk.h>
#define SLCR_LOCK_MAGIC 0x767B
#define SLCR_UNLOCK_MAGIC 0xDF0D
+#define SLCR_USB_L1_SEL 0x04
+
#define SLCR_IDCODE_MASK 0x1F000
#define SLCR_IDCODE_SHIFT 12
+/*
+ * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
+ *
+ * @peri_name: Name of the peripheral for checking MIO status
+ * @get_pins: Pointer to array of get pin for this peripheral
+ * @num_pins: Number of pins for this peripheral
+ * @mask: Mask value
+ * @check_val: Required check value to get the status of periph
+ */
+struct zynq_slcr_mio_get_status {
+ const char *peri_name;
+ const int *get_pins;
+ int num_pins;
+ u32 mask;
+ u32 check_val;
+};
+
+static const int usb0_pins[] = {
+ 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
+};
+
+static const int usb1_pins[] = {
+ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
+};
+
+static const struct zynq_slcr_mio_get_status mio_periphs[] = {
+ {
+ "usb0",
+ usb0_pins,
+ ARRAY_SIZE(usb0_pins),
+ SLCR_USB_L1_SEL,
+ SLCR_USB_L1_SEL,
+ },
+ {
+ "usb1",
+ usb1_pins,
+ ARRAY_SIZE(usb1_pins),
+ SLCR_USB_L1_SEL,
+ SLCR_USB_L1_SEL,
+ },
+};
+
static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
void zynq_slcr_lock(void)
{
- if (!slcr_lock)
+ if (!slcr_lock) {
writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
+ slcr_lock = 1;
+ }
}
void zynq_slcr_unlock(void)
{
- if (slcr_lock)
+ if (slcr_lock) {
writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
+ slcr_lock = 0;
+ }
}
/* Reset the entire system */
@@ -82,7 +131,7 @@ void zynq_slcr_devcfg_disable(void)
{
zynq_slcr_unlock();
- /* Disable AXI interface */
+ /* Disable AXI interface by asserting FPGA resets */
writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
/* Set Level Shifters DT618760 */
@@ -98,7 +147,7 @@ void zynq_slcr_devcfg_enable(void)
/* Set Level Shifters DT618760 */
writel(0xF, &slcr_base->lvl_shftr_en);
- /* Disable AXI interface */
+ /* Enable AXI interface by de-asserting FPGA resets */
writel(0x0, &slcr_base->fpga_rst_ctrl);
zynq_slcr_lock();
@@ -115,3 +164,33 @@ u32 zynq_slcr_get_idcode(void)
return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
SLCR_IDCODE_SHIFT;
}
+
+/*
+ * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
+ *
+ * @periph: Name of the peripheral
+ *
+ * Returns count to indicate the number of pins configured for the
+ * given @periph.
+ */
+int zynq_slcr_get_mio_pin_status(const char *periph)
+{
+ const struct zynq_slcr_mio_get_status *mio_ptr;
+ int val, i, j;
+ int mio = 0;
+
+ for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
+ if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
+ mio_ptr = &mio_periphs[i];
+ for (j = 0; j < mio_ptr->num_pins; j++) {
+ val = readl(&slcr_base->mio_pin
+ [mio_ptr->get_pins[j]]);
+ if ((val & mio_ptr->mask) == mio_ptr->check_val)
+ mio++;
+ }
+ break;
+ }
+ }
+
+ return mio;
+}
diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c
index fcad762..d73e5cb 100644
--- a/arch/arm/cpu/armv7/zynq/spl.c
+++ b/arch/arm/cpu/armv7/zynq/spl.c
@@ -28,6 +28,13 @@ void board_init_f(ulong dummy)
board_init_r(NULL, 0);
}
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+ board_init();
+}
+#endif
+
u32 spl_boot_device(void)
{
u32 mode;
@@ -67,3 +74,11 @@ int spl_start_uboot(void)
return 0;
}
#endif
+
+__weak void ps7_init(void)
+{
+ /*
+ * This function is overridden by the one in
+ * board/xilinx/zynq/ps7_init.c, if it exists.
+ */
+}
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index f20b8bd..2d076f1 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -10,4 +10,198 @@
/ {
compatible = "xlnx,zynq-7000";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&clkc 3>;
+ clock-latency = <1000>;
+ operating-points = <
+ /* kHz uV */
+ 666667 1000000
+ 333334 1000000
+ 222223 1000000
+ >;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <1>;
+ clocks = <&clkc 3>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 5 4>, <0 6 4>;
+ interrupt-parent = <&intc>;
+ reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
+ };
+
+ amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+
+ i2c0: zynq-i2c@e0004000 {
+ compatible = "cdns,i2c-r1p10";
+ status = "disabled";
+ clocks = <&clkc 38>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 25 4>;
+ reg = <0xe0004000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: zynq-i2c@e0005000 {
+ compatible = "cdns,i2c-r1p10";
+ status = "disabled";
+ clocks = <&clkc 39>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 48 4>;
+ reg = <0xe0005000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ intc: interrupt-controller@f8f01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ interrupt-controller;
+ reg = <0xF8F01000 0x1000>,
+ <0xF8F00100 0x100>;
+ };
+
+ L2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0xF8F02000 0x1000>;
+ arm,data-latency = <3 2 2>;
+ arm,tag-latency = <2 2 2>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ uart0: uart@e0000000 {
+ compatible = "xlnx,xuartps";
+ status = "disabled";
+ clocks = <&clkc 23>, <&clkc 40>;
+ clock-names = "ref_clk", "aper_clk";
+ reg = <0xE0000000 0x1000>;
+ interrupts = <0 27 4>;
+ };
+
+ uart1: uart@e0001000 {
+ compatible = "xlnx,xuartps";
+ status = "disabled";
+ clocks = <&clkc 24>, <&clkc 41>;
+ clock-names = "ref_clk", "aper_clk";
+ reg = <0xE0001000 0x1000>;
+ interrupts = <0 50 4>;
+ };
+
+ gem0: ethernet@e000b000 {
+ compatible = "cdns,gem";
+ reg = <0xe000b000 0x4000>;
+ status = "disabled";
+ interrupts = <0 22 4>;
+ clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
+ clock-names = "pclk", "hclk", "tx_clk";
+ };
+
+ gem1: ethernet@e000c000 {
+ compatible = "cdns,gem";
+ reg = <0xe000c000 0x4000>;
+ status = "disabled";
+ interrupts = <0 45 4>;
+ clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
+ clock-names = "pclk", "hclk", "tx_clk";
+ };
+
+ sdhci0: ps7-sdhci@e0100000 {
+ compatible = "arasan,sdhci-8.9a";
+ status = "disabled";
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clkc 21>, <&clkc 32>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 24 4>;
+ reg = <0xe0100000 0x1000>;
+ } ;
+
+ sdhci1: ps7-sdhci@e0101000 {
+ compatible = "arasan,sdhci-8.9a";
+ status = "disabled";
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clkc 22>, <&clkc 33>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 47 4>;
+ reg = <0xe0101000 0x1000>;
+ } ;
+
+ slcr: slcr@f8000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynq-slcr", "syscon";
+ reg = <0xF8000000 0x1000>;
+ ranges;
+ clkc: clkc@100 {
+ #clock-cells = <1>;
+ compatible = "xlnx,ps7-clkc";
+ ps-clk-frequency = <33333333>;
+ fclk-enable = <0>;
+ clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+ "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+ "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+ "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+ "dma", "usb0_aper", "usb1_aper", "gem0_aper",
+ "gem1_aper", "sdio0_aper", "sdio1_aper",
+ "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+ "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+ "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+ "dbg_trc", "dbg_apb";
+ reg = <0x100 0x100>;
+ };
+ };
+
+ global_timer: timer@f8f00200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0xf8f00200 0x20>;
+ interrupts = <1 11 0x301>;
+ interrupt-parent = <&intc>;
+ clocks = <&clkc 4>;
+ };
+
+ ttc0: ttc0@f8001000 {
+ interrupt-parent = <&intc>;
+ interrupts = < 0 10 4 0 11 4 0 12 4 >;
+ compatible = "cdns,ttc";
+ clocks = <&clkc 6>;
+ reg = <0xF8001000 0x1000>;
+ };
+
+ ttc1: ttc1@f8002000 {
+ interrupt-parent = <&intc>;
+ interrupts = < 0 37 4 0 38 4 0 39 4 >;
+ compatible = "cdns,ttc";
+ clocks = <&clkc 6>;
+ reg = <0xF8002000 0x1000>;
+ };
+ scutimer: scutimer@f8f00600 {
+ interrupt-parent = <&intc>;
+ interrupts = < 1 13 0x301 >;
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = < 0xf8f00600 0x20 >;
+ clocks = <&clkc 4>;
+ } ;
+ };
};
diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts
index 6da71c1..c373a2c 100644
--- a/arch/arm/dts/zynq-microzed.dts
+++ b/arch/arm/dts/zynq-microzed.dts
@@ -11,4 +11,13 @@
/ {
model = "Zynq MicroZED Board";
compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x40000000>;
+ };
};
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 667dc28..4fa0b00 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -11,4 +11,13 @@
/ {
model = "Zynq ZC702 Board";
compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x40000000>;
+ };
};
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index 526fc88..2a80195 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -11,4 +11,13 @@
/ {
model = "Zynq ZC706 Board";
compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x40000000>;
+ };
};
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts
index 8b542a1..5e661749 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -11,4 +11,13 @@
/ {
model = "Zynq ZC770 XM010 Board";
compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x40000000>;
+ };
};
diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts
index 0379a07..127a661 100644
--- a/arch/arm/dts/zynq-zc770-xm012.dts
+++ b/arch/arm/dts/zynq-zc770-xm012.dts
@@ -11,4 +11,13 @@
/ {
model = "Zynq ZC770 XM012 Board";
compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x40000000>;
+ };
};
diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts
index a4f9e05..c61c7e7 100644
--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -11,4 +11,13 @@
/ {
model = "Zynq ZC770 XM013 Board";
compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x40000000>;
+ };
};
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index 91a5deb..70cc8a6 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -11,4 +11,13 @@
/ {
model = "Zynq ZED Board";
compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x20000000>;
+ };
};
diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h
index ceb7bcd..c817088 100644
--- a/arch/arm/include/asm/arch-tegra/usb.h
+++ b/arch/arm/include/asm/arch-tegra/usb.h
@@ -349,6 +349,8 @@ struct usb_ctlr {
/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
#define VBUS_VLD_STS (1 << 26)
+#define VBUS_B_SESS_VLD_SW_VALUE (1 << 12)
+#define VBUS_B_SESS_VLD_SW_EN (1 << 11)
/* Setup USB on the board */
int usb_process_devicetree(const void *blob);
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index 39184da..2aede0c 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -22,9 +22,12 @@
#define ZYNQ_SPI_BASEADDR0 0xE0006000
#define ZYNQ_SPI_BASEADDR1 0xE0007000
#define ZYNQ_DDRC_BASEADDR 0xF8006000
+#define ZYNQ_EFUSE_BASEADDR 0xF800D000
+#define ZYNQ_USB_BASEADDR0 0xE0002000
+#define ZYNQ_USB_BASEADDR1 0xE0003000
/* Bootmode setting values */
-#define ZYNQ_BM_MASK 0xF
+#define ZYNQ_BM_MASK 0x7
#define ZYNQ_BM_NOR 0x2
#define ZYNQ_BM_SD 0x5
#define ZYNQ_BM_JTAG 0x0
@@ -130,4 +133,12 @@ struct ddrc_regs {
};
#define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
+struct efuse_reg {
+ u32 reserved1[4];
+ u32 status;
+ u32 reserved2[3];
+};
+
+#define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR)
+
#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index a68e1b3..53c30ec 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -15,7 +15,9 @@ extern void zynq_slcr_devcfg_disable(void);
extern void zynq_slcr_devcfg_enable(void);
extern u32 zynq_slcr_get_boot_mode(void);
extern u32 zynq_slcr_get_idcode(void);
+extern int zynq_slcr_get_mio_pin_status(const char *periph);
extern void zynq_ddrc_init(void);
+extern unsigned int zynq_get_silicon_version(void);
/* Driver extern functions */
extern int zynq_sdhci_init(u32 regbase);
generated by cgit v1.1 at 2024-12-18 20:40:40 +0000