diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 7 | ||||
-rw-r--r-- | arch/arm/include/asm/imx-common/regs-bch.h | 10 |
2 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 2ea8ca3..69b8487 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -30,6 +30,7 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/dma.h> #include <stdbool.h> struct scu_regs { @@ -151,6 +152,12 @@ int arch_cpu_init(void) set_vddsoc(1200); /* Set VDDSOC to 1.2V */ imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ + +#ifdef CONFIG_APBH_DMA + /* Start APBH DMA */ + mxs_dma_init(); +#endif + return 0; } diff --git a/arch/arm/include/asm/imx-common/regs-bch.h b/arch/arm/include/asm/imx-common/regs-bch.h index 3a73de4..dbe7ac8 100644 --- a/arch/arm/include/asm/imx-common/regs-bch.h +++ b/arch/arm/include/asm/imx-common/regs-bch.h @@ -136,8 +136,13 @@ struct mxs_bch_regs { #define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 #define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16) #define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16 +#if defined(CONFIG_MX6) +#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11) +#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11 +#else #define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12) #define BCH_FLASHLAYOUT0_ECC0_OFFSET 12 +#endif #define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12) @@ -161,8 +166,13 @@ struct mxs_bch_regs { #define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) #define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16 +#if defined(CONFIG_MX6) +#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11) +#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11 +#else #define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12) #define BCH_FLASHLAYOUT1_ECCN_OFFSET 12 +#endif #define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12) |