diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/io.h | 7 | ||||
| -rw-r--r-- | arch/mips/dts/pic32mzda.dtsi | 12 | ||||
| -rw-r--r-- | arch/mips/dts/pic32mzda_sk.dts | 4 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 9 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 30 |
5 files changed, 55 insertions, 7 deletions
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 75773bd..9d185a6 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -284,6 +284,13 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define insw_p(port,to,len) insw(port,to,len) #define insl_p(port,to,len) insl(port,to,len) +#define writesl(a, d, s) __raw_writesl((unsigned long)a, d, s) +#define readsl(a, d, s) __raw_readsl((unsigned long)a, d, s) +#define writesw(a, d, s) __raw_writesw((unsigned long)a, d, s) +#define readsw(a, d, s) __raw_readsw((unsigned long)a, d, s) +#define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s) +#define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s) + /* * ioremap and friends. * diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi index 7d180d9..8a554f9 100644 --- a/arch/mips/dts/pic32mzda.dtsi +++ b/arch/mips/dts/pic32mzda.dtsi @@ -171,4 +171,16 @@ #address-cells = <1>; #size-cells = <0>; }; + + usb: musb@1f8e3000 { + compatible = "microchip,pic32mzda-usb"; + reg = <0x1f8e3000 0x1000>, + <0x1f884000 0x1000>; + reg-names = "mc", "control"; + interrupts = <132 IRQ_TYPE_EDGE_RISING>, + <133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock PB5CLK>; + clock-names = "usb_clk"; + status = "disabled"; + }; }; diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts index e5ce0bd..0a7847e 100644 --- a/arch/mips/dts/pic32mzda_sk.dts +++ b/arch/mips/dts/pic32mzda_sk.dts @@ -52,4 +52,8 @@ ethernet_phy: lan8740_phy@0 { reg = <0>; }; +}; + +&usb { + status = "okay"; };
\ No newline at end of file diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 235a635..aa519b0 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -82,7 +82,6 @@ void setup_ifc(void) void cpu_init_early_f(void *fdt) { u32 mas0, mas1, mas2, mas3, mas7; - int i; #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif @@ -90,17 +89,13 @@ void cpu_init_early_f(void *fdt) ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; u32 *dst, *src; void (*setup_ifc_sram)(void); + int i; #endif /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - /* - * Clear initial global data - * we don't use memset so we can share this code with NAND_SPL - */ - for (i = 0; i < sizeof(gd_t); i++) - ((char *)gd)[i] = 0; + /* gd area was zeroed during startup */ #ifdef CONFIG_QEMU_E500 /* diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index d867e2a..82a151a 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1152,6 +1152,36 @@ _start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ + +#ifdef CONFIG_SYS_MALLOC_F_LEN + +#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE +#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM." +#endif + + /* Leave 16+ byte for back chain termination and NULL return address */ + subi r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf) +#endif + + /* End of RAM */ + lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h + ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l + + li r0,0 + +1: subi r4,r4,4 + stw r0,0(r4) + cmplw r4,r3 + bne 1b + +#ifdef CONFIG_SYS_MALLOC_F_LEN + lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h + ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l + + addi r3,r3,16 /* Pre-relocation malloc area */ + stw r3,GD_MALLOC_BASE(r4) + subi r3,r3,16 +#endif li r0,0 stw r0,0(r3) /* Terminate Back Chain */ stw r0,+4(r3) /* NULL return address. */ |