diff options
Diffstat (limited to 'arch')
29 files changed, 169 insertions, 152 deletions
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index f1dc6c8..4c5696b 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -118,21 +118,21 @@ config SYS_DCACHE_OFF choice prompt "Target select" - default TARGET_AXS101 + default TARGET_AXS10X config TARGET_TB100 bool "Support tb100" -config TARGET_ARCANGEL4 - bool "Support arcangel4" +config TARGET_NSIM + bool "Support standalone nSIM & Free nSIM" -config TARGET_AXS101 - bool "Support axs101" +config TARGET_AXS10X + bool "Support Synopsys Designware SDP board (AXS101 & AXS103)" endchoice source "board/abilis/tb100/Kconfig" source "board/synopsys/Kconfig" -source "board/synopsys/axs101/Kconfig" +source "board/synopsys/axs10x/Kconfig" endmenu diff --git a/arch/arc/cpu/arcv2/ivt.S b/arch/arc/cpu/arcv2/ivt.S index d110b5b..7924375 100644 --- a/arch/arc/cpu/arcv2/ivt.S +++ b/arch/arc/cpu/arcv2/ivt.S @@ -7,21 +7,26 @@ .section .ivt, "a",@progbits .align 4 /* Critical system events */ -.word _start /* 0 - 0x000 */ -.word memory_error /* 1 - 0x008 */ -.word instruction_error /* 2 - 0x010 */ +.word _start /* 0x00 - Reset */ +.word memory_error /* 0x01 - Memory Error */ +.word instruction_error /* 0x02 - Instruction Error */ /* Exceptions */ -.word EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */ -.word EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */ -.word EV_TLBMissD /* 0x110, Data TLB miss (0x22) */ -.word EV_TLBProtV /* 0x118, Protection Violation (0x23) - or Misaligned Access */ -.word EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */ -.word EV_Trap /* 0x128, Trap exception (0x25) */ -.word EV_Extension /* 0x130, Extn Intruction Excp (0x26) */ +.word EV_MachineCheck /* 0x03 - Fatal Machine check */ +.word EV_TLBMissI /* 0x04 - Intruction TLB miss */ +.word EV_TLBMissD /* 0x05 - Data TLB miss */ +.word EV_TLBProtV /* 0x06 - Protection Violation or Misaligned Access */ +.word EV_PrivilegeV /* 0x07 - Privilege Violation */ +.word EV_SWI /* 0x08 - Software Interrupt */ +.word EV_Trap /* 0x09 - Trap */ +.word EV_Extension /* 0x0A - Extension Intruction Exception */ +.word EV_DivZero /* 0x0B - Division by Zero */ +.word EV_DCError /* 0x0C - Data cache consistency error */ +.word EV_Maligned /* 0x0D - Misaligned data access */ +.word 0 /* 0x0E - Unused */ +.word 0 /* 0x0F - Unused */ /* Device interrupts */ -.rept 29 - j interrupt_handler /* 3:31 - 0x018:0xF8 */ +.rept 240 +.word interrupt_handler /* 0x10 - 0xFF */ .endr diff --git a/arch/arc/cpu/u-boot.lds b/arch/arc/cpu/u-boot.lds index 693df74..d3d0a53 100644 --- a/arch/arc/cpu/u-boot.lds +++ b/arch/arc/cpu/u-boot.lds @@ -4,38 +4,29 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <config.h> + OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc") OUTPUT_ARCH(arc) ENTRY(_start) SECTIONS { - . = ALIGN(4); + . = CONFIG_SYS_TEXT_BASE; + __image_copy_start = .; + __text_start = .; .text : { - *(.__text_start) - *(.__image_copy_start) arch/arc/lib/start.o (.text*) *(.text*) } - - . = ALIGN(4); - .text_end : - { - *(.__text_end) - } + __text_end = .; . = ALIGN(1024); - .ivt_start : { - *(.__ivt_start) - } - + __ivt_start = .; .ivt : { *(.ivt) } - - .ivt_end : { - *(.__ivt_end) - } + __ivt_end = .; . = ALIGN(4); .rodata : { @@ -53,34 +44,20 @@ SECTIONS } . = ALIGN(4); - .rel_dyn_start : { - *(.__rel_dyn_start) - } - + __rel_dyn_start = .; .rela.dyn : { *(.rela.dyn) } - - .rel_dyn_end : { - *(.__rel_dyn_end) - } + __rel_dyn_end = .; . = ALIGN(4); - .bss_start : { - *(.__bss_start); - } - + __bss_start = .; .bss : { *(.bss*) } - - .bss_end : { - *(.__bss_end); - } + __bss_end = .; . = ALIGN(4); - .image_copy_end : { - *(.__image_copy_end) - *(.__init_end) - } + __image_copy_end = .; + __init_end = .; } diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile index d4772ec..1d94c08 100644 --- a/arch/arc/dts/Makefile +++ b/arch/arc/dts/Makefile @@ -2,8 +2,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -dtb-$(CONFIG_TARGET_AXS101) += axs10x.dtb -dtb-$(CONFIG_TARGET_ARCANGEL4) += arcangel4.dtb +dtb-$(CONFIG_TARGET_AXS10X) += axs10x.dtb +dtb-$(CONFIG_TARGET_NSIM) += nsim.dtb dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb targets += $(dtb-y) diff --git a/arch/arc/dts/arcangel4.dts b/arch/arc/dts/nsim.dts index bfcb9d8..69e16c2 100644 --- a/arch/arc/dts/arcangel4.dts +++ b/arch/arc/dts/nsim.dts @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Synopsys, Inc. (www.synopsys.com) + * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com) * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h index b8f2a85..00f1217 100644 --- a/arch/arc/include/asm/sections.h +++ b/arch/arc/include/asm/sections.h @@ -9,9 +9,7 @@ #include <asm-generic/sections.h> -extern ulong __text_end; extern ulong __ivt_start; extern ulong __ivt_end; -extern ulong __image_copy_start; #endif /* __ASM_ARC_SECTIONS_H */ diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile index e592802..eb62b3c 100644 --- a/arch/arc/lib/Makefile +++ b/arch/arc/lib/Makefile @@ -9,7 +9,6 @@ head-y := start.o obj-y += cache.o obj-y += cpu.o obj-y += interrupts.o -obj-y += sections.o obj-y += relocate.o obj-y += strchr-700.o obj-y += strcmp.o diff --git a/arch/arc/lib/interrupts.c b/arch/arc/lib/interrupts.c index d7cab3b..ee638d5 100644 --- a/arch/arc/lib/interrupts.c +++ b/arch/arc/lib/interrupts.c @@ -141,3 +141,29 @@ void do_extension(struct pt_regs *regs) printf("Extension instruction exception\n"); bad_mode(regs); } + +#ifdef CONFIG_ISA_ARCV2 +void do_swi(struct pt_regs *regs) +{ + printf("Software Interrupt exception\n"); + bad_mode(regs); +} + +void do_divzero(unsigned long address, struct pt_regs *regs) +{ + printf("Division by zero exception @ 0x%lx\n", address); + bad_mode(regs); +} + +void do_dcerror(struct pt_regs *regs) +{ + printf("Data cache consistency error exception\n"); + bad_mode(regs); +} + +void do_maligned(unsigned long address, struct pt_regs *regs) +{ + printf("Misaligned data access exception @ 0x%lx\n", address); + bad_mode(regs); +} +#endif diff --git a/arch/arc/lib/ints_low.S b/arch/arc/lib/ints_low.S index 161cf37..e377884 100644 --- a/arch/arc/lib/ints_low.S +++ b/arch/arc/lib/ints_low.S @@ -149,3 +149,31 @@ ENTRY(EV_Extension) mov %r0, %sp j do_extension ENDPROC(EV_Extension) + +#ifdef CONFIG_ISA_ARCV2 +ENTRY(EV_SWI) + SAVE_ALL_SYS + mov %r0, %sp + j do_swi +ENDPROC(EV_SWI) + +ENTRY(EV_DivZero) + SAVE_ALL_SYS + SAVE_EXCEPTION_SOURCE + mov %r1, %sp + j do_divzero +ENDPROC(EV_DivZero) + +ENTRY(EV_DCError) + SAVE_ALL_SYS + mov %r0, %sp + j do_dcerror +ENDPROC(EV_DCError) + +ENTRY(EV_Maligned) + SAVE_ALL_SYS + SAVE_EXCEPTION_SOURCE + mov %r1, %sp + j do_maligned +ENDPROC(EV_Maligned) +#endif diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c index 5c2c2d1..7802f40 100644 --- a/arch/arc/lib/relocate.c +++ b/arch/arc/lib/relocate.c @@ -6,7 +6,10 @@ #include <common.h> #include <elf.h> -#include <asm/sections.h> +#include <asm-generic/sections.h> + +extern ulong __image_copy_start; +extern ulong __ivt_end; DECLARE_GLOBAL_DATA_PTR; @@ -37,6 +40,9 @@ int do_elf_reloc_fixups(void) Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start); Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end); + debug("Section .rela.dyn is located at %08x-%08x\n", + (unsigned int)re_src, (unsigned int)re_end); + Elf32_Addr *offset_ptr_rom, *last_offset = NULL; Elf32_Addr *offset_ptr_ram; @@ -52,6 +58,10 @@ int do_elf_reloc_fixups(void) offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom + gd->reloc_off); + debug("Patching value @ %08x (relocated to %08x)\n", + (unsigned int)offset_ptr_rom, + (unsigned int)offset_ptr_ram); + /* * Use "memcpy" because target location might be * 16-bit aligned on ARC so we may need to read diff --git a/arch/arc/lib/sections.c b/arch/arc/lib/sections.c deleted file mode 100644 index a72c694..0000000 --- a/arch/arc/lib/sections.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * For some reason linker sets linker-generated symbols to zero in PIE mode. - * A work-around is substitution of linker-generated symbols with - * compiler-generated symbols which are properly handled by linker in PAE mode. - */ - -char __bss_start[0] __attribute__((section(".__bss_start"))); -char __bss_end[0] __attribute__((section(".__bss_end"))); -char __image_copy_start[0] __attribute__((section(".__image_copy_start"))); -char __image_copy_end[0] __attribute__((section(".__image_copy_end"))); -char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start"))); -char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end"))); -char __text_start[0] __attribute__((section(".__text_start"))); -char __text_end[0] __attribute__((section(".__text_end"))); -char __init_end[0] __attribute__((section(".__init_end"))); -char __ivt_start[0] __attribute__((section(".__ivt_start"))); -char __ivt_end[0] __attribute__((section(".__ivt_end"))); diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a0a866e..5ac9401 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -6,6 +6,7 @@ config SYS_ARCH config ARM64 bool + select PHYS_64BIT config DMA_ADDR_T_64BIT bool @@ -553,11 +554,14 @@ config TARGET_MX53SMD config OMAP34XX bool "OMAP34XX SoC" select CPU_V7 + select SUPPORT_SPL + select USE_TINY_PRINTF config OMAP44XX bool "OMAP44XX SoC" select CPU_V7 select SUPPORT_SPL + select USE_TINY_PRINTF config OMAP54XX bool "OMAP54XX SoC" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 6a07cd1..82f2fd0 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -20,6 +20,14 @@ arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, \ $(call cc-option, -march=armv7, -march=armv5)) arch-$(CONFIG_ARM64) =-march=armv8-a +# On Tegra systems we must build SPL for the armv4 core on the device +# but otherwise we can use the value in CONFIG_SYS_ARM_ARCH +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy) +arch-y += -D__LINUX_ARM_ARCH__=4 +else +arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH) +endif + # Evaluate arch cc-option calls now arch-y := $(arch-y) diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 52f1856..c4bbcc3 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -75,7 +75,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) } /* DSB to make sure the operation is complete */ - DSB; + dsb(); } /* Invalidate TLB */ @@ -88,9 +88,9 @@ static void v7_inval_tlb(void) /* Invalidate entire instruction TLB */ asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); /* Full system DSB - make sure that the invalidation is complete */ - DSB; + dsb(); /* Full system ISB - make sure the instruction stream sees it */ - ISB; + isb(); } void invalidate_dcache_all(void) @@ -194,10 +194,10 @@ void invalidate_icache_all(void) asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); /* Full system DSB - make sure that the invalidation is complete */ - DSB; + dsb(); /* ISB - make sure the instruction stream sees it */ - ISB; + isb(); } #else void invalidate_icache_all(void) diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 85d6436..99a25f9 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -6,55 +6,39 @@ choice config TARGET_AM3517_EVM bool "AM3517 EVM" - select SUPPORT_SPL config TARGET_MT_VENTOUX bool "TeeJet Mt.Ventoux" - select SUPPORT_SPL config TARGET_OMAP3_BEAGLE bool "TI OMAP3 BeagleBoard" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO config TARGET_CM_T35 bool "CompuLab CM-T3530 and CM-T3730 boards" - select SUPPORT_SPL config TARGET_CM_T3517 bool "CompuLab CM-T3517 boards" config TARGET_DEVKIT8000 bool "TimLL OMAP3 Devkit8000" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO config TARGET_OMAP3_EVM bool "TI OMAP3 EVM" - select SUPPORT_SPL - -config TARGET_OMAP3_EVM_QUICK_MMC - bool "TI OMAP3 EVM Quick MMC" - select SUPPORT_SPL - -config TARGET_OMAP3_EVM_QUICK_NAND - bool "TI OMAP3 EVM Quick NAND" - select SUPPORT_SPL config TARGET_OMAP3_IGEP00X0 bool "IGEP" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO config TARGET_OMAP3_OVERO bool "OMAP35xx Gumstix Overo" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO @@ -67,51 +51,42 @@ config TARGET_OMAP3_ZOOM1 config TARGET_AM3517_CRANE bool "am3517_crane" - select SUPPORT_SPL config TARGET_OMAP3_PANDORA bool "OMAP3 Pandora" config TARGET_ECO5PK bool "ECO5PK" - select SUPPORT_SPL config TARGET_TRICORDER bool "Tricorder" - select SUPPORT_SPL config TARGET_MCX bool "MCX" - select SUPPORT_SPL config TARGET_OMAP3_LOGIC bool "OMAP3 Logic" select DM select DM_SERIAL select DM_GPIO - select SUPPORT_SPL config TARGET_NOKIA_RX51 bool "Nokia RX51" config TARGET_TAO3530 bool "TAO3530" - select SUPPORT_SPL config TARGET_TWISTER bool "Twister" - select SUPPORT_SPL config TARGET_OMAP3_CAIRO bool "QUIPOS CAIRO" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO config TARGET_SNIPER bool "LG Optimus Black" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index 4fb5ef9..a8600b1 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -13,6 +13,7 @@ config TARGET_OMAP5_UEVM config TARGET_DRA7XX_EVM bool "TI DRA7XX" select TI_I2C_BOARD_DETECT + select PHYS_64BIT config TARGET_AM57XX_EVM bool "AM57XX" diff --git a/arch/arm/cpu/armv7/psci-common.c b/arch/arm/cpu/armv7/psci-common.c index d14b693..8cb4107 100644 --- a/arch/arm/cpu/armv7/psci-common.c +++ b/arch/arm/cpu/armv7/psci-common.c @@ -29,7 +29,7 @@ static u32 psci_target_pc[CONFIG_ARMV7_PSCI_NR_CPUS] __secure_data = { 0 }; void __secure psci_save_target_pc(int cpu, u32 pc) { psci_target_pc[cpu] = pc; - DSB; + dsb(); } u32 __secure psci_get_target_pc(int cpu) diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index 7ac8406..766b8c7 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -53,16 +53,16 @@ static void __secure __mdelay(u32 ms) u32 reg = ONE_MS * ms; cp15_write_cntp_tval(reg); - ISB; + isb(); cp15_write_cntp_ctl(3); do { - ISB; + isb(); reg = cp15_read_cntp_ctl(); } while (!(reg & BIT(2))); cp15_write_cntp_ctl(0); - ISB; + isb(); } static void __secure clamp_release(u32 __maybe_unused *clamp) @@ -164,7 +164,7 @@ static u32 __secure cp15_read_scr(void) static void __secure cp15_write_scr(u32 scr) { asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr)); - ISB; + isb(); } /* @@ -190,7 +190,7 @@ void __secure __irq psci_fiq_enter(void) /* End of interrupt */ writel(reg, GICC_BASE + GICC_EOIR); - DSB; + dsb(); /* Get CPU number */ cpu = (reg >> 10) & 0x7; @@ -242,7 +242,7 @@ void __secure psci_cpu_off(void) /* Ask CPU0 via SGI15 to pull the rug... */ writel(BIT(16) | 15, GICD_BASE + GICD_SGIR); - DSB; + dsb(); /* Wait to be turned off */ while (1) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index ac909a1..cd3f6c1 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -380,6 +380,7 @@ void setup_pgtables(void) static void setup_all_pgtables(void) { u64 tlb_addr = gd->arch.tlb_addr; + u64 tlb_size = gd->arch.tlb_size; /* Reset the fill ptr */ gd->arch.tlb_fillptr = tlb_addr; @@ -388,10 +389,13 @@ static void setup_all_pgtables(void) setup_pgtables(); /* Create emergency page tables */ + gd->arch.tlb_size -= (uintptr_t)gd->arch.tlb_fillptr - + (uintptr_t)gd->arch.tlb_addr; gd->arch.tlb_addr = gd->arch.tlb_fillptr; setup_pgtables(); gd->arch.tlb_emerg = gd->arch.tlb_addr; gd->arch.tlb_addr = tlb_addr; + gd->arch.tlb_size = tlb_size; } /* to activate the MMU we need to set up virtual memory */ diff --git a/arch/arm/include/asm/barriers.h b/arch/arm/include/asm/barriers.h index 37870f9..04784b7 100644 --- a/arch/arm/include/asm/barriers.h +++ b/arch/arm/include/asm/barriers.h @@ -30,15 +30,22 @@ #endif /* !CONFIG_ARM64 */ -#if defined(__ARM_ARCH_7A__) || defined(CONFIG_ARM64) +#if __LINUX_ARM_ARCH__ >= 7 #define ISB asm volatile ("isb sy" : : : "memory") #define DSB asm volatile ("dsb sy" : : : "memory") #define DMB asm volatile ("dmb sy" : : : "memory") -#else +#elif __LINUX_ARM_ARCH__ == 6 #define ISB CP15ISB #define DSB CP15DSB #define DMB CP15DMB +#else +#define ISB asm volatile ("" : : : "memory") +#define DSB CP15DSB +#define DMB asm volatile ("" : : : "memory") #endif +#define isb() ISB +#define dsb() DSB +#define dmb() DMB #endif /* __ASSEMBLY__ */ #endif /* __BARRIERS_H__ */ diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 435fc45..1ad221a 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_BOOT_RAMDISK_HIGH #ifdef CONFIG_ARM64 -#define CONFIG_PHYS_64BIT #define CONFIG_STATIC_RELA #endif diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 6121f1d..5834f5b 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -25,6 +25,7 @@ #include <linux/types.h> #include <asm/byteorder.h> #include <asm/memory.h> +#include <asm/barriers.h> #if 0 /* XXX###XXX */ #include <asm/arch/hardware.h> #endif /* XXX###XXX */ @@ -136,8 +137,7 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) * TODO: The kernel offers some more advanced versions of barriers, it might * have some advantages to use them instead of the simple one here. */ -#define mb() asm volatile("dsb sy" : : : "memory") -#define dmb() __asm__ __volatile__ ("" : : : "memory") +#define mb() dsb() #define __iormb() dmb() #define __iowmb() dmb() diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 2bdc0be..7b7b867 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -3,6 +3,7 @@ #include <common.h> #include <linux/compiler.h> +#include <asm/barriers.h> #ifdef CONFIG_ARM64 @@ -34,11 +35,6 @@ enum dcache_option { DCACHE_WRITEALLOC = 4 << 2, }; -#define isb() \ - ({asm volatile( \ - "isb" : : : "memory"); \ - }) - #define wfi() \ ({asm volatile( \ "wfi" : : : "memory"); \ @@ -227,8 +223,6 @@ void __noreturn psci_system_reset(bool smc); */ void save_boot_params_ret(void); -#define isb() __asm__ __volatile__ ("" : : : "memory") - #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); #ifdef __ARM_ARCH_7A__ diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 9f71376..a8d1557 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -67,11 +67,6 @@ extra-y += eabi_compat.o endif asflags-y += -DCONFIG_ARM_ASM_UNIFIED -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy) -asflags-y += -D__LINUX_ARM_ARCH__=4 -else -asflags-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH) -endif # some files can only build in ARM or THUMB2, not THUMB1 diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h index 3ffb296..2c94a6b 100644 --- a/arch/arm/mach-exynos/include/mach/system.h +++ b/arch/arm/mach-exynos/include/mach/system.h @@ -38,16 +38,6 @@ struct exynos5_sysreg { #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) /* - * Data Synchronization Barrier acts as a special kind of memory barrier. - * No instruction in program order after this instruction executes until - * this instruction completes. This instruction completes when: - * - All explicit memory accesses before this instruction complete. - * - All Cache, Branch predictor and TLB maintenance operations before - * this instruction complete. - */ -#define dsb() __asm__ __volatile__ ("dsb\n\t" : : ); - -/* * This instruction causes an event to be signaled to all cores * within a multiprocessor system. If SEV is implemented, * WFE must also be implemented. diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c index 20b430f..95143d1 100644 --- a/arch/arm/mach-sunxi/dram_helpers.c +++ b/arch/arm/mach-sunxi/dram_helpers.c @@ -32,7 +32,7 @@ bool mctl_mem_matches(u32 offset) /* Try to write different values to RAM at two addresses */ writel(0, CONFIG_SYS_SDRAM_BASE); writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); - DSB; + dsb(); /* Check if the same value is actually observed when reading back */ return readl(CONFIG_SYS_SDRAM_BASE) == readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index 17c1990..72d82a5 100644 --- a/arch/arm/mach-tegra/tegra20/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -10,7 +10,8 @@ endif # The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. -CFLAGS_warmboot_avp.o += -march=armv4t +CFLAGS_warmboot_avp.o = -march=armv4t -U__LINUX_ARM_ARCH__ \ + -D__LINUX_ARM_ARCH__=4 obj-y += clock.o funcmux.o pinmux.o obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 0b89157..9bcbda0 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -17,6 +17,7 @@ config TARGET_SOCRATES config TARGET_B4860QDS bool "Support B4860QDS" select SUPPORT_SPL + select PHYS_64BIT config TARGET_BSC9131RDB bool "Support BSC9131RDB" @@ -30,18 +31,23 @@ config TARGET_C29XPCIE bool "Support C29XPCIE" select SUPPORT_SPL select SUPPORT_TPL + select PHYS_64BIT config TARGET_P3041DS bool "Support P3041DS" + select PHYS_64BIT config TARGET_P4080DS bool "Support P4080DS" + select PHYS_64BIT config TARGET_P5020DS bool "Support P5020DS" + select PHYS_64BIT config TARGET_P5040DS bool "Support P5040DS" + select PHYS_64BIT config TARGET_MPC8536DS bool "Support MPC8536DS" @@ -96,46 +102,57 @@ config TARGET_P1_TWR config TARGET_P2041RDB bool "Support P2041RDB" + select PHYS_64BIT config TARGET_QEMU_PPCE500 bool "Support qemu-ppce500" + select PHYS_64BIT config TARGET_T102XQDS bool "Support T102xQDS" select SUPPORT_SPL + select PHYS_64BIT config TARGET_T102XRDB bool "Support T102xRDB" select SUPPORT_SPL + select PHYS_64BIT config TARGET_T1040QDS bool "Support T1040QDS" + select PHYS_64BIT config TARGET_T104XRDB bool "Support T104xRDB" select SUPPORT_SPL + select PHYS_64BIT config TARGET_T208XQDS bool "Support T208xQDS" select SUPPORT_SPL + select PHYS_64BIT config TARGET_T208XRDB bool "Support T208xRDB" select SUPPORT_SPL + select PHYS_64BIT config TARGET_T4240QDS bool "Support T4240QDS" select SUPPORT_SPL + select PHYS_64BIT config TARGET_T4240RDB bool "Support T4240RDB" select SUPPORT_SPL + select PHYS_64BIT config TARGET_CONTROLCENTERD bool "Support controlcenterd" config TARGET_KMP204X bool "Support kmp204x" + select PHYS_64BIT config TARGET_XPEDITE520X bool "Support xpedite520x" @@ -151,6 +168,7 @@ config TARGET_UCP1020 config TARGET_CYRUS bool "Support Varisys Cyrus" + select PHYS_64BIT endchoice diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 36af1b9..92a330d 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -30,6 +30,7 @@ config TARGET_CANYONLANDS config TARGET_KATMAI bool "Support katmai" + select PHYS_64BIT config TARGET_KILAUEA bool "Support kilauea" |