diff options
Diffstat (limited to 'arch')
63 files changed, 854 insertions, 114 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6542c38..408e4ff 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -589,36 +589,46 @@ config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" select ARM64 -config TARGET_LS2085A_EMU - bool "Support ls2085a_emu" +config TARGET_LS2080A_EMU + bool "Support ls2080a_emu" select ARM64 select ARMV8_MULTIENTRY + help + Support for Freescale LS2080A_EMU platform + The LS2080A Development System (EMULATOR) is a pre silicon + development platform that supports the QorIQ LS2080A + Layerscape Architecture processor. -config TARGET_LS2085A_SIMU - bool "Support ls2085a_simu" +config TARGET_LS2080A_SIMU + bool "Support ls2080a_simu" select ARM64 select ARMV8_MULTIENTRY + help + Support for Freescale LS2080A_SIMU platform + The LS2080A Development System (QDS) is a pre silicon + development platform that supports the QorIQ LS2080A + Layerscape Architecture processor. -config TARGET_LS2085AQDS - bool "Support ls2085aqds" +config TARGET_LS2080AQDS + bool "Support ls2080aqds" select ARM64 select ARMV8_MULTIENTRY select SUPPORT_SPL help - Support for Freescale LS2085AQDS platform - The LS2085A Development System (QDS) is a high-performance - development platform that supports the QorIQ LS2085A + Support for Freescale LS2080AQDS platform + The LS2080A Development System (QDS) is a high-performance + development platform that supports the QorIQ LS2080A Layerscape Architecture processor. -config TARGET_LS2085ARDB - bool "Support ls2085ardb" +config TARGET_LS2080ARDB + bool "Support ls2080ardb" select ARM64 select ARMV8_MULTIENTRY select SUPPORT_SPL help - Support for Freescale LS2085ARDB platform. - The LS2085A Reference design board (RDB) is a high-performance - development platform that supports the QorIQ LS2085A + Support for Freescale LS2080ARDB platform. + The LS2080A Reference design board (RDB) is a high-performance + development platform that supports the QorIQ LS2080A Layerscape Architecture processor. config TARGET_HIKEY @@ -640,6 +650,14 @@ config TARGET_LS1021ATWR select CPU_V7 select SUPPORT_SPL +config TARGET_LS1043AQDS + bool "Support ls1043aqds" + select ARM64 + select ARMV8_MULTIENTRY + select SUPPORT_SPL + help + Support for Freescale LS1043AQDS platform. + config TARGET_LS1043ARDB bool "Support ls1043ardb" select ARM64 @@ -721,7 +739,7 @@ source "arch/arm/cpu/armv7/rmobile/Kconfig" source "arch/arm/mach-rockchip/Kconfig" -source "arch/arm/cpu/armv7/s5pc1xx/Kconfig" +source "arch/arm/mach-s5pc1xx/Kconfig" source "arch/arm/mach-socfpga/Kconfig" @@ -759,10 +777,11 @@ source "board/compulab/cm_t43/Kconfig" source "board/creative/xfi3/Kconfig" source "board/denx/m28evk/Kconfig" source "board/denx/m53evk/Kconfig" -source "board/freescale/ls2085a/Kconfig" -source "board/freescale/ls2085aqds/Kconfig" -source "board/freescale/ls2085ardb/Kconfig" +source "board/freescale/ls2080a/Kconfig" +source "board/freescale/ls2080aqds/Kconfig" +source "board/freescale/ls2080ardb/Kconfig" source "board/freescale/ls1021aqds/Kconfig" +source "board/freescale/ls1043aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/ls1043ardb/Kconfig" source "board/freescale/mx23evk/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 58f9bbb..18283d1 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -53,6 +53,7 @@ machine-$(CONFIG_ARMADA_XP) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X machine-$(CONFIG_ORION5X) += orion5x +machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_TEGRA) += tegra diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index c8d1422..45f346c 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -49,7 +49,6 @@ obj-$(CONFIG_OMAP34XX) += omap3/ obj-$(CONFIG_OMAP44XX) += omap4/ obj-$(CONFIG_OMAP54XX) += omap5/ obj-$(CONFIG_RMOBILE) += rmobile/ -obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/ obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_VF610) += vf610/ diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index df2e1b7..2215fe9 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -372,3 +372,13 @@ void reset_cpu(ulong addr) */ } } + +void arch_preboot_os(void) +{ + unsigned long ctrl; + + /* Disable PL1 Physical Timer */ + asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl)); + ctrl &= ~ARCH_TIMER_CTRL_ENABLE; + asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl)); +} diff --git a/arch/arm/cpu/armv7/ls102xa/timer.c b/arch/arm/cpu/armv7/ls102xa/timer.c index 11b17b2..e6a32ca 100644 --- a/arch/arm/cpu/armv7/ls102xa/timer.c +++ b/arch/arm/cpu/armv7/ls102xa/timer.c @@ -56,7 +56,8 @@ static inline unsigned long long us_to_tick(unsigned long long usec) int timer_init(void) { struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; - unsigned long ctrl, val, freq; + unsigned long ctrl, freq; + unsigned long long val; /* Enable System Counter */ writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr); diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 1ece6a2..53bac3b 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -13,13 +13,13 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SYS_DCACHE_OFF inline void set_pgtable_section(u64 *page_table, u64 index, u64 section, - u64 memory_type, u64 share) + u64 memory_type, u64 attribute) { u64 value; value = section | PMD_TYPE_SECT | PMD_SECT_AF; value |= PMD_ATTRINDX(memory_type); - value |= share; + value |= attribute; page_table[index] = value; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 6fa08c8..cce7405 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -21,10 +21,14 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o endif endif +ifneq ($(CONFIG_LS2080A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o +endif + ifneq ($(CONFIG_LS2085A),) -obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o -else +obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o +endif + ifneq ($(CONFIG_LS1043A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o endif -endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 index 03e18f6..f9323c1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 @@ -7,7 +7,7 @@ Freescale LayerScape with Chassis Generation 3 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, -for example LS2085A. +for example LS2080A. DDR Layout ============ @@ -152,7 +152,7 @@ u-boot command nand write <rcw image in memory> 0 <size of rcw image> To form the NAND image, build u-boot with NAND config, for example, -ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin. +ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin. The u-boot image should be written to match SRC_ADDR, in above example 0x20000. nand write <u-boot image in memory> 200000 <size of u-boot image> @@ -242,3 +242,84 @@ MMU Translation Tables | 0x81_0000_0000 | | 0x08_0080_0000 | ------------------ ------------------ ... ... + + +DPAA2 commands to manage Management Complex (MC) +------------------------------------------------ +DPAA2 commands has been introduced to manage Management Complex +(MC). These commands are used to start mc, aiop and apply DPL +from u-boot command prompt. + +Please note Management complex Firmware(MC), DPL and DPC are no +more deployed during u-boot boot-sequence. + +Commands: +a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex +b) fsl_mc apply DPL <DPL_addr> - Apply DPL file +c) fsl_mc start aiop <FW_addr> - Start AIOP + +How to use commands :- +1. Command sequence for u-boot ethernet: + a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex + b) DPMAC net-devices are now available for use + + Example- + Assumption: MC firmware, DPL and DPC dtb is already programmed + on NOR flash. + + => fsl_mc start mc 580300000 580800000 + => setenv ethact DPMAC1@xgmii + => ping $serverip + +2. Command sequence for Linux boot: + a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex + b) fsl_mc apply DPL <DPL_addr> - Apply DPL file + c) No DPMAC net-devices are available for use in u-boot + d) boot Linux + + Example- + Assumption: MC firmware, DPL and DPC dtb is already programmed + on NOR flash. + + => fsl_mc start mc 580300000 580800000 + => setenv ethact DPMAC1@xgmii + => tftp a0000000 kernel.itb + => fsl_mc apply dpl 580700000 + => bootm a0000000 + +3. Command sequence for AIOP boot: + a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex + b) fsl_mc start aiop <FW_addr> - Start AIOP + c) fsl_mc apply DPL <DPL_addr> - Apply DPL file + d) No DPMAC net-devices are availabe for use in u-boot + Please note actual AIOP start will happen during DPL parsing of + Management complex + + Example- + Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already + programmed on NOR flash. + + => fsl_mc start mc 580300000 580800000 + => fsl_mc start aiop 0x580900000 + => setenv ethact DPMAC1@xgmii + => fsl_mc apply dpl 580700000 + +Errata A009635 +--------------- +If the core runs at higher than x3 speed of the platform, there is +possiblity about sev instruction to getting missed by other cores. +This is because of SoC Run Control block may not able to sample +the EVENTI(Sev) signals. + +Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to +wake up A57 cores + +Errata workaround uses Env variable "a009635_interval_val". It uses decimal +value. +- Default value of env variable is platform clock (MHz) + +- User can modify default value by updating the env variable + setenv a009635_interval_val 600; saveenv; + It configure platform clock as 600 MHz + +- Env variable as 0 signifies no workaround diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 0cb0afa..8847fc0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -76,7 +76,7 @@ static int set_block_entry(const struct sys_mmu_table *list, index, block_addr, list->memory_type, - list->share); + list->attribute); block_addr += block_size; index++; } @@ -438,7 +438,7 @@ int print_cpuinfo(void) #ifdef CONFIG_SYS_DPAA_FMAN printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); #endif -#ifdef CONFIG_FSL_LSCH3 +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2)); #endif puts("\n"); @@ -484,7 +484,13 @@ int arch_early_init_r(void) { #ifdef CONFIG_MP int rv = 1; +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 + erratum_a009635(); +#endif + +#ifdef CONFIG_MP rv = fsl_layerscape_wake_seconday_cores(); if (rv) printf("Did not wake secondary cores\n"); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 47599c1..eafdd71 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -141,7 +141,7 @@ void append_mmu_masters(void *blob, const char *smmu_path, /* * The info below summarizes how streamID partitioning works - * for ls2085a and how it is conveyed to the OS via the device tree. + * for ls2080a and how it is conveyed to the OS via the device tree. * * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) * -all legacy devices get a unique ICID assigned and programmed in diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 2ab8da6..918e889 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -18,6 +18,11 @@ static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; #endif +#ifdef CONFIG_FSL_MC_ENET +int xfi_dpmac[XFI8 + 1]; +int sgmii_dpmac[SGMII16 + 1]; +#endif + int is_serdes_configured(enum srds_prtcl device) { int ret = 0; @@ -116,9 +121,15 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, wriop_init_dpmac(sd, 12, (int)lane_prtcl); break; default: + if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8) + wriop_init_dpmac(sd, + xfi_dpmac[lane_prtcl], + (int)lane_prtcl); + if (lane_prtcl >= SGMII1 && - lane_prtcl <= SGMII16) - wriop_init_dpmac(sd, lane + 1, + lane_prtcl <= SGMII16) + wriop_init_dpmac(sd, sgmii_dpmac[ + lane_prtcl], (int)lane_prtcl); break; } @@ -129,6 +140,16 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, void fsl_serdes_init(void) { +#ifdef CONFIG_FSL_MC_ENET + int i , j; + + for (i = XFI1, j = 1; i <= XFI8; i++, j++) + xfi_dpmac[i] = j; + + for (i = SGMII1, j = 1; i <= SGMII16; i++, j++) + sgmii_dpmac[i] = j; +#endif + #ifdef CONFIG_SYS_FSL_SRDS_1 serdes_init(FSL_SRDS_1, CONFIG_SYS_FSL_LSCH3_SERDES_ADDR, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 4054c3c..81cf470 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -11,6 +11,7 @@ #include <fsl_ifc.h> #include <asm/processor.h> #include <asm/io.h> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> #include <asm/arch/clock.h> #include <asm/arch/soc.h> #include "cpu.h" @@ -77,11 +78,15 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_systembus = sysclk; #ifdef CONFIG_DDR_CLK_FREQ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ; +#endif #else sys_info->freq_ddrbus = sysclk; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR sys_info->freq_ddrbus2 = sysclk; #endif +#endif sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & @@ -91,9 +96,11 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK; +#endif for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { /* @@ -133,7 +140,9 @@ int get_clocks(void) gd->cpu_clk = sys_info.freq_processor[0]; gd->bus_clk = sys_info.freq_systembus; gd->mem_clk = sys_info.freq_ddrbus; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR gd->arch.mem2_clk = sys_info.freq_ddrbus2; +#endif #if defined(CONFIG_FSL_ESDHC) gd->arch.sdhc_clk = gd->bus_clk / 2; #endif /* defined(CONFIG_FSL_ESDHC) */ @@ -169,8 +178,10 @@ ulong get_ddr_freq(ulong ctrl_num) * DDR controller 0 & 1 are on memory complex 0 * DDR controler 2 is on memory complext 1 */ +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (ctrl_num >= 2) return gd->arch.mem2_clk; +#endif return gd->mem_clk; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c index ea3114c..8ef4f1c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c @@ -28,7 +28,12 @@ static struct serdes_config serdes1_cfg_tbl[] = { SGMII1 } }, {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } }, {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } }, +#ifdef CONFIG_LS2080A + {0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } }, +#endif +#ifdef CONFIG_LS2085A {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, +#endif {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 0d600db..df7ffb8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -192,6 +192,12 @@ int cpu_release(int nr, int argc, char * const argv[]) (unsigned long)table + SPIN_TABLE_ELEM_SIZE); asm volatile("dsb st"); smp_kick_all_cpus(); /* only those with entry addr set will run */ + /* + * When the first release command runs, all cores are set to go. Those + * without a valid entry address will be trapped by "wfe". "sev" kicks + * them off to check the address again. When set, they continue to run. + */ + asm volatile("sev"); return 0; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 637853d..8896b70 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -9,10 +9,53 @@ #include <asm/arch/soc.h> #include <asm/io.h> #include <asm/global_data.h> +#include <asm/arch-fsl-layerscape/config.h> DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_LS2085A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 +#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" + +static unsigned long get_internval_val_mhz(void) +{ + char *interval = getenv(PLATFORM_CYCLE_ENV_VAR); + /* + * interval is the number of platform cycles(MHz) between + * wake up events generated by EPU. + */ + ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); + + if (interval) + interval_mhz = simple_strtoul(interval, NULL, 10); + + return interval_mhz; +} + +void erratum_a009635(void) +{ + u32 val; + unsigned long interval_mhz = get_internval_val_mhz(); + + if (!interval_mhz) + return; + + val = in_le32(DCSR_CGACRE5); + writel(val | 0x00000200, DCSR_CGACRE5); + + val = in_le32(EPU_EPCMPR5); + writel(interval_mhz, EPU_EPCMPR5); + val = in_le32(EPU_EPCCR5); + writel(val | 0x82820000, EPU_EPCCR5); + val = in_le32(EPU_EPSMCR5); + writel(val | 0x002f0000, EPU_EPSMCR5); + val = in_le32(EPU_EPECR5); + writel(val | 0x20000000, EPU_EPECR5); + val = in_le32(EPU_EPGCR); + writel(val | 0x80000000, EPU_EPGCR); +} +#endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ + static void erratum_a008751(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A008751 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index ba551aa..f434c44 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -44,11 +44,9 @@ u32 spl_boot_mode(void) #ifdef CONFIG_SPL_BUILD void board_init_f(ulong dummy) { - /* Set global data pointer */ - gd = &gdata; /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); -#ifdef CONFIG_LS2085A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) arch_cpu_init(); #endif #ifdef CONFIG_FSL_IFC @@ -56,7 +54,7 @@ void board_init_f(ulong dummy) #endif board_early_init_f(); timer_init(); -#ifdef CONFIG_LS2085A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) env_init(); #endif get_clocks(); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 65e76ac..76d1faf 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -87,8 +87,10 @@ dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \ ls1021a-twr.dtb -dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \ - fsl-ls2085a-rdb.dtb +dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ + fsl-ls2080a-rdb.dtb +dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \ + fsl-ls1043a-rdb.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ diff --git a/arch/arm/dts/fsl-ls1043a-qds.dts b/arch/arm/dts/fsl-ls1043a-qds.dts new file mode 100644 index 0000000..7435222 --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a-qds.dts @@ -0,0 +1,124 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2015, Freescale Semiconductor + * + * Mingkai Hu <Mingkai.hu@freescale.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +/include/ "fsl-ls1043a.dtsi" + +/ { + model = "LS1043A QDS Board"; +}; + +&i2c0 { + status = "okay"; + pca9547@77 { + compatible = "philips,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + /* IRQ10_B */ + interrupts = <0 150 0x4>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + ina220@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + eeprom@56 { + compatible = "at24,24c512"; + reg = <0x56>; + }; + + eeprom@57 { + compatible = "at24,24c512"; + reg = <0x57>; + }; + + adt7461a@4c { + compatible = "adt7461a"; + reg = <0x4c>; + }; + }; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000 + 0x2 0x0 0x0 0x7e800000 0x00010000 + 0x3 0x0 0x0 0x7fb00000 0x00000100>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@2,0 { + compatible = "fsl,ifc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1 0x0 0x10000>; + }; + + fpga: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + reg = <0x3 0x0 0x0000100>; + bank-width = <1>; + device-width = <1>; + ranges = <0 3 0 0x100>; + }; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts new file mode 100644 index 0000000..16c5c89 --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a-rdb.dts @@ -0,0 +1,103 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2015, Freescale Semiconductor + * + * Mingkai Hu <Mingkai.hu@freescale.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +/include/ "fsl-ls1043a.dtsi" + +/ { + model = "LS1043A RDB Board"; + + aliases { + spi1 = &dspi0; + }; + +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + dspiflash: n25q12a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <1000000>; /* input clock */ + }; + +}; + +&i2c0 { + status = "okay"; + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + adt7461a@4c { + compatible = "adi,adt7461a"; + reg = <0x4c>; + }; + eeprom@56 { + compatible = "at24,24c512"; + reg = <0x52>; + }; + + eeprom@57 { + compatible = "at24,24c512"; + reg = <0x53>; + }; + + rtc@68 { + compatible = "pericom,pt7c4338"; + reg = <0x68>; + }; +}; + +&ifc { + status = "okay"; + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000 + 0x2 0x0 0x0 0x7e800000 0x00010000 + 0x3 0x0 0x0 0x7fb00000 0x00000100>; + + nor@0,0 { + compatible = "cfi-flash"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@1,0 { + compatible = "fsl,ifc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1 0x0 0x10000>; + }; + + cpld: board-control@2,0 { + compatible = "fsl,ls1043ardb-cpld"; + reg = <0x2 0x0 0x0000100>; + }; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi new file mode 100644 index 0000000..85ea81e --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -0,0 +1,186 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2014-2015, Freescale Semiconductor + * + * Mingkai Hu <Mingkai.hu@freescale.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/include/ "skeleton64.dtsi" + +/ { + compatible = "fsl,ls1043a"; + interrupt-parent = <&gic>; + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&clockgen 1 0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + clocks = <&clockgen 1 0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + clocks = <&clockgen 1 0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + clocks = <&clockgen 1 0>; + }; + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + gic: interrupt-controller@1400000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0 0x1000>, /* GICD */ + <0x0 0x1402000 0 0x2000>, /* GICC */ + <0x0 0x1404000 0 0x2000>, /* GICH */ + <0x0 0x1406000 0 0x2000>; /* GICV */ + interrupts = <1 9 0xf08>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clockgen: clocking@1ee1000 { + compatible = "fsl,ls1043a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 64 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <6>; + big-endian; + status = "disabled"; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <0 65 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <6>; + big-endian; + status = "disabled"; + }; + + ifc: ifc@1530000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x0 0x1530000 0x0 0x10000>; + interrupts = <0 43 0x4>; + }; + + i2c0: i2c@2180000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = <0 56 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c1: i2c@2190000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = <0 57 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c2: i2c@21a0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21a0000 0x0 0x10000>; + interrupts = <0 58 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c3: i2c@21b0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21b0000 0x0 0x10000>; + interrupts = <0 59 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + duart0: serial@21c0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0500 0x0 0x100>; + interrupts = <0 54 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart1: serial@21c0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0600 0x0 0x100>; + interrupts = <0 54 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart2: serial@21d0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21d0500 0x0 0x100>; + interrupts = <0 55 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart3: serial@21d0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21d0600 0x0 0x100>; + interrupts = <0 55 0x4>; + clocks = <&clockgen 4 0>; + }; + }; +}; diff --git a/arch/arm/dts/fsl-ls2085a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts index 4477e54..547ec27 100644 --- a/arch/arm/dts/fsl-ls2085a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -1,5 +1,5 @@ /* - * Freescale ls2085a QDS board device tree source + * Freescale ls2080a QDS board device tree source * * Copyright 2013-2015 Freescale Semiconductor, Inc. * @@ -8,11 +8,11 @@ /dts-v1/; -#include "fsl-ls2085a.dtsi" +#include "fsl-ls2080a.dtsi" / { - model = "Freescale Layerscape 2085a QDS Board"; - compatible = "fsl,ls2085a-qds", "fsl,ls2085a"; + model = "Freescale Layerscape 2080a QDS Board"; + compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; aliases { spi1 = &dspi; diff --git a/arch/arm/dts/fsl-ls2085a-rdb.dts b/arch/arm/dts/fsl-ls2080a-rdb.dts index 25278df..1a1813b 100644 --- a/arch/arm/dts/fsl-ls2085a-rdb.dts +++ b/arch/arm/dts/fsl-ls2080a-rdb.dts @@ -1,5 +1,5 @@ /* - * Freescale ls2085a RDB board device tree source + * Freescale ls2080a RDB board device tree source * * Copyright 2013-2015 Freescale Semiconductor, Inc. * @@ -8,11 +8,11 @@ /dts-v1/; -#include "fsl-ls2085a.dtsi" +#include "fsl-ls2080a.dtsi" / { - model = "Freescale Layerscape 2085a RDB Board"; - compatible = "fsl,ls2085a-rdb", "fsl,ls2085a"; + model = "Freescale Layerscape 2080a RDB Board"; + compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; aliases { spi1 = &dspi; diff --git a/arch/arm/dts/fsl-ls2085a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 96404c5..a5c579c 100644 --- a/arch/arm/dts/fsl-ls2085a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -1,5 +1,5 @@ /* - * Freescale ls2085a SOC common device tree source + * Freescale ls2080a SOC common device tree source * * Copyright 2013-2015 Freescale Semiconductor, Inc. * @@ -7,7 +7,7 @@ */ / { - compatible = "fsl,ls2085a"; + compatible = "fsl,ls2080a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm/dts/socfpga_arria5.dtsi b/arch/arm/dts/socfpga_arria5.dtsi index 5175f03..fa0bd7d 100644 --- a/arch/arm/dts/socfpga_arria5.dtsi +++ b/arch/arm/dts/socfpga_arria5.dtsi @@ -25,6 +25,8 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + drvsel = <3>; + smplsel = <0>; }; sysmgr@ffd08000 { diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi index de36209..040b236 100644 --- a/arch/arm/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/dts/socfpga_cyclone5.dtsi @@ -25,6 +25,8 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + drvsel = <3>; + smplsel = <0>; }; sysmgr@ffd08000 { diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 6782691..05b935d 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -19,6 +19,10 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; + + soc { + u-boot,dm-pre-reloc; + }; }; &gmac1 { @@ -37,6 +41,7 @@ &mmc0 { status = "okay"; + u-boot,dm-pre-reloc; }; &qspi { diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 87bb937..b5a2d28 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -17,10 +17,16 @@ #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 -#if defined(CONFIG_LS2085A) +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#ifdef CONFIG_LS2080A +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#endif +#ifdef CONFIG_LS2085A #define CONFIG_NUM_DDR_CONTROLLERS 3 +#define CONFIG_SYS_FSL_HAS_DP_DDR +#endif #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 #define CONFIG_SYS_FSL_SRDS_1 @@ -44,6 +50,7 @@ #define CONFIG_SYS_FSL_CCSR_SCFG_LE #define CONFIG_SYS_FSL_ESDHC_LE #define CONFIG_SYS_FSL_IFC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN @@ -60,6 +67,13 @@ #define CCI_MN_DVM_DOMAIN_CTL 0x200 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 +#define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) +#define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) +#define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ +#define CCN_HN_F_SAM_NODEID_MASK 0x7f +#define CCN_HN_F_SAM_NODEID_DDR0 0x4 +#define CCN_HN_F_SAM_NODEID_DDR1 0xe + #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) @@ -84,11 +98,20 @@ #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) +#define DCSR_CGACRE5 0x700070914ULL +#define EPU_EPCMPR5 0x700060914ULL +#define EPU_EPCCR5 0x700060814ULL +#define EPU_EPSMCR5 0x700060228ULL +#define EPU_EPECR5 0x700060314ULL +#define EPU_EPCTR5 0x700060a14ULL +#define EPU_EPGCR 0x700060000ULL + #define CONFIG_SYS_FSL_ERRATUM_A008336 #define CONFIG_SYS_FSL_ERRATUM_A008511 #define CONFIG_SYS_FSL_ERRATUM_A008514 #define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 +#define CONFIG_SYS_FSL_ERRATUM_A009635 #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 @@ -113,6 +136,7 @@ #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE +#define CONFIG_SYS_FSL_PEX_LUT_BE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 2903996..4544094 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -8,8 +8,8 @@ #define _FSL_LAYERSCAPE_CPU_H static struct cpu_type cpu_type_list[] = { - CPU_TYPE_ENTRY(LS2085, LS2085, 8), CPU_TYPE_ENTRY(LS2080, LS2080, 8), + CPU_TYPE_ENTRY(LS2085, LS2085, 8), CPU_TYPE_ENTRY(LS2045, LS2045, 4), CPU_TYPE_ENTRY(LS1043, LS1043, 4), }; @@ -103,7 +103,7 @@ struct sys_mmu_table { u64 phys_addr; u64 size; u64 memory_type; - u64 share; + u64 attribute; }; struct table_info { @@ -115,7 +115,8 @@ struct table_info { static const struct sys_mmu_table early_mmu_table[] = { #ifdef CONFIG_FSL_LSCH3 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, /* For IFC Region #1, only the first 4MB is cache-enabled */ @@ -129,17 +130,24 @@ static const struct sys_mmu_table early_mmu_table[] = { CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ + { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, + CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, @@ -152,72 +160,93 @@ static const struct sys_mmu_table early_mmu_table[] = { static const struct sys_mmu_table final_mmu_table[] = { #ifdef CONFIG_FSL_LSCH3 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, - CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, - CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, - CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, /* For QBMAN portal, only the first 64MB is cache-enabled */ { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, - MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, -#ifdef CONFIG_LS2085A + CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, - CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, #endif { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, - CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, - CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, - CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, - CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, - CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE }, #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h index 4da73ab..099563e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h @@ -11,4 +11,5 @@ void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt); void append_mmu_masters(void *blob, const char *smmu_path, const char *master_name, u32 *stream_ids, int count); void fdt_fixup_smmu_pcie(void *blob); +void fdt_fixup_board_enet(void *fdt); #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index e1043b5..d1fbde7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -9,7 +9,7 @@ #include <config.h> -#if defined(CONFIG_LS2085A) +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) enum srds_prtcl { NONE = 0, PCIE1, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index d941437..83caa91 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -30,9 +30,9 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) +#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) +#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) @@ -60,6 +60,10 @@ #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL +/* LUT registers */ +#define PCIE_LUT_BASE 0x10000 +#define PCIE_LUT_LCTRL0 0x7F8 +#define PCIE_LUT_DBG 0x7FC /* TZ Address Space Controller Definitions */ #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 6a70d44..cd96604 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -51,8 +51,8 @@ #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) -#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) +#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) /* TZ Address Space Controller Definitions */ #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ @@ -78,6 +78,10 @@ #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL +/* LUT registers */ +#define PCIE_LUT_BASE 0x80000 +#define PCIE_LUT_LCTRL0 0x7F8 +#define PCIE_LUT_DBG 0x7FC /* Device Configuration */ #define DCFG_BASE 0x01e00000 @@ -115,7 +119,9 @@ struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; unsigned long freq_systembus; unsigned long freq_ddrbus; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR unsigned long freq_ddrbus2; +#endif unsigned long freq_localbus; unsigned long freq_qe; #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h index 5c94530..954104b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h @@ -7,7 +7,7 @@ #ifndef __FSL_STREAM_ID_H #define __FSL_STREAM_ID_H -/* Stream IDs on ls2085a devices are not hardwired and are +/* Stream IDs on ls2080a devices are not hardwired and are * programmed by sw. There are a limited number of stream IDs * available, and the partitioning of them is scenario dependent. * This header defines the partitioning between legacy, PCI, @@ -17,7 +17,7 @@ * on the specific hardware config-- e.g. perhaps not all * PEX controllers are in use. * - * On LS2085 stream IDs are programmed in AMQ registers (32-bits) for + * On LS2080 stream IDs are programmed in AMQ registers (32-bits) for * each of the different bus masters. The relationship between * the AMQ registers and stream IDs is defined in the table below: * AMQ bit streamID bit diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 5ed456e..504c1f9 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -23,6 +23,14 @@ #define scfg_out32(a, v) out_be32(a, v) #endif +#ifdef CONFIG_SYS_FSL_PEX_LUT_LE +#define pex_lut_in32(a) in_le32(a) +#define pex_lut_out32(a, v) out_le32(a, v) +#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) +#define pex_lut_in32(a) in_be32(a) +#define pex_lut_out32(a, v) out_be32(a, v) +#endif + struct cpu_type { char name[15]; u32 soc_ver; @@ -50,4 +58,7 @@ void fsl_lsch2_early_init_f(void); #endif void cpu_name(char *name); +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 +void erratum_a009635(void); +#endif #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 09ed980..1bcdf04 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -31,7 +31,7 @@ #define RCWSR4_SRDS1_PRTCL_SHIFT 24 #define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 -#define TIMER_COMP_VAL 0xffffffff +#define TIMER_COMP_VAL 0xffffffffffffffffull #define ARCH_TIMER_CTRL_ENABLE (1 << 0) #define SYS_COUNTER_CTRL_ENABLE (1 << 24) diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index d8d9af4..2e2a3a8 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -119,7 +119,7 @@ void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type, - u64 share); + u64 attribute); void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr); diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 4e3ea55..bd27281 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -46,7 +46,7 @@ struct arch_global_data { u32 omap_boot_mode; u8 omap_ch_flags; #endif -#ifdef CONFIG_FSL_LSCH3 +#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR) unsigned long mem2_clk; #endif }; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index f7737bf..9205b1e 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -49,6 +49,9 @@ config TARGET_GOFLEXHOME config TARGET_NAS220 bool "BlackArmor NAS220" +config TARGET_NSA310S + bool "Zyxel NSA310S" + endchoice config SYS_SOC @@ -69,5 +72,6 @@ source "board/raidsonic/ib62x0/Kconfig" source "board/Seagate/dockstar/Kconfig" source "board/Seagate/goflexhome/Kconfig" source "board/Seagate/nas220/Kconfig" +source "board/zyxel/nsa310s/Kconfig" endif diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 9dde710..1d49cab 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -70,6 +70,8 @@ #define CONFIG_PHYLIB #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ #define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ +#define CONFIG_ARP_TIMEOUT 200 +#define CONFIG_NET_RETRY_COUNT 50 #endif /* CONFIG_CMD_NET */ /* diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/mach-s5pc1xx/Kconfig index 04acdaa..04acdaa 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/Kconfig +++ b/arch/arm/mach-s5pc1xx/Kconfig diff --git a/arch/arm/cpu/armv7/s5pc1xx/Makefile b/arch/arm/mach-s5pc1xx/Makefile index 9f43ded..9f43ded 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/Makefile +++ b/arch/arm/mach-s5pc1xx/Makefile diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.c b/arch/arm/mach-s5pc1xx/cache.c index 51af299..51af299 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/cache.c +++ b/arch/arm/mach-s5pc1xx/cache.c diff --git a/arch/arm/cpu/armv7/s5pc1xx/clock.c b/arch/arm/mach-s5pc1xx/clock.c index 3da0071..3da0071 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/clock.c +++ b/arch/arm/mach-s5pc1xx/clock.c diff --git a/arch/arm/include/asm/arch-s5pc1xx/clk.h b/arch/arm/mach-s5pc1xx/include/mach/clk.h index 6457ac7..6457ac7 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/clk.h +++ b/arch/arm/mach-s5pc1xx/include/mach/clk.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/clock.h b/arch/arm/mach-s5pc1xx/include/mach/clock.h index 858496a..858496a 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/clock.h +++ b/arch/arm/mach-s5pc1xx/include/mach/clock.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/mach-s5pc1xx/include/mach/cpu.h index 5ae5c87..5ae5c87 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h +++ b/arch/arm/mach-s5pc1xx/include/mach/cpu.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/mach-s5pc1xx/include/mach/gpio.h index 2de205e..2de205e 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/mach-s5pc1xx/include/mach/gpio.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/mach-s5pc1xx/include/mach/mmc.h index dd473c8..dd473c8 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h +++ b/arch/arm/mach-s5pc1xx/include/mach/mmc.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/periph.h b/arch/arm/mach-s5pc1xx/include/mach/periph.h index 5c1c3d4..5c1c3d4 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/periph.h +++ b/arch/arm/mach-s5pc1xx/include/mach/periph.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/pinmux.h b/arch/arm/mach-s5pc1xx/include/mach/pinmux.h index 0b91ef6..0b91ef6 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/pinmux.h +++ b/arch/arm/mach-s5pc1xx/include/mach/pinmux.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/power.h b/arch/arm/mach-s5pc1xx/include/mach/power.h index 8400cda..8400cda 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/power.h +++ b/arch/arm/mach-s5pc1xx/include/mach/power.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/pwm.h b/arch/arm/mach-s5pc1xx/include/mach/pwm.h index 7a33ed8..7a33ed8 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/pwm.h +++ b/arch/arm/mach-s5pc1xx/include/mach/pwm.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/sromc.h b/arch/arm/mach-s5pc1xx/include/mach/sromc.h index df1bf51..df1bf51 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/sromc.h +++ b/arch/arm/mach-s5pc1xx/include/mach/sromc.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h b/arch/arm/mach-s5pc1xx/include/mach/sys_proto.h index 647d6c4..647d6c4 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h +++ b/arch/arm/mach-s5pc1xx/include/mach/sys_proto.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/uart.h b/arch/arm/mach-s5pc1xx/include/mach/uart.h index 26db098..26db098 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/uart.h +++ b/arch/arm/mach-s5pc1xx/include/mach/uart.h diff --git a/arch/arm/include/asm/arch-s5pc1xx/watchdog.h b/arch/arm/mach-s5pc1xx/include/mach/watchdog.h index 2f9746c..2f9746c 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/watchdog.h +++ b/arch/arm/mach-s5pc1xx/include/mach/watchdog.h diff --git a/arch/arm/cpu/armv7/s5pc1xx/reset.S b/arch/arm/mach-s5pc1xx/reset.S index bd74f2b..bd74f2b 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/reset.S +++ b/arch/arm/mach-s5pc1xx/reset.S diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index a413ea4..e4cc468 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -22,6 +22,10 @@ config TARGET_SOCFPGA_DENX_MCVEVK bool "DENX MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_EBV_SOCRATES + bool "EBV SoCrates (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + config TARGET_SOCFPGA_TERASIC_DE0_NANO bool "Terasic DE0-Nano-Atlas (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -38,11 +42,13 @@ config SYS_BOARD default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT + default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "denx" if TARGET_SOCFPGA_DENX_MCVEVK + default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT @@ -55,5 +61,6 @@ config SYS_CONFIG_NAME default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT + default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES endif diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h new file mode 100644 index 0000000..a7056d4 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2014 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SOCFPGA_A10_BASE_HARDWARE_H_ +#define _SOCFPGA_A10_BASE_HARDWARE_H_ + +#define SOCFPGA_EMAC0_ADDRESS 0xff800000 +#define SOCFPGA_EMAC1_ADDRESS 0xff802000 +#define SOCFPGA_EMAC2_ADDRESS 0xff804000 +#define SOCFPGA_SDMMC_ADDRESS 0xff808000 +#define SOCFPGA_QSPIREGS_ADDRESS 0xff809000 +#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 +#define SOCFPGA_UART1_ADDRESS 0xffc02100 +#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xffcfa000 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffcfe400 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xffd03000 +#define SOCFPGA_L4WD0_ADDRESS 0xffd00200 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd06000 +#define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS 0xffd07000 +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd07200 +#define SOCFPGA_PINMUX_DEDICATED_IO_CFG_ADDRESS 0xffd07300 +#define SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS 0xffd07400 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 +#define SOCFPGA_MPUSCU_ADDRESS 0xffffc000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffff000 +#define SOCFPGA_I2C0_ADDRESS 0xffc02200 +#define SOCFPGA_I2C1_ADDRESS 0xffc02300 + +#define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 + +#define SOCFPGA_SDR_ADDRESS 0xffcfb000 +#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400 +#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200 +#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300 +#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400 + +#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h index 6534283..6534283 100644 --- a/arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 666a2ef..e50fbd8 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -25,6 +25,7 @@ struct socfpga_reset_manager { u32 per2_mod_reset; u32 brg_mod_reset; u32 misc_mod_reset; + u32 padding2[12]; u32 tstscratch; }; diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 945e771..efd3165 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -152,7 +152,7 @@ source "board/gdsys/405ex/Kconfig" source "board/gdsys/dlvision/Kconfig" source "board/gdsys/gdppc440etx/Kconfig" source "board/gdsys/intip/Kconfig" -source "board/lwmon5/Kconfig" +source "board/liebherr/lwmon5/Kconfig" source "board/mosaixtech/icon/Kconfig" source "board/mpl/mip405/Kconfig" source "board/mpl/pip405/Kconfig" diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 77d4040..3dd0557 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -1795,34 +1795,11 @@ ppc405ep_init: ..no_pllset: #endif /* CONFIG_BUBINGA */ -#ifdef CONFIG_TAIHU - mfdcr r4, CPC0_BOOT - andi. r5, r4, CPC0_BOOT_SEP@l - bne strap_1 /* serial eeprom present */ - addis r5,0,CPLD_REG0_ADDR@h - ori r5,r5,CPLD_REG0_ADDR@l - andi. r5, r5, 0x10 - bne _pci_66mhz -#endif /* CONFIG_TAIHU */ - addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ ori r3,r3,PLLMR0_DEFAULT@l /* */ addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ ori r4,r4,PLLMR1_DEFAULT@l /* */ -#ifdef CONFIG_TAIHU - b 1f -_pci_66mhz: - addis r3,0,PLLMR0_DEFAULT_PCI66@h - ori r3,r3,PLLMR0_DEFAULT_PCI66@l - addis r4,0,PLLMR1_DEFAULT_PCI66@h - ori r4,r4,PLLMR1_DEFAULT_PCI66@l - b 1f -strap_1: - mfdcr r3, CPC0_PLLMR0 - mfdcr r4, CPC0_PLLMR1 -#endif /* CONFIG_TAIHU */ - 1: b pll_write /* Write the CPC0_PLLMR with new value */ |