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-rw-r--r--arch/arm/cpu/armv7/omap4/board.c30
-rw-r--r--arch/arm/include/asm/arch-omap4/omap4.h10
2 files changed, 39 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 195be6e..8c1f395 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -30,6 +30,7 @@
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
+#include <asm/sizes.h>
/*
* Routine: s_init
@@ -66,6 +67,33 @@ void watchdog_init(void)
writel(WD_UNLOCK2, &wd2_base->wspr);
}
+
+/*
+ * This function finds the SDRAM size available in the system
+ * based on DMM section configurations
+ * This is needed because the size of memory installed may be
+ * different on different versions of the board
+ */
+u32 sdram_size(void)
+{
+ u32 section, i, total_size = 0, size, addr;
+ for (i = 0; i < 4; i++) {
+ section = __raw_readl(DMM_LISA_MAP_BASE + i*4);
+ addr = section & DMM_LISA_MAP_SYS_ADDR_MASK;
+ /* See if the address is valid */
+ if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
+ (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) {
+ size = ((section & DMM_LISA_MAP_SYS_SIZE_MASK) >>
+ DMM_LISA_MAP_SYS_SIZE_SHIFT);
+ size = 1 << size;
+ size *= SZ_16M;
+ total_size += size;
+ }
+ }
+ return total_size;
+}
+
+
/*
* Routine: dram_init
* Description: sets uboots idea of sdram size
@@ -75,7 +103,7 @@ int dram_init(void)
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = 0x80000000;
- gd->bd->bi_dram[0].size = 512 << 20;
+ gd->bd->bi_dram[0].size = sdram_size();
return 0;
}
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index d0c808d..a30bb33 100644
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -42,6 +42,10 @@
#define OMAP44XX_L4_WKUP_BASE 0x4A300000
#define OMAP44XX_L4_PER_BASE 0x48000000
+#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
+#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
+
+
/* CONTROL */
#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
#define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000)
@@ -66,6 +70,12 @@
/* GPMC */
#define OMAP44XX_GPMC_BASE 0x50000000
+/* DMM */
+#define OMAP44XX_DMM_BASE 0x4E000000
+#define DMM_LISA_MAP_BASE (OMAP44XX_DMM_BASE + 0x40)
+#define DMM_LISA_MAP_SYS_SIZE_MASK (7 << 20)
+#define DMM_LISA_MAP_SYS_SIZE_SHIFT 20
+#define DMM_LISA_MAP_SYS_ADDR_MASK (0xFF << 24)
/*
* Hardware Register Details
*/