diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/mx7/soc.c | 36 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx7/imx-regs.h | 15 |
2 files changed, 31 insertions, 20 deletions
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index 0e80d0e..5b8ae2e 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -338,32 +338,30 @@ const struct boot_mode soc_boot_modes[] = { enum boot_device get_boot_device(void) { - enum boot_device boot_dev = UNKNOWN_BOOT; - uint32_t soc_smbr = readl(&src_reg->sbmr1); - uint32_t bt_mem_ctl = (soc_smbr & 0xF000) >> 12; - uint32_t bt_dev_port = (soc_smbr & 0xC00) >> 10; - uint32_t bt_mem_type = (soc_smbr & 0x800) >> 11; - - switch (bt_mem_ctl) { - case 0x1: - boot_dev = bt_dev_port + SD1_BOOT; + struct bootrom_sw_info **p = + (struct bootrom_sw_info **)ROM_SW_INFO_ADDR; + + enum boot_device boot_dev = SD1_BOOT; + u8 boot_type = (*p)->boot_dev_type; + u8 boot_instance = (*p)->boot_dev_instance; + + switch (boot_type) { + case BOOT_TYPE_SD: + boot_dev = boot_instance + SD1_BOOT; break; - case 0x2: - boot_dev = bt_dev_port + MMC1_BOOT; + case BOOT_TYPE_MMC: + boot_dev = boot_instance + MMC1_BOOT; break; - case 0x3: + case BOOT_TYPE_NAND: boot_dev = NAND_BOOT; break; - case 0x4: + case BOOT_TYPE_QSPI: boot_dev = QSPI_BOOT; break; - case 0x5: - if (bt_mem_type) - boot_dev = ONE_NAND_BOOT; - else - boot_dev = WEIM_NOR_BOOT; + case BOOT_TYPE_WEIM: + boot_dev = WEIM_NOR_BOOT; break; - case 0x6: + case BOOT_TYPE_SPINOR: boot_dev = SPI_NOR_BOOT; break; default: diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index 3f82807..9061773 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -11,6 +11,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 +#define ROM_SW_INFO_ADDR 0x000001E8 #define ROMCP_ARB_BASE_ADDR 0x00000000 #define ROMCP_ARB_END_ADDR 0x00017FFF #define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR @@ -1283,7 +1284,19 @@ extern void pcie_power_off(void); #define BOOT_TYPE_NAND 0x3 #define BOOT_TYPE_QSPI 0x4 #define BOOT_TYPE_WEIM 0x5 -#define BOOT_TYPE_EEPROM 0x6 +#define BOOT_TYPE_SPINOR 0x6 + +struct bootrom_sw_info { + u8 reserved_1; + u8 boot_dev_instance; + u8 boot_dev_type; + u8 reserved_2; + u32 arm_core_freq; + u32 axi_freq; + u32 ddr_freq; + u32 gpt1_freq; + u32 reserved_3[3]; +}; #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX7_IMX_REGS_H__ */ |