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-rw-r--r--arch/arm/cpu/armv7/zynq/slcr.c61
-rw-r--r--arch/arm/cpu/armv7/zynq/timer.c49
-rw-r--r--arch/arm/include/asm/arch-zynq/hardware.h36
-rw-r--r--arch/arm/include/asm/arch-zynq/sys_proto.h7
4 files changed, 134 insertions, 19 deletions
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 788a8fd..52048c6 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -28,6 +28,9 @@
#define SLCR_LOCK_MAGIC 0x767B
#define SLCR_UNLOCK_MAGIC 0xDF0D
+#define SLCR_IDCODE_MASK 0x1F000
+#define SLCR_IDCODE_SHIFT 12
+
static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
void zynq_slcr_lock(void)
@@ -61,3 +64,61 @@ void zynq_slcr_cpu_reset(void)
writel(1, &slcr_base->pss_rst_ctrl);
}
+
+/* Setup clk for network */
+void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
+{
+ zynq_slcr_unlock();
+
+ if (gem_id > 1) {
+ printf("Non existing GEM id %d\n", gem_id);
+ goto out;
+ }
+
+ if (gem_id) {
+ /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
+ writel(clk, &slcr_base->gem1_clk_ctrl);
+ /* Configure GEM_RCLK_CTRL */
+ writel(rclk, &slcr_base->gem1_rclk_ctrl);
+ } else {
+ /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
+ writel(clk, &slcr_base->gem0_clk_ctrl);
+ /* Configure GEM_RCLK_CTRL */
+ writel(rclk, &slcr_base->gem0_rclk_ctrl);
+ }
+
+out:
+ zynq_slcr_lock();
+}
+
+void zynq_slcr_devcfg_disable(void)
+{
+ zynq_slcr_unlock();
+
+ /* Disable AXI interface */
+ writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
+
+ /* Set Level Shifters DT618760 */
+ writel(0xA, &slcr_base->lvl_shftr_en);
+
+ zynq_slcr_lock();
+}
+
+void zynq_slcr_devcfg_enable(void)
+{
+ zynq_slcr_unlock();
+
+ /* Set Level Shifters DT618760 */
+ writel(0xF, &slcr_base->lvl_shftr_en);
+
+ /* Disable AXI interface */
+ writel(0x0, &slcr_base->fpga_rst_ctrl);
+
+ zynq_slcr_lock();
+}
+
+u32 zynq_slcr_get_idcode(void)
+{
+ return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
+ SLCR_IDCODE_SHIFT;
+}
diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/cpu/armv7/zynq/timer.c
index 45b405a..8c4357d 100644
--- a/arch/arm/cpu/armv7/zynq/timer.c
+++ b/arch/arm/cpu/armv7/zynq/timer.c
@@ -44,6 +44,7 @@
#include <common.h>
#include <div64.h>
#include <asm/io.h>
+#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -54,7 +55,7 @@ struct scu_timer {
};
static struct scu_timer *timer_base =
- (struct scu_timer *) CONFIG_SCUTIMER_BASEADDR;
+ (struct scu_timer *)ZYNQ_SCUTIMER_BASEADDR;
#define SCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /* Prescaler */
#define SCUTIMER_CONTROL_PRESCALER_SHIFT 8
@@ -114,15 +115,43 @@ ulong get_timer_masked(void)
void __udelay(unsigned long usec)
{
- unsigned long long tmp;
- ulong tmo;
-
- tmo = usec / (1000000 / CONFIG_SYS_HZ);
- tmp = get_ticks() + tmo; /* Get current timestamp */
-
- while (get_ticks() < tmp) { /* Loop till event */
- /* NOP */;
- }
+ u32 countticks;
+ u32 timeend;
+ u32 timediff;
+ u32 timenow;
+
+ if (usec == 0)
+ return;
+
+ countticks = (u32) (((unsigned long long) TIMER_TICK_HZ * usec) /
+ 1000000);
+
+ /* decrementing timer */
+ timeend = readl(&timer_base->counter) - countticks;
+
+#if TIMER_LOAD_VAL != 0xFFFFFFFF
+ /* do not manage multiple overflow */
+ if (countticks >= TIMER_LOAD_VAL)
+ countticks = TIMER_LOAD_VAL - 1;
+#endif
+
+ do {
+ timenow = readl(&timer_base->counter);
+
+ if (timenow >= timeend) {
+ /* normal case */
+ timediff = timenow - timeend;
+ } else {
+ if ((TIMER_LOAD_VAL - timeend + timenow) <=
+ countticks) {
+ /* overflow */
+ timediff = TIMER_LOAD_VAL - timeend + timenow;
+ } else {
+ /* missed the exact match */
+ break;
+ }
+ }
+ } while (timediff > 0);
}
/* Timer without interrupts */
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index d0c69da..8b8a91a 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -23,16 +23,28 @@
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
-#define XPSS_SYS_CTRL_BASEADDR 0xF8000000
-#define XPSS_DEV_CFG_APB_BASEADDR 0xF8007000
-#define XPSS_SCU_BASEADDR 0xF8F00000
+#define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
+#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
+#define ZYNQ_SCU_BASEADDR 0xF8F00000
+#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
+#define ZYNQ_GEM_BASEADDR0 0xE000B000
+#define ZYNQ_GEM_BASEADDR1 0xE000C000
+#define ZYNQ_SDHCI_BASEADDR0 0xE0100000
+#define ZYNQ_SDHCI_BASEADDR1 0xE0101000
+#define ZYNQ_I2C_BASEADDR0 0xE0004000
+#define ZYNQ_I2C_BASEADDR1 0xE0005000
/* Reflect slcr offsets */
struct slcr_regs {
u32 scl; /* 0x0 */
u32 slcr_lock; /* 0x4 */
u32 slcr_unlock; /* 0x8 */
- u32 reserved1[125];
+ u32 reserved0[75];
+ u32 gem0_rclk_ctrl; /* 0x138 */
+ u32 gem1_rclk_ctrl; /* 0x13c */
+ u32 gem0_clk_ctrl; /* 0x140 */
+ u32 gem1_clk_ctrl; /* 0x144 */
+ u32 reserved1[46];
u32 pss_rst_ctrl; /* 0x200 */
u32 reserved2[15];
u32 fpga_rst_ctrl; /* 0x240 */
@@ -41,15 +53,21 @@ struct slcr_regs {
u32 boot_mode; /* 0x25c */
u32 reserved4[116];
u32 trust_zone; /* 0x430 */ /* FIXME */
- u32 reserved5[115];
+ u32 reserved5_1[63];
+ u32 pss_idcode; /* 0x530 */
+ u32 reserved5_2[51];
u32 ddr_urgent; /* 0x600 */
u32 reserved6[6];
u32 ddr_urgent_sel; /* 0x61c */
- u32 reserved7[188];
+ u32 reserved7[56];
+ u32 mio_pin[54]; /* 0x700 - 0x7D4 */
+ u32 reserved8[74];
+ u32 lvl_shftr_en; /* 0x900 */
+ u32 reserved9[3];
u32 ocm_cfg; /* 0x910 */
};
-#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
+#define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)
struct devcfg_regs {
u32 ctrl; /* 0x0 */
@@ -72,7 +90,7 @@ struct devcfg_regs {
u32 read_count; /* 0x8c */
};
-#define devcfg_base ((struct devcfg_regs *) XPSS_DEV_CFG_APB_BASEADDR)
+#define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)
struct scu_regs {
u32 reserved1[16];
@@ -80,6 +98,6 @@ struct scu_regs {
u32 filter_end; /* 0x44 */
};
-#define scu_base ((struct scu_regs *) XPSS_SCU_BASEADDR)
+#define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index e788900..2317121 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -26,5 +26,12 @@
extern void zynq_slcr_lock(void);
extern void zynq_slcr_unlock(void);
extern void zynq_slcr_cpu_reset(void);
+extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
+extern void zynq_slcr_devcfg_disable(void);
+extern void zynq_slcr_devcfg_enable(void);
+extern u32 zynq_slcr_get_idcode(void);
+
+/* Driver extern functions */
+extern int zynq_sdhci_init(u32 regbase);
#endif /* _SYS_PROTO_H_ */
generated by cgit v1.1 at 2024-09-12 21:18:01 +0000