summaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/Kconfig2
-rw-r--r--arch/arc/Kconfig128
-rw-r--r--arch/arc/config.mk27
-rw-r--r--arch/arc/cpu/arcv1/config.mk7
-rw-r--r--arch/arc/cpu/arcv2/Makefile7
-rw-r--r--arch/arc/cpu/arcv2/start.S254
-rw-r--r--arch/arc/include/asm/arcregs.h6
-rw-r--r--arch/arc/include/asm/cache.h23
-rw-r--r--arch/arc/include/asm/config.h2
-rw-r--r--arch/arc/lib/Makefile2
-rw-r--r--arch/arc/lib/_millicodethunk.S226
-rw-r--r--arch/arc/lib/cache.c7
-rw-r--r--arch/arc/lib/libgcc2.c161
-rw-r--r--arch/arc/lib/libgcc2.h132
-rw-r--r--arch/arc/lib/memcmp.S2
-rw-r--r--arch/arm/Kconfig213
-rw-r--r--arch/arm/Makefile24
-rw-r--r--arch/arm/cpu/Makefile7
-rw-r--r--arch/arm/cpu/arm1176/bcm2835/Kconfig12
-rw-r--r--arch/arm/cpu/arm1176/bcm2835/Makefile12
-rw-r--r--arch/arm/cpu/arm720t/Makefile6
-rw-r--r--arch/arm/cpu/arm720t/tegra-common/Makefile11
-rw-r--r--arch/arm/cpu/arm720t/tegra114/Makefile21
-rw-r--r--arch/arm/cpu/arm720t/tegra124/Makefile8
-rw-r--r--arch/arm/cpu/arm720t/tegra20/Makefile10
-rw-r--r--arch/arm/cpu/arm720t/tegra30/Makefile20
-rw-r--r--arch/arm/cpu/arm920t/Makefile1
-rw-r--r--arch/arm/cpu/arm926ejs/Makefile6
-rw-r--r--arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c189
-rw-r--r--arch/arm/cpu/arm926ejs/at91/config.mk2
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_boot.c6
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c13
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c18
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_power_init.c110
-rw-r--r--arch/arm/cpu/armv7/Makefile6
-rw-r--r--arch/arm/cpu/armv7/am33xx/clock_am43xx.c3
-rw-r--r--arch/arm/cpu/armv7/armada-xp/Makefile2
-rw-r--r--arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S62
-rw-r--r--arch/arm/cpu/armv7/armada-xp/spl.c38
-rw-r--r--arch/arm/cpu/armv7/at91/config.mk8
-rw-r--r--arch/arm/cpu/armv7/at91/sama5d4_devices.c46
-rw-r--r--arch/arm/cpu/armv7/bcm2835/Makefile13
-rw-r--r--arch/arm/cpu/armv7/cpu.c2
-rw-r--r--arch/arm/cpu/armv7/exynos/Kconfig21
-rw-r--r--arch/arm/cpu/armv7/exynos/clock.c621
-rw-r--r--arch/arm/cpu/armv7/exynos/pinmux.c27
-rw-r--r--arch/arm/cpu/armv7/exynos/power.c28
-rw-r--r--arch/arm/cpu/armv7/exynos/spl_boot.c1
-rw-r--r--arch/arm/cpu/armv7/mx6/ddr.c96
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c2
-rw-r--r--arch/arm/cpu/armv7/omap-common/clocks-common.c83
-rw-r--r--arch/arm/cpu/armv7/omap-common/emif-common.c4
-rw-r--r--arch/arm/cpu/armv7/omap-common/lowlevel_init.S2
-rw-r--r--arch/arm/cpu/armv7/omap3/Kconfig15
-rw-r--r--arch/arm/cpu/armv7/omap3/clock.c9
-rw-r--r--arch/arm/cpu/armv7/omap3/lowlevel_init.S2
-rw-r--r--arch/arm/cpu/armv7/omap3/sdrc.c6
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c43
-rw-r--r--arch/arm/cpu/armv7/omap5/sdram.c83
-rw-r--r--arch/arm/cpu/armv7/rmobile/Kconfig6
-rw-r--r--arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S12
-rw-r--r--arch/arm/cpu/armv7/start.S13
-rw-r--r--arch/arm/cpu/armv7/sunxi/Makefile7
-rw-r--r--arch/arm/cpu/armv7/sunxi/board.c46
-rw-r--r--arch/arm/cpu/armv7/sunxi/config.mk2
-rw-r--r--arch/arm/cpu/armv7/sunxi/dram_helpers.c37
-rw-r--r--arch/arm/cpu/armv7/sunxi/fel_utils.S42
-rw-r--r--arch/arm/cpu/armv7/sunxi/rsb.c22
-rw-r--r--arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds82
-rw-r--r--arch/arm/cpu/armv7/tegra-common/Kconfig28
-rw-r--r--arch/arm/cpu/armv7/tegra-common/Makefile10
-rw-r--r--arch/arm/cpu/armv7/tegra20/Makefile11
-rw-r--r--arch/arm/cpu/armv7/uniphier/Kconfig17
-rw-r--r--arch/arm/cpu/armv7/uniphier/Makefile27
-rw-r--r--arch/arm/cpu/armv7/uniphier/board_early_init_f.c22
-rw-r--r--arch/arm/cpu/armv7/uniphier/board_postclk_init.c47
-rw-r--r--arch/arm/cpu/armv7/uniphier/cmd_pinmon.c15
-rw-r--r--arch/arm/cpu/armv7/uniphier/dram_init.c23
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile14
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile13
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c16
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c6
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile14
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c16
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c9
-rw-r--r--arch/arm/cpu/armv7/uniphier/print_misc_info.c (renamed from arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c)7
-rw-r--r--arch/arm/cpu/armv7/uniphier/spl.c52
-rw-r--r--arch/arm/dts/exynos4.dtsi31
-rw-r--r--arch/arm/dts/exynos4210-origen.dts2
-rw-r--r--arch/arm/dts/exynos4210-trats.dts4
-rw-r--r--arch/arm/dts/exynos4210-universal_c210.dts12
-rw-r--r--arch/arm/dts/exynos4412-odroid.dts14
-rw-r--r--arch/arm/dts/exynos4412-trats2.dts6
-rw-r--r--arch/arm/dts/exynos5.dtsi4
-rw-r--r--arch/arm/dts/exynos5250-arndale.dts8
-rw-r--r--arch/arm/dts/exynos5250-smdk5250.dts2
-rw-r--r--arch/arm/dts/exynos5250-snow.dts11
-rw-r--r--arch/arm/dts/exynos5420-peach-pit.dts8
-rw-r--r--arch/arm/dts/exynos5422-odroidxu3.dts7
-rw-r--r--arch/arm/dts/exynos5800-peach-pi.dts10
-rw-r--r--arch/arm/dts/tegra114-dalmore.dts5
-rw-r--r--arch/arm/dts/tegra124-jetson-tk1.dts9
-rw-r--r--arch/arm/dts/tegra124-venice2.dts9
-rw-r--r--arch/arm/dts/tegra20-colibri_t20_iris.dts10
-rw-r--r--arch/arm/dts/tegra20-harmony.dts28
-rw-r--r--arch/arm/dts/tegra20-medcom-wide.dts9
-rw-r--r--arch/arm/dts/tegra20-paz00.dts18
-rw-r--r--arch/arm/dts/tegra20-seaboard.dts22
-rw-r--r--arch/arm/dts/tegra20-tamonten.dtsi9
-rw-r--r--arch/arm/dts/tegra20-tec.dts9
-rw-r--r--arch/arm/dts/tegra20-trimslice.dts8
-rw-r--r--arch/arm/dts/tegra20-ventana.dts18
-rw-r--r--arch/arm/dts/tegra20-whistler.dts2
-rw-r--r--arch/arm/dts/tegra30-apalis.dts10
-rw-r--r--arch/arm/dts/tegra30-beaver.dts10
-rw-r--r--arch/arm/dts/tegra30-cardhu.dts8
-rw-r--r--arch/arm/dts/tegra30-colibri.dts6
-rw-r--r--arch/arm/dts/tegra30-tamonten.dtsi4
-rw-r--r--arch/arm/dts/uniphier-ph1-ld4-ref.dts7
-rw-r--r--arch/arm/dts/uniphier-ph1-pro4-ref.dts7
-rw-r--r--arch/arm/dts/uniphier-ph1-sld3-ref.dts7
-rw-r--r--arch/arm/dts/uniphier-ph1-sld8-ref.dts7
-rw-r--r--arch/arm/dts/uniphier-ref-daughter.dtsi16
-rw-r--r--arch/arm/include/asm/arch-am33xx/cpu.h2
-rw-r--r--arch/arm/include/asm/arch-armada-xp/config.h4
-rw-r--r--arch/arm/include/asm/arch-armada-xp/cpu.h16
-rw-r--r--arch/arm/include/asm/arch-at91/at91cap9.h78
-rw-r--r--arch/arm/include/asm/arch-at91/at91cap9_matrix.h129
-rw-r--r--arch/arm/include/asm/arch-bcm2835/gpio.h5
-rw-r--r--arch/arm/include/asm/arch-bcm2835/mbox.h10
-rw-r--r--arch/arm/include/asm/arch-bcm2835/sdhci.h18
-rw-r--r--arch/arm/include/asm/arch-bcm2835/timer.h18
-rw-r--r--arch/arm/include/asm/arch-bcm2835/wdog.h18
-rw-r--r--arch/arm/include/asm/arch-exynos/clk.h4
-rw-r--r--arch/arm/include/asm/arch-exynos/pinmux.h3
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/config.h4
-rw-r--r--arch/arm/include/asm/arch-mx6/imx-regs.h16
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6-ddr.h46
-rw-r--r--arch/arm/include/asm/arch-mxs/sys_proto.h17
-rw-r--r--arch/arm/include/asm/arch-omap3/mem.h43
-rw-r--r--arch/arm/include/asm/arch-omap3/mmc_host_def.h1
-rw-r--r--arch/arm/include/asm/arch-omap3/mux.h51
-rw-r--r--arch/arm/include/asm/arch-omap3/sys_proto.h1
-rw-r--r--arch/arm/include/asm/arch-omap5/clock.h20
-rw-r--r--arch/arm/include/asm/arch-pantheon/gpio.h0
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun4i.h11
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun6i.h2
-rw-r--r--arch/arm/include/asm/arch-sunxi/cpu_sun9i.h5
-rw-r--r--arch/arm/include/asm/arch-sunxi/dram.h28
-rw-r--r--arch/arm/include/asm/arch-sunxi/gpio.h9
-rw-r--r--arch/arm/include/asm/arch-sunxi/rsb.h4
-rw-r--r--arch/arm/include/asm/arch-sunxi/sys_proto.h10
-rw-r--r--arch/arm/include/asm/arch-tegra/tegra_mmc.h7
-rw-r--r--arch/arm/include/asm/arch-tegra20/display.h9
-rw-r--r--arch/arm/include/asm/arch-uniphier/boot-device.h2
-rw-r--r--arch/arm/include/asm/arch-uniphier/gpio.h6
-rw-r--r--arch/arm/include/asm/arch-zynq/gpio.h15
-rw-r--r--arch/arm/include/asm/emif.h1
-rw-r--r--arch/arm/include/asm/spl.h4
-rw-r--r--arch/arm/include/asm/system.h15
-rw-r--r--arch/arm/include/asm/u-boot-arm.h1
-rw-r--r--arch/arm/lib/Makefile1
-rw-r--r--arch/arm/lib/stack.c42
-rw-r--r--arch/arm/mach-at91/Kconfig168
-rw-r--r--arch/arm/mach-at91/Makefile (renamed from arch/arm/cpu/at91-common/Makefile)15
-rw-r--r--arch/arm/mach-at91/arm920t/Makefile (renamed from arch/arm/cpu/arm920t/at91/Makefile)0
-rw-r--r--arch/arm/mach-at91/arm920t/at91rm9200_devices.c (renamed from arch/arm/cpu/arm920t/at91/at91rm9200_devices.c)0
-rw-r--r--arch/arm/mach-at91/arm920t/clock.c (renamed from arch/arm/cpu/arm920t/at91/clock.c)0
-rw-r--r--arch/arm/mach-at91/arm920t/cpu.c (renamed from arch/arm/cpu/arm920t/at91/cpu.c)0
-rw-r--r--arch/arm/mach-at91/arm920t/lowlevel_init.S (renamed from arch/arm/cpu/arm920t/at91/lowlevel_init.S)0
-rw-r--r--arch/arm/mach-at91/arm920t/reset.c (renamed from arch/arm/cpu/arm920t/at91/reset.c)0
-rw-r--r--arch/arm/mach-at91/arm920t/timer.c (renamed from arch/arm/cpu/arm920t/at91/timer.c)0
-rw-r--r--arch/arm/mach-at91/arm926ejs/Makefile (renamed from arch/arm/cpu/arm926ejs/at91/Makefile)1
-rw-r--r--arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c (renamed from arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c)0
-rw-r--r--arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c (renamed from arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c)0
-rw-r--r--arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c (renamed from arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c)0
-rw-r--r--arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c (renamed from arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c)0
-rw-r--r--arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c (renamed from arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c)0
-rw-r--r--arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c (renamed from arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c)0
-rw-r--r--arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c (renamed from arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c)0
-rw-r--r--arch/arm/mach-at91/arm926ejs/clock.c (renamed from arch/arm/cpu/arm926ejs/at91/clock.c)0
-rw-r--r--arch/arm/mach-at91/arm926ejs/cpu.c (renamed from arch/arm/cpu/arm926ejs/at91/cpu.c)0
-rw-r--r--arch/arm/mach-at91/arm926ejs/eflash.c (renamed from arch/arm/cpu/arm926ejs/at91/eflash.c)0
-rw-r--r--arch/arm/mach-at91/arm926ejs/led.c (renamed from arch/arm/cpu/arm926ejs/at91/led.c)0
-rw-r--r--arch/arm/mach-at91/arm926ejs/lowlevel_init.S (renamed from arch/arm/cpu/arm926ejs/at91/lowlevel_init.S)0
-rw-r--r--arch/arm/mach-at91/arm926ejs/reset.c (renamed from arch/arm/cpu/arm926ejs/at91/reset.c)0
-rw-r--r--arch/arm/mach-at91/arm926ejs/timer.c (renamed from arch/arm/cpu/arm926ejs/at91/timer.c)0
-rw-r--r--arch/arm/mach-at91/armv7/Makefile (renamed from arch/arm/cpu/armv7/at91/Makefile)0
-rw-r--r--arch/arm/mach-at91/armv7/clock.c (renamed from arch/arm/cpu/armv7/at91/clock.c)8
-rw-r--r--arch/arm/mach-at91/armv7/cpu.c (renamed from arch/arm/cpu/armv7/at91/cpu.c)0
-rw-r--r--arch/arm/mach-at91/armv7/reset.c (renamed from arch/arm/cpu/armv7/at91/reset.c)0
-rw-r--r--arch/arm/mach-at91/armv7/sama5d3_devices.c (renamed from arch/arm/cpu/armv7/at91/sama5d3_devices.c)0
-rw-r--r--arch/arm/mach-at91/armv7/sama5d4_devices.c93
-rw-r--r--arch/arm/mach-at91/armv7/timer.c (renamed from arch/arm/cpu/armv7/at91/timer.c)0
-rw-r--r--arch/arm/mach-at91/config.mk9
-rw-r--r--arch/arm/mach-at91/include/mach/at91_common.h (renamed from arch/arm/include/asm/arch-at91/at91_common.h)1
-rw-r--r--arch/arm/mach-at91/include/mach/at91_dbu.h (renamed from arch/arm/include/asm/arch-at91/at91_dbu.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91_eefc.h (renamed from arch/arm/include/asm/arch-at91/at91_eefc.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91_emac.h (renamed from arch/arm/include/asm/arch-at91/at91_emac.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91_gpbr.h (renamed from arch/arm/include/asm/arch-at91/at91_gpbr.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91_matrix.h (renamed from arch/arm/include/asm/arch-at91/at91_matrix.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91_mc.h (renamed from arch/arm/include/asm/arch-at91/at91_mc.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pdc.h (renamed from arch/arm/include/asm/arch-at91/at91_pdc.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pio.h (renamed from arch/arm/include/asm/arch-at91/at91_pio.h)12
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pit.h (renamed from arch/arm/include/asm/arch-at91/at91_pit.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pmc.h (renamed from arch/arm/include/asm/arch-at91/at91_pmc.h)9
-rw-r--r--arch/arm/mach-at91/include/mach/at91_rstc.h (renamed from arch/arm/include/asm/arch-at91/at91_rstc.h)2
-rw-r--r--arch/arm/mach-at91/include/mach/at91_rtt.h (renamed from arch/arm/include/asm/arch-at91/at91_rtt.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91_spi.h (renamed from arch/arm/include/asm/arch-at91/at91_spi.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91_st.h (renamed from arch/arm/include/asm/arch-at91/at91_st.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91_tc.h (renamed from arch/arm/include/asm/arch-at91/at91_tc.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91_wdt.h (renamed from arch/arm/include/asm/arch-at91/at91_wdt.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200.h (renamed from arch/arm/include/asm/arch-at91/at91rm9200.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h (renamed from arch/arm/include/asm/arch-at91/at91sam9260.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260_matrix.h (renamed from arch/arm/include/asm/arch-at91/at91sam9260_matrix.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h (renamed from arch/arm/include/asm/arch-at91/at91sam9261.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261_matrix.h (renamed from arch/arm/include/asm/arch-at91/at91sam9261_matrix.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263.h (renamed from arch/arm/include/asm/arch-at91/at91sam9263.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263_matrix.h (renamed from arch/arm/include/asm/arch-at91/at91sam9263_matrix.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_matrix.h (renamed from arch/arm/include/asm/arch-at91/at91sam9_matrix.h)2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_sdramc.h (renamed from arch/arm/include/asm/arch-at91/at91sam9_sdramc.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_smc.h (renamed from arch/arm/include/asm/arch-at91/at91sam9_smc.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h (renamed from arch/arm/include/asm/arch-at91/at91sam9g45.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h (renamed from arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl.h (renamed from arch/arm/include/asm/arch-at91/at91sam9rl.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h (renamed from arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9x5.h (renamed from arch/arm/include/asm/arch-at91/at91sam9x5.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h (renamed from arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/atmel_mpddrc.h (renamed from arch/arm/include/asm/arch-at91/atmel_mpddrc.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/atmel_serial.h (renamed from arch/arm/include/asm/arch-at91/atmel_serial.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/atmel_usba_udc.h (renamed from arch/arm/include/asm/arch-at91/atmel_usba_udc.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/clk.h (renamed from arch/arm/include/asm/arch-at91/clk.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/gpio.h (renamed from arch/arm/include/asm/arch-at91/gpio.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h (renamed from arch/arm/include/asm/arch-at91/hardware.h)2
-rw-r--r--arch/arm/mach-at91/include/mach/sama5_matrix.h37
-rw-r--r--arch/arm/mach-at91/include/mach/sama5_sfr.h38
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d3.h (renamed from arch/arm/include/asm/arch-at91/sama5d3.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d3_smc.h (renamed from arch/arm/include/asm/arch-at91/sama5d3_smc.h)0
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d4.h (renamed from arch/arm/include/asm/arch-at91/sama5d4.h)2
-rw-r--r--arch/arm/mach-at91/mpddrc.c (renamed from arch/arm/cpu/at91-common/mpddrc.c)2
-rw-r--r--arch/arm/mach-at91/phy.c (renamed from arch/arm/cpu/at91-common/phy.c)0
-rw-r--r--arch/arm/mach-at91/sdram.c (renamed from arch/arm/cpu/at91-common/sdram.c)0
-rw-r--r--arch/arm/mach-at91/spl.c (renamed from arch/arm/cpu/at91-common/spl.c)4
-rw-r--r--arch/arm/mach-at91/spl_at91.c (renamed from arch/arm/cpu/at91-common/spl_at91.c)0
-rw-r--r--arch/arm/mach-at91/spl_atmel.c (renamed from arch/arm/cpu/at91-common/spl_atmel.c)16
-rw-r--r--arch/arm/mach-at91/u-boot-spl.lds (renamed from arch/arm/cpu/at91-common/u-boot-spl.lds)0
-rw-r--r--arch/arm/mach-davinci/Kconfig (renamed from arch/arm/cpu/arm926ejs/davinci/Kconfig)0
-rw-r--r--arch/arm/mach-davinci/Makefile (renamed from arch/arm/cpu/arm926ejs/davinci/Makefile)0
-rw-r--r--arch/arm/mach-davinci/config.mk (renamed from arch/arm/cpu/arm926ejs/davinci/config.mk)0
-rw-r--r--arch/arm/mach-davinci/cpu.c (renamed from arch/arm/cpu/arm926ejs/davinci/cpu.c)0
-rw-r--r--arch/arm/mach-davinci/da830_pinmux.c (renamed from arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c)0
-rw-r--r--arch/arm/mach-davinci/da850_lowlevel.c (renamed from arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c)0
-rw-r--r--arch/arm/mach-davinci/da850_pinmux.c (renamed from arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c)0
-rw-r--r--arch/arm/mach-davinci/dm355.c (renamed from arch/arm/cpu/arm926ejs/davinci/dm355.c)0
-rw-r--r--arch/arm/mach-davinci/dm365.c (renamed from arch/arm/cpu/arm926ejs/davinci/dm365.c)0
-rw-r--r--arch/arm/mach-davinci/dm365_lowlevel.c (renamed from arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c)0
-rw-r--r--arch/arm/mach-davinci/dm644x.c (renamed from arch/arm/cpu/arm926ejs/davinci/dm644x.c)0
-rw-r--r--arch/arm/mach-davinci/dm646x.c (renamed from arch/arm/cpu/arm926ejs/davinci/dm646x.c)0
-rw-r--r--arch/arm/mach-davinci/dp83848.c (renamed from arch/arm/cpu/arm926ejs/davinci/dp83848.c)2
-rw-r--r--arch/arm/mach-davinci/et1011c.c (renamed from arch/arm/cpu/arm926ejs/davinci/et1011c.c)2
-rw-r--r--arch/arm/mach-davinci/include/mach/aintc_defs.h (renamed from arch/arm/include/asm/arch-davinci/aintc_defs.h)0
-rw-r--r--arch/arm/mach-davinci/include/mach/da850_lowlevel.h (renamed from arch/arm/include/asm/arch-davinci/da850_lowlevel.h)0
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx-usb.h (renamed from arch/arm/include/asm/arch-davinci/da8xx-usb.h)0
-rw-r--r--arch/arm/mach-davinci/include/mach/davinci_misc.h (renamed from arch/arm/include/asm/arch-davinci/davinci_misc.h)0
-rw-r--r--arch/arm/mach-davinci/include/mach/ddr2_defs.h (renamed from arch/arm/include/asm/arch-davinci/ddr2_defs.h)0
-rw-r--r--arch/arm/mach-davinci/include/mach/dm365_lowlevel.h (renamed from arch/arm/include/asm/arch-davinci/dm365_lowlevel.h)0
-rw-r--r--arch/arm/mach-davinci/include/mach/emac_defs.h (renamed from arch/arm/include/asm/arch-davinci/emac_defs.h)0
-rw-r--r--arch/arm/mach-davinci/include/mach/gpio.h (renamed from arch/arm/include/asm/arch-davinci/gpio.h)0
-rw-r--r--arch/arm/mach-davinci/include/mach/hardware.h (renamed from arch/arm/include/asm/arch-davinci/hardware.h)0
-rw-r--r--arch/arm/mach-davinci/include/mach/i2c_defs.h (renamed from arch/arm/include/asm/arch-davinci/i2c_defs.h)0
-rw-r--r--arch/arm/mach-davinci/include/mach/pinmux_defs.h (renamed from arch/arm/include/asm/arch-davinci/pinmux_defs.h)0
-rw-r--r--arch/arm/mach-davinci/include/mach/pll_defs.h (renamed from arch/arm/include/asm/arch-davinci/pll_defs.h)0
-rw-r--r--arch/arm/mach-davinci/include/mach/psc_defs.h (renamed from arch/arm/include/asm/arch-davinci/psc_defs.h)0
-rw-r--r--arch/arm/mach-davinci/include/mach/sdmmc_defs.h (renamed from arch/arm/include/asm/arch-davinci/sdmmc_defs.h)0
-rw-r--r--arch/arm/mach-davinci/include/mach/syscfg_defs.h (renamed from arch/arm/include/asm/arch-davinci/syscfg_defs.h)0
-rw-r--r--arch/arm/mach-davinci/include/mach/timer_defs.h (renamed from arch/arm/include/asm/arch-davinci/timer_defs.h)0
-rw-r--r--arch/arm/mach-davinci/ksz8873.c (renamed from arch/arm/cpu/arm926ejs/davinci/ksz8873.c)2
-rw-r--r--arch/arm/mach-davinci/lowlevel_init.S (renamed from arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S)0
-rw-r--r--arch/arm/mach-davinci/lxt972.c (renamed from arch/arm/cpu/arm926ejs/davinci/lxt972.c)2
-rw-r--r--arch/arm/mach-davinci/misc.c (renamed from arch/arm/cpu/arm926ejs/davinci/misc.c)0
-rw-r--r--arch/arm/mach-davinci/pinmux.c (renamed from arch/arm/cpu/arm926ejs/davinci/pinmux.c)0
-rw-r--r--arch/arm/mach-davinci/psc.c (renamed from arch/arm/cpu/arm926ejs/davinci/psc.c)0
-rw-r--r--arch/arm/mach-davinci/reset.c (renamed from arch/arm/cpu/arm926ejs/davinci/reset.c)0
-rw-r--r--arch/arm/mach-davinci/spl.c (renamed from arch/arm/cpu/arm926ejs/davinci/spl.c)17
-rw-r--r--arch/arm/mach-davinci/timer.c (renamed from arch/arm/cpu/arm926ejs/davinci/timer.c)0
-rw-r--r--arch/arm/mach-highbank/Kconfig (renamed from arch/arm/cpu/armv7/highbank/Kconfig)0
-rw-r--r--arch/arm/mach-highbank/Makefile (renamed from arch/arm/cpu/armv7/highbank/Makefile)0
-rw-r--r--arch/arm/mach-highbank/timer.c (renamed from arch/arm/cpu/armv7/highbank/timer.c)0
-rw-r--r--arch/arm/mach-keystone/Kconfig (renamed from arch/arm/cpu/armv7/keystone/Kconfig)0
-rw-r--r--arch/arm/mach-keystone/Makefile (renamed from arch/arm/cpu/armv7/keystone/Makefile)0
-rw-r--r--arch/arm/mach-keystone/clock-k2e.c (renamed from arch/arm/cpu/armv7/keystone/clock-k2e.c)0
-rw-r--r--arch/arm/mach-keystone/clock-k2hk.c (renamed from arch/arm/cpu/armv7/keystone/clock-k2hk.c)0
-rw-r--r--arch/arm/mach-keystone/clock-k2l.c (renamed from arch/arm/cpu/armv7/keystone/clock-k2l.c)0
-rw-r--r--arch/arm/mach-keystone/clock.c (renamed from arch/arm/cpu/armv7/keystone/clock.c)0
-rw-r--r--arch/arm/mach-keystone/cmd_clock.c (renamed from arch/arm/cpu/armv7/keystone/cmd_clock.c)0
-rw-r--r--arch/arm/mach-keystone/cmd_ddr3.c (renamed from arch/arm/cpu/armv7/keystone/cmd_ddr3.c)0
-rw-r--r--arch/arm/mach-keystone/cmd_mon.c (renamed from arch/arm/cpu/armv7/keystone/cmd_mon.c)0
-rw-r--r--arch/arm/mach-keystone/ddr3.c (renamed from arch/arm/cpu/armv7/keystone/ddr3.c)5
-rw-r--r--arch/arm/mach-keystone/include/mach/clock-k2e.h (renamed from arch/arm/include/asm/arch-keystone/clock-k2e.h)0
-rw-r--r--arch/arm/mach-keystone/include/mach/clock-k2hk.h (renamed from arch/arm/include/asm/arch-keystone/clock-k2hk.h)0
-rw-r--r--arch/arm/mach-keystone/include/mach/clock-k2l.h (renamed from arch/arm/include/asm/arch-keystone/clock-k2l.h)0
-rw-r--r--arch/arm/mach-keystone/include/mach/clock.h (renamed from arch/arm/include/asm/arch-keystone/clock.h)0
-rw-r--r--arch/arm/mach-keystone/include/mach/clock_defs.h (renamed from arch/arm/include/asm/arch-keystone/clock_defs.h)0
-rw-r--r--arch/arm/mach-keystone/include/mach/ddr3.h (renamed from arch/arm/include/asm/arch-keystone/ddr3.h)5
-rw-r--r--arch/arm/mach-keystone/include/mach/hardware-k2e.h (renamed from arch/arm/include/asm/arch-keystone/hardware-k2e.h)0
-rw-r--r--arch/arm/mach-keystone/include/mach/hardware-k2hk.h (renamed from arch/arm/include/asm/arch-keystone/hardware-k2hk.h)0
-rw-r--r--arch/arm/mach-keystone/include/mach/hardware-k2l.h (renamed from arch/arm/include/asm/arch-keystone/hardware-k2l.h)0
-rw-r--r--arch/arm/mach-keystone/include/mach/hardware.h (renamed from arch/arm/include/asm/arch-keystone/hardware.h)0
-rw-r--r--arch/arm/mach-keystone/include/mach/i2c_defs.h (renamed from arch/arm/include/asm/arch-keystone/i2c_defs.h)0
-rw-r--r--arch/arm/mach-keystone/include/mach/mon.h (renamed from arch/arm/include/asm/arch-keystone/mon.h)0
-rw-r--r--arch/arm/mach-keystone/include/mach/msmc.h (renamed from arch/arm/include/asm/arch-keystone/msmc.h)0
-rw-r--r--arch/arm/mach-keystone/include/mach/psc_defs.h (renamed from arch/arm/include/asm/arch-keystone/psc_defs.h)0
-rw-r--r--arch/arm/mach-keystone/include/mach/xhci-keystone.h (renamed from arch/arm/include/asm/arch-keystone/xhci-keystone.h)0
-rw-r--r--arch/arm/mach-keystone/init.c (renamed from arch/arm/cpu/armv7/keystone/init.c)0
-rw-r--r--arch/arm/mach-keystone/keystone.c (renamed from arch/arm/cpu/armv7/keystone/keystone.c)0
-rw-r--r--arch/arm/mach-keystone/msmc.c (renamed from arch/arm/cpu/armv7/keystone/msmc.c)0
-rw-r--r--arch/arm/mach-keystone/psc.c (renamed from arch/arm/cpu/armv7/keystone/psc.c)0
-rw-r--r--arch/arm/mach-kirkwood/Kconfig (renamed from arch/arm/cpu/arm926ejs/kirkwood/Kconfig)0
-rw-r--r--arch/arm/mach-kirkwood/Makefile (renamed from arch/arm/cpu/arm926ejs/kirkwood/Makefile)0
-rw-r--r--arch/arm/mach-kirkwood/cache.c (renamed from arch/arm/cpu/arm926ejs/kirkwood/cache.c)0
-rw-r--r--arch/arm/mach-kirkwood/cpu.c (renamed from arch/arm/cpu/arm926ejs/kirkwood/cpu.c)0
-rw-r--r--arch/arm/mach-kirkwood/include/mach/config.h (renamed from arch/arm/include/asm/arch-kirkwood/config.h)0
-rw-r--r--arch/arm/mach-kirkwood/include/mach/cpu.h (renamed from arch/arm/include/asm/arch-kirkwood/cpu.h)0
-rw-r--r--arch/arm/mach-kirkwood/include/mach/gpio.h (renamed from arch/arm/include/asm/arch-kirkwood/gpio.h)0
-rw-r--r--arch/arm/mach-kirkwood/include/mach/kw88f6192.h (renamed from arch/arm/include/asm/arch-kirkwood/kw88f6192.h)0
-rw-r--r--arch/arm/mach-kirkwood/include/mach/kw88f6281.h (renamed from arch/arm/include/asm/arch-kirkwood/kw88f6281.h)0
-rw-r--r--arch/arm/mach-kirkwood/include/mach/mpp.h (renamed from arch/arm/include/asm/arch-kirkwood/mpp.h)0
-rw-r--r--arch/arm/mach-kirkwood/include/mach/soc.h (renamed from arch/arm/include/asm/arch-kirkwood/soc.h)0
-rw-r--r--arch/arm/mach-kirkwood/mpp.c (renamed from arch/arm/cpu/arm926ejs/kirkwood/mpp.c)0
-rw-r--r--arch/arm/mach-nomadik/Kconfig (renamed from arch/arm/cpu/arm926ejs/nomadik/Kconfig)0
-rw-r--r--arch/arm/mach-nomadik/Makefile (renamed from arch/arm/cpu/arm926ejs/nomadik/Makefile)0
-rw-r--r--arch/arm/mach-nomadik/gpio.c (renamed from arch/arm/cpu/arm926ejs/nomadik/gpio.c)0
-rw-r--r--arch/arm/mach-nomadik/include/mach/gpio.h (renamed from arch/arm/include/asm/arch-nomadik/gpio.h)0
-rw-r--r--arch/arm/mach-nomadik/include/mach/mtu.h (renamed from arch/arm/include/asm/arch-nomadik/mtu.h)0
-rw-r--r--arch/arm/mach-nomadik/reset.S (renamed from arch/arm/cpu/arm926ejs/nomadik/reset.S)0
-rw-r--r--arch/arm/mach-nomadik/timer.c (renamed from arch/arm/cpu/arm926ejs/nomadik/timer.c)0
-rw-r--r--arch/arm/mach-orion5x/Kconfig (renamed from arch/arm/cpu/arm926ejs/orion5x/Kconfig)0
-rw-r--r--arch/arm/mach-orion5x/Makefile (renamed from arch/arm/cpu/arm926ejs/orion5x/Makefile)0
-rw-r--r--arch/arm/mach-orion5x/cpu.c (renamed from arch/arm/cpu/arm926ejs/orion5x/cpu.c)0
-rw-r--r--arch/arm/mach-orion5x/dram.c (renamed from arch/arm/cpu/arm926ejs/orion5x/dram.c)0
-rw-r--r--arch/arm/mach-orion5x/include/mach/cpu.h (renamed from arch/arm/include/asm/arch-orion5x/cpu.h)0
-rw-r--r--arch/arm/mach-orion5x/include/mach/mv88f5182.h (renamed from arch/arm/include/asm/arch-orion5x/mv88f5182.h)0
-rw-r--r--arch/arm/mach-orion5x/include/mach/orion5x.h (renamed from arch/arm/include/asm/arch-orion5x/orion5x.h)0
-rw-r--r--arch/arm/mach-orion5x/lowlevel_init.S (renamed from arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S)0
-rw-r--r--arch/arm/mach-orion5x/timer.c (renamed from arch/arm/cpu/arm926ejs/orion5x/timer.c)0
-rw-r--r--arch/arm/mach-tegra/Kconfig52
-rw-r--r--arch/arm/mach-tegra/Makefile (renamed from arch/arm/cpu/tegra-common/Makefile)12
-rw-r--r--arch/arm/mach-tegra/ap.c (renamed from arch/arm/cpu/tegra-common/ap.c)0
-rw-r--r--arch/arm/mach-tegra/board.c (renamed from arch/arm/cpu/tegra-common/board.c)0
-rw-r--r--arch/arm/mach-tegra/cache.c (renamed from arch/arm/cpu/tegra-common/cache.c)0
-rw-r--r--arch/arm/mach-tegra/clock.c (renamed from arch/arm/cpu/tegra-common/clock.c)0
-rw-r--r--arch/arm/mach-tegra/cmd_enterrcm.c (renamed from arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c)0
-rw-r--r--arch/arm/mach-tegra/cpu.c (renamed from arch/arm/cpu/arm720t/tegra-common/cpu.c)0
-rw-r--r--arch/arm/mach-tegra/cpu.h (renamed from arch/arm/cpu/arm720t/tegra-common/cpu.h)0
-rw-r--r--arch/arm/mach-tegra/lowlevel_init.S (renamed from arch/arm/cpu/tegra-common/lowlevel_init.S)0
-rw-r--r--arch/arm/mach-tegra/pinmux-common.c (renamed from arch/arm/cpu/tegra-common/pinmux-common.c)0
-rw-r--r--arch/arm/mach-tegra/powergate.c (renamed from arch/arm/cpu/tegra-common/powergate.c)0
-rw-r--r--arch/arm/mach-tegra/spl.c (renamed from arch/arm/cpu/arm720t/tegra-common/spl.c)0
-rw-r--r--arch/arm/mach-tegra/sys_info.c (renamed from arch/arm/cpu/tegra-common/sys_info.c)0
-rw-r--r--arch/arm/mach-tegra/tegra114/Kconfig (renamed from arch/arm/cpu/armv7/tegra114/Kconfig)0
-rw-r--r--arch/arm/mach-tegra/tegra114/Makefile (renamed from arch/arm/cpu/tegra114-common/Makefile)5
-rw-r--r--arch/arm/mach-tegra/tegra114/clock.c (renamed from arch/arm/cpu/tegra114-common/clock.c)0
-rw-r--r--arch/arm/mach-tegra/tegra114/cpu.c (renamed from arch/arm/cpu/arm720t/tegra114/cpu.c)2
-rw-r--r--arch/arm/mach-tegra/tegra114/funcmux.c (renamed from arch/arm/cpu/tegra114-common/funcmux.c)0
-rw-r--r--arch/arm/mach-tegra/tegra114/pinmux.c (renamed from arch/arm/cpu/tegra114-common/pinmux.c)0
-rw-r--r--arch/arm/mach-tegra/tegra124/Kconfig (renamed from arch/arm/cpu/armv7/tegra124/Kconfig)0
-rw-r--r--arch/arm/mach-tegra/tegra124/Makefile (renamed from arch/arm/cpu/tegra124-common/Makefile)2
-rw-r--r--arch/arm/mach-tegra/tegra124/clock.c (renamed from arch/arm/cpu/tegra124-common/clock.c)0
-rw-r--r--arch/arm/mach-tegra/tegra124/cpu.c (renamed from arch/arm/cpu/arm720t/tegra124/cpu.c)2
-rw-r--r--arch/arm/mach-tegra/tegra124/funcmux.c (renamed from arch/arm/cpu/tegra124-common/funcmux.c)0
-rw-r--r--arch/arm/mach-tegra/tegra124/pinmux.c (renamed from arch/arm/cpu/tegra124-common/pinmux.c)0
-rw-r--r--arch/arm/mach-tegra/tegra124/xusb-padctl.c (renamed from arch/arm/cpu/tegra124-common/xusb-padctl.c)0
-rw-r--r--arch/arm/mach-tegra/tegra20/Kconfig (renamed from arch/arm/cpu/armv7/tegra20/Kconfig)0
-rw-r--r--arch/arm/mach-tegra/tegra20/Makefile (renamed from arch/arm/cpu/tegra20-common/Makefile)10
-rw-r--r--arch/arm/mach-tegra/tegra20/clock.c (renamed from arch/arm/cpu/tegra20-common/clock.c)0
-rw-r--r--arch/arm/mach-tegra/tegra20/cpu.c (renamed from arch/arm/cpu/arm720t/tegra20/cpu.c)2
-rw-r--r--arch/arm/mach-tegra/tegra20/crypto.c (renamed from arch/arm/cpu/tegra20-common/crypto.c)0
-rw-r--r--arch/arm/mach-tegra/tegra20/crypto.h (renamed from arch/arm/cpu/tegra20-common/crypto.h)0
-rw-r--r--arch/arm/mach-tegra/tegra20/display.c (renamed from arch/arm/cpu/armv7/tegra20/display.c)0
-rw-r--r--arch/arm/mach-tegra/tegra20/emc.c (renamed from arch/arm/cpu/tegra20-common/emc.c)0
-rw-r--r--arch/arm/mach-tegra/tegra20/funcmux.c (renamed from arch/arm/cpu/tegra20-common/funcmux.c)0
-rw-r--r--arch/arm/mach-tegra/tegra20/pinmux.c (renamed from arch/arm/cpu/tegra20-common/pinmux.c)0
-rw-r--r--arch/arm/mach-tegra/tegra20/pmu.c (renamed from arch/arm/cpu/tegra20-common/pmu.c)2
-rw-r--r--arch/arm/mach-tegra/tegra20/pwm.c (renamed from arch/arm/cpu/armv7/tegra20/pwm.c)0
-rw-r--r--arch/arm/mach-tegra/tegra20/warmboot.c (renamed from arch/arm/cpu/tegra20-common/warmboot.c)0
-rw-r--r--arch/arm/mach-tegra/tegra20/warmboot_avp.c (renamed from arch/arm/cpu/tegra20-common/warmboot_avp.c)0
-rw-r--r--arch/arm/mach-tegra/tegra20/warmboot_avp.h (renamed from arch/arm/cpu/tegra20-common/warmboot_avp.h)0
-rw-r--r--arch/arm/mach-tegra/tegra30/Kconfig (renamed from arch/arm/cpu/armv7/tegra30/Kconfig)0
-rw-r--r--arch/arm/mach-tegra/tegra30/Makefile (renamed from arch/arm/cpu/tegra30-common/Makefile)5
-rw-r--r--arch/arm/mach-tegra/tegra30/clock.c (renamed from arch/arm/cpu/tegra30-common/clock.c)0
-rw-r--r--arch/arm/mach-tegra/tegra30/cpu.c (renamed from arch/arm/cpu/arm720t/tegra30/cpu.c)2
-rw-r--r--arch/arm/mach-tegra/tegra30/funcmux.c (renamed from arch/arm/cpu/tegra30-common/funcmux.c)0
-rw-r--r--arch/arm/mach-tegra/tegra30/pinmux.c (renamed from arch/arm/cpu/tegra30-common/pinmux.c)0
-rw-r--r--arch/arm/mach-tegra/vpr.c (renamed from arch/arm/cpu/tegra-common/vpr.c)0
-rw-r--r--arch/arm/mach-tegra/xusb-padctl.c (renamed from arch/arm/cpu/tegra-common/xusb-padctl.c)0
-rw-r--r--arch/arm/mach-versatile/Kconfig (renamed from arch/arm/cpu/arm926ejs/versatile/Kconfig)0
-rw-r--r--arch/arm/mach-versatile/Makefile (renamed from arch/arm/cpu/arm926ejs/versatile/Makefile)0
-rw-r--r--arch/arm/mach-versatile/reset.S (renamed from arch/arm/cpu/arm926ejs/versatile/reset.S)0
-rw-r--r--arch/arm/mach-versatile/timer.c (renamed from arch/arm/cpu/arm926ejs/versatile/timer.c)0
-rw-r--r--arch/arm/mvebu-common/Makefile2
-rw-r--r--arch/arm/mvebu-common/serdes/Makefile6
-rw-r--r--arch/arm/mvebu-common/serdes/board_env_spec.h262
-rw-r--r--arch/arm/mvebu-common/serdes/high_speed_env_lib.c1572
-rw-r--r--arch/arm/mvebu-common/serdes/high_speed_env_spec.c185
-rw-r--r--arch/arm/mvebu-common/serdes/high_speed_env_spec.h87
-rw-r--r--arch/arm/mvebu-common/u-boot-spl.lds57
-rw-r--r--arch/avr32/config.mk3
-rw-r--r--arch/avr32/cpu/Makefile1
-rw-r--r--arch/avr32/cpu/at32ap700x/mmu.c8
-rw-r--r--arch/avr32/cpu/cpu.c2
-rw-r--r--arch/avr32/cpu/exception.c6
-rw-r--r--arch/avr32/cpu/mmc.c16
-rw-r--r--arch/avr32/cpu/u-boot.lds2
-rw-r--r--arch/avr32/include/asm/arch-at32ap700x/mmu.h6
-rw-r--r--arch/avr32/include/asm/config.h1
-rw-r--r--arch/avr32/include/asm/dma-mapping.h7
-rw-r--r--arch/avr32/include/asm/global_data.h1
-rw-r--r--arch/avr32/include/asm/u-boot.h10
-rw-r--r--arch/avr32/lib/Makefile3
-rw-r--r--arch/avr32/lib/board.c83
-rw-r--r--arch/avr32/lib/dram_init.c17
-rw-r--r--arch/avr32/lib/interrupts.c5
-rw-r--r--arch/blackfin/cpu/cpu.c3
-rw-r--r--arch/microblaze/config.mk5
-rw-r--r--arch/microblaze/cpu/exception.c35
-rw-r--r--arch/microblaze/cpu/interrupts.c76
-rw-r--r--arch/microblaze/cpu/irq.S121
-rw-r--r--arch/microblaze/cpu/spl.c2
-rw-r--r--arch/microblaze/cpu/start.S126
-rw-r--r--arch/microblaze/cpu/u-boot-spl.lds6
-rw-r--r--arch/microblaze/cpu/u-boot.lds12
-rw-r--r--arch/microblaze/include/asm/asm.h4
-rw-r--r--arch/microblaze/include/asm/config.h7
-rw-r--r--arch/microblaze/include/asm/microblaze_intc.h2
-rw-r--r--arch/microblaze/include/asm/u-boot.h11
-rw-r--r--arch/microblaze/lib/Makefile1
-rw-r--r--arch/microblaze/lib/board.c201
-rw-r--r--arch/mips/Kconfig6
-rw-r--r--arch/mips/Makefile8
-rw-r--r--arch/mips/cpu/Makefile9
-rw-r--r--arch/mips/cpu/cpu.c38
-rw-r--r--arch/mips/cpu/interrupts.c (renamed from arch/mips/cpu/mips32/interrupts.c)0
-rw-r--r--arch/mips/cpu/mips32/Makefile12
-rw-r--r--arch/mips/cpu/mips64/Makefile9
-rw-r--r--arch/mips/cpu/mips64/cache.S213
-rw-r--r--arch/mips/cpu/mips64/cpu.c95
-rw-r--r--arch/mips/cpu/mips64/interrupts.c22
-rw-r--r--arch/mips/cpu/mips64/start.S291
-rw-r--r--arch/mips/cpu/mips64/time.c19
-rw-r--r--arch/mips/cpu/start.S (renamed from arch/mips/cpu/mips32/start.S)137
-rw-r--r--arch/mips/cpu/time.c (renamed from arch/mips/cpu/mips32/time.c)0
-rw-r--r--arch/mips/include/asm/cacheops.h13
-rw-r--r--arch/mips/include/asm/malta.h5
-rw-r--r--arch/mips/lib/Makefile2
-rw-r--r--arch/mips/lib/cache.c (renamed from arch/mips/cpu/mips32/cpu.c)75
-rw-r--r--arch/mips/lib/cache_init.S (renamed from arch/mips/cpu/mips32/cache.S)222
-rw-r--r--arch/mips/mach-au1x00/Makefile (renamed from arch/mips/cpu/mips32/au1x00/Makefile)0
-rw-r--r--arch/mips/mach-au1x00/au1x00_eth.c (renamed from arch/mips/cpu/mips32/au1x00/au1x00_eth.c)6
-rw-r--r--arch/mips/mach-au1x00/au1x00_ide.c (renamed from arch/mips/cpu/mips32/au1x00/au1x00_ide.c)0
-rw-r--r--arch/mips/mach-au1x00/au1x00_serial.c (renamed from arch/mips/cpu/mips32/au1x00/au1x00_serial.c)0
-rw-r--r--arch/mips/mach-au1x00/au1x00_usb_ohci.c (renamed from arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c)0
-rw-r--r--arch/mips/mach-au1x00/au1x00_usb_ohci.h (renamed from arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h)0
-rw-r--r--arch/mips/mach-au1x00/config.mk (renamed from arch/mips/cpu/mips32/au1x00/config.mk)0
-rw-r--r--arch/nds32/include/asm/u-boot-nds32.h1
-rw-r--r--arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c8
-rw-r--r--arch/powerpc/cpu/ppc4xx/config.mk5
-rw-r--r--arch/powerpc/cpu/ppc4xx/cpu_init.c2
-rw-r--r--arch/powerpc/cpu/ppc4xx/start.S18
-rw-r--r--arch/powerpc/cpu/ppc4xx/u-boot.lds8
-rw-r--r--arch/powerpc/dts/Makefile11
-rw-r--r--arch/powerpc/dts/arches.dts339
-rw-r--r--arch/powerpc/dts/canyonlands.dts561
-rw-r--r--arch/powerpc/dts/glacier.dts582
-rw-r--r--arch/powerpc/include/asm/arch-ppc4xx/gpio.h7
-rw-r--r--arch/powerpc/include/asm/linkage.h7
-rw-r--r--arch/powerpc/include/asm/ppc460ex_gt.h2
-rw-r--r--arch/powerpc/lib/Makefile1
-rw-r--r--arch/powerpc/lib/stack.c31
-rw-r--r--arch/sandbox/Kconfig24
-rw-r--r--arch/sandbox/config.mk12
-rw-r--r--arch/sandbox/cpu/start.c26
-rw-r--r--arch/sandbox/cpu/state.c5
-rw-r--r--arch/sandbox/dts/sandbox.dts17
-rw-r--r--arch/sandbox/include/asm/state.h15
-rw-r--r--arch/sandbox/include/asm/u-boot-sandbox.h1
-rw-r--r--arch/x86/Kconfig111
-rw-r--r--arch/x86/cpu/Makefile2
-rw-r--r--arch/x86/cpu/baytrail/Kconfig9
-rw-r--r--arch/x86/cpu/baytrail/Makefile10
-rw-r--r--arch/x86/cpu/baytrail/early_uart.c77
-rw-r--r--arch/x86/cpu/baytrail/fsp_configs.c156
-rw-r--r--arch/x86/cpu/baytrail/pci.c46
-rw-r--r--arch/x86/cpu/baytrail/valleyview.c38
-rw-r--r--arch/x86/cpu/ivybridge/gma.c3
-rw-r--r--arch/x86/cpu/ivybridge/sdram.c2
-rw-r--r--arch/x86/cpu/quark/Kconfig126
-rw-r--r--arch/x86/cpu/quark/Makefile9
-rw-r--r--arch/x86/cpu/quark/car.S105
-rw-r--r--arch/x86/cpu/quark/dram.c134
-rw-r--r--arch/x86/cpu/quark/hte.c396
-rw-r--r--arch/x86/cpu/quark/hte.h44
-rw-r--r--arch/x86/cpu/quark/mrc.c204
-rw-r--r--arch/x86/cpu/quark/mrc_util.c1475
-rw-r--r--arch/x86/cpu/quark/mrc_util.h153
-rw-r--r--arch/x86/cpu/quark/msg_port.c77
-rw-r--r--arch/x86/cpu/quark/pci.c70
-rw-r--r--arch/x86/cpu/quark/quark.c118
-rw-r--r--arch/x86/cpu/quark/smc.c2764
-rw-r--r--arch/x86/cpu/quark/smc.h446
-rw-r--r--arch/x86/cpu/queensbay/Kconfig38
-rw-r--r--arch/x86/cpu/queensbay/Makefile4
-rw-r--r--arch/x86/cpu/queensbay/fsp_configs.c2
-rw-r--r--arch/x86/cpu/queensbay/tnc.c29
-rw-r--r--arch/x86/cpu/queensbay/tnc_pci.c17
-rw-r--r--arch/x86/cpu/queensbay/topcliff.c33
-rw-r--r--arch/x86/dts/Makefile4
-rw-r--r--arch/x86/dts/galileo.dts95
-rw-r--r--arch/x86/dts/microcode/m0130673322.dtsi3284
-rw-r--r--arch/x86/dts/minnowmax.dts45
-rw-r--r--arch/x86/dts/serial.dtsi2
-rw-r--r--arch/x86/include/asm/arch-baytrail/fsp/azalia.h39
-rw-r--r--arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h95
-rw-r--r--arch/x86/include/asm/arch-baytrail/gpio.h13
-rw-r--r--arch/x86/include/asm/arch-ivybridge/sandybridge.h2
-rw-r--r--arch/x86/include/asm/arch-quark/device.h28
-rw-r--r--arch/x86/include/asm/arch-quark/gpio.h13
-rw-r--r--arch/x86/include/asm/arch-quark/mrc.h187
-rw-r--r--arch/x86/include/asm/arch-quark/msg_port.h106
-rw-r--r--arch/x86/include/asm/arch-quark/quark.h72
-rw-r--r--arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h2
-rw-r--r--arch/x86/include/asm/fsp/fsp_api.h (renamed from arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h)6
-rw-r--r--arch/x86/include/asm/fsp/fsp_bootmode.h (renamed from arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h)0
-rw-r--r--arch/x86/include/asm/fsp/fsp_ffs.h (renamed from arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h)0
-rw-r--r--arch/x86/include/asm/fsp/fsp_fv.h (renamed from arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h)0
-rw-r--r--arch/x86/include/asm/fsp/fsp_hob.h (renamed from arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h)0
-rw-r--r--arch/x86/include/asm/fsp/fsp_infoheader.h (renamed from arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h)0
-rw-r--r--arch/x86/include/asm/fsp/fsp_platform.h (renamed from arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h)0
-rw-r--r--arch/x86/include/asm/fsp/fsp_support.h (renamed from arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h)6
-rw-r--r--arch/x86/include/asm/fsp/fsp_types.h (renamed from arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h)0
-rw-r--r--arch/x86/include/asm/pci.h13
-rw-r--r--arch/x86/include/asm/u-boot-x86.h9
-rw-r--r--arch/x86/lib/Makefile1
-rw-r--r--arch/x86/lib/cmd_hob.c2
-rw-r--r--arch/x86/lib/fsp/Makefile10
-rw-r--r--arch/x86/lib/fsp/fsp_car.S (renamed from arch/x86/cpu/queensbay/tnc_car.S)0
-rw-r--r--arch/x86/lib/fsp/fsp_common.c55
-rw-r--r--arch/x86/lib/fsp/fsp_dram.c (renamed from arch/x86/cpu/queensbay/tnc_dram.c)2
-rw-r--r--arch/x86/lib/fsp/fsp_support.c (renamed from arch/x86/cpu/queensbay/fsp_support.c)20
-rw-r--r--arch/x86/lib/pci_type1.c7
549 files changed, 18395 insertions, 3339 deletions
diff --git a/arch/Kconfig b/arch/Kconfig
index f63cc5a..3d419bc 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -4,6 +4,7 @@ choice
config ARC
bool "ARC architecture"
+ select HAVE_PRIVATE_LIBGCC
config ARM
bool "ARM architecture"
@@ -39,6 +40,7 @@ config OPENRISC
config PPC
bool "PowerPC architecture"
select HAVE_PRIVATE_LIBGCC
+ select SUPPORT_OF_CONTROL
config SANDBOX
bool "Sandbox"
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index c6b1efe..24f5c02 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -4,8 +4,131 @@ menu "ARC architecture"
config SYS_ARCH
default "arc"
+config USE_PRIVATE_LIBGCC
+ default y
+
config SYS_CPU
- default "arcv1"
+ default "arcv1" if ISA_ARCOMPACT
+ default "arcv2" if ISA_ARCV2
+
+choice
+ prompt "ARC Instruction Set"
+ default ISA_ARCOMPACT
+
+config ISA_ARCOMPACT
+ bool "ARCompact ISA"
+ help
+ The original ARC ISA of ARC600/700 cores
+
+config ISA_ARCV2
+ bool "ARC ISA v2"
+ help
+ ISA for the Next Generation ARC-HS cores
+
+endchoice
+
+choice
+ prompt "CPU selection"
+ default CPU_ARC770D if ISA_ARCOMPACT
+ default CPU_ARCHS38 if ISA_ARCV2
+
+config CPU_ARC750D
+ bool "ARC 750D"
+ select ARC_MMU_V2
+ depends on ISA_ARCOMPACT
+ help
+ Choose this option to build an U-Boot for ARC750D CPU.
+
+config CPU_ARC770D
+ bool "ARC 770D"
+ select ARC_MMU_V3
+ depends on ISA_ARCOMPACT
+ help
+ Choose this option to build an U-Boot for ARC770D CPU.
+
+config CPU_ARCEM6
+ bool "ARC EM6"
+ select ARC_MMU_ABSENT
+ depends on ISA_ARCV2
+ help
+ Next Generation ARC Core based on ISA-v2 ISA without MMU.
+
+config CPU_ARCHS36
+ bool "ARC HS36"
+ select ARC_MMU_ABSENT
+ depends on ISA_ARCV2
+ help
+ Next Generation ARC Core based on ISA-v2 ISA without MMU.
+
+config CPU_ARCHS38
+ bool "ARC HS38"
+ select ARC_MMU_V4
+ depends on ISA_ARCV2
+ help
+ Next Generation ARC Core based on ISA-v2 ISA with MMU.
+
+endchoice
+
+choice
+ prompt "MMU Version"
+ default ARC_MMU_V3 if CPU_ARC770D
+ default ARC_MMU_V2 if CPU_ARC750D
+ default ARC_MMU_ABSENT if CPU_ARCEM6
+ default ARC_MMU_ABSENT if CPU_ARCHS36
+ default ARC_MMU_V4 if CPU_ARCHS38
+
+config ARC_MMU_ABSENT
+ bool "No MMU"
+ help
+ No MMU
+
+config ARC_MMU_V2
+ bool "MMU v2"
+ depends on CPU_ARC750D
+ help
+ Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
+ when 2 D-TLB and 1 I-TLB entries index into same 2way set.
+
+config ARC_MMU_V3
+ bool "MMU v3"
+ depends on CPU_ARC770D
+ help
+ Introduced with ARC700 4.10: New Features
+ Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
+ Shared Address Spaces (SASID)
+
+config ARC_MMU_V4
+ bool "MMU v4"
+ depends on CPU_ARCHS38
+ help
+ Introduced as a part of ARC HS38 release.
+
+endchoice
+
+config CPU_BIG_ENDIAN
+ bool "Enable Big Endian Mode"
+ default n
+ help
+ Build kernel for Big Endian Mode of ARC CPU
+
+config SYS_ICACHE_OFF
+ bool "Do not use Instruction Cache"
+ default n
+
+config SYS_DCACHE_OFF
+ bool "Do not use Data Cache"
+ default n
+
+config ARC_CACHE_LINE_SHIFT
+ int "Cache Line Length (as power of 2)"
+ range 5 7
+ default "6"
+ depends on !SYS_DCACHE_OFF || !SYS_DCACHE_OFF
+ help
+ Starting with ARC700 4.9, Cache line length is configurable,
+ This option specifies "N", with Line-len = 2 power N
+ So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
+ Linux only supports same line lengths for I and D caches.
choice
prompt "Target select"
@@ -16,9 +139,6 @@ config TARGET_TB100
config TARGET_ARCANGEL4
bool "Support arcangel4"
-config TARGET_ARCANGEL4_BE
- bool "Support arcangel4-be"
-
config TARGET_AXS101
bool "Support axs101"
diff --git a/arch/arc/config.mk b/arch/arc/config.mk
index 5321987..4fcd407 100644
--- a/arch/arc/config.mk
+++ b/arch/arc/config.mk
@@ -4,17 +4,22 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifndef CONFIG_SYS_BIG_ENDIAN
+ifndef CONFIG_CPU_BIG_ENDIAN
CONFIG_SYS_LITTLE_ENDIAN = 1
+else
+CONFIG_SYS_BIG_ENDIAN = 1
endif
ifdef CONFIG_SYS_LITTLE_ENDIAN
ARC_CROSS_COMPILE := arc-buildroot-linux-uclibc-
+PLATFORM_LDFLAGS += -EL
+PLATFORM_CPPFLAGS += -mlittle-endian
endif
ifdef CONFIG_SYS_BIG_ENDIAN
ARC_CROSS_COMPILE := arceb-buildroot-linux-uclibc-
PLATFORM_LDFLAGS += -EB
+PLATFORM_CPPFLAGS += -mbig-endian
endif
ifeq ($(CROSS_COMPILE),)
@@ -25,6 +30,26 @@ ifdef CONFIG_ARC_MMU_VER
CONFIG_MMU = 1
endif
+ifdef CONFIG_CPU_ARC750D
+PLATFORM_CPPFLAGS += -marc700
+endif
+
+ifdef CONFIG_CPU_ARC770D
+PLATFORM_CPPFLAGS += -marc700 -mlock -mswape
+endif
+
+ifdef CONFIG_CPU_ARCEM6
+PLATFORM_CPPFLAGS += -marcem
+endif
+
+ifdef CONFIG_CPU_ARCHS34
+PLATFORM_CPPFLAGS += -marchs
+endif
+
+ifdef CONFIG_CPU_ARCHS38
+PLATFORM_CPPFLAGS += -marchs
+endif
+
PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
# Needed for relocation
diff --git a/arch/arc/cpu/arcv1/config.mk b/arch/arc/cpu/arcv1/config.mk
deleted file mode 100644
index 3206ff4..0000000
--- a/arch/arc/cpu/arcv1/config.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mA7
diff --git a/arch/arc/cpu/arcv2/Makefile b/arch/arc/cpu/arcv2/Makefile
new file mode 100644
index 0000000..cc69e5a
--- /dev/null
+++ b/arch/arc/cpu/arcv2/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += start.o
diff --git a/arch/arc/cpu/arcv2/start.S b/arch/arc/cpu/arcv2/start.S
new file mode 100644
index 0000000..3ce6896
--- /dev/null
+++ b/arch/arc/cpu/arcv2/start.S
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/arcregs.h>
+
+/*
+ * Note on the LD/ST addressing modes with address register write-back
+ *
+ * LD.a same as LD.aw
+ *
+ * LD.a reg1, [reg2, x] => Pre Incr
+ * Eff Addr for load = [reg2 + x]
+ *
+ * LD.ab reg1, [reg2, x] => Post Incr
+ * Eff Addr for load = [reg2]
+ */
+
+.macro PUSH reg
+ st.a \reg, [%sp, -4]
+.endm
+
+.macro PUSHAX aux
+ lr %r9, [\aux]
+ PUSH %r9
+.endm
+
+.macro SAVE_R1_TO_R24
+ PUSH %r1
+ PUSH %r2
+ PUSH %r3
+ PUSH %r4
+ PUSH %r5
+ PUSH %r6
+ PUSH %r7
+ PUSH %r8
+ PUSH %r9
+ PUSH %r10
+ PUSH %r11
+ PUSH %r12
+ PUSH %r13
+ PUSH %r14
+ PUSH %r15
+ PUSH %r16
+ PUSH %r17
+ PUSH %r18
+ PUSH %r19
+ PUSH %r20
+ PUSH %r21
+ PUSH %r22
+ PUSH %r23
+ PUSH %r24
+.endm
+
+.macro SAVE_ALL_SYS
+ /* saving %r0 to reg->r0 in advance since weread %ecr into it */
+ st %r0, [%sp, -8]
+ lr %r0, [%ecr] /* all stack addressing is manual so far */
+ st %r0, [%sp]
+ st %sp, [%sp, -4]
+ /* now move %sp to reg->r0 position so we can do "push" automatically */
+ sub %sp, %sp, 8
+
+ SAVE_R1_TO_R24
+ PUSH %r25
+ PUSH %gp
+ PUSH %fp
+ PUSH %blink
+ PUSHAX %eret
+ PUSHAX %erstatus
+ PUSH %lp_count
+ PUSHAX %lp_end
+ PUSHAX %lp_start
+ PUSHAX %erbta
+.endm
+
+.macro SAVE_EXCEPTION_SOURCE
+#ifdef CONFIG_MMU
+ /* If MMU exists exception faulting address is loaded in EFA reg */
+ lr %r0, [%efa]
+#else
+ /* Otherwise in ERET (exception return) reg */
+ lr %r0, [%eret]
+#endif
+.endm
+
+.section .ivt, "a",@progbits
+.align 4
+ /* Critical system events */
+.word _start /* 0 - 0x000 */
+.word memory_error /* 1 - 0x008 */
+.word instruction_error /* 2 - 0x010 */
+
+ /* Exceptions */
+.word EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */
+.word EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */
+.word EV_TLBMissD /* 0x110, Data TLB miss (0x22) */
+.word EV_TLBProtV /* 0x118, Protection Violation (0x23)
+ or Misaligned Access */
+.word EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */
+.word EV_Trap /* 0x128, Trap exception (0x25) */
+.word EV_Extension /* 0x130, Extn Intruction Excp (0x26) */
+
+ /* Device interrupts */
+.rept 29
+ j interrupt_handler /* 3:31 - 0x018:0xF8 */
+.endr
+
+.text
+.globl _start
+_start:
+ /* Setup interrupt vector base that matches "__text_start" */
+ sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
+
+ /* Setup stack pointer */
+ mov %sp, CONFIG_SYS_INIT_SP_ADDR
+ mov %fp, %sp
+
+ /* Clear bss */
+ mov %r0, __bss_start
+ mov %r1, __bss_end
+
+clear_bss:
+ st.ab 0, [%r0, 4]
+ brlt %r0, %r1, clear_bss
+
+ /* Zero the one and only argument of "board_init_f" */
+ mov_s %r0, 0
+ j board_init_f
+
+memory_error:
+ SAVE_ALL_SYS
+ SAVE_EXCEPTION_SOURCE
+ mov %r1, %sp
+ j do_memory_error
+
+instruction_error:
+ SAVE_ALL_SYS
+ SAVE_EXCEPTION_SOURCE
+ mov %r1, %sp
+ j do_instruction_error
+
+interrupt_handler:
+ /* Todo - save and restore CPU context when interrupts will be in use */
+ bl do_interrupt_handler
+ rtie
+
+EV_MachineCheck:
+ SAVE_ALL_SYS
+ SAVE_EXCEPTION_SOURCE
+ mov %r1, %sp
+ j do_machine_check_fault
+
+EV_TLBMissI:
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_itlb_miss
+
+EV_TLBMissD:
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_dtlb_miss
+
+EV_TLBProtV:
+ SAVE_ALL_SYS
+ SAVE_EXCEPTION_SOURCE
+ mov %r1, %sp
+ j do_tlb_prot_violation
+
+EV_PrivilegeV:
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_privilege_violation
+
+EV_Trap:
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_trap
+
+EV_Extension:
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_extension
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r0 = start_addr_sp
+ * r1 = new__gd
+ * r2 = relocaddr
+ */
+.align 4
+.globl relocate_code
+relocate_code:
+ /*
+ * r0-r12 might be clobbered by C functions
+ * so we use r13-r16 for storage here
+ */
+ mov %r13, %r0 /* save addr_sp */
+ mov %r14, %r1 /* save addr of gd */
+ mov %r15, %r2 /* save addr of destination */
+
+ mov %r16, %r2 /* %r9 - relocation offset */
+ sub %r16, %r16, __image_copy_start
+
+/* Set up the stack */
+stack_setup:
+ mov %sp, %r13
+ mov %fp, %sp
+
+/* Check if monitor is loaded right in place for relocation */
+ mov %r0, __image_copy_start
+ cmp %r0, %r15 /* skip relocation if code loaded */
+ bz do_board_init_r /* in target location already */
+
+/* Copy data (__image_copy_start - __image_copy_end) to new location */
+ mov %r1, %r15
+ mov %r2, __image_copy_end
+ sub %r2, %r2, %r0 /* r3 <- amount of bytes to copy */
+ asr %r2, %r2, 2 /* r3 <- amount of words to copy */
+ mov %lp_count, %r2
+ lp copy_end
+ ld.ab %r2,[%r0,4]
+ st.ab %r2,[%r1,4]
+copy_end:
+
+/* Fix relocations related issues */
+ bl do_elf_reloc_fixups
+#ifndef CONFIG_SYS_ICACHE_OFF
+ bl invalidate_icache_all
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ bl flush_dcache_all
+#endif
+
+/* Update position of intterupt vector table */
+ lr %r0, [ARC_AUX_INTR_VEC_BASE] /* Read current position */
+ add %r0, %r0, %r16 /* Update address */
+ sr %r0, [ARC_AUX_INTR_VEC_BASE] /* Write new position */
+
+do_board_init_r:
+/* Prepare for exection of "board_init_r" in relocated monitor */
+ mov %r2, board_init_r /* old address of "board_init_r()" */
+ add %r2, %r2, %r16 /* new address of "board_init_r()" */
+ mov %r0, %r14 /* 1-st parameter: gd_t */
+ mov %r1, %r15 /* 2-nd parameter: dest_addr */
+ j [%r2]
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 8ace87f..6a36a81 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -7,6 +7,8 @@
#ifndef _ASM_ARC_ARCREGS_H
#define _ASM_ARC_ARCREGS_H
+#include <asm/cache.h>
+
/*
* ARC architecture has additional address space - auxiliary registers.
* These registers are mostly used for configuration purposes.
@@ -21,7 +23,7 @@
#define ARC_AUX_IC_IVIC 0x10
#define ARC_AUX_IC_CTRL 0x11
#define ARC_AUX_IC_IVIL 0x19
-#if (CONFIG_ARC_MMU_VER > 2)
+#if (CONFIG_ARC_MMU_VER == 3)
#define ARC_AUX_IC_PTAG 0x1E
#endif
#define ARC_BCR_IC_BUILD 0x77
@@ -40,7 +42,7 @@
#define ARC_AUX_DC_IVDL 0x4A
#define ARC_AUX_DC_FLSH 0x4B
#define ARC_AUX_DC_FLDL 0x4C
-#if (CONFIG_ARC_MMU_VER > 2)
+#if (CONFIG_ARC_MMU_VER == 3)
#define ARC_AUX_DC_PTAG 0x5C
#endif
#define ARC_BCR_DC_BUILD 0x72
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index 16e7568..8a77cd9 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -9,15 +9,22 @@
#include <config.h>
-/*
- * The current upper bound for ARC L1 data cache line sizes is 128 bytes.
- * We use that value for aligning DMA buffers unless the board config has
- * specified an alternate cache line size.
- */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#ifdef CONFIG_ARC_CACHE_LINE_SHIFT
+#define CONFIG_SYS_CACHELINE_SIZE (1 << CONFIG_ARC_CACHE_LINE_SHIFT)
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#else
-#define ARCH_DMA_MINALIGN 128
+/* Satisfy users of ARCH_DMA_MINALIGN */
+#define ARCH_DMA_MINALIGN 128
+#endif
+
+#if defined(ARC_MMU_ABSENT)
+#define CONFIG_ARC_MMU_VER 0
+#elif defined(CONFIG_ARC_MMU_V2)
+#define CONFIG_ARC_MMU_VER 2
+#elif defined(CONFIG_ARC_MMU_V3)
+#define CONFIG_ARC_MMU_VER 3
+#elif defined(CONFIG_ARC_MMU_V4)
+#define CONFIG_ARC_MMU_VER 4
#endif
#endif /* __ASM_ARC_CACHE_H */
diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h
index e5be078..b4e9099 100644
--- a/arch/arc/include/asm/config.h
+++ b/arch/arc/include/asm/config.h
@@ -7,8 +7,10 @@
#ifndef __ASM_ARC_CONFIG_H_
#define __ASM_ARC_CONFIG_H_
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_LMB
diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile
index bae4419..b8028c9 100644
--- a/arch/arc/lib/Makefile
+++ b/arch/arc/lib/Makefile
@@ -20,3 +20,5 @@ obj-y += reset.o
obj-y += timer.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
+
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _millicodethunk.o libgcc2.o
diff --git a/arch/arc/lib/_millicodethunk.S b/arch/arc/lib/_millicodethunk.S
new file mode 100644
index 0000000..b332416
--- /dev/null
+++ b/arch/arc/lib/_millicodethunk.S
@@ -0,0 +1,226 @@
+/*
+ * Copyright (C) 1995, 1997, 2007-2013 Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+ /* ANSI concatenation macros. */
+
+ #define CONCAT1(a, b) CONCAT2(a, b)
+ #define CONCAT2(a, b) a ## b
+
+ /* Use the right prefix for global labels. */
+
+ #define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
+
+#ifndef WORKING_ASSEMBLER
+#define abs_l abs
+#define asl_l asl
+#define mov_l mov
+#endif
+
+#define FUNC(X) .type SYM(X),@function
+#define HIDDEN_FUNC(X) FUNC(X)` .hidden X
+#define ENDFUNC0(X) .Lfe_##X: .size X,.Lfe_##X-X
+#define ENDFUNC(X) ENDFUNC0(X)
+
+ .section .text
+ .align 4
+ .global SYM(__st_r13_to_r15)
+ .global SYM(__st_r13_to_r16)
+ .global SYM(__st_r13_to_r17)
+ .global SYM(__st_r13_to_r18)
+ .global SYM(__st_r13_to_r19)
+ .global SYM(__st_r13_to_r20)
+ .global SYM(__st_r13_to_r21)
+ .global SYM(__st_r13_to_r22)
+ .global SYM(__st_r13_to_r23)
+ .global SYM(__st_r13_to_r24)
+ .global SYM(__st_r13_to_r25)
+ HIDDEN_FUNC(__st_r13_to_r15)
+ HIDDEN_FUNC(__st_r13_to_r16)
+ HIDDEN_FUNC(__st_r13_to_r17)
+ HIDDEN_FUNC(__st_r13_to_r18)
+ HIDDEN_FUNC(__st_r13_to_r19)
+ HIDDEN_FUNC(__st_r13_to_r20)
+ HIDDEN_FUNC(__st_r13_to_r21)
+ HIDDEN_FUNC(__st_r13_to_r22)
+ HIDDEN_FUNC(__st_r13_to_r23)
+ HIDDEN_FUNC(__st_r13_to_r24)
+ HIDDEN_FUNC(__st_r13_to_r25)
+ .align 4
+SYM(__st_r13_to_r25):
+ st r25, [sp,48]
+SYM(__st_r13_to_r24):
+ st r24, [sp,44]
+SYM(__st_r13_to_r23):
+ st r23, [sp,40]
+SYM(__st_r13_to_r22):
+ st r22, [sp,36]
+SYM(__st_r13_to_r21):
+ st r21, [sp,32]
+SYM(__st_r13_to_r20):
+ st r20, [sp,28]
+SYM(__st_r13_to_r19):
+ st r19, [sp,24]
+SYM(__st_r13_to_r18):
+ st r18, [sp,20]
+SYM(__st_r13_to_r17):
+ st r17, [sp,16]
+SYM(__st_r13_to_r16):
+ st r16, [sp,12]
+SYM(__st_r13_to_r15):
+#ifdef __ARC700__
+ st r15, [sp,8] ; minimum function size to avoid stall: 6 bytes.
+#else
+ st_s r15, [sp,8]
+#endif
+ st_s r14, [sp,4]
+ j_s.d [%blink]
+ st_s r13, [sp,0]
+ ENDFUNC(__st_r13_to_r15)
+ ENDFUNC(__st_r13_to_r16)
+ ENDFUNC(__st_r13_to_r17)
+ ENDFUNC(__st_r13_to_r18)
+ ENDFUNC(__st_r13_to_r19)
+ ENDFUNC(__st_r13_to_r20)
+ ENDFUNC(__st_r13_to_r21)
+ ENDFUNC(__st_r13_to_r22)
+ ENDFUNC(__st_r13_to_r23)
+ ENDFUNC(__st_r13_to_r24)
+ ENDFUNC(__st_r13_to_r25)
+
+ .section .text
+ .align 4
+; ==================================
+; the loads
+
+ .global SYM(__ld_r13_to_r15)
+ .global SYM(__ld_r13_to_r16)
+ .global SYM(__ld_r13_to_r17)
+ .global SYM(__ld_r13_to_r18)
+ .global SYM(__ld_r13_to_r19)
+ .global SYM(__ld_r13_to_r20)
+ .global SYM(__ld_r13_to_r21)
+ .global SYM(__ld_r13_to_r22)
+ .global SYM(__ld_r13_to_r23)
+ .global SYM(__ld_r13_to_r24)
+ .global SYM(__ld_r13_to_r25)
+ HIDDEN_FUNC(__ld_r13_to_r15)
+ HIDDEN_FUNC(__ld_r13_to_r16)
+ HIDDEN_FUNC(__ld_r13_to_r17)
+ HIDDEN_FUNC(__ld_r13_to_r18)
+ HIDDEN_FUNC(__ld_r13_to_r19)
+ HIDDEN_FUNC(__ld_r13_to_r20)
+ HIDDEN_FUNC(__ld_r13_to_r21)
+ HIDDEN_FUNC(__ld_r13_to_r22)
+ HIDDEN_FUNC(__ld_r13_to_r23)
+ HIDDEN_FUNC(__ld_r13_to_r24)
+ HIDDEN_FUNC(__ld_r13_to_r25)
+SYM(__ld_r13_to_r25):
+ ld r25, [sp,48]
+SYM(__ld_r13_to_r24):
+ ld r24, [sp,44]
+SYM(__ld_r13_to_r23):
+ ld r23, [sp,40]
+SYM(__ld_r13_to_r22):
+ ld r22, [sp,36]
+SYM(__ld_r13_to_r21):
+ ld r21, [sp,32]
+SYM(__ld_r13_to_r20):
+ ld r20, [sp,28]
+SYM(__ld_r13_to_r19):
+ ld r19, [sp,24]
+SYM(__ld_r13_to_r18):
+ ld r18, [sp,20]
+SYM(__ld_r13_to_r17):
+ ld r17, [sp,16]
+SYM(__ld_r13_to_r16):
+ ld r16, [sp,12]
+SYM(__ld_r13_to_r15):
+#ifdef __ARC700__
+ ld r15, [sp,8] ; minimum function size to avoid stall: 6 bytes.
+#else
+ ld_s r15, [sp,8]
+#endif
+ ld_s r14, [sp,4]
+ j_s.d [%blink]
+ ld_s r13, [sp,0]
+ ENDFUNC(__ld_r13_to_r15)
+ ENDFUNC(__ld_r13_to_r16)
+ ENDFUNC(__ld_r13_to_r17)
+ ENDFUNC(__ld_r13_to_r18)
+ ENDFUNC(__ld_r13_to_r19)
+ ENDFUNC(__ld_r13_to_r20)
+ ENDFUNC(__ld_r13_to_r21)
+ ENDFUNC(__ld_r13_to_r22)
+ ENDFUNC(__ld_r13_to_r23)
+ ENDFUNC(__ld_r13_to_r24)
+ ENDFUNC(__ld_r13_to_r25)
+
+ .global SYM(__ld_r13_to_r14_ret)
+ .global SYM(__ld_r13_to_r15_ret)
+ .global SYM(__ld_r13_to_r16_ret)
+ .global SYM(__ld_r13_to_r17_ret)
+ .global SYM(__ld_r13_to_r18_ret)
+ .global SYM(__ld_r13_to_r19_ret)
+ .global SYM(__ld_r13_to_r20_ret)
+ .global SYM(__ld_r13_to_r21_ret)
+ .global SYM(__ld_r13_to_r22_ret)
+ .global SYM(__ld_r13_to_r23_ret)
+ .global SYM(__ld_r13_to_r24_ret)
+ .global SYM(__ld_r13_to_r25_ret)
+ HIDDEN_FUNC(__ld_r13_to_r14_ret)
+ HIDDEN_FUNC(__ld_r13_to_r15_ret)
+ HIDDEN_FUNC(__ld_r13_to_r16_ret)
+ HIDDEN_FUNC(__ld_r13_to_r17_ret)
+ HIDDEN_FUNC(__ld_r13_to_r18_ret)
+ HIDDEN_FUNC(__ld_r13_to_r19_ret)
+ HIDDEN_FUNC(__ld_r13_to_r20_ret)
+ HIDDEN_FUNC(__ld_r13_to_r21_ret)
+ HIDDEN_FUNC(__ld_r13_to_r22_ret)
+ HIDDEN_FUNC(__ld_r13_to_r23_ret)
+ HIDDEN_FUNC(__ld_r13_to_r24_ret)
+ HIDDEN_FUNC(__ld_r13_to_r25_ret)
+ .section .text
+ .align 4
+SYM(__ld_r13_to_r25_ret):
+ ld r25, [sp,48]
+SYM(__ld_r13_to_r24_ret):
+ ld r24, [sp,44]
+SYM(__ld_r13_to_r23_ret):
+ ld r23, [sp,40]
+SYM(__ld_r13_to_r22_ret):
+ ld r22, [sp,36]
+SYM(__ld_r13_to_r21_ret):
+ ld r21, [sp,32]
+SYM(__ld_r13_to_r20_ret):
+ ld r20, [sp,28]
+SYM(__ld_r13_to_r19_ret):
+ ld r19, [sp,24]
+SYM(__ld_r13_to_r18_ret):
+ ld r18, [sp,20]
+SYM(__ld_r13_to_r17_ret):
+ ld r17, [sp,16]
+SYM(__ld_r13_to_r16_ret):
+ ld r16, [sp,12]
+SYM(__ld_r13_to_r15_ret):
+ ld r15, [sp,8]
+SYM(__ld_r13_to_r14_ret):
+ ld blink,[sp,r12]
+ ld_s r14, [sp,4]
+ ld.ab r13, [sp,r12]
+ j_s.d [%blink]
+ add_s sp,sp,4
+ ENDFUNC(__ld_r13_to_r14_ret)
+ ENDFUNC(__ld_r13_to_r15_ret)
+ ENDFUNC(__ld_r13_to_r16_ret)
+ ENDFUNC(__ld_r13_to_r17_ret)
+ ENDFUNC(__ld_r13_to_r18_ret)
+ ENDFUNC(__ld_r13_to_r19_ret)
+ ENDFUNC(__ld_r13_to_r20_ret)
+ ENDFUNC(__ld_r13_to_r21_ret)
+ ENDFUNC(__ld_r13_to_r22_ret)
+ ENDFUNC(__ld_r13_to_r23_ret)
+ ENDFUNC(__ld_r13_to_r24_ret)
+ ENDFUNC(__ld_r13_to_r25_ret)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index fa19a13..a227723 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -6,6 +6,7 @@
#include <config.h>
#include <asm/arcregs.h>
+#include <asm/cache.h>
/* Bit values in IC_CTRL */
#define IC_CTRL_CACHE_DISABLE (1 << 0)
@@ -101,7 +102,7 @@ void flush_dcache_all(void)
#ifndef CONFIG_SYS_DCACHE_OFF
static void dcache_flush_line(unsigned addr)
{
-#if (CONFIG_ARC_MMU_VER > 2)
+#if (CONFIG_ARC_MMU_VER == 3)
write_aux_reg(ARC_AUX_DC_PTAG, addr);
#endif
write_aux_reg(ARC_AUX_DC_FLDL, addr);
@@ -115,7 +116,7 @@ static void dcache_flush_line(unsigned addr)
* Invalidate I$ for addresses range just flushed from D$.
* If we try to execute data flushed above it will be valid/correct
*/
-#if (CONFIG_ARC_MMU_VER > 2)
+#if (CONFIG_ARC_MMU_VER == 3)
write_aux_reg(ARC_AUX_IC_PTAG, addr);
#endif
write_aux_reg(ARC_AUX_IC_IVIL, addr);
@@ -145,7 +146,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
-#if (CONFIG_ARC_MMU_VER > 2)
+#if (CONFIG_ARC_MMU_VER == 3)
write_aux_reg(ARC_AUX_DC_PTAG, addr);
#endif
write_aux_reg(ARC_AUX_DC_IVDL, addr);
diff --git a/arch/arc/lib/libgcc2.c b/arch/arc/lib/libgcc2.c
new file mode 100644
index 0000000..d5ad327
--- /dev/null
+++ b/arch/arc/lib/libgcc2.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright (C) 1989-2013 Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "libgcc2.h"
+
+DWtype
+__ashldi3(DWtype u, shift_count_type b)
+{
+ if (b == 0)
+ return u;
+
+ const DWunion uu = {.ll = u};
+ const shift_count_type bm = W_TYPE_SIZE - b;
+ DWunion w;
+
+ if (bm <= 0) {
+ w.s.low = 0;
+ w.s.high = (UWtype)uu.s.low << -bm;
+ } else {
+ const UWtype carries = (UWtype) uu.s.low >> bm;
+
+ w.s.low = (UWtype)uu.s.low << b;
+ w.s.high = ((UWtype)uu.s.high << b) | carries;
+ }
+
+ return w.ll;
+}
+
+DWtype
+__ashrdi3(DWtype u, shift_count_type b)
+{
+ if (b == 0)
+ return u;
+
+ const DWunion uu = {.ll = u};
+ const shift_count_type bm = W_TYPE_SIZE - b;
+ DWunion w;
+
+ if (bm <= 0) {
+ /* w.s.high = 1..1 or 0..0 */
+ w.s.high = uu.s.high >> (W_TYPE_SIZE - 1);
+ w.s.low = uu.s.high >> -bm;
+ } else {
+ const UWtype carries = (UWtype) uu.s.high << bm;
+
+ w.s.high = uu.s.high >> b;
+ w.s.low = ((UWtype)uu.s.low >> b) | carries;
+ }
+
+ return w.ll;
+}
+
+DWtype
+__lshrdi3(DWtype u, shift_count_type b)
+{
+ if (b == 0)
+ return u;
+
+ const DWunion uu = {.ll = u};
+ const shift_count_type bm = W_TYPE_SIZE - b;
+ DWunion w;
+
+ if (bm <= 0) {
+ w.s.high = 0;
+ w.s.low = (UWtype)uu.s.high >> -bm;
+ } else {
+ const UWtype carries = (UWtype)uu.s.high << bm;
+
+ w.s.high = (UWtype)uu.s.high >> b;
+ w.s.low = ((UWtype)uu.s.low >> b) | carries;
+ }
+
+ return w.ll;
+}
+
+unsigned long
+udivmodsi4(unsigned long num, unsigned long den, int modwanted)
+{
+ unsigned long bit = 1;
+ unsigned long res = 0;
+
+ while (den < num && bit && !(den & (1L<<31))) {
+ den <<= 1;
+ bit <<= 1;
+ }
+
+ while (bit) {
+ if (num >= den) {
+ num -= den;
+ res |= bit;
+ }
+ bit >>= 1;
+ den >>= 1;
+ }
+
+ if (modwanted)
+ return num;
+
+ return res;
+}
+
+long
+__divsi3(long a, long b)
+{
+ int neg = 0;
+ long res;
+
+ if (a < 0) {
+ a = -a;
+ neg = !neg;
+ }
+
+ if (b < 0) {
+ b = -b;
+ neg = !neg;
+ }
+
+ res = udivmodsi4(a, b, 0);
+
+ if (neg)
+ res = -res;
+
+ return res;
+}
+
+long
+__modsi3(long a, long b)
+{
+ int neg = 0;
+ long res;
+
+ if (a < 0) {
+ a = -a;
+ neg = 1;
+ }
+
+ if (b < 0)
+ b = -b;
+
+ res = udivmodsi4(a, b, 1);
+
+ if (neg)
+ res = -res;
+
+ return res;
+}
+
+long
+__udivsi3(long a, long b)
+{
+ return udivmodsi4(a, b, 0);
+}
+
+long
+__umodsi3(long a, long b)
+{
+ return udivmodsi4(a, b, 1);
+}
diff --git a/arch/arc/lib/libgcc2.h b/arch/arc/lib/libgcc2.h
new file mode 100644
index 0000000..8813c3b
--- /dev/null
+++ b/arch/arc/lib/libgcc2.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 1989-2013 Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_LIBGCC_H
+#define __ASM_LIBGCC_H
+
+#define UNITS_PER_WORD 4 /* for ARC */
+#define BITS_PER_UNIT 8 /* for ARC */
+
+#define W_TYPE_SIZE (4 * BITS_PER_UNIT)
+
+#define MIN_UNITS_PER_WORD UNITS_PER_WORD
+
+/* Work out the largest "word" size that we can deal with on this target. */
+#if MIN_UNITS_PER_WORD > 4
+# define LIBGCC2_MAX_UNITS_PER_WORD 8
+#elif (MIN_UNITS_PER_WORD > 2 \
+ || (MIN_UNITS_PER_WORD > 1 && __SIZEOF_LONG_LONG__ > 4))
+# define LIBGCC2_MAX_UNITS_PER_WORD 4
+#else
+# define LIBGCC2_MAX_UNITS_PER_WORD MIN_UNITS_PER_WORD
+#endif
+
+/* Work out what word size we are using for this compilation.
+ The value can be set on the command line. */
+#ifndef LIBGCC2_UNITS_PER_WORD
+#define LIBGCC2_UNITS_PER_WORD LIBGCC2_MAX_UNITS_PER_WORD
+#endif
+
+typedef int QItype __attribute__ ((mode (QI)));
+typedef unsigned int UQItype __attribute__ ((mode (QI)));
+typedef int HItype __attribute__ ((mode (HI)));
+typedef unsigned int UHItype __attribute__ ((mode (HI)));
+#if MIN_UNITS_PER_WORD > 1
+/* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1. */
+typedef int SItype __attribute__ ((mode (SI)));
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+#if __SIZEOF_LONG_LONG__ > 4
+/* These typedefs are usually forbidden on archs with UNITS_PER_WORD 2. */
+typedef int DItype __attribute__ ((mode (DI)));
+typedef unsigned int UDItype __attribute__ ((mode (DI)));
+#if MIN_UNITS_PER_WORD > 4
+/* These typedefs are usually forbidden on archs with UNITS_PER_WORD 4. */
+typedef int TItype __attribute__ ((mode (TI)));
+typedef unsigned int UTItype __attribute__ ((mode (TI)));
+#endif
+#endif
+#endif
+
+#if LIBGCC2_UNITS_PER_WORD == 8
+#define W_TYPE_SIZE (8 * BITS_PER_UNIT)
+#define Wtype DItype
+#define UWtype UDItype
+#define HWtype DItype
+#define UHWtype UDItype
+#define DWtype TItype
+#define UDWtype UTItype
+#ifdef LIBGCC2_GNU_PREFIX
+#define __NW(a,b) __gnu_ ## a ## di ## b
+#define __NDW(a,b) __gnu_ ## a ## ti ## b
+#else
+#define __NW(a,b) __ ## a ## di ## b
+#define __NDW(a,b) __ ## a ## ti ## b
+#endif
+#elif LIBGCC2_UNITS_PER_WORD == 4
+#define W_TYPE_SIZE (4 * BITS_PER_UNIT)
+#define Wtype SItype
+#define UWtype USItype
+#define HWtype SItype
+#define UHWtype USItype
+#define DWtype DItype
+#define UDWtype UDItype
+#ifdef LIBGCC2_GNU_PREFIX
+#define __NW(a,b) __gnu_ ## a ## si ## b
+#define __NDW(a,b) __gnu_ ## a ## di ## b
+#else
+#define __NW(a,b) __ ## a ## si ## b
+#define __NDW(a,b) __ ## a ## di ## b
+#endif
+#elif LIBGCC2_UNITS_PER_WORD == 2
+#define W_TYPE_SIZE (2 * BITS_PER_UNIT)
+#define Wtype HItype
+#define UWtype UHItype
+#define HWtype HItype
+#define UHWtype UHItype
+#define DWtype SItype
+#define UDWtype USItype
+#ifdef LIBGCC2_GNU_PREFIX
+#define __NW(a,b) __gnu_ ## a ## hi ## b
+#define __NDW(a,b) __gnu_ ## a ## si ## b
+#else
+#define __NW(a,b) __ ## a ## hi ## b
+#define __NDW(a,b) __ ## a ## si ## b
+#endif
+#else
+#define W_TYPE_SIZE BITS_PER_UNIT
+#define Wtype QItype
+#define UWtype UQItype
+#define HWtype QItype
+#define UHWtype UQItype
+#define DWtype HItype
+#define UDWtype UHItype
+#ifdef LIBGCC2_GNU_PREFIX
+#define __NW(a,b) __gnu_ ## a ## qi ## b
+#define __NDW(a,b) __gnu_ ## a ## hi ## b
+#else
+#define __NW(a,b) __ ## a ## qi ## b
+#define __NDW(a,b) __ ## a ## hi ## b
+#endif
+#endif
+
+typedef int shift_count_type __attribute__((mode (__libgcc_shift_count__)));
+
+#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
+ struct DWstruct {Wtype high, low;};
+#else
+ struct DWstruct {Wtype low, high;};
+#endif
+
+/* We need this union to unpack/pack DImode values, since we don't have
+ any arithmetic yet. Incoming DImode parameters are stored into the
+ `ll' field, and the unpacked result is read from the struct `s'. */
+
+typedef union {
+ struct DWstruct s;
+ DWtype ll;
+} DWunion;
+
+#endif /* __ASM_LIBGCC_H */
diff --git a/arch/arc/lib/memcmp.S b/arch/arc/lib/memcmp.S
index fa5aac5..87bccab 100644
--- a/arch/arc/lib/memcmp.S
+++ b/arch/arc/lib/memcmp.S
@@ -29,6 +29,7 @@ memcmp:
ld.a %r4, [%r0, 8]
ld.a %r5, [%r1, 8]
brne WORD2, %r12, .Lodd
+ nop
.Loop_end:
asl_s SHIFT, SHIFT, 3
bhs_s .Last_cmp
@@ -105,6 +106,7 @@ memcmp:
ldb.a %r4, [%r0, 2]
ldb.a %r5, [%r1, 2]
brne %r3, %r12, .Lbyte_odd
+ nop
.Lbyte_end:
bcc .Lbyte_even
brne %r4, %r5, .Lbyte_even
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5eb1d03..820ba1c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -51,6 +51,13 @@ config SYS_CPU
default "sa1100" if CPU_SA1100
default "armv8" if ARM64
+config SEMIHOSTING
+ bool "support boot from semihosting"
+ help
+ In emulated environments, semihosting is a way for
+ the hosted environment to call out to the emulator to
+ retrieve files from the host machine.
+
choice
prompt "Target select"
@@ -70,17 +77,8 @@ config TARGET_A320EVB
bool "Support a320evb"
select CPU_ARM920T
-config TARGET_AT91RM9200EK
- bool "Support at91rm9200ek"
- select CPU_ARM920T
-
-config TARGET_EB_CPUX9K2
- bool "Support eb_cpux9k2"
- select CPU_ARM920T
-
-config TARGET_CPUAT91
- bool "Support cpuat91"
- select CPU_ARM920T
+config ARCH_AT91
+ bool "Atmel AT91"
config TARGET_EDB93XX
bool "Support edb93xx"
@@ -122,100 +120,6 @@ config TARGET_GPLUGD
bool "Support gplugd"
select CPU_ARM926EJS
-config TARGET_AFEB9260
- bool "Support afeb9260"
- select CPU_ARM926EJS
-
-config TARGET_AT91SAM9260EK
- bool "Support at91sam9260ek"
- select CPU_ARM926EJS
-
-config TARGET_AT91SAM9261EK
- bool "Support at91sam9261ek"
- select CPU_ARM926EJS
-
-config TARGET_AT91SAM9263EK
- bool "Support at91sam9263ek"
- select CPU_ARM926EJS
-
-config TARGET_AT91SAM9M10G45EK
- bool "Support at91sam9m10g45ek"
- select CPU_ARM926EJS
-
-config TARGET_AT91SAM9N12EK
- bool "Support at91sam9n12ek"
- select CPU_ARM926EJS
-
-config TARGET_AT91SAM9RLEK
- bool "Support at91sam9rlek"
- select CPU_ARM926EJS
-
-config TARGET_AT91SAM9X5EK
- bool "Support at91sam9x5ek"
- select CPU_ARM926EJS
-
-config TARGET_SNAPPER9260
- bool "Support snapper9260"
- select CPU_ARM926EJS
-
-config TARGET_VL_MA2SC
- bool "Support vl_ma2sc"
- select CPU_ARM926EJS
-
-config TARGET_SBC35_A9G20
- bool "Support sbc35_a9g20"
- select CPU_ARM926EJS
-
-config TARGET_TNY_A9260
- bool "Support tny_a9260"
- select CPU_ARM926EJS
-
-config TARGET_USB_A9263
- bool "Support usb_a9263"
- select CPU_ARM926EJS
-
-config TARGET_ETHERNUT5
- bool "Support ethernut5"
- select CPU_ARM926EJS
-
-config TARGET_MEESC
- bool "Support meesc"
- select CPU_ARM926EJS
-
-config TARGET_OTC570
- bool "Support otc570"
- select CPU_ARM926EJS
-
-config TARGET_CPU9260
- bool "Support cpu9260"
- select CPU_ARM926EJS
-
-config TARGET_PM9261
- bool "Support pm9261"
- select CPU_ARM926EJS
-
-config TARGET_PM9263
- bool "Support pm9263"
- select CPU_ARM926EJS
-
-config TARGET_PM9G45
- bool "Support pm9g45"
- select CPU_ARM926EJS
-
-config TARGET_CORVUS
- select SUPPORT_SPL
- bool "Support corvus"
- select CPU_ARM926EJS
-
-config TARGET_TAURUS
- select SUPPORT_SPL
- bool "Support taurus"
- select CPU_ARM926EJS
-
-config TARGET_STAMP9G20
- bool "Support stamp9g20"
- select CPU_ARM926EJS
-
config ARCH_DAVINCI
bool "TI DaVinci"
select CPU_ARM926EJS
@@ -229,10 +133,12 @@ config KIRKWOOD
config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
select CPU_V7
+ select SUPPORT_SPL
config TARGET_MAXBCM
bool "Support maxbcm"
select CPU_V7
+ select SUPPORT_SPL
config TARGET_DEVKIT3250
bool "Support devkit3250"
@@ -404,6 +310,10 @@ config TARGET_RPI
bool "Support rpi"
select CPU_ARM1176
+config TARGET_RPI_2
+ bool "Support rpi_2"
+ select CPU_V7
+
config TARGET_TNETV107X_EVM
bool "Support tnetv107x_evm"
select CPU_ARM1176
@@ -505,24 +415,6 @@ config TARGET_TI816X_EVM
select CPU_V7
select SUPPORT_SPL
-config TARGET_SAMA5D3_XPLAINED
- bool "Support sama5d3_xplained"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_SAMA5D3XEK
- bool "Support sama5d3xek"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_SAMA5D4_XPLAINED
- bool "Support sama5d4_xplained"
- select CPU_V7
-
-config TARGET_SAMA5D4EK
- bool "Support sama5d4ek"
- select CPU_V7
-
config TARGET_BCM28155_AP
bool "Support bcm28155_ap"
select CPU_V7
@@ -637,6 +529,7 @@ config TARGET_MX6SLEVK
config TARGET_MX6SXSABRESD
bool "Support mx6sxsabresd"
select CPU_V7
+ select SUPPORT_SPL
config TARGET_GW_VENTANA
bool "Support gw_ventana"
@@ -663,6 +556,17 @@ config TARGET_TQMA6
config TARGET_OT1200
bool "Bachmann OT1200"
select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_PLATINUM_PICON
+ bool "Support platinum-picon"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_PLATINUM_TITANIUM
+ bool "Support platinum-titanium"
+ select CPU_V7
+ select SUPPORT_SPL
config OMAP34XX
bool "OMAP34XX SoC"
@@ -720,10 +624,19 @@ config TEGRA
select CPU_ARM720T if SPL_BUILD
select CPU_V7 if !SPL_BUILD
-config TARGET_VEXPRESS_AEMV8A
+config TARGET_VEXPRESS64_AEMV8A
bool "Support vexpress_aemv8a"
select ARM64
+config TARGET_VEXPRESS64_BASE_FVP
+ bool "Support Versatile Express ARMv8a FVP BASE model"
+ select ARM64
+ select SEMIHOSTING
+
+config TARGET_VEXPRESS64_JUNO
+ bool "Support Versatile Express Juno Development Platform"
+ select ARM64
+
config TARGET_LS2085A_EMU
bool "Support ls2085a_emu"
select ARM64
@@ -805,17 +718,21 @@ config ARCH_UNIPHIER
endchoice
-source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
+source "arch/arm/mach-at91/Kconfig"
+
+source "arch/arm/mach-davinci/Kconfig"
+
+source "arch/arm/cpu/arm1176/bcm2835/Kconfig"
source "arch/arm/cpu/armv7/exynos/Kconfig"
-source "arch/arm/cpu/armv7/highbank/Kconfig"
+source "arch/arm/mach-highbank/Kconfig"
-source "arch/arm/cpu/armv7/keystone/Kconfig"
+source "arch/arm/mach-keystone/Kconfig"
-source "arch/arm/cpu/arm926ejs/kirkwood/Kconfig"
+source "arch/arm/mach-kirkwood/Kconfig"
-source "arch/arm/cpu/arm926ejs/nomadik/Kconfig"
+source "arch/arm/mach-nomadik/Kconfig"
source "arch/arm/cpu/armv7/omap3/Kconfig"
@@ -823,17 +740,17 @@ source "arch/arm/cpu/armv7/omap4/Kconfig"
source "arch/arm/cpu/armv7/omap5/Kconfig"
-source "arch/arm/cpu/arm926ejs/orion5x/Kconfig"
+source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/cpu/armv7/rmobile/Kconfig"
source "arch/arm/cpu/armv7/s5pc1xx/Kconfig"
-source "arch/arm/cpu/armv7/tegra-common/Kconfig"
+source "arch/arm/mach-tegra/Kconfig"
source "arch/arm/cpu/armv7/uniphier/Kconfig"
-source "arch/arm/cpu/arm926ejs/versatile/Kconfig"
+source "arch/arm/mach-versatile/Kconfig"
source "arch/arm/cpu/armv7/zynq/Kconfig"
@@ -842,43 +759,25 @@ source "arch/arm/cpu/armv7/Kconfig"
source "board/aristainetos/Kconfig"
source "board/BuR/kwb/Kconfig"
source "board/BuR/tseries/Kconfig"
-source "board/BuS/eb_cpux9k2/Kconfig"
-source "board/BuS/vl_ma2sc/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/db-mv784mp-gp/Kconfig"
source "board/Marvell/dkb/Kconfig"
source "board/Marvell/gplugd/Kconfig"
-source "board/afeb9260/Kconfig"
source "board/altera/socfpga/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/integrator/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
-source "board/atmel/at91rm9200ek/Kconfig"
-source "board/atmel/at91sam9260ek/Kconfig"
-source "board/atmel/at91sam9261ek/Kconfig"
-source "board/atmel/at91sam9263ek/Kconfig"
-source "board/atmel/at91sam9m10g45ek/Kconfig"
-source "board/atmel/at91sam9n12ek/Kconfig"
-source "board/atmel/at91sam9rlek/Kconfig"
-source "board/atmel/at91sam9x5ek/Kconfig"
-source "board/atmel/sama5d3_xplained/Kconfig"
-source "board/atmel/sama5d3xek/Kconfig"
-source "board/atmel/sama5d4_xplained/Kconfig"
-source "board/atmel/sama5d4ek/Kconfig"
source "board/bachmann/ot1200/Kconfig"
source "board/balloon3/Kconfig"
+source "board/barco/platinum/Kconfig"
source "board/barco/titanium/Kconfig"
source "board/bluegiga/apx4devkit/Kconfig"
-source "board/bluewater/snapper9260/Kconfig"
source "board/boundary/nitrogen6x/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
-source "board/calao/sbc35_a9g20/Kconfig"
-source "board/calao/tny_a9260/Kconfig"
-source "board/calao/usb_a9263/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
source "board/cm4008/Kconfig"
source "board/cm41xx/Kconfig"
@@ -889,13 +788,8 @@ source "board/creative/xfi3/Kconfig"
source "board/davedenx/qong/Kconfig"
source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
-source "board/egnite/ethernut5/Kconfig"
source "board/embest/mx6boards/Kconfig"
-source "board/esd/meesc/Kconfig"
-source "board/esd/otc570/Kconfig"
source "board/esg/ima3-mx53/Kconfig"
-source "board/eukrea/cpu9260/Kconfig"
-source "board/eukrea/cpuat91/Kconfig"
source "board/faraday/a320evb/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
@@ -940,18 +834,14 @@ source "board/phytec/pcm051/Kconfig"
source "board/ppcag/bg0900/Kconfig"
source "board/pxa255_idp/Kconfig"
source "board/raspberrypi/rpi/Kconfig"
-source "board/ronetix/pm9261/Kconfig"
-source "board/ronetix/pm9263/Kconfig"
-source "board/ronetix/pm9g45/Kconfig"
+source "board/raspberrypi/rpi_2/Kconfig"
source "board/samsung/smdk2410/Kconfig"
source "board/sandisk/sansa_fuze_plus/Kconfig"
source "board/scb9328/Kconfig"
source "board/schulercontrol/sc_sps_1/Kconfig"
-source "board/siemens/corvus/Kconfig"
source "board/siemens/draco/Kconfig"
source "board/siemens/pxm2/Kconfig"
source "board/siemens/rut/Kconfig"
-source "board/siemens/taurus/Kconfig"
source "board/silica/pengwyn/Kconfig"
source "board/solidrun/hummingboard/Kconfig"
source "board/spear/spear300/Kconfig"
@@ -965,7 +855,6 @@ source "board/st/stv0991/Kconfig"
source "board/sunxi/Kconfig"
source "board/syteco/jadecpu/Kconfig"
source "board/syteco/zmx25/Kconfig"
-source "board/taskit/stamp9g20/Kconfig"
source "board/tbs/tbs2910/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ebb7dc3..878ae26 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -2,6 +2,27 @@
# SPDX-License-Identifier: GPL-2.0+
#
+# Machine directory name. This list is sorted alphanumerically
+# by CONFIG_* macro name.
+machine-$(CONFIG_ARCH_AT91) += at91
+machine-$(CONFIG_ARCH_DAVINCI) += davinci
+machine-$(CONFIG_ARCH_HIGHBANK) += highbank
+machine-$(CONFIG_ARCH_KEYSTONE) += keystone
+# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
+machine-$(CONFIG_KIRKWOOD) += kirkwood
+# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
+machine-$(CONFIG_ARCH_NOMADIK) += nomadik
+# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
+machine-$(CONFIG_ORION5X) += orion5x
+machine-$(CONFIG_TEGRA) += tegra
+machine-$(CONFIG_ARCH_VERSATILE) += versatile
+
+machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
+
+PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
+
+libs-y += $(machdirs)
+
head-y := arch/arm/cpu/$(CPU)/start.o
ifeq ($(CONFIG_SPL_BUILD),y)
@@ -27,3 +48,6 @@ endif
ifneq (,$(filter $(SOC), armada-xp kirkwood))
libs-y += arch/arm/mvebu-common/
endif
+
+# deprecated
+-include $(machdirs)/config.mk
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index 35d8d38..6bea3d3 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -1,6 +1 @@
-obj-$(CONFIG_AT91FAMILY) += at91-common/
-obj-$(CONFIG_TEGRA20) += tegra20-common/
-obj-$(CONFIG_TEGRA30) += tegra30-common/
-obj-$(CONFIG_TEGRA114) += tegra114-common/
-obj-$(CONFIG_TEGRA124) += tegra124-common/
-obj-$(CONFIG_TEGRA) += tegra-common/
+obj- += dummy.o
diff --git a/arch/arm/cpu/arm1176/bcm2835/Kconfig b/arch/arm/cpu/arm1176/bcm2835/Kconfig
new file mode 100644
index 0000000..162f973
--- /dev/null
+++ b/arch/arm/cpu/arm1176/bcm2835/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_RPI || TARGET_RPI_2
+
+config DM
+ default y if !SPL_BUILD
+
+config DM_SERIAL
+ default y if !SPL_BUILD
+
+config DM_GPIO
+ default y if !SPL_BUILD
+
+endif
diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/cpu/arm1176/bcm2835/Makefile
index 0ad3690..7e5dbe1 100644
--- a/arch/arm/cpu/arm1176/bcm2835/Makefile
+++ b/arch/arm/cpu/arm1176/bcm2835/Makefile
@@ -1,15 +1,7 @@
#
-# See file CREDITS for list of people who contributed to this
-# project.
+# (C) Copyright 2012 Stephen Warren
#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# version 2 as published by the Free Software Foundation.
-#
-# This program is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
+# SPDX-License-Identifier: GPL-2.0
#
obj-y := lowlevel_init.o
diff --git a/arch/arm/cpu/arm720t/Makefile b/arch/arm/cpu/arm720t/Makefile
index 9f61ea2..243a123 100644
--- a/arch/arm/cpu/arm720t/Makefile
+++ b/arch/arm/cpu/arm720t/Makefile
@@ -7,9 +7,3 @@
extra-y = start.o
obj-y = interrupts.o cpu.o
-
-obj-$(CONFIG_TEGRA) += tegra-common/
-obj-$(CONFIG_TEGRA20) += tegra20/
-obj-$(CONFIG_TEGRA30) += tegra30/
-obj-$(CONFIG_TEGRA114) += tegra114/
-obj-$(CONFIG_TEGRA124) += tegra124/
diff --git a/arch/arm/cpu/arm720t/tegra-common/Makefile b/arch/arm/cpu/arm720t/tegra-common/Makefile
deleted file mode 100644
index a9c2b67..0000000
--- a/arch/arm/cpu/arm720t/tegra-common/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_SPL_BUILD) += spl.o
-obj-y += cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra114/Makefile b/arch/arm/cpu/arm720t/tegra114/Makefile
deleted file mode 100644
index ea3e55e..0000000
--- a/arch/arm/cpu/arm720t/tegra114/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-
-#obj-y += cpu.o t11x.o
-obj-y += cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra124/Makefile b/arch/arm/cpu/arm720t/tegra124/Makefile
deleted file mode 100644
index 61abf45..0000000
--- a/arch/arm/cpu/arm720t/tegra124/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2013-2014
-# NVIDIA Corporation <www.nvidia.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra20/Makefile b/arch/arm/cpu/arm720t/tegra20/Makefile
deleted file mode 100644
index 12243fa..0000000
--- a/arch/arm/cpu/arm720t/tegra20/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra30/Makefile b/arch/arm/cpu/arm720t/tegra30/Makefile
deleted file mode 100644
index 6ff4c55..0000000
--- a/arch/arm/cpu/arm720t/tegra30/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-
-obj-y += cpu.o
diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile
index a72e5de..a16838b 100644
--- a/arch/arm/cpu/arm920t/Makefile
+++ b/arch/arm/cpu/arm920t/Makefile
@@ -11,7 +11,6 @@ obj-y += cpu.o
obj-$(CONFIG_USE_IRQ) += interrupts.o
obj-$(if $(filter a320,$(SOC)),y) += a320/
-obj-$(CONFIG_AT91FAMILY) += at91/
obj-$(CONFIG_EP93XX) += ep93xx/
obj-$(CONFIG_IMX) += imx/
obj-$(CONFIG_KS8695) += ks8695/
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index adcea9f..f5944cc 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -15,16 +15,10 @@ endif
endif
obj-$(CONFIG_ARMADA100) += armada100/
-obj-$(CONFIG_AT91FAMILY) += at91/
-obj-$(CONFIG_ARCH_DAVINCI) += davinci/
-obj-$(CONFIG_KIRKWOOD) += kirkwood/
obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
obj-$(CONFIG_MB86R0x) += mb86r0x/
obj-$(CONFIG_MX25) += mx25/
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
-obj-$(CONFIG_ARCH_NOMADIK) += nomadik/
-obj-$(CONFIG_ORION5X) += orion5x/
obj-$(CONFIG_PANTHEON) += pantheon/
obj-$(if $(filter spear,$(SOC)),y) += spear/
-obj-$(CONFIG_ARCH_VERSATILE) += versatile/
diff --git a/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c b/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
deleted file mode 100644
index 16eeca7..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2009
- * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
- * esd electronic system design gmbh <www.esd.eu>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-
-void at91_serial0_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-
- at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* RXD0 */
- writel(1 << AT91CAP9_ID_US0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-
- at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */
- writel(1 << AT91CAP9_ID_US1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-
- at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */
- at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */
- writel(1 << AT91CAP9_ID_US2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-
- at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */
- writel(1 << AT91_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial_hw_init(void)
-{
-#ifdef CONFIG_USART0
- at91_serial0_hw_init();
-#endif
-
-#ifdef CONFIG_USART1
- at91_serial1_hw_init();
-#endif
-
-#ifdef CONFIG_USART2
- at91_serial2_hw_init();
-#endif
-
-#ifdef CONFIG_USART3 /* DBGU */
- at91_serial3_hw_init();
-#endif
-}
-
-#ifdef CONFIG_HAS_DATAFLASH
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-
- at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */
- at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */
- at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */
-
- /* Enable clock */
- writel(1 << AT91CAP9_ID_SPI0, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_b_periph(AT91_PIO_PORTD, 0, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_b_periph(AT91_PIO_PORTD, 1, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTD, 0, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTD, 1, 1);
- }
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-
- at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */
- at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */
- at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */
-
- /* Enable clock */
- writel(1 << AT91CAP9_ID_SPI1, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
- }
-
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTB, 21, 0); /* ETXCK_EREFCK */
- at91_set_a_periph(AT91_PIO_PORTB, 22, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTB, 25, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 26, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 27, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTB, 23, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 24, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* EMDC */
-
-#ifndef CONFIG_RMII
- at91_set_b_periph(AT91_PIO_PORTC, 25, 0); /* ECRS */
- at91_set_b_periph(AT91_PIO_PORTC, 26, 0); /* ECOL */
- at91_set_b_periph(AT91_PIO_PORTC, 22, 0); /* ERX2 */
- at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* ERX3 */
- at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ERXCK */
- at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ETX2 */
- at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ETX3 */
- at91_set_b_periph(AT91_PIO_PORTC, 24, 0); /* ETXER */
-#endif
-}
-#endif
-
-#ifdef CONFIG_AT91_CAN
-void at91_can_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* CAN_TX */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* CAN_RX */
-
- /* Enable clock */
- writel(1 << AT91CAP9_ID_CAN, &pmc->pcer);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/config.mk b/arch/arm/cpu/arm926ejs/at91/config.mk
deleted file mode 100644
index 370630d..0000000
--- a/arch/arm/cpu/arm926ejs/at91/config.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-PF_CPPFLAGS_TUNE := $(call cc-option,-mtune=arm926ejs,)
-PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_TUNE)
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index d29b9aa..d7956e5 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -147,6 +147,7 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
mxs_spl_console_init();
+ debug("SPL: Serial Console Initialised\n");
mxs_power_init();
@@ -156,6 +157,11 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
data->boot_mode_idx = bootmode;
mxs_power_wait_pswitch();
+
+ if (mxs_boot_modes[data->boot_mode_idx].boot_pads == MXS_BM_JTAG) {
+ debug("SPL: Waiting for JTAG user\n");
+ asm volatile ("x: b x");
+ }
}
/* Support aparatus */
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
index cdfcddd..96bd32f 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
@@ -18,6 +18,8 @@ void mxs_lradc_init(void)
{
struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
+ debug("SPL: Initialisating LRADC\n");
+
writel(LRADC_CTRL0_SFTRST, &regs->hw_lradc_ctrl0_clr);
writel(LRADC_CTRL0_CLKGATE, &regs->hw_lradc_ctrl0_clr);
writel(LRADC_CTRL0_ONCHIP_GROUNDREF, &regs->hw_lradc_ctrl0_clr);
@@ -37,9 +39,15 @@ void mxs_lradc_enable_batt_measurement(void)
{
struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
+ debug("SPL: Enabling LRADC battery measurement\n");
+
/* Check if the channel is present at all. */
- if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))
+ if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT)) {
+ debug("SPL: LRADC channel 7 is not present - aborting\n");
return;
+ }
+
+ debug("SPL: LRADC channel 7 is present - configuring\n");
writel(LRADC_CTRL1_LRADC7_IRQ_EN, &regs->hw_lradc_ctrl1_clr);
writel(LRADC_CTRL1_LRADC7_IRQ, &regs->hw_lradc_ctrl1_clr);
@@ -65,6 +73,7 @@ void mxs_lradc_enable_batt_measurement(void)
100, &regs->hw_lradc_delay3);
writel(0xffffffff, &regs->hw_lradc_ch7_clr);
-
writel(LRADC_DELAY_KICK, &regs->hw_lradc_delay3_set);
+
+ debug("SPL: LRADC channel 7 configuration complete\n");
}
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 97ef67d..a744e5d 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -92,6 +92,7 @@ static uint32_t dram_vals[] = {
__weak void mxs_adjust_memory_params(uint32_t *dram_vals)
{
+ debug("SPL: Using default SDRAM parameters\n");
}
#ifdef CONFIG_MX28
@@ -99,8 +100,10 @@ static void initialize_dram_values(void)
{
int i;
+ debug("SPL: Setting mx28 board specific SDRAM parameters\n");
mxs_adjust_memory_params(dram_vals);
+ debug("SPL: Applying SDRAM parameters\n");
for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
@@ -109,6 +112,7 @@ static void initialize_dram_values(void)
{
int i;
+ debug("SPL: Setting mx23 board specific SDRAM parameters\n");
mxs_adjust_memory_params(dram_vals);
/*
@@ -120,6 +124,7 @@ static void initialize_dram_values(void)
* HW_DRAM_CTL8 is setup as the last element.
* So skip the initialization of these HW_DRAM_CTL registers.
*/
+ debug("SPL: Applying SDRAM parameters\n");
for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
if (i == 8 || i == 27 || i == 28 || i == 35)
continue;
@@ -146,6 +151,8 @@ static void mxs_mem_init_clock(void)
const unsigned char divider = 21;
#endif
+ debug("SPL: Initialising FRAC0\n");
+
/* Gate EMI clock */
writeb(CLKCTRL_FRAC_CLKGATE,
&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
@@ -170,6 +177,7 @@ static void mxs_mem_init_clock(void)
&clkctrl_regs->hw_clkctrl_clkseq_clr);
early_delay(10000);
+ debug("SPL: FRAC0 Initialised\n");
}
static void mxs_mem_setup_cpu_and_hbus(void)
@@ -177,6 +185,8 @@ static void mxs_mem_setup_cpu_and_hbus(void)
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ debug("SPL: Setting CPU and HBUS clock frequencies\n");
+
/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
* and ungate CPU clock */
writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
@@ -209,6 +219,8 @@ static void mxs_mem_setup_vdda(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Configuring VDDA\n");
+
writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
(0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
@@ -240,6 +252,8 @@ static void mx23_mem_setup_vddmem(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Setting mx23 VDDMEM\n");
+
/* We must wait before and after disabling the current limiter! */
early_delay(10000);
@@ -252,6 +266,8 @@ static void mx23_mem_setup_vddmem(void)
static void mx23_mem_init(void)
{
+ debug("SPL: Initialising mx23 SDRAM Controller\n");
+
/*
* Reset/ungate the EMI block. This is essential, otherwise the system
* suffers from memory instability. This thing is mx23 specific and is
@@ -297,6 +313,8 @@ static void mx28_mem_init(void)
struct mxs_pinctrl_regs *pinctrl_regs =
(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
+ debug("SPL: Initialising mx28 SDRAM Controller\n");
+
/* Set DDR2 mode */
writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index 1c54ab7..c342217 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -14,6 +14,13 @@
#include "mxs_init.h"
+#ifdef CONFIG_SYS_MXS_VDD5V_ONLY
+#define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
+ POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2
+#else
+#define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
+ POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL
+#endif
/**
* mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
*
@@ -26,6 +33,8 @@ static void mxs_power_clock2xtal(void)
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ debug("SPL: Switching CPU clock to 24MHz XTAL\n");
+
/* Set XTAL as CPU reference clock */
writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
&clkctrl_regs->hw_clkctrl_clkseq_set);
@@ -43,9 +52,23 @@ static void mxs_power_clock2pll(void)
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ debug("SPL: Switching CPU core clock source to PLL\n");
+
+ /*
+ * TODO: Are we really? It looks like we turn on PLL0, but we then
+ * set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
+ * set by mxs_power_clock2xtal()). Clearing this bit here seems to
+ * introduce some instability (causing the CPU core to hang). Maybe
+ * we aren't giving PLL0 enough time to stabilise?
+ */
setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
CLKCTRL_PLL0CTRL0_POWER);
early_delay(100);
+
+ /*
+ * TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
+ * wait on the PLL0 LOCK bit?
+ */
setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
CLKCTRL_CLKSEQ_BYPASS_CPU);
}
@@ -62,6 +85,8 @@ static void mxs_power_set_auto_restart(void)
struct mxs_rtc_regs *rtc_regs =
(struct mxs_rtc_regs *)MXS_RTC_BASE;
+ debug("SPL: Setting auto-restart bit\n");
+
writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
;
@@ -101,14 +126,17 @@ static void mxs_power_set_linreg(void)
(struct mxs_power_regs *)MXS_POWER_BASE;
/* Set linear regulator 25mV below switching converter */
+ debug("SPL: Setting VDDD 25mV below DC-DC converters\n");
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
+ debug("SPL: Setting VDDA 25mV below DC-DC converters\n");
clrsetbits_le32(&power_regs->hw_power_vddactrl,
POWER_VDDACTRL_LINREG_OFFSET_MASK,
POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
+ debug("SPL: Setting VDDIO 25mV below DC-DC converters\n");
clrsetbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
@@ -127,6 +155,8 @@ static int mxs_get_batt_volt(void)
volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
volt *= 8;
+
+ debug("SPL: Battery Voltage = %dmV\n", volt);
return volt;
}
@@ -154,8 +184,10 @@ static int mxs_is_batt_good(void)
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t volt = mxs_get_batt_volt();
- if ((volt >= 2400) && (volt <= 4300))
+ if ((volt >= 2400) && (volt <= 4300)) {
+ debug("SPL: Battery is good\n");
return 1;
+ }
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
@@ -175,16 +207,21 @@ static int mxs_is_batt_good(void)
volt = mxs_get_batt_volt();
- if (volt >= 3500)
+ if (volt >= 3500) {
+ debug("SPL: Battery Voltage too high\n");
return 0;
+ }
- if (volt >= 2400)
+ if (volt >= 2400) {
+ debug("SPL: Battery is good\n");
return 1;
+ }
writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
&power_regs->hw_power_charge_clr);
writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
+ debug("SPL: Battery Voltage too low\n");
return 0;
}
@@ -203,6 +240,7 @@ static void mxs_power_setup_5v_detect(void)
(struct mxs_power_regs *)MXS_POWER_BASE;
/* Start 5V detection */
+ debug("SPL: Starting 5V input detection comparator\n");
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_VBUSVALID_TRSH_MASK,
POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
@@ -220,6 +258,8 @@ static void mxs_src_power_init(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Pre-Configuring power block\n");
+
/* Improve efficieny and reduce transient ripple */
writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
@@ -257,6 +297,8 @@ static void mxs_power_init_4p2_params(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Configuring common 4P2 regulator params\n");
+
/* Setup 4P2 parameters */
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
@@ -268,8 +310,7 @@ static void mxs_power_init_4p2_params(void)
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_DROPOUT_CTRL_MASK,
- POWER_DCDC4P2_DROPOUT_CTRL_100MV |
- POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
+ DCDC4P2_DROPOUT_CONFIG);
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
@@ -289,6 +330,8 @@ static void mxs_enable_4p2_dcdc_input(int xfer)
uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
uint32_t prev_5v_brnout, prev_5v_droop;
+ debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
+
prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_PWDN_5VBRNOUT;
prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
@@ -390,6 +433,8 @@ static void mxs_power_init_4p2_regulator(void)
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, tmp2;
+ debug("SPL: Enabling 4P2 regulator\n");
+
setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
@@ -407,6 +452,7 @@ static void mxs_power_init_4p2_regulator(void)
* gradually to avoid large inrush current from the 5V cable which can
* cause transients/problems
*/
+ debug("SPL: Charging 4P2 capacitor\n");
mxs_enable_4p2_dcdc_input(0);
if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
@@ -420,6 +466,8 @@ static void mxs_power_init_4p2_regulator(void)
POWER_DCDC4P2_ENABLE_DCDC);
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_set);
+
+ debug("SPL: Unable to recover from mx23 errata 5837\n");
hang();
}
@@ -433,6 +481,7 @@ static void mxs_power_init_4p2_regulator(void)
* current limit until the brownout status is false or until we've
* reached our maximum defined 4p2 current limit.
*/
+ debug("SPL: Setting 4P2 brownout level\n");
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_BO_MASK,
22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
@@ -479,8 +528,11 @@ static void mxs_power_init_dcdc_4p2_source(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Switching DC-DC converters to 4P2\n");
+
if (!(readl(&power_regs->hw_power_dcdc4p2) &
POWER_DCDC4P2_ENABLE_DCDC)) {
+ debug("SPL: Already switched - aborting\n");
hang();
}
@@ -509,6 +561,8 @@ static void mxs_power_enable_4p2(void)
uint32_t vdddctrl, vddactrl, vddioctrl;
uint32_t tmp;
+ debug("SPL: Powering up 4P2 regulator\n");
+
vdddctrl = readl(&power_regs->hw_power_vdddctrl);
vddactrl = readl(&power_regs->hw_power_vddactrl);
vddioctrl = readl(&power_regs->hw_power_vddioctrl);
@@ -559,6 +613,8 @@ static void mxs_power_enable_4p2(void)
if (tmp)
writel(POWER_CHARGE_ENABLE_LOAD,
&power_regs->hw_power_charge_clr);
+
+ debug("SPL: 4P2 regulator powered-up\n");
}
/**
@@ -574,6 +630,8 @@ static void mxs_boot_valid_5v(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Booting from 5V supply\n");
+
/*
* Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
* disconnect event. FIXME
@@ -601,6 +659,9 @@ static void mxs_powerdown(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+
+ debug("Powering Down\n");
+
writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
&power_regs->hw_power_reset);
@@ -617,6 +678,8 @@ static void mxs_batt_boot(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Configuring power block to boot from battery\n");
+
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
@@ -672,6 +735,8 @@ static void mxs_handle_5v_conflict(void)
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
+ debug("SPL: Resolving 5V conflict\n");
+
setbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_BO_OFFSET_MASK);
@@ -683,19 +748,27 @@ static void mxs_handle_5v_conflict(void)
* VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
* unreliable
*/
+ debug("SPL: VDDIO has a brownout\n");
mxs_powerdown();
break;
}
if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
+ debug("SPL: POWER_STS_VDD5V_GT_VDDIO is set\n");
mxs_boot_valid_5v();
break;
} else {
+ debug("SPL: POWER_STS_VDD5V_GT_VDDIO is not set\n");
mxs_powerdown();
break;
}
+ /*
+ * TODO: I can't see this being reached. We'll either
+ * powerdown or boot from a stable 5V supply.
+ */
if (tmp & POWER_STS_PSWITCH_MASK) {
+ debug("SPL: POWER_STS_PSWITCH_MASK is set\n");
mxs_batt_boot();
break;
}
@@ -713,21 +786,26 @@ static void mxs_5v_boot(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Configuring power block to boot from 5V input\n");
+
/*
* NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
* but their implementation always returns 1 so we omit it here.
*/
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ debug("SPL: 5V VDD good\n");
mxs_boot_valid_5v();
return;
}
early_delay(1000);
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ debug("SPL: 5V VDD good (after delay)\n");
mxs_boot_valid_5v();
return;
}
+ debug("SPL: 5V VDD not good\n");
mxs_handle_5v_conflict();
}
@@ -742,6 +820,8 @@ static void mxs_init_batt_bo(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Initialising battery brown-out level to 3.0V\n");
+
/* Brownout at 3V */
clrsetbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
@@ -762,6 +842,8 @@ static void mxs_switch_vddd_to_dcdc_source(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Switching VDDD to DC-DC converters\n");
+
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
@@ -788,6 +870,8 @@ static void mxs_power_configure_power_source(void)
struct mxs_lradc_regs *lradc_regs =
(struct mxs_lradc_regs *)MXS_LRADC_BASE;
+ debug("SPL: Configuring power source\n");
+
mxs_src_power_init();
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
@@ -811,6 +895,10 @@ static void mxs_power_configure_power_source(void)
mxs_batt_boot();
}
+ /*
+ * TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
+ * from USB VBUS
+ */
mxs_power_clock2pll();
mxs_init_batt_bo();
@@ -819,6 +907,7 @@ static void mxs_power_configure_power_source(void)
#ifdef CONFIG_MX23
/* Fire up the VDDMEM LinReg now that we're all set. */
+ debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
&power_regs->hw_power_vddmemctrl);
#endif
@@ -838,6 +927,8 @@ static void mxs_enable_output_rail_protection(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Enabling output rail protection\n");
+
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
@@ -1077,6 +1168,8 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
*/
static void mxs_setup_batt_detect(void)
{
+ debug("SPL: Starting battery voltage measurement logic\n");
+
mxs_lradc_init();
mxs_lradc_enable_batt_measurement();
early_delay(10);
@@ -1111,6 +1204,8 @@ void mxs_power_init(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Initialising Power Block\n");
+
mxs_ungate_power();
mxs_power_clock2xtal();
@@ -1123,9 +1218,13 @@ void mxs_power_init(void)
mxs_power_configure_power_source();
mxs_enable_output_rail_protection();
+ debug("SPL: Setting VDDIO to 3V3 (brownout @ 3v15)\n");
mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
+
+ debug("SPL: Setting VDDD to 1V5 (brownout @ 1v0)\n");
mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
#ifdef CONFIG_MX23
+ debug("SPL: Setting mx23 VDDMEM to 2V5 (brownout @ 1v7)\n");
mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
#endif
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
@@ -1150,6 +1249,7 @@ void mxs_power_wait_pswitch(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Waiting for power switch input\n");
while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
;
}
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 409e6f5..b228ed6 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,6 @@ obj-$(CONFIG_IPROC) += iproc-common/
obj-$(CONFIG_KONA) += kona-common/
obj-$(CONFIG_OMAP_COMMON) += omap-common/
obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
-obj-$(CONFIG_TEGRA) += tegra-common/
ifneq (,$(filter s5pc1xx exynos,$(SOC)))
obj-y += s5p-common/
@@ -40,13 +39,11 @@ endif
obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
-obj-$(CONFIG_AT91FAMILY) += at91/
+obj-$(CONFIG_BCM2835) += bcm2835/
obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
obj-$(CONFIG_ARCH_EXYNOS) += exynos/
-obj-$(CONFIG_ARCH_HIGHBANK) += highbank/
-obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
obj-$(if $(filter mx5,$(SOC)),y) += mx5/
obj-$(CONFIG_MX6) += mx6/
@@ -58,7 +55,6 @@ obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
obj-$(CONFIG_SOCFPGA) += socfpga/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
-obj-$(CONFIG_TEGRA20) += tegra20/
obj-$(CONFIG_U8500) += u8500/
obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
obj-$(CONFIG_VF610) += vf610/
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 31188c8..529a119 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -118,4 +118,7 @@ void enable_basic_clocks(void)
/* Select the Master osc clk as Timer2 clock source */
writel(0x1, &cmdpll->clktimer2clk);
+
+ /* For OPP100 the mac clock should be /5. */
+ writel(0x4, &cmdpll->clkselmacclk);
}
diff --git a/arch/arm/cpu/armv7/armada-xp/Makefile b/arch/arm/cpu/armv7/armada-xp/Makefile
index 885dcee..737159b 100644
--- a/arch/arm/cpu/armv7/armada-xp/Makefile
+++ b/arch/arm/cpu/armv7/armada-xp/Makefile
@@ -5,3 +5,5 @@
#
obj-y = cpu.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
diff --git a/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S b/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
new file mode 100644
index 0000000..1febd7b
--- /dev/null
+++ b/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
@@ -0,0 +1,62 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+ bx lr
+ENDPROC(save_boot_params)
+
+/*
+ * cache_inv - invalidate Cache line
+ * r0 - dest
+ */
+ .global cache_inv
+ .type cache_inv, %function
+ cache_inv:
+
+ stmfd sp!, {r1-r12}
+
+ mcr p15, 0, r0, c7, c6, 1
+
+ ldmfd sp!, {r1-r12}
+ bx lr
+
+
+/*
+ * flush_l1_v6 - l1 cache clean invalidate
+ * r0 - dest
+ */
+ .global flush_l1_v6
+ .type flush_l1_v6, %function
+ flush_l1_v6:
+
+ stmfd sp!, {r1-r12}
+
+ mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
+ mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
+ mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
+
+ ldmfd sp!, {r1-r12}
+ bx lr
+
+
+/*
+ * flush_l1_v7 - l1 cache clean invalidate
+ * r0 - dest
+ */
+ .global flush_l1_v7
+ .type flush_l1_v7, %function
+ flush_l1_v7:
+
+ stmfd sp!, {r1-r12}
+
+ dmb /* @data memory barrier */
+ mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
+ dsb /* @data sync barrier */
+
+ ldmfd sp!, {r1-r12}
+ bx lr
diff --git a/arch/arm/cpu/armv7/armada-xp/spl.c b/arch/arm/cpu/armv7/armada-xp/spl.c
new file mode 100644
index 0000000..402e520
--- /dev/null
+++ b/arch/arm/cpu/armv7/armada-xp/spl.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+ /* Right now only booting via SPI NOR flash is supported */
+ return BOOT_DEVICE_SPI;
+}
+
+void board_init_f(ulong dummy)
+{
+ /* Set global data pointer */
+ gd = &gdata;
+
+ /* Linux expects the internal registers to be at 0xf1000000 */
+ arch_cpu_init();
+
+ preloader_console_init();
+
+ /* First init the serdes PHY's */
+ serdes_phy_config();
+
+ /* Setup DDR */
+ ddr3_init();
+
+ board_init_r(NULL, 0);
+}
diff --git a/arch/arm/cpu/armv7/at91/config.mk b/arch/arm/cpu/armv7/at91/config.mk
deleted file mode 100644
index db60308..0000000
--- a/arch/arm/cpu/armv7/at91/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (C) 2014, Andreas Bießmann <andreas.devel@googlemail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-ifndef CONFIG_SPL_BUILD
-ALL-y += u-boot.img
-endif
diff --git a/arch/arm/cpu/armv7/at91/sama5d4_devices.c b/arch/arm/cpu/armv7/at91/sama5d4_devices.c
deleted file mode 100644
index 7469825..0000000
--- a/arch/arm/cpu/armv7/at91/sama5d4_devices.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (C) 2014 Atmel
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/sama5d4.h>
-
-char *get_cpu_name()
-{
- unsigned int extension_id = get_extension_chip_id();
-
- if (cpu_is_sama5d4())
- switch (extension_id) {
- case ARCH_EXID_SAMA5D41:
- return "SAMA5D41";
- case ARCH_EXID_SAMA5D42:
- return "SAMA5D42";
- case ARCH_EXID_SAMA5D43:
- return "SAMA5D43";
- case ARCH_EXID_SAMA5D44:
- return "SAMA5D44";
- default:
- return "Unknown CPU type";
- }
- else
- return "Unknown CPU type";
-}
-
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-void at91_udp_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- /* Enable UPLL clock */
- writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
- /* Enable UDPHS clock */
- at91_periph_clk_enable(ATMEL_ID_UDPHS);
-}
-#endif
diff --git a/arch/arm/cpu/armv7/bcm2835/Makefile b/arch/arm/cpu/armv7/bcm2835/Makefile
new file mode 100644
index 0000000..ed1ee47
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm2835/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2012 Stephen Warren
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+src_dir := ../../arm1176/bcm2835/
+
+obj-y :=
+obj-y += $(src_dir)/init.o
+obj-y += $(src_dir)/reset.o
+obj-y += $(src_dir)/timer.o
+obj-y += $(src_dir)/mbox.o
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 01cdb7e..c56417d 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -53,7 +53,7 @@ int cleanup_before_linux(void)
* After D-cache is flushed and before it is disabled there may
* be some new valid entries brought into the cache. We are sure
* that these lines are not dirty and will not affect our execution.
- * (because unwinding the call-stack and setting a bit in CP15 SCTRL
+ * (because unwinding the call-stack and setting a bit in CP15 SCTLR
* is all we did during this. We have not pushed anything on to the
* stack. Neither have we affected any static data)
* So just invalidate the entire d-cache again to avoid coherency
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig
index 7fcb5d2..2064efa 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -65,6 +65,27 @@ endchoice
config SYS_SOC
default "exynos"
+config DM
+ default y if !SPL_BUILD
+
+config DM_SERIAL
+ default y if !SPL_BUILD
+
+config DM_SPI
+ default y if !SPL_BUILD
+
+config DM_SPI_FLASH
+ default y if !SPL_BUILD
+
+config DM_GPIO
+ default y if !SPL_BUILD
+
+config SYS_MALLOC_F
+ default y if !SPL_BUILD
+
+config SYS_MALLOC_F_LEN
+ default 0x400 if !SPL_BUILD
+
source "board/samsung/smdkv310/Kconfig"
source "board/samsung/trats/Kconfig"
source "board/samsung/universal_c210/Kconfig"
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index b31c13b..c6455c2 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -20,42 +20,84 @@
* positions of the peripheral clocks of the src and div registers
*/
struct clk_bit_info {
+ enum periph_id id;
+ int32_t src_mask;
+ int32_t div_mask;
+ int32_t prediv_mask;
int8_t src_bit;
int8_t div_bit;
int8_t prediv_bit;
};
-/* src_bit div_bit prediv_bit */
-static struct clk_bit_info clk_bit_info[] = {
- {0, 0, -1},
- {4, 4, -1},
- {8, 8, -1},
- {12, 12, -1},
- {0, 0, 8},
- {4, 16, 24},
- {8, 0, 8},
- {12, 16, 24},
- {-1, -1, -1},
- {16, 0, 8},
- {20, 16, 24},
- {24, 0, 8},
- {0, 0, 4},
- {4, 12, 16},
- {-1, -1, -1},
- {-1, -1, -1},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {24, 0, -1},
- {24, 0, -1},
- {24, 0, -1},
- {24, 0, -1},
- {24, 0, -1},
+static struct clk_bit_info exynos5_bit_info[] = {
+ /* periph id s_mask d_mask p_mask s_bit d_bit p_bit */
+ {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1},
+ {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1},
+ {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1},
+ {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1},
+ {PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C2, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C3, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C4, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C5, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C6, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C7, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 16, 0, 8},
+ {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 20, 16, 24},
+ {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 24, 0, 8},
+ {PERIPH_ID_SDMMC0, 0xf, 0xf, 0xff, 0, 0, 8},
+ {PERIPH_ID_SDMMC1, 0xf, 0xf, 0xff, 4, 16, 24},
+ {PERIPH_ID_SDMMC2, 0xf, 0xf, 0xff, 8, 0, 8},
+ {PERIPH_ID_SDMMC3, 0xf, 0xf, 0xff, 12, 16, 24},
+ {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4},
+ {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16},
+ {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 0, 0, 4},
+ {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 4, 12, 16},
+ {PERIPH_ID_SDMMC4, 0xf, 0xf, 0xff, 16, 0, 8},
+ {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 0, -1},
+ {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 0, -1},
+ {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 0, -1},
+ {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 0, -1},
+ {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 0, -1},
+
+ {PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1},
+};
+
+static struct clk_bit_info exynos542x_bit_info[] = {
+ /* periph id s_mask d_mask p_mask s_bit d_bit p_bit */
+ {PERIPH_ID_UART0, 0xf, 0xf, -1, 4, 8, -1},
+ {PERIPH_ID_UART1, 0xf, 0xf, -1, 8, 12, -1},
+ {PERIPH_ID_UART2, 0xf, 0xf, -1, 12, 16, -1},
+ {PERIPH_ID_UART3, 0xf, 0xf, -1, 16, 20, -1},
+ {PERIPH_ID_I2C0, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C1, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C2, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C3, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C4, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C5, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C6, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C7, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 20, 20, 8},
+ {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 24, 24, 16},
+ {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 28, 28, 24},
+ {PERIPH_ID_SDMMC0, 0x7, 0x3ff, -1, 8, 0, -1},
+ {PERIPH_ID_SDMMC1, 0x7, 0x3ff, -1, 12, 10, -1},
+ {PERIPH_ID_SDMMC2, 0x7, 0x3ff, -1, 16, 20, -1},
+ {PERIPH_ID_I2C8, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C9, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4},
+ {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16},
+ {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 12, 16, 0},
+ {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 16, 20, 8},
+ {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 28, -1},
+ {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 28, -1},
+ {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 28, -1},
+ {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 28, -1},
+ {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 28, -1},
+ {PERIPH_ID_I2C10, -1, 0x3f, -1, -1, 8, -1},
+
+ {PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1},
};
/* Epll Clock division values to achive different frequency output */
@@ -260,11 +302,72 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
return fout;
}
+/* exynos542x: return pll clock frequency */
+static unsigned long exynos542x_get_pll_clk(int pllreg)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long r, k = 0;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con0);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con0);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con0);
+ k = readl(&clk->epll_con1);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con0);
+ k = readl(&clk->vpll_con1);
+ break;
+ case BPLL:
+ r = readl(&clk->bpll_con0);
+ break;
+ case RPLL:
+ r = readl(&clk->rpll_con0);
+ k = readl(&clk->rpll_con1);
+ break;
+ case SPLL:
+ r = readl(&clk->spll_con0);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ return exynos_get_pll_clk(pllreg, r, k);
+}
+
+static struct clk_bit_info *get_clk_bit_info(int peripheral)
+{
+ int i;
+ struct clk_bit_info *info;
+
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ info = exynos542x_bit_info;
+ else
+ info = exynos5_bit_info;
+
+ for (i = 0; info[i].id != PERIPH_ID_NONE; i++) {
+ if (info[i].id == peripheral)
+ break;
+ }
+
+ if (info[i].id == PERIPH_ID_NONE)
+ debug("ERROR: Peripheral ID %d not found\n", peripheral);
+
+ return &info[i];
+}
+
static unsigned long exynos5_get_periph_rate(int peripheral)
{
- struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
- unsigned long sclk, sub_clk;
- unsigned int src, div, sub_div;
+ struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
+ unsigned long sclk = 0;
+ unsigned int src = 0, div = 0, sub_div = 0;
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
@@ -286,27 +389,30 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
break;
case PERIPH_ID_I2S0:
src = readl(&clk->src_mau);
- div = readl(&clk->div_mau);
+ div = sub_div = readl(&clk->div_mau);
case PERIPH_ID_SPI0:
case PERIPH_ID_SPI1:
src = readl(&clk->src_peric1);
- div = readl(&clk->div_peric1);
+ div = sub_div = readl(&clk->div_peric1);
break;
case PERIPH_ID_SPI2:
src = readl(&clk->src_peric1);
- div = readl(&clk->div_peric2);
+ div = sub_div = readl(&clk->div_peric2);
break;
case PERIPH_ID_SPI3:
case PERIPH_ID_SPI4:
src = readl(&clk->sclk_src_isp);
- div = readl(&clk->sclk_div_isp);
+ div = sub_div = readl(&clk->sclk_div_isp);
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC1:
+ src = readl(&clk->src_fsys);
+ div = sub_div = readl(&clk->div_fsys1);
+ break;
case PERIPH_ID_SDMMC2:
case PERIPH_ID_SDMMC3:
src = readl(&clk->src_fsys);
- div = readl(&clk->div_fsys1);
+ div = sub_div = readl(&clk->div_fsys2);
break;
case PERIPH_ID_I2C0:
case PERIPH_ID_I2C1:
@@ -316,18 +422,17 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
case PERIPH_ID_I2C5:
case PERIPH_ID_I2C6:
case PERIPH_ID_I2C7:
- sclk = exynos5_get_pll_clk(MPLL);
- sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
- & 0x7) + 1;
- div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
- & 0x7) + 1;
- return (sclk / sub_div) / div;
+ src = EXYNOS_SRC_MPLL;
+ div = readl(&clk->div_top0);
+ sub_div = readl(&clk->div_top1);
+ break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
};
- src = (src >> bit_info->src_bit) & 0xf;
+ if (bit_info->src_bit >= 0)
+ src = (src >> bit_info->src_bit) & bit_info->src_mask;
switch (src) {
case EXYNOS_SRC_MPLL:
@@ -340,68 +445,126 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
sclk = exynos5_get_pll_clk(VPLL);
break;
default:
+ debug("%s: EXYNOS_SRC %d not supported\n", __func__, src);
return 0;
}
- /* Ratio clock division for this peripheral */
- sub_div = (div >> bit_info->div_bit) & 0xf;
- sub_clk = sclk / (sub_div + 1);
-
- /* Pre-ratio clock division for SDMMC0 and 2 */
- if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
- div = (div >> bit_info->prediv_bit) & 0xff;
- return sub_clk / (div + 1);
- }
+ /* Clock divider ratio for this peripheral */
+ if (bit_info->div_bit >= 0)
+ div = (div >> bit_info->div_bit) & bit_info->div_mask;
- return sub_clk;
-}
+ /* Clock pre-divider ratio for this peripheral */
+ if (bit_info->prediv_bit >= 0)
+ sub_div = (sub_div >> bit_info->prediv_bit)
+ & bit_info->prediv_mask;
-unsigned long clock_get_periph_rate(int peripheral)
-{
- if (cpu_is_exynos5())
- return exynos5_get_periph_rate(peripheral);
- else
- return 0;
+ /* Calculate and return required clock rate */
+ return (sclk / (div + 1)) / (sub_div + 1);
}
-/* exynos5420: return pll clock frequency */
-static unsigned long exynos5420_get_pll_clk(int pllreg)
+static unsigned long exynos542x_get_periph_rate(int peripheral)
{
+ struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
+ unsigned long sclk = 0;
+ unsigned int src = 0, div = 0, sub_div = 0;
struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long r, k = 0;
+ (struct exynos5420_clock *)samsung_get_base_clock();
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con0);
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ case PERIPH_ID_PWM0:
+ case PERIPH_ID_PWM1:
+ case PERIPH_ID_PWM2:
+ case PERIPH_ID_PWM3:
+ case PERIPH_ID_PWM4:
+ src = readl(&clk->src_peric0);
+ div = readl(&clk->div_peric0);
break;
- case MPLL:
- r = readl(&clk->mpll_con0);
+ case PERIPH_ID_SPI0:
+ case PERIPH_ID_SPI1:
+ case PERIPH_ID_SPI2:
+ src = readl(&clk->src_peric1);
+ div = readl(&clk->div_peric1);
+ sub_div = readl(&clk->div_peric4);
break;
- case EPLL:
- r = readl(&clk->epll_con0);
- k = readl(&clk->epll_con1);
+ case PERIPH_ID_SPI3:
+ case PERIPH_ID_SPI4:
+ src = readl(&clk->src_isp);
+ div = readl(&clk->div_isp1);
+ sub_div = readl(&clk->div_isp1);
break;
- case VPLL:
- r = readl(&clk->vpll_con0);
- k = readl(&clk->vpll_con1);
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC3:
+ src = readl(&clk->src_fsys);
+ div = readl(&clk->div_fsys1);
break;
- case BPLL:
- r = readl(&clk->bpll_con0);
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ case PERIPH_ID_I2C8:
+ case PERIPH_ID_I2C9:
+ case PERIPH_ID_I2C10:
+ src = EXYNOS542X_SRC_MPLL;
+ div = readl(&clk->div_top1);
break;
- case RPLL:
- r = readl(&clk->rpll_con0);
- k = readl(&clk->rpll_con1);
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ };
+
+ if (bit_info->src_bit >= 0)
+ src = (src >> bit_info->src_bit) & bit_info->src_mask;
+
+ switch (src) {
+ case EXYNOS542X_SRC_MPLL:
+ sclk = exynos542x_get_pll_clk(MPLL);
break;
- case SPLL:
- r = readl(&clk->spll_con0);
+ case EXYNOS542X_SRC_SPLL:
+ sclk = exynos542x_get_pll_clk(SPLL);
+ break;
+ case EXYNOS542X_SRC_EPLL:
+ sclk = exynos542x_get_pll_clk(EPLL);
+ break;
+ case EXYNOS542X_SRC_RPLL:
+ sclk = exynos542x_get_pll_clk(RPLL);
break;
default:
- printf("Unsupported PLL (%d)\n", pllreg);
+ debug("%s: EXYNOS542X_SRC %d not supported", __func__, src);
return 0;
}
- return exynos_get_pll_clk(pllreg, r, k);
+ /* Clock divider ratio for this peripheral */
+ if (bit_info->div_bit >= 0)
+ div = (div >> bit_info->div_bit) & bit_info->div_mask;
+
+ /* Clock pre-divider ratio for this peripheral */
+ if (bit_info->prediv_bit >= 0)
+ sub_div = (sub_div >> bit_info->prediv_bit)
+ & bit_info->prediv_mask;
+
+ /* Calculate and return required clock rate */
+ return (sclk / (div + 1)) / (sub_div + 1);
+}
+
+unsigned long clock_get_periph_rate(int peripheral)
+{
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ return exynos542x_get_periph_rate(peripheral);
+ return exynos5_get_periph_rate(peripheral);
+ } else {
+ return 0;
+ }
}
/* exynos4: return ARM clock frequency */
@@ -527,27 +690,6 @@ static unsigned long exynos4x12_get_pwm_clk(void)
return pclk;
}
-/* exynos5420: return pwm clock frequency */
-static unsigned long exynos5420_get_pwm_clk(void)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long pclk, sclk;
- unsigned int ratio;
-
- /*
- * CLK_DIV_PERIC0
- * PWM_RATIO [31:28]
- */
- ratio = readl(&clk->div_peric0);
- ratio = (ratio >> 28) & 0xf;
- sclk = get_pll_clk(MPLL);
-
- pclk = sclk / (ratio + 1);
-
- return pclk;
-}
-
/* exynos4: return uart clock frequency */
static unsigned long exynos4_get_uart_clk(int dev_index)
{
@@ -640,100 +782,6 @@ static unsigned long exynos4x12_get_uart_clk(int dev_index)
return uclk;
}
-/* exynos5: return uart clock frequency */
-static unsigned long exynos5_get_uart_clk(int dev_index)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_PERIC0
- * UART0_SEL [3:0]
- * UART1_SEL [7:4]
- * UART2_SEL [8:11]
- * UART3_SEL [12:15]
- * UART4_SEL [16:19]
- * UART5_SEL [23:20]
- */
- sel = readl(&clk->src_peric0);
- sel = (sel >> (dev_index << 2)) & 0xf;
-
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_PERIC0
- * UART0_RATIO [3:0]
- * UART1_RATIO [7:4]
- * UART2_RATIO [8:11]
- * UART3_RATIO [12:15]
- * UART4_RATIO [16:19]
- * UART5_RATIO [23:20]
- */
- ratio = readl(&clk->div_peric0);
- ratio = (ratio >> (dev_index << 2)) & 0xf;
-
- uclk = sclk / (ratio + 1);
-
- return uclk;
-}
-
-/* exynos5420: return uart clock frequency */
-static unsigned long exynos5420_get_uart_clk(int dev_index)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_PERIC0
- * UART0_SEL [6:4]
- * UART1_SEL [10:8]
- * UART2_SEL [14:12]
- * UART3_SEL [18:16]
- * generalised calculation as follows
- * sel = (sel >> ((dev_index * 4) + 4)) & mask;
- */
- sel = readl(&clk->src_peric0);
- sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
-
- if (sel == 0x3)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x6)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(RPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_PERIC0
- * UART0_RATIO [11:8]
- * UART1_RATIO [15:12]
- * UART2_RATIO [19:16]
- * UART3_RATIO [23:20]
- * generalised calculation as follows
- * ratio = (ratio >> ((dev_index * 4) + 8)) & mask;
- */
- ratio = readl(&clk->div_peric0);
- ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
-
- uclk = sclk / (ratio + 1);
-
- return uclk;
-}
-
static unsigned long exynos4_get_mmc_clk(int dev_index)
{
struct exynos4_clock *clk =
@@ -783,94 +831,6 @@ static unsigned long exynos4_get_mmc_clk(int dev_index)
return uclk;
}
-static unsigned long exynos5_get_mmc_clk(int dev_index)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel, ratio, pre_ratio;
- int shift = 0;
-
- sel = readl(&clk->src_fsys);
- sel = (sel >> (dev_index << 2)) & 0xf;
-
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- switch (dev_index) {
- case 0:
- case 1:
- ratio = readl(&clk->div_fsys1);
- pre_ratio = readl(&clk->div_fsys1);
- break;
- case 2:
- case 3:
- ratio = readl(&clk->div_fsys2);
- pre_ratio = readl(&clk->div_fsys2);
- break;
- default:
- return 0;
- }
-
- if (dev_index == 1 || dev_index == 3)
- shift = 16;
-
- ratio = (ratio >> shift) & 0xf;
- pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
- uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
-
- return uclk;
-}
-
-static unsigned long exynos5420_get_mmc_clk(int dev_index)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel, ratio;
-
- /*
- * CLK_SRC_FSYS
- * MMC0_SEL [10:8]
- * MMC1_SEL [14:12]
- * MMC2_SEL [18:16]
- * generalised calculation as follows
- * sel = (sel >> ((dev_index * 4) + 8)) & mask
- */
- sel = readl(&clk->src_fsys);
- sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
-
- if (sel == 0x3)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x4)
- sclk = get_pll_clk(SPLL);
- else if (sel == 0x6)
- sclk = get_pll_clk(EPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_FSYS1
- * MMC0_RATIO [9:0]
- * MMC1_RATIO [19:10]
- * MMC2_RATIO [29:20]
- * generalised calculation as follows
- * ratio = (ratio >> (dev_index * 10)) & mask
- */
- ratio = readl(&clk->div_fsys1);
- ratio = (ratio >> (dev_index * 10)) & 0x3ff;
-
- uclk = (sclk / (ratio + 1));
-
- return uclk;
-}
-
/* exynos4: set the mmc clock */
static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
{
@@ -1249,29 +1209,6 @@ void exynos4_set_mipi_clk(void)
clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
}
-/*
- * I2C
- *
- * exynos5: obtaining the I2C clock
- */
-static unsigned long exynos5_get_i2c_clk(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned long aclk_66, aclk_66_pre, sclk;
- unsigned int ratio;
-
- sclk = get_pll_clk(MPLL);
-
- ratio = (readl(&clk->div_top1)) >> 24;
- ratio &= 0x7;
- aclk_66_pre = sclk / (ratio + 1);
- ratio = readl(&clk->div_top0);
- ratio &= 0x7;
- aclk_66 = aclk_66_pre / (ratio + 1);
- return aclk_66;
-}
-
int exynos5_set_epll_clk(unsigned long rate)
{
unsigned int epll_con, epll_con_k;
@@ -1585,7 +1522,7 @@ unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_pll_clk(pllreg);
+ return exynos542x_get_pll_clk(pllreg);
return exynos5_get_pll_clk(pllreg);
} else {
if (proid_is_exynos4412())
@@ -1608,7 +1545,7 @@ unsigned long get_arm_clk(void)
unsigned long get_i2c_clk(void)
{
if (cpu_is_exynos5()) {
- return exynos5_get_i2c_clk();
+ return clock_get_periph_rate(PERIPH_ID_I2C0);
} else if (cpu_is_exynos4()) {
return exynos4_get_i2c_clk();
} else {
@@ -1620,8 +1557,6 @@ unsigned long get_i2c_clk(void)
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_pwm_clk();
return clock_get_periph_rate(PERIPH_ID_PWM0);
} else {
if (proid_is_exynos4412())
@@ -1632,10 +1567,28 @@ unsigned long get_pwm_clk(void)
unsigned long get_uart_clk(int dev_index)
{
+ enum periph_id id;
+
+ switch (dev_index) {
+ case 0:
+ id = PERIPH_ID_UART0;
+ break;
+ case 1:
+ id = PERIPH_ID_UART1;
+ break;
+ case 2:
+ id = PERIPH_ID_UART2;
+ break;
+ case 3:
+ id = PERIPH_ID_UART3;
+ break;
+ default:
+ debug("%s: invalid UART index %d", __func__, dev_index);
+ return -1;
+ }
+
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_uart_clk(dev_index);
- return exynos5_get_uart_clk(dev_index);
+ return clock_get_periph_rate(id);
} else {
if (proid_is_exynos4412())
return exynos4x12_get_uart_clk(dev_index);
@@ -1645,10 +1598,28 @@ unsigned long get_uart_clk(int dev_index)
unsigned long get_mmc_clk(int dev_index)
{
+ enum periph_id id;
+
+ switch (dev_index) {
+ case 0:
+ id = PERIPH_ID_SDMMC0;
+ break;
+ case 1:
+ id = PERIPH_ID_SDMMC1;
+ break;
+ case 2:
+ id = PERIPH_ID_SDMMC2;
+ break;
+ case 3:
+ id = PERIPH_ID_SDMMC3;
+ break;
+ default:
+ debug("%s: invalid MMC index %d", __func__, dev_index);
+ return -1;
+ }
+
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_mmc_clk(dev_index);
- return exynos5_get_mmc_clk(dev_index);
+ return clock_get_periph_rate(id);
} else {
return exynos4_get_mmc_clk(dev_index);
}
@@ -1656,6 +1627,10 @@ unsigned long get_mmc_clk(int dev_index)
void set_mmc_clk(int dev_index, unsigned int div)
{
+ /* If want to set correct value, it needs to substract one from div.*/
+ if (div > 0)
+ div -= 1;
+
if (cpu_is_exynos5()) {
if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_set_mmc_clk(dev_index, div);
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index 94d0297..be43e22 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -266,22 +266,33 @@ static void exynos5_sromc_config(int flags)
static void exynos5_i2c_config(int peripheral, int flags)
{
+ int func01, func23;
+
+ /* High-Speed I2C */
+ if (flags & PINMUX_FLAG_HS_MODE) {
+ func01 = 4;
+ func23 = 4;
+ } else {
+ func01 = 2;
+ func23 = 3;
+ }
+
switch (peripheral) {
case PERIPH_ID_I2C0:
- gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(func01));
+ gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(func01));
break;
case PERIPH_ID_I2C1:
- gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(func01));
+ gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(func01));
break;
case PERIPH_ID_I2C2:
- gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(func23));
+ gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(func23));
break;
case PERIPH_ID_I2C3:
- gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(func23));
+ gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(func23));
break;
case PERIPH_ID_I2C4:
gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
index 1520d64..1b12051 100644
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -102,10 +102,34 @@ static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
}
}
+static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable)
+{
+ struct exynos5420_power *power =
+ (struct exynos5420_power *)samsung_get_base_power();
+
+ if (enable) {
+ /* Enabling USBDEV_PHY */
+ setbits_le32(&power->usbdev_phy_control,
+ POWER_USB_DRD_PHY_CTRL_EN);
+ setbits_le32(&power->usbdev1_phy_control,
+ POWER_USB_DRD_PHY_CTRL_EN);
+ } else {
+ /* Disabling USBDEV_PHY */
+ clrbits_le32(&power->usbdev_phy_control,
+ POWER_USB_DRD_PHY_CTRL_EN);
+ clrbits_le32(&power->usbdev1_phy_control,
+ POWER_USB_DRD_PHY_CTRL_EN);
+ }
+}
+
void set_usbdrd_phy_ctrl(unsigned int enable)
{
- if (cpu_is_exynos5())
- exynos5_set_usbdrd_phy_ctrl(enable);
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ exynos5420_set_usbdev_phy_ctrl(enable);
+ else
+ exynos5_set_usbdrd_phy_ctrl(enable);
+ }
}
static void exynos5_dp_phy_control(unsigned int enable)
diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c
index bc237c9..c7f943e 100644
--- a/arch/arm/cpu/armv7/exynos/spl_boot.c
+++ b/arch/arm/cpu/armv7/exynos/spl_boot.c
@@ -309,4 +309,3 @@ void board_init_r(gd_t *id, ulong dest_addr)
while (1)
;
}
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 7a9b03a..fef2231 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -12,6 +12,65 @@
#include <asm/io.h>
#include <asm/types.h>
+#if defined(CONFIG_MX6SX)
+/* Configure MX6SX mmdc iomux */
+void mx6sx_dram_iocfg(unsigned width,
+ const struct mx6sx_iomux_ddr_regs *ddr,
+ const struct mx6sx_iomux_grp_regs *grp)
+{
+ struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
+ struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
+
+ /* DDR IO TYPE */
+ writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
+ writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
+
+ /* CLOCK */
+ writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
+
+ /* ADDRESS */
+ writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
+ writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
+ writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
+
+ /* Control */
+ writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
+ writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
+ writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
+ writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
+ writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
+ writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
+ writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
+
+ /* Data Strobes */
+ writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
+ writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
+ writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
+ if (width >= 32) {
+ writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
+ writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
+ }
+
+ /* Data */
+ writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
+ writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
+ writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
+ if (width >= 32) {
+ writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
+ writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
+ }
+ writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
+ writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
+ if (width >= 32) {
+ writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
+ writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
+ }
+}
+#endif
+
#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
/* Configure MX6DQ mmdc iomux */
void mx6dq_dram_iocfg(unsigned width,
@@ -184,12 +243,19 @@ void mx6sdl_dram_iocfg(unsigned width,
*/
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
+#ifdef CONFIG_MX6SX
+#define MMDC1(entry, value) do {} while (0)
+#else
+#define MMDC1(entry, value) do { mmdc1->entry = value; } while (0)
+#endif
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
const struct mx6_mmdc_calibration *calib,
const struct mx6_ddr3_cfg *ddr3_cfg)
{
volatile struct mmdc_p_regs *mmdc0;
+#ifndef CONFIG_MX6SX
volatile struct mmdc_p_regs *mmdc1;
+#endif
u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@@ -203,7 +269,9 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
int cs;
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+#ifndef CONFIG_MX6SX
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+#endif
/* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
@@ -362,12 +430,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
mmdc0->mprddlctl = calib->p0_mprddlctl;
mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
if (sysinfo->dsize > 1) {
- mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0;
- mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1;
- mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0;
- mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1;
- mmdc1->mprddlctl = calib->p1_mprddlctl;
- mmdc1->mpwrdlctl = calib->p1_mpwrdlctl;
+ MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
+ MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
+ MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
+ MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
+ MMDC1(mprddlctl, calib->p1_mprddlctl);
+ MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
}
/* Read data DQ Byte0-3 delay */
@@ -379,23 +447,23 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
}
if (sysinfo->dsize > 1) {
- mmdc1->mprddqby0dl = 0x33333333;
- mmdc1->mprddqby1dl = 0x33333333;
- mmdc1->mprddqby2dl = 0x33333333;
- mmdc1->mprddqby3dl = 0x33333333;
+ MMDC1(mprddqby0dl, 0x33333333);
+ MMDC1(mprddqby1dl, 0x33333333);
+ MMDC1(mprddqby2dl, 0x33333333);
+ MMDC1(mprddqby3dl, 0x33333333);
}
/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
mmdc0->mpodtctrl = val;
if (sysinfo->dsize > 1)
- mmdc1->mpodtctrl = val;
+ MMDC1(mpodtctrl, val);
/* complete calibration */
val = (1 << 11); /* Force measurement on delay-lines */
mmdc0->mpmur0 = val;
if (sysinfo->dsize > 1)
- mmdc1->mpmur0 = val;
+ MMDC1(mpmur0, val);
/* Step 1: configuration request */
mmdc0->mdscr = (u32)(1 << 15); /* config request */
@@ -435,7 +503,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
val = 0xa1390001; /* one-time HW ZQ calib */
mmdc0->mpzqhwctrl = val;
if (sysinfo->dsize > 1)
- mmdc1->mpzqhwctrl = val;
+ MMDC1(mpzqhwctrl, val);
/* Step 7: Enable MMDC with desired chip select */
mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
@@ -477,7 +545,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
val = 0xa1390003;
mmdc0->mpzqhwctrl = val;
if (sysinfo->dsize > 1)
- mmdc1->mpzqhwctrl = val;
+ MMDC1(mpzqhwctrl, val);
/* Step 12: Configure and activate periodic refresh */
mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 5f5f497..e599a12 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -109,7 +109,7 @@ void init_aips(void)
aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
#ifdef CONFIG_MX6SX
- aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
+ aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
#endif
/*
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 8e7411d..03674e6 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -437,12 +437,15 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
{
u32 offset_code;
u32 offset = volt_mv;
+#ifndef CONFIG_DRA7XX
int ret = 0;
+#endif
if (!volt_mv)
return;
pmic->pmic_bus_init();
+#ifndef CONFIG_DRA7XX
/* See if we can first get the GPIO if needed */
if (pmic->gpio_en)
ret = gpio_request(pmic->gpio, "PMIC_GPIO");
@@ -456,7 +459,7 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
/* Pull the GPIO low to select SET0 register, while we program SET1 */
if (pmic->gpio_en)
gpio_direction_output(pmic->gpio, 0);
-
+#endif
/* convert to uV for better accuracy in the calculations */
offset *= 1000;
@@ -467,9 +470,10 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
printf("Scaling voltage failed for 0x%x\n", vcore_reg);
-
+#ifndef CONFIG_DRA7XX
if (pmic->gpio_en)
gpio_direction_output(pmic->gpio, 1);
+#endif
}
static u32 optimize_vcore_voltage(struct volts const *v)
@@ -505,13 +509,79 @@ static u32 optimize_vcore_voltage(struct volts const *v)
}
/*
- * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
- * We set the maximum voltages allowed here because Smart-Reflex is not
- * enabled in bootloader. Voltage initialization in the kernel will set
- * these to the nominal values after enabling Smart-Reflex
+ * Setup the voltages for the main SoC core power domains.
+ * We start with the maximum voltages allowed here, as set in the corresponding
+ * vcores_data struct, and then scale (usually down) to the fused values that
+ * are retrieved from the SoC. The scaling happens only if the efuse.reg fields
+ * are initialised.
+ * Rail grouping is supported for the DRA7xx SoCs only, therefore the code is
+ * compiled conditionally. Note that the new code writes the scaled (or zeroed)
+ * values back to the vcores_data struct for eventual reuse. Zero values mean
+ * that the corresponding rails are not controlled separately, and are not sent
+ * to the PMIC.
*/
void scale_vcores(struct vcores_data const *vcores)
{
+#if defined(CONFIG_DRA7XX)
+ int i;
+ struct volts *pv = (struct volts *)vcores;
+ struct volts *px;
+
+ for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) {
+ debug("%d -> ", pv->value);
+ if (pv->value) {
+ /* Handle non-empty members only */
+ pv->value = optimize_vcore_voltage(pv);
+ px = (struct volts *)vcores;
+ while (px < pv) {
+ /*
+ * Scan already handled non-empty members to see
+ * if we have a group and find the max voltage,
+ * which is set to the first occurance of the
+ * particular SMPS; the other group voltages are
+ * zeroed.
+ */
+ if (px->value) {
+ if ((pv->pmic->i2c_slave_addr ==
+ px->pmic->i2c_slave_addr) &&
+ (pv->addr == px->addr)) {
+ /* Same PMIC, same SMPS */
+ if (pv->value > px->value)
+ px->value = pv->value;
+
+ pv->value = 0;
+ }
+ }
+ px++;
+ }
+ }
+ debug("%d\n", pv->value);
+ pv++;
+ }
+
+ debug("cor: %d\n", vcores->core.value);
+ do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic);
+ debug("mpu: %d\n", vcores->mpu.value);
+ do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic);
+ /* Configure MPU ABB LDO after scale */
+ abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
+ (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
+ (*prcm)->prm_abbldo_mpu_setup,
+ (*prcm)->prm_abbldo_mpu_ctrl,
+ (*prcm)->prm_irqstatus_mpu_2,
+ OMAP_ABB_MPU_TXDONE_MASK,
+ OMAP_ABB_FAST_OPP);
+
+ /* The .mm member is not used for the DRA7xx */
+
+ debug("gpu: %d\n", vcores->gpu.value);
+ do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic);
+ debug("eve: %d\n", vcores->eve.value);
+ do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic);
+ debug("iva: %d\n", vcores->iva.value);
+ do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic);
+ /* Might need udelay(1000) here if debug is enabled to see all prints */
+#else
u32 val;
val = optimize_vcore_voltage(&vcores->core);
@@ -540,6 +610,7 @@ void scale_vcores(struct vcores_data const *vcores)
val = optimize_vcore_voltage(&vcores->iva);
do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
+#endif
}
static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index e601ba1..c01a98f 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -252,6 +252,8 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
+ writel(regs->sdram_config_init, &emif->emif_sdram_config);
/*
* Set SDRAM_CONFIG and PHY control registers to locked frequency
* and RL =7. As the default values of the Mode Registers are not
@@ -265,7 +267,6 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
- writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
/*
@@ -274,6 +275,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
*/
if (is_dra7xx()) {
do_ext_phy_settings(base, regs);
+ writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
} else {
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index 86c0e42..e19c7ae 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -19,7 +19,7 @@
ENTRY(save_boot_params)
ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
str r0, [r1]
- bx lr
+ b save_boot_params_ret
ENDPROC(save_boot_params)
ENTRY(set_pl310_ctrl_reg)
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index a029379..4644098 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -93,6 +93,21 @@ config TARGET_TWISTER
endchoice
+config DM
+ default y if !SPL_BUILD
+
+config DM_GPIO
+ default y if DM && !SPL_BUILD
+
+config DM_SERIAL
+ default y if DM && !SPL_BUILD
+
+config SYS_MALLOC_F
+ default y if DM && !SPL_BUILD
+
+config SYS_MALLOC_F_LEN
+ default 0x400 if DM && !SPL_BUILD
+
config SYS_SOC
default "omap3"
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 529ad9a..006969e 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -732,11 +732,20 @@ void per_clocks_enable(void)
setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */
setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */
+ /* Enable GP9 timer. */
+ setbits_le32(&prcm_base->clksel_per, 0x80); /* GPT9 = 32kHz clk */
+ setbits_le32(&prcm_base->iclken_per, 0x400); /* ICKen GPT9 */
+ setbits_le32(&prcm_base->fclken_per, 0x400); /* FCKen GPT9 */
+
#ifdef CONFIG_SYS_NS16550
/* Enable UART1 clocks */
setbits_le32(&prcm_base->fclken1_core, 0x00002000);
setbits_le32(&prcm_base->iclken1_core, 0x00002000);
+ /* Enable UART2 clocks */
+ setbits_le32(&prcm_base->fclken1_core, 0x00004000);
+ setbits_le32(&prcm_base->iclken1_core, 0x00004000);
+
/* UART 3 Clocks */
setbits_le32(&prcm_base->fclken_per, 0x00000800);
setbits_le32(&prcm_base->iclken_per, 0x00000800);
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index 78577b1..80cb263 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -23,7 +23,7 @@ ENTRY(save_boot_params)
ldr r5, [r0, #0x4]
and r5, r5, #0xff
str r5, [r4]
- bx lr
+ b save_boot_params_ret
ENDPROC(save_boot_params)
#endif
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index 7a29131..4f15ac9 100644
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -135,6 +135,9 @@ void do_sdrc_init(u32 cs, u32 early)
sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+ /* set some default timings */
+ timings.sharing = SDRC_SHARING;
+
/*
* When called in the early context this may be SPL and we will
* need to set all of the timings. This ends up being board
@@ -145,6 +148,7 @@ void do_sdrc_init(u32 cs, u32 early)
* setup CS1.
*/
#ifdef CONFIG_SPL_BUILD
+ /* set/modify board-specific timings */
get_board_mem_timings(&timings);
#endif
if (early) {
@@ -155,7 +159,7 @@ void do_sdrc_init(u32 cs, u32 early)
writel(0, &sdrc_base->sysconfig);
/* setup sdrc to ball mux */
- writel(SDRC_SHARING, &sdrc_base->sharing);
+ writel(timings.sharing, &sdrc_base->sharing);
/* Disable Power Down of CKE because of 1 CKE on combo part */
writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 95f1686..b9734fe 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -320,6 +320,7 @@ struct pmic_data palmas = {
.pmic_write = omap_vc_bypass_send_value,
};
+/* The TPS659038 and TPS65917 are software-compatible, use common struct */
struct pmic_data tps659038 = {
.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
.step = 10000, /* 10 mV represented in uV */
@@ -394,34 +395,38 @@ struct vcores_data dra752_volts = {
};
struct vcores_data dra722_volts = {
- .mpu.value = 1000,
+ .mpu.value = VDD_MPU_DRA72x,
.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
- .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = 0x23,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = TPS65917_REG_ADDR_SMPS1,
.mpu.pmic = &tps659038,
- .eve.value = 1000,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
- .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = 0x2f,
- .eve.pmic = &tps659038,
+ .core.value = VDD_CORE_DRA72x,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = TPS65917_REG_ADDR_SMPS2,
+ .core.pmic = &tps659038,
- .gpu.value = 1000,
+ /*
+ * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
+ * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
+ */
+ .gpu.value = VDD_GPU_DRA72x,
.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
- .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = 0x2f,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = TPS65917_REG_ADDR_SMPS3,
.gpu.pmic = &tps659038,
- .core.value = 1000,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
- .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = 0x27,
- .core.pmic = &tps659038,
+ .eve.value = VDD_EVE_DRA72x,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = TPS65917_REG_ADDR_SMPS3,
+ .eve.pmic = &tps659038,
- .iva.value = 1000,
+ .iva.value = VDD_IVA_DRA72x,
.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
- .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = 0x2f,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = TPS65917_REG_ADDR_SMPS3,
.iva.pmic = &tps659038,
};
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 7d8cec0..5f8daa1 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -141,7 +141,8 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61851ab2,
.sdram_config = 0x61851ab2,
.sdram_config2 = 0x08000000,
- .ref_ctrl = 0x00001035,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
@@ -151,10 +152,10 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
@@ -165,7 +166,8 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x08000000,
- .ref_ctrl = 0x00001035,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
@@ -175,10 +177,10 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
@@ -186,18 +188,19 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
};
const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
- .sdram_config_init = 0x61851AB2,
- .sdram_config = 0x61851AB2,
+ .sdram_config_init = 0x61862B32,
+ .sdram_config = 0x61862B32,
.sdram_config2 = 0x08000000,
- .ref_ctrl = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x027F88A8,
+ .ref_ctrl = 0x0000493E,
+ .ref_ctrl_final = 0x0000144A,
+ .sdram_tim1 = 0xD113781C,
+ .sdram_tim2 = 0x308F7FE3,
+ .sdram_tim3 = 0x009F86A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400A,
- .emif_ddr_phy_ctlr_1 = 0x0024400A,
+ .emif_ddr_phy_ctlr_1_init = 0x0E24400D,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400D,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
.emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
@@ -420,22 +423,22 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
- 0x00BB00BB,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
+ 0x00980098,
+ 0x00340034,
+ 0x00350035,
+ 0x00340034,
+ 0x00310031,
+ 0x00340034,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
+ 0x00480048,
+ 0x004A004A,
+ 0x00520052,
+ 0x00550055,
+ 0x00500050,
0x00000000,
0x00600020,
0x40010080,
@@ -449,22 +452,22 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
- 0x00BB00BB,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
+ 0x00980098,
+ 0x00330033,
+ 0x00330033,
+ 0x002F002F,
+ 0x00320032,
+ 0x00310031,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
+ 0x00520052,
+ 0x00520052,
+ 0x00470047,
+ 0x00490049,
+ 0x00500050,
0x00000000,
0x00600020,
0x40010080,
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig
index 6d94199..3586650 100644
--- a/arch/arm/cpu/armv7/rmobile/Kconfig
+++ b/arch/arm/cpu/armv7/rmobile/Kconfig
@@ -21,6 +21,9 @@ config TARGET_KZM9G
config TARGET_ALT
bool "Alt board"
+config TARGET_SILK
+ bool "Silk board"
+
endchoice
config SYS_SOC
@@ -28,7 +31,7 @@ config SYS_SOC
config RMOBILE_EXTRAM_BOOT
bool "Enable boot from RAM"
- depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER
+ depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_SILK
default n
source "board/atmark-techno/armadillo-800eva/Kconfig"
@@ -37,5 +40,6 @@ source "board/renesas/koelsch/Kconfig"
source "board/renesas/lager/Kconfig"
source "board/kmc/kzm9g/Kconfig"
source "board/renesas/alt/Kconfig"
+source "board/renesas/silk/Kconfig"
endif
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
index d47546a..a5dbbea 100644
--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
@@ -40,7 +40,7 @@ do_lowlevel_init:
and r1, r1, #0x7F00
lsrs r1, r1, #8
cmp r1, #0x4C /* 0x4C is ID of r8a7794 */
- beq _exit_init_l2_a15
+ beq _enable_actlr_smp
/* surpress wfe if ca15 */
tst r4, #4
@@ -64,6 +64,16 @@ do_lowlevel_init:
orrne r0, r0, #0x20 /* L2CTLR[5] */
#endif
mcrne p15, 1, r0, c9, c0, 2
+
+ b _exit_init_l2_a15
+
+_enable_actlr_smp: /* R8A7794 only (CA7) */
+#ifndef CONFIG_DCACHE_OFF
+ mrc p15, 0, r0, c1, c0, 1
+ orr r0, r0, #0x40
+ mcr p15, 0, r0, c1, c0, 1
+#endif
+
_exit_init_l2_a15:
ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
sub sp, r3, #4
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index fdc05b9..9b49ece 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -31,9 +31,12 @@
*************************************************************************/
.globl reset
+ .globl save_boot_params_ret
reset:
- bl save_boot_params
+ /* Allow the board to save important registers */
+ b save_boot_params
+save_boot_params_ret:
/*
* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
* except if in HYP mode already
@@ -52,10 +55,10 @@ reset:
* Continue to use ROM code vector only in OMAP4 spl)
*/
#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
- /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
- mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
+ /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
+ mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
bic r0, #CR_V @ V = 0
- mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
+ mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
/* Set vector address in CP15 VBAR register */
ldr r0, =_start
@@ -96,7 +99,7 @@ ENDPROC(c_runtime_cpu_setup)
*
*************************************************************************/
ENTRY(save_boot_params)
- bx lr @ back to my caller
+ b save_boot_params_ret @ back to my caller
ENDPROC(save_boot_params)
.weak save_boot_params
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 1c4b763..4bb12ad 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -11,12 +11,15 @@ obj-y += timer.o
obj-y += board.o
obj-y += clock.o
obj-y += cpu_info.o
+obj-y += dram_helpers.o
obj-y += pinmux.o
obj-y += usbc.o
obj-$(CONFIG_MACH_SUN6I) += prcm.o
obj-$(CONFIG_MACH_SUN8I) += prcm.o
+obj-$(CONFIG_MACH_SUN9I) += prcm.o
obj-$(CONFIG_MACH_SUN6I) += p2wi.o
obj-$(CONFIG_MACH_SUN8I) += rsb.o
+obj-$(CONFIG_MACH_SUN9I) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
@@ -36,7 +39,5 @@ obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o
-ifdef CONFIG_SPL_FEL
-obj-y += start.o
-endif
+obj-y += fel_utils.o
endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 6e28bcd..c02c015 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -27,6 +27,17 @@
#include <linux/compiler.h>
+struct fel_stash {
+ uint32_t sp;
+ uint32_t lr;
+ uint32_t cpsr;
+ uint32_t sctlr;
+ uint32_t vbar;
+ uint32_t cr;
+};
+
+struct fel_stash fel_stash __attribute__((section(".data")));
+
static int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
@@ -65,6 +76,12 @@ static int gpio_init(void)
return 0;
}
+void spl_board_load_image(void)
+{
+ debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
+ return_to_fel(fel_stash.sp, fel_stash.lr);
+}
+
void s_init(void)
{
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
@@ -95,7 +112,34 @@ void s_init(void)
*/
u32 spl_boot_device(void)
{
- return BOOT_DEVICE_MMC1;
+#ifdef CONFIG_SPL_FEL
+ /*
+ * This is the legacy compile time configuration for a special FEL
+ * enabled build. It has many restrictions and can only boot over USB.
+ */
+ return BOOT_DEVICE_BOARD;
+#else
+ /*
+ * When booting from the SD card, the "eGON.BT0" signature is expected
+ * to be found in memory at the address 0x0004 (see the "mksunxiboot"
+ * tool, which generates this header).
+ *
+ * When booting in the FEL mode over USB, this signature is patched in
+ * memory and replaced with something else by the 'fel' tool. This other
+ * signature is selected in such a way, that it can't be present in a
+ * valid bootable SD card image (because the BROM would refuse to
+ * execute the SPL in this case).
+ *
+ * This branch is just making a decision at runtime whether to load
+ * the main u-boot binary from the SD card (if the "eGON.BT0" signature
+ * is found) or return to the FEL code in the BROM to wait and receive
+ * the main u-boot binary over USB.
+ */
+ if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */
+ return BOOT_DEVICE_MMC1;
+ else
+ return BOOT_DEVICE_BOARD;
+#endif
}
/* No confirmation data available in SPL yet. Hardcode bootmode */
diff --git a/arch/arm/cpu/armv7/sunxi/config.mk b/arch/arm/cpu/armv7/sunxi/config.mk
index 00f5ffc..76ffec9 100644
--- a/arch/arm/cpu/armv7/sunxi/config.mk
+++ b/arch/arm/cpu/armv7/sunxi/config.mk
@@ -1,8 +1,6 @@
# Build a combined spl + u-boot image
ifdef CONFIG_SPL
ifndef CONFIG_SPL_BUILD
-ifndef CONFIG_SPL_FEL
ALL-y += u-boot-sunxi-with-spl.bin
endif
endif
-endif
diff --git a/arch/arm/cpu/armv7/sunxi/dram_helpers.c b/arch/arm/cpu/armv7/sunxi/dram_helpers.c
new file mode 100644
index 0000000..9a94e1b
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/dram_helpers.c
@@ -0,0 +1,37 @@
+/*
+ * DRAM init helper functions
+ *
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/dram.h>
+
+/*
+ * Wait up to 1s for value to be set in given part of reg.
+ */
+void mctl_await_completion(u32 *reg, u32 mask, u32 val)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+
+ while ((readl(reg) & mask) != val) {
+ if (timer_get_us() > tmo)
+ panic("Timeout initialising DRAM\n");
+ }
+}
+
+/*
+ * Test if memory at offset offset matches memory at begin of DRAM
+ */
+bool mctl_mem_matches(u32 offset)
+{
+ /* Try to write different values to RAM at two addresses */
+ writel(0, CONFIG_SYS_SDRAM_BASE);
+ writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset);
+ /* Check if the same value is actually observed when reading back */
+ return readl(CONFIG_SYS_SDRAM_BASE) ==
+ readl(CONFIG_SYS_SDRAM_BASE + offset);
+}
diff --git a/arch/arm/cpu/armv7/sunxi/fel_utils.S b/arch/arm/cpu/armv7/sunxi/fel_utils.S
new file mode 100644
index 0000000..bf00335
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/fel_utils.S
@@ -0,0 +1,42 @@
+/*
+ * Utility functions for FEL mode.
+ *
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+ ldr r0, =fel_stash
+ str sp, [r0, #0]
+ str lr, [r0, #4]
+ mrs lr, cpsr @ Read CPSR
+ str lr, [r0, #8]
+ mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
+ str lr, [r0, #12]
+ mrc p15, 0, lr, c12, c0, 0 @ Read VBAR
+ str lr, [r0, #16]
+ mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
+ str lr, [r0, #20]
+ b save_boot_params_ret
+ENDPROC(save_boot_params)
+
+ENTRY(return_to_fel)
+ mov sp, r0
+ mov lr, r1
+ ldr r0, =fel_stash
+ ldr r1, [r0, #20]
+ mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
+ ldr r1, [r0, #16]
+ mcr p15, 0, r1, c12, c0, 0 @ Write VBAR
+ ldr r1, [r0, #12]
+ mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
+ ldr r1, [r0, #8]
+ msr cpsr, r1 @ Write CPSR
+ bx lr
+ENDPROC(return_to_fel)
diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c
index b72bb9d..b00befb 100644
--- a/arch/arm/cpu/armv7/sunxi/rsb.c
+++ b/arch/arm/cpu/armv7/sunxi/rsb.c
@@ -16,14 +16,27 @@
#include <asm/arch/prcm.h>
#include <asm/arch/rsb.h>
+static int rsb_set_device_mode(void);
+
static void rsb_cfg_io(void)
{
+#ifdef CONFIG_MACH_SUN8I
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
+#elif defined CONFIG_MACH_SUN9I
+ sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN0_R_RSB_SCK);
+ sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN1_R_RSB_SDA);
+ sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
+ sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
+ sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
+ sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
+#else
+#error unsupported MACH_SUNXI
+#endif
}
static void rsb_set_clk(void)
@@ -42,7 +55,7 @@ static void rsb_set_clk(void)
writel((cd_odly << 8) | div, &rsb->ccr);
}
-void rsb_init(void)
+int rsb_init(void)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
@@ -54,6 +67,8 @@ void rsb_init(void)
writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
rsb_set_clk();
+
+ return rsb_set_device_mode();
}
static int rsb_await_trans(void)
@@ -88,13 +103,14 @@ static int rsb_await_trans(void)
return ret;
}
-int rsb_set_device_mode(u32 device_mode_data)
+static int rsb_set_device_mode(void)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
unsigned long tmo = timer_get_us() + 1000000;
- writel(RSB_DMCR_DEVICE_MODE_START | device_mode_data, &rsb->dmcr);
+ writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
+ &rsb->dmcr);
while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
if (timer_get_us() > tmo)
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
deleted file mode 100644
index 928b7c1..0000000
--- a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2013
- * Henrik Nordstrom <henrik@henriknordstrom.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(s_init)
-SECTIONS
-{
- . = 0x00002000;
-
- . = ALIGN(4);
- .text :
- {
- *(.text.s_init)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
- . = .;
-
- . = ALIGN(4);
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- . = ALIGN(4);
- .note.gnu.build-id :
- {
- *(.note.gnu.build-id)
- }
- _end = .;
-
- . = ALIGN(4096);
- .mmutable : {
- *(.mmutable)
- }
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
- /DISCARD/ : { *(.note*) }
-}
diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig
deleted file mode 100644
index 1446452..0000000
--- a/arch/arm/cpu/armv7/tegra-common/Kconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-if TEGRA
-
-choice
- prompt "Tegra SoC select"
-
-config TEGRA20
- bool "Tegra20 family"
-
-config TEGRA30
- bool "Tegra30 family"
-
-config TEGRA114
- bool "Tegra114 family"
-
-config TEGRA124
- bool "Tegra124 family"
-
-endchoice
-
-config USE_PRIVATE_LIBGCC
- default y if SPL_BUILD
-
-source "arch/arm/cpu/armv7/tegra20/Kconfig"
-source "arch/arm/cpu/armv7/tegra30/Kconfig"
-source "arch/arm/cpu/armv7/tegra114/Kconfig"
-source "arch/arm/cpu/armv7/tegra124/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/tegra-common/Makefile b/arch/arm/cpu/armv7/tegra-common/Makefile
deleted file mode 100644
index 463c260..0000000
--- a/arch/arm/cpu/armv7/tegra-common/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
diff --git a/arch/arm/cpu/armv7/tegra20/Makefile b/arch/arm/cpu/armv7/tegra20/Makefile
deleted file mode 100644
index 9b4295c..0000000
--- a/arch/arm/cpu/armv7/tegra20/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_PWM_TEGRA) += pwm.o
-obj-$(CONFIG_VIDEO_TEGRA) += display.o
diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig
index 0556e4b..1a47ac9 100644
--- a/arch/arm/cpu/armv7/uniphier/Kconfig
+++ b/arch/arm/cpu/armv7/uniphier/Kconfig
@@ -48,23 +48,20 @@ config DCC_MICRO_SUPPORT_CARD
endchoice
+config SYS_MALLOC_F
+ default y
+
+config SYS_MALLOC_F_LEN
+ default 0x2000
+
config CMD_PINMON
bool "Enable boot mode pins monitor command"
- depends on !SPL_BUILD
default y
help
The command "pinmon" shows the state of the boot mode pins.
The boot mode pins are latched when the system reset is deasserted
and determine which device the system should load a boot image from.
-config SOC_INIT
- bool
- default SPL_BUILD
-
-config DRAM_INIT
- bool
- default SPL_BUILD
-
config CMD_DDRPHY_DUMP
bool "Enable dump command of DDR PHY parameters"
depends on !SPL_BUILD
@@ -74,7 +71,7 @@ config CMD_DDRPHY_DUMP
choice
prompt "DDR3 Frequency select"
- depends on DRAM_INIT
+ depends on SPL_BUILD
config DDR_FREQ_1600
bool "DDR3 1600"
diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile
index 0546232..df418dd 100644
--- a/arch/arm/cpu/armv7/uniphier/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/Makefile
@@ -2,23 +2,32 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_SPL_BUILD) += lowlevel_init.o init_page_table.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+ifdef CONFIG_SPL_BUILD
-obj-y += timer.o
-obj-y += reset.o
-obj-y += cache_uniphier.o
-obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o
-obj-y += dram_init.o
-obj-$(CONFIG_DRAM_INIT) += ddrphy_training.o
+obj-y += lowlevel_init.o
+obj-y += init_page_table.o
+obj-y += spl.o
+obj-y += ddrphy_training.o
+
+else
+
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
+obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o
+obj-y += dram_init.o
+obj-y += board_common.o
obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
+obj-y += reset.o
+obj-y += cache_uniphier.o
obj-$(CONFIG_UNIPHIER_SMP) += smp.o
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
-obj-y += board_common.o
+endif
+
+obj-y += timer.o
+
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
diff --git a/arch/arm/cpu/armv7/uniphier/board_early_init_f.c b/arch/arm/cpu/armv7/uniphier/board_early_init_f.c
new file mode 100644
index 0000000..d25bbae
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/board_early_init_f.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2012-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/led.h>
+#include <asm/arch/board.h>
+
+void pin_init(void);
+
+int board_early_init_f(void)
+{
+ led_write(U, 0, , );
+
+ pin_init();
+
+ led_write(U, 1, , );
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/uniphier/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/board_postclk_init.c
deleted file mode 100644
index 89e44bb..0000000
--- a/arch/arm/cpu/armv7/uniphier/board_postclk_init.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/compiler.h>
-#include <asm/arch/led.h>
-#include <asm/arch/board.h>
-
-void __weak bcu_init(void)
-{
-};
-void sbc_init(void);
-void sg_init(void);
-void pll_init(void);
-void pin_init(void);
-void clkrst_init(void);
-
-int board_postclk_init(void)
-{
-#ifdef CONFIG_SOC_INIT
- bcu_init();
-
- sbc_init();
-
- sg_init();
-
- uniphier_board_reset();
-
- pll_init();
-
- uniphier_board_init();
-
- led_write(B, 1, , );
-
- clkrst_init();
-
- led_write(B, 2, , );
-#endif
- pin_init();
-
- led_write(B, 3, , );
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c b/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c
index 3561b40..3c1b325 100644
--- a/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c
+++ b/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c
@@ -11,20 +11,17 @@
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- struct boot_device_info *table;
- u32 mode_sel, n = 0;
-
- mode_sel = get_boot_mode_sel();
+ int mode_sel, i;
printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
+ mode_sel = get_boot_mode_sel();
+
puts("Boot Mode Pin:\n");
- for (table = boot_device_table; strlen(table->info); table++) {
- printf(" %c %02x %s\n", n == mode_sel ? '*' : ' ', n,
- table->info);
- n++;
- }
+ for (i = 0; boot_device_table[i].info; i++)
+ printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+ boot_device_table[i].info);
return 0;
}
diff --git a/arch/arm/cpu/armv7/uniphier/dram_init.c b/arch/arm/cpu/armv7/uniphier/dram_init.c
index 7de657b..4b8c938 100644
--- a/arch/arm/cpu/armv7/uniphier/dram_init.c
+++ b/arch/arm/cpu/armv7/uniphier/dram_init.c
@@ -1,37 +1,16 @@
/*
- * Copyright (C) 2012-2014 Panasonic Corporation
+ * Copyright (C) 2012-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <asm/arch/led.h>
-
-int umc_init(void);
-void enable_dpll_ssc(void);
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-#ifdef CONFIG_DRAM_INIT
- led_write(B, 4, , );
-
- {
- int res;
-
- res = umc_init();
- if (res < 0)
- return res;
- }
- led_write(B, 5, , );
-
- enable_dpll_ssc();
-#endif
-
- led_write(B, 6, , );
-
return 0;
}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
index 0752906..72f4663 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
@@ -2,11 +2,13 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
+obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
+ pll_spectrum.o umc_init.o ddrphy_init.o
+else
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
+endif
+
obj-y += boot-mode.o
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
- clkrst_init.o
-obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
-obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
index 8206e2a..e330fda 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
@@ -2,10 +2,13 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
+obj-y += sbc_init.o sg_init.o pll_init.o clkrst_init.o \
+ pll_spectrum.o umc_init.o ddrphy_init.o
+else
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
+endif
+
obj-y += boot-mode.o
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o
-obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
-obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c
deleted file mode 100644
index 325a4f6..0000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/board.h>
-
-int checkboard(void)
-{
- puts("Board: PH1-Pro4 Board\n");
-
- return check_support_card();
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c
index 33bccff..c31b74b 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c
@@ -45,17 +45,17 @@ struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, ""}
+ { /* sentinel */ }
};
-u32 get_boot_mode_sel(void)
+int get_boot_mode_sel(void)
{
return (readl(SG_PINMON0) >> 1) & 0x1f;
}
u32 spl_boot_device(void)
{
- u32 boot_mode;
+ int boot_mode;
if (boot_is_swapped())
return BOOT_DEVICE_NOR;
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
index 0752906..72f4663 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
@@ -2,11 +2,13 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
+obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
+ pll_spectrum.o umc_init.o ddrphy_init.o
+else
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
+endif
+
obj-y += boot-mode.o
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
- clkrst_init.o
-obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
-obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c
deleted file mode 100644
index 15dc289..0000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/board.h>
-
-int checkboard(void)
-{
- puts("Board: PH1-sLD8 Board\n");
-
- return check_support_card();
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c
index 2b6403f..5e80335 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c
@@ -26,6 +26,15 @@ void pin_init(void)
sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
#endif
+#ifdef CONFIG_SYS_I2C_UNIPHIER
+ {
+ u32 tmp;
+ tmp = readl(SG_IECTRL);
+ tmp |= 0xc00; /* enable SCL0, SDA0, SCL1, SDA1 */
+ writel(tmp, SG_IECTRL);
+ }
+#endif
+
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(15, 0); /* XNFRE_GB -> XNFRE_GB */
sg_set_pinsel(16, 0); /* XNFWE_GB -> XNFWE_GB */
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c b/arch/arm/cpu/armv7/uniphier/print_misc_info.c
index 27d772e..69cfab5 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c
+++ b/arch/arm/cpu/armv7/uniphier/print_misc_info.c
@@ -1,16 +1,13 @@
/*
- * Copyright (C) 2012-2014 Panasonic Corporation
+ * Copyright (C) 2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
#include <asm/arch/board.h>
-int checkboard(void)
+int misc_init_f(void)
{
- puts("Board: PH1-LD4 Board\n");
-
return check_support_card();
}
diff --git a/arch/arm/cpu/armv7/uniphier/spl.c b/arch/arm/cpu/armv7/uniphier/spl.c
index 40d28ad..8a4eafc 100644
--- a/arch/arm/cpu/armv7/uniphier/spl.c
+++ b/arch/arm/cpu/armv7/uniphier/spl.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2013-2014 Panasonic Corporation
+ * Copyright (C) 2013-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -7,11 +7,53 @@
#include <common.h>
#include <spl.h>
+#include <linux/compiler.h>
+#include <asm/arch/led.h>
+#include <asm/arch/board.h>
+
+void __weak bcu_init(void)
+{
+};
+void sbc_init(void);
+void sg_init(void);
+void pll_init(void);
+void pin_init(void);
+void clkrst_init(void);
+int umc_init(void);
+void enable_dpll_ssc(void);
void spl_board_init(void)
{
-#if defined(CONFIG_BOARD_POSTCLK_INIT)
- board_postclk_init();
-#endif
- dram_init();
+ bcu_init();
+
+ sbc_init();
+
+ sg_init();
+
+ uniphier_board_reset();
+
+ pll_init();
+
+ uniphier_board_init();
+
+ led_write(L, 0, , );
+
+ clkrst_init();
+
+ led_write(L, 1, , );
+
+ {
+ int res;
+
+ res = umc_init();
+ if (res < 0) {
+ while (1)
+ ;
+ }
+ }
+ led_write(L, 2, , );
+
+ enable_dpll_ssc();
+
+ led_write(L, 3, , );
}
diff --git a/arch/arm/dts/exynos4.dtsi b/arch/arm/dts/exynos4.dtsi
index 77fad48..7de227c 100644
--- a/arch/arm/dts/exynos4.dtsi
+++ b/arch/arm/dts/exynos4.dtsi
@@ -51,56 +51,64 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- interrupts = <0 0 0>;
+ reg = <0x13860000 0x100>;
+ interrupts = <0 56 0>;
};
i2c@13870000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- interrupts = <1 1 0>;
+ reg = <0x13870000 0x100>;
+ interrupts = <1 57 0>;
};
i2c@13880000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- interrupts = <2 2 0>;
+ reg = <0x13880000 0x100>;
+ interrupts = <2 58 0>;
};
i2c@13890000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- interrupts = <3 3 0>;
+ reg = <0x13890000 0x100>;
+ interrupts = <3 59 0>;
};
i2c@138a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- interrupts = <4 4 0>;
+ reg = <0x138a0000 0x100>;
+ interrupts = <4 60 0>;
};
i2c@138b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- interrupts = <5 5 0>;
+ reg = <0x138b0000 0x100>;
+ interrupts = <5 61 0>;
};
i2c@138c0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- interrupts = <6 6 0>;
+ reg = <0x138c0000 0x100>;
+ interrupts = <6 62 0>;
};
i2c@138d0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- interrupts = <7 7 0>;
+ reg = <0x138d0000 0x100>;
+ interrupts = <7 63 0>;
};
sdhci@12510000 {
@@ -143,11 +151,4 @@
interrupts = <0 131 0>;
};
- gpio: gpio {
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
};
diff --git a/arch/arm/dts/exynos4210-origen.dts b/arch/arm/dts/exynos4210-origen.dts
index dd2476c..3f87761 100644
--- a/arch/arm/dts/exynos4210-origen.dts
+++ b/arch/arm/dts/exynos4210-origen.dts
@@ -36,7 +36,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 0xA2 0>;
+ cd-gpios = <&gpk2 2 0>;
};
sdhci@12540000 {
diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts
index 8c7a2c3..36d02df 100644
--- a/arch/arm/dts/exynos4210-trats.dts
+++ b/arch/arm/dts/exynos4210-trats.dts
@@ -101,7 +101,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
- pwr-gpios = <&gpio 146 0>;
+ pwr-gpios = <&gpk0 2 0>;
};
sdhci@12520000 {
@@ -111,7 +111,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 284 0>;
+ cd-gpios = <&gpx3 4 0>;
};
sdhci@12540000 {
diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts
index 808c3f7..16948c9 100644
--- a/arch/arm/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/dts/exynos4210-universal_c210.dts
@@ -24,7 +24,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
- pwr-gpios = <&gpio 146 0>;
+ pwr-gpios = <&gpk0 2 0>;
};
sdhci@12520000 {
@@ -34,7 +34,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 284 0>;
+ cd-gpios = <&gpx3 4 0>;
};
sdhci@12540000 {
@@ -43,10 +43,10 @@
soft-spi {
compatible = "u-boot,soft-spi";
- cs-gpio = <&gpio 235 0>; /* Y43 */
- sclk-gpio = <&gpio 225 0>; /* Y31 */
- mosi-gpio = <&gpio 227 0>; /* Y33 */
- miso-gpio = <&gpio 224 0>; /* Y30 */
+ cs-gpio = <&gpy4 3 0>;
+ sclk-gpio = <&gpy3 1 0>;
+ mosi-gpio = <&gpy3 3 0>;
+ miso-gpio = <&gpy3 0 0>;
spi-delay-us = <1>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts
index c78efec..582f6e5 100644
--- a/arch/arm/dts/exynos4412-odroid.dts
+++ b/arch/arm/dts/exynos4412-odroid.dts
@@ -16,6 +16,13 @@
aliases {
i2c0 = "/i2c@13860000";
+ i2c1 = "/i2c@13870000";
+ i2c2 = "/i2c@13880000";
+ i2c3 = "/i2c@13890000";
+ i2c4 = "/i2c@138a0000";
+ i2c5 = "/i2c@138b0000";
+ i2c6 = "/i2c@138c0000";
+ i2c7 = "/i2c@138d0000";
serial0 = "/serial@13800000";
console = "/serial@13810000";
mmc2 = "sdhci@12530000";
@@ -51,7 +58,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 122 0>;
+ cd-gpios = <&gpk2 2 0>;
};
sdhci@12540000 {
@@ -78,4 +85,9 @@
reg = <0x125B0000 0x100>;
};
};
+
+ emmc-reset {
+ compatible = "samsung,emmc-reset";
+ reset-gpio = <&gpk1 2 0>;
+ };
};
diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts
index 60e4515..dd238df 100644
--- a/arch/arm/dts/exynos4412-trats2.dts
+++ b/arch/arm/dts/exynos4412-trats2.dts
@@ -416,7 +416,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
- pwr-gpios = <&gpio 0x6a 0>;
+ pwr-gpios = <&gpk0 4 0>;
status = "disabled";
};
@@ -427,7 +427,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
- cd-gpios = <&gpio 0x7a 0>;
+ cd-gpios = <&gpk2 2 0>;
};
sdhci@12540000 {
@@ -437,7 +437,7 @@
dwmmc@12550000 {
samsung,bus-width = <8>;
samsung,timing = <2 1 0>;
- pwr-gpios = <&gpio 0x6a 0>;
+ pwr-gpios = <&gpk0 4 0>;
fifoth_val = <0x203f0040>;
bus_hz = <400000000>;
div = <0x3>;
diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
index e539068..238acb8 100644
--- a/arch/arm/dts/exynos5.dtsi
+++ b/arch/arm/dts/exynos5.dtsi
@@ -6,6 +6,7 @@
*/
#include "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "samsung,exynos5";
@@ -247,7 +248,4 @@
u-boot,dm-pre-reloc;
id = <3>;
};
-
- gpio: gpio {
- };
};
diff --git a/arch/arm/dts/exynos5250-arndale.dts b/arch/arm/dts/exynos5250-arndale.dts
index 202f2ea..21c0a21 100644
--- a/arch/arm/dts/exynos5250-arndale.dts
+++ b/arch/arm/dts/exynos5250-arndale.dts
@@ -15,6 +15,14 @@
compatible = "samsung,arndale", "samsung,exynos5250";
aliases {
+ i2c0 = "/i2c@12c60000";
+ i2c1 = "/i2c@12c70000";
+ i2c2 = "/i2c@12c80000";
+ i2c3 = "/i2c@12c90000";
+ i2c4 = "/i2c@12ca0000";
+ i2c5 = "/i2c@12cb0000";
+ i2c6 = "/i2c@12cc0000";
+ i2c7 = "/i2c@12cd0000";
serial0 = "/serial@12C20000";
console = "/serial@12C20000";
};
diff --git a/arch/arm/dts/exynos5250-smdk5250.dts b/arch/arm/dts/exynos5250-smdk5250.dts
index 8850409..9273562 100644
--- a/arch/arm/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/dts/exynos5250-smdk5250.dts
@@ -146,6 +146,6 @@
};
ehci@12110000 {
- samsung,vbus-gpio = <&gpio 0x316 0>; /* X26 */
+ samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts
index bac5015..7d8be69 100644
--- a/arch/arm/dts/exynos5250-snow.dts
+++ b/arch/arm/dts/exynos5250-snow.dts
@@ -44,7 +44,8 @@
reg = <0x1e>;
compatible = "google,cros-ec";
i2c-max-frequency = <100000>;
- ec-interrupt = <&gpio 182 1>;
+ u-boot,i2c-offset-len = <0>;
+ ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>;
};
power-regulator@48 {
@@ -68,7 +69,7 @@
reg = <0>;
compatible = "google,cros-ec";
spi-max-frequency = <5000000>;
- ec-interrupt = <&gpio 182 1>;
+ ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>;
optimise-flash-write;
status = "disabled";
};
@@ -76,7 +77,7 @@
sound@3830000 {
samsung,codec-type = "max98095";
- codec-enable-gpio = <&gpio 0xb7 0>;
+ codec-enable-gpio = <&gpx1 7 GPIO_ACTIVE_HIGH>;
};
sound@12d60000 {
@@ -131,11 +132,11 @@
};
ehci@12110000 {
- samsung,vbus-gpio = <&gpio 0xb1 0>; /* X11 */
+ samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
};
xhci@12000000 {
- samsung,vbus-gpio = <&gpio 0xbf 0>; /* X27 */
+ samsung,vbus-gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>;
};
tmu@10060000 {
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts
index d1d8735..b801de9 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -17,7 +17,7 @@
"google,peach", "samsung,exynos5420", "samsung,exynos5";
config {
- google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */
+ google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
hwid = "PIT TEST A-A 7848";
lazy-init = <1>;
};
@@ -108,7 +108,7 @@
spi-half-duplex;
spi-max-timeout-ms = <1100>;
spi-frame-header = <0xec>;
- ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
+ ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
/*
* This describes the flash memory within the EC. Note
@@ -124,11 +124,11 @@
};
xhci@12000000 {
- samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */
+ samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>;
};
xhci@12400000 {
- samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
+ samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>;
};
fimd@14400000 {
diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts
index 79a7acd..d0a8621 100644
--- a/arch/arm/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/dts/exynos5422-odroidxu3.dts
@@ -32,7 +32,7 @@
};
ehci@12110000 {
- samsung,vbus-gpio = <&gpio 0x66 0>; /* X26 */
+ samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
};
serial@12C20000 {
@@ -46,4 +46,9 @@
mmc@12220000 {
fifoth_val = <0x201f0020>;
};
+
+ emmc-reset {
+ compatible = "samsung,emmc-reset";
+ reset-gpio = <&gpd1 0 0>;
+ };
};
diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts
index e7c380f..e4bc100 100644
--- a/arch/arm/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/dts/exynos5800-peach-pi.dts
@@ -17,7 +17,7 @@
"google,peach", "samsung,exynos5800", "samsung,exynos5";
config {
- google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */
+ google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
hwid = "PIT TEST A-A 7848";
lazy-init = <1>;
};
@@ -32,7 +32,7 @@
mem-manuf = "samsung";
mem-type = "ddr3";
clock-frequency = <800000000>;
- arm-frequency = <1700000000>;
+ arm-frequency = <900000000>;
};
tmu@10060000 {
@@ -102,7 +102,7 @@
spi-half-duplex;
spi-max-timeout-ms = <1100>;
spi-frame-header = <0xec>;
- ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
+ ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
/*
* This describes the flash memory within the EC. Note
@@ -118,11 +118,11 @@
};
xhci@12000000 {
- samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */
+ samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>;
};
xhci@12400000 {
- samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
+ samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>;
};
fimd@14400000 {
diff --git a/arch/arm/dts/tegra114-dalmore.dts b/arch/arm/dts/tegra114-dalmore.dts
index 81ad212..51ff266 100644
--- a/arch/arm/dts/tegra114-dalmore.dts
+++ b/arch/arm/dts/tegra114-dalmore.dts
@@ -57,7 +57,7 @@
};
sdhci@78000400 {
- cd-gpios = <&gpio 170 1>; /* gpio PV2 */
+ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
@@ -68,8 +68,7 @@
};
usb@7d008000 {
- /* SPDIF_IN: USB_VBUS_EN1 */
- nvidia,vbus-gpio = <&gpio 86 0>;
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts
index 51fef54..e7b66d8 100644
--- a/arch/arm/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/dts/tegra124-jetson-tk1.dts
@@ -303,8 +303,9 @@
sdhci@700b0400 {
status = "okay";
- cd-gpios = <&gpio 170 1>; /* gpio PV2 */
- power-gpios = <&gpio 136 0>; /* gpio PR0 */
+ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -316,12 +317,12 @@
usb@7d000000 {
status = "okay";
dr_mode = "otg";
- nvidia,vbus-gpio = <&gpio 108 0>; /* gpio PN4, USB_VBUS_EN0 */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
};
usb@7d008000 {
status = "okay";
- nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
};
regulators {
diff --git a/arch/arm/dts/tegra124-venice2.dts b/arch/arm/dts/tegra124-venice2.dts
index f7ccfc5..9e93cf9 100644
--- a/arch/arm/dts/tegra124-venice2.dts
+++ b/arch/arm/dts/tegra124-venice2.dts
@@ -72,8 +72,9 @@
sdhci@700b0400 {
status = "okay";
- cd-gpios = <&gpio 170 0>; /* gpio PV2 */
- power-gpios = <&gpio 136 0>; /* gpio PR0 */
+ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
bus-width = <4>;
};
@@ -85,11 +86,11 @@
usb@7d000000 {
status = "okay";
dr_mode = "otg";
- nvidia,vbus-gpio = <&gpio 108 0>; /* gpio PN4, USB_VBUS_EN0 */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
};
usb@7d008000 {
status = "okay";
- nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/dts/tegra20-colibri_t20_iris.dts b/arch/arm/dts/tegra20-colibri_t20_iris.dts
index 7cf08f4..3131b92 100644
--- a/arch/arm/dts/tegra20-colibri_t20_iris.dts
+++ b/arch/arm/dts/tegra20-colibri_t20_iris.dts
@@ -22,16 +22,16 @@
};
usb@c5004000 {
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* PV1 */
- nvidia,vbus-gpio = <&gpio 217 0>; /* PBB1 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
};
usb@c5008000 {
- nvidia,vbus-gpio = <&gpio 178 1>; /* PW2 low-active */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
};
nand-controller@70008000 {
- nvidia,wp-gpios = <&gpio 144 0>; /* PS0 */
+ nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
nvidia,width = <8>;
nvidia,timing = <15 100 25 80 25 10 15 10 100>;
@@ -43,7 +43,7 @@
sdhci@c8000600 {
status = "okay";
- cd-gpios = <&gpio 23 1>; /* gpio PC7 */
+ cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
bus-width = <4>;
};
};
diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts
index 982a14c..e6e4229 100644
--- a/arch/arm/dts/tegra20-harmony.dts
+++ b/arch/arm/dts/tegra20-harmony.dts
@@ -37,7 +37,7 @@
};
nand-controller@70008000 {
- nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
+ nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
nvidia,width = <8>;
nvidia,timing = <26 100 20 80 20 10 12 10 70>;
nand@0 {
@@ -67,22 +67,22 @@
};
usb@c5004000 {
- nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+ nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
};
sdhci@c8000200 {
status = "okay";
- cd-gpios = <&gpio 69 1>; /* gpio PI5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 155 0>; /* gpio PT3 */
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
sdhci@c8000600 {
status = "okay";
- cd-gpios = <&gpio 58 1>; /* gpio PH2 */
- wp-gpios = <&gpio 59 0>; /* gpio PH3 */
- power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <8>;
};
@@ -100,10 +100,14 @@
vsyncx-active-high;
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 0 0>;
- nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
- nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
- nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
- nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */
+ nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
+ GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <0 0 200 0 0>;
};
};
diff --git a/arch/arm/dts/tegra20-medcom-wide.dts b/arch/arm/dts/tegra20-medcom-wide.dts
index be2ed42..b6b57ab 100644
--- a/arch/arm/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/dts/tegra20-medcom-wide.dts
@@ -73,9 +73,12 @@
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 0 500000>;
- nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
- nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
- nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
+ nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
+ GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <0 0 0 0>;
};
};
diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts
index 9d735b5..16381c3 100644
--- a/arch/arm/dts/tegra20-paz00.dts
+++ b/arch/arm/dts/tegra20-paz00.dts
@@ -61,9 +61,9 @@
sdhci@c8000000 {
status = "okay";
- cd-gpios = <&gpio 173 1>; /* gpio PV5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 169 0>; /* gpio PV1 */
+ cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -86,10 +86,14 @@
hsync-active-high;
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 0 0>;
- nvidia,backlight-enable-gpios = <&gpio 164 0>; /* PU4 */
- nvidia,lvds-shutdown-gpios = <&gpio 102 0>; /* PM6 */
- nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
- nvidia,panel-vdd-gpios = <&gpio 4 0>; /* PA4 */
+ nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(U, 4)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(M, 6)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(A, 4)
+ GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <400 4 203 17 15>;
};
};
diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts
index 43b9911..10f3992 100644
--- a/arch/arm/dts/tegra20-seaboard.dts
+++ b/arch/arm/dts/tegra20-seaboard.dts
@@ -65,7 +65,7 @@
};
nand-controller@70008000 {
- nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */
+ nvidia,wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
nvidia,width = <8>;
nvidia,timing = <26 100 20 80 20 10 12 10 70>;
nand@0 {
@@ -151,7 +151,7 @@
};
usb@c5000000 {
- nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
dr_mode = "otg";
};
@@ -161,9 +161,9 @@
sdhci@c8000400 {
status = "okay";
- cd-gpios = <&gpio 69 1>; /* gpio PI5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -186,10 +186,14 @@
hsync-active-high;
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 2 0>;
- nvidia,backlight-enable-gpios = <&gpio 28 0>; /* PD4 */
- nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
- nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
- nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */
+ nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
+ GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <400 4 203 17 15>;
};
};
diff --git a/arch/arm/dts/tegra20-tamonten.dtsi b/arch/arm/dts/tegra20-tamonten.dtsi
index f379622..78449e6 100644
--- a/arch/arm/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/dts/tegra20-tamonten.dtsi
@@ -14,7 +14,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
- nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
};
};
@@ -280,7 +281,7 @@
};
nand-controller@70008000 {
- nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
+ nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
nvidia,width = <8>;
nvidia,timing = <26 100 20 80 20 10 12 10 70>;
@@ -476,8 +477,8 @@
};
sdhci@c8000600 {
- cd-gpios = <&gpio 58 1>; /* gpio PH2 */
- wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+ cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
status = "okay";
};
diff --git a/arch/arm/dts/tegra20-tec.dts b/arch/arm/dts/tegra20-tec.dts
index e99bd44..94ba6dc 100644
--- a/arch/arm/dts/tegra20-tec.dts
+++ b/arch/arm/dts/tegra20-tec.dts
@@ -73,9 +73,12 @@
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 0 500000>;
- nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
- nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
- nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
+ nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
+ GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <0 0 0 0>;
};
};
diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts
index 1637cbd..27b118f 100644
--- a/arch/arm/dts/tegra20-trimslice.dts
+++ b/arch/arm/dts/tegra20-trimslice.dts
@@ -62,7 +62,7 @@
};
usb@c5000000 {
- nvidia,vbus-gpio = <&gpio 170 0>; /* PV2 */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
};
usb@c5004000 {
@@ -76,8 +76,8 @@
sdhci@c8000600 {
status = "okay";
- cd-gpios = <&gpio 121 1>; /* gpio PP1 */
- wp-gpios = <&gpio 122 0>; /* gpio PP2 */
+ cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -111,7 +111,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
+ gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
};
diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts
index 6812203..939e567 100644
--- a/arch/arm/dts/tegra20-ventana.dts
+++ b/arch/arm/dts/tegra20-ventana.dts
@@ -61,9 +61,9 @@
sdhci@c8000400 {
status = "okay";
- cd-gpios = <&gpio 69 1>; /* gpio PI5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -86,10 +86,14 @@
vsync-active-high;
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 2 0>;
- nvidia,backlight-enable-gpios = <&gpio 28 0>; /* PD4 */
- nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
- nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
- nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */
+ nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
+ GPIO_ACTIVE_HIGH>;
+ nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
+ GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <0 0 200 0 0>;
};
};
diff --git a/arch/arm/dts/tegra20-whistler.dts b/arch/arm/dts/tegra20-whistler.dts
index 4fd2496..c4a28eb 100644
--- a/arch/arm/dts/tegra20-whistler.dts
+++ b/arch/arm/dts/tegra20-whistler.dts
@@ -66,7 +66,7 @@
sdhci@c8000400 {
status = "okay";
- wp-gpios = <&gpio 173 0>; /* gpio PV5 */
+ wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
bus-width = <8>;
};
diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index 5bad3e7..15db0f2 100644
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -243,13 +243,13 @@
sdhci@78000000 {
status = "okay";
bus-width = <4>;
- cd-gpios = <&gpio 229 1>; /* PCC5, SD1_CD# */
+ cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
};
sdhci@78000400 {
status = "okay";
bus-width = <8>;
- cd-gpios = <&gpio 171 1>; /* PV3, MMC1_CD# */
+ cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
};
sdhci@78000600 {
@@ -262,20 +262,20 @@
usb@7d000000 {
status = "okay";
dr_mode = "peripheral";
- nvidia,vbus-gpio = <&gpio 157 0>; /* PT5, USBO1_EN */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
};
/* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
usb@7d004000 {
status = "okay";
- nvidia,vbus-gpio = <&gpio 233 0>; /* PDD1, USBH_EN */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
phy_type = "utmi";
};
/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
usb@7d008000 {
status = "okay";
- nvidia,vbus-gpio = <&gpio 233 0>; /* PDD1, USBH_EN */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
};
regulators {
diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts
index 5903af6..ae83636 100644
--- a/arch/arm/dts/tegra30-beaver.dts
+++ b/arch/arm/dts/tegra30-beaver.dts
@@ -196,9 +196,9 @@
sdhci@78000000 {
status = "okay";
- cd-gpios = <&gpio 69 1>; /* gpio PI5 */
- wp-gpios = <&gpio 155 0>; /* gpio PT3 */
- power-gpios = <&gpio 31 0>; /* gpio PD7 */
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -210,11 +210,11 @@
usb@7d000000 {
status = "okay";
dr_mode = "otg";
- nvidia,vbus-gpio = <&gpio 238 0>; /* gpio DD6, PEX_L1_CLKREQ */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
};
usb@7d008000 {
- nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
status = "okay";
};
diff --git a/arch/arm/dts/tegra30-cardhu.dts b/arch/arm/dts/tegra30-cardhu.dts
index e13d0fb..23ca141 100644
--- a/arch/arm/dts/tegra30-cardhu.dts
+++ b/arch/arm/dts/tegra30-cardhu.dts
@@ -185,9 +185,9 @@
sdhci@78000000 {
status = "okay";
- cd-gpios = <&gpio 69 1>; /* gpio PI5 */
- wp-gpios = <&gpio 155 0>; /* gpio PT3 */
- power-gpios = <&gpio 31 0>; /* gpio PD7 */
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@@ -197,7 +197,7 @@
};
usb@7d008000 {
- nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
status = "okay";
};
diff --git a/arch/arm/dts/tegra30-colibri.dts b/arch/arm/dts/tegra30-colibri.dts
index 37b6abd..6cd1902 100644
--- a/arch/arm/dts/tegra30-colibri.dts
+++ b/arch/arm/dts/tegra30-colibri.dts
@@ -64,7 +64,7 @@
sdhci@78000200 {
status = "okay";
bus-width = <4>;
- cd-gpios = <&gpio 23 1>; /* PC7, MMCD */
+ cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
};
sdhci@78000600 {
@@ -83,12 +83,12 @@
usb@7d004000 {
status = "okay";
phy_type = "utmi";
- nvidia,vbus-gpio = <&gpio 234 0>; /* PDD2, VBUS_LAN */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
};
/* EHCI instance 2: USB3_DP/N -> USBH_P/N */
usb@7d008000 {
status = "okay";
- nvidia,vbus-gpio = <&gpio 178 1>; /* PW2, USBH_PEN */
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/dts/tegra30-tamonten.dtsi b/arch/arm/dts/tegra30-tamonten.dtsi
index c73afef..8eff627 100644
--- a/arch/arm/dts/tegra30-tamonten.dtsi
+++ b/arch/arm/dts/tegra30-tamonten.dtsi
@@ -55,8 +55,8 @@
/* SD slot on the base board */
sdhci@78000400 {
- cd-gpios = <&gpio 69 1>; /* gpio PI5 */
- wp-gpios = <&gpio 67 0>; /* gpio PI3 */
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
index 6855878..d479be1 100644
--- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
@@ -1,7 +1,7 @@
/*
* Device Tree Source for UniPhier PH1-LD4 Reference Board
*
- * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2014-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -9,6 +9,7 @@
/dts-v1/;
/include/ "uniphier-ph1-ld4.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
/ {
model = "Panasonic UniPhier PH1-LD4 Reference Board";
@@ -46,10 +47,6 @@
&i2c0 {
status = "okay";
- eeprom {
- compatible = "i2c-eeprom";
- reg = <0x50>;
- };
};
&usb0 {
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
index 1227b62..d9e7a8c 100644
--- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
@@ -1,7 +1,7 @@
/*
* Device Tree Source for UniPhier PH1-Pro4 Reference Board
*
- * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2014-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -9,6 +9,7 @@
/dts-v1/;
/include/ "uniphier-ph1-pro4.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
/ {
model = "Panasonic UniPhier PH1-Pro4 Reference Board";
@@ -48,10 +49,6 @@
&i2c0 {
status = "okay";
- eeprom {
- compatible = "i2c-eeprom";
- reg = <0x50>;
- };
};
&usb0 {
diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
index fefc592..8a7f90a 100644
--- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
@@ -1,7 +1,7 @@
/*
* Device Tree Source for UniPhier PH1-sLD3 Reference Board
*
- * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2014-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -9,6 +9,7 @@
/dts-v1/;
/include/ "uniphier-ph1-sld3.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
/ {
model = "Panasonic UniPhier PH1-sLD3 Reference Board";
@@ -45,10 +46,6 @@
&i2c0 {
status = "okay";
- eeprom {
- compatible = "i2c-eeprom";
- reg = <0x50>;
- };
};
&usb0 {
diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
index 9b6d95c..0cb9c47 100644
--- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
@@ -1,7 +1,7 @@
/*
* Device Tree Source for UniPhier PH1-sLD8 Reference Board
*
- * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2014-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -9,6 +9,7 @@
/dts-v1/;
/include/ "uniphier-ph1-sld8.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
/ {
model = "Panasonic UniPhier PH1-sLD8 Reference Board";
@@ -46,10 +47,6 @@
&i2c0 {
status = "okay";
- eeprom {
- compatible = "i2c-eeprom";
- reg = <0x50>;
- };
};
&usb0 {
diff --git a/arch/arm/dts/uniphier-ref-daughter.dtsi b/arch/arm/dts/uniphier-ref-daughter.dtsi
new file mode 100644
index 0000000..0145b51
--- /dev/null
+++ b/arch/arm/dts/uniphier-ref-daughter.dtsi
@@ -0,0 +1,16 @@
+/*
+ * Device Tree Source for UniPhier Reference Daughter Board
+ *
+ * Copyright (C) 2014-2015 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&i2c0 {
+ eeprom {
+ compatible = "i2c-eeprom";
+ reg = <0x50>;
+ u-boot,i2c-offset-len = <2>;
+ };
+};
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index b94b56c..523d22e 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -400,6 +400,8 @@ struct prm_device_inst {
struct cm_dpll {
unsigned int resv1;
unsigned int clktimer2clk; /* offset 0x04 */
+ unsigned int resv2[11];
+ unsigned int clkselmacclk; /* offset 0x34 */
};
#endif /* CONFIG_AM43XX */
diff --git a/arch/arm/include/asm/arch-armada-xp/config.h b/arch/arm/include/asm/arch-armada-xp/config.h
index 00ee775..f9fd424 100644
--- a/arch/arm/include/asm/arch-armada-xp/config.h
+++ b/arch/arm/include/asm/arch-armada-xp/config.h
@@ -31,7 +31,11 @@
#endif /* CONFIG_SYS_KWD_CONFIG */
/* Add target to build it automatically upon "make" */
+#ifdef CONFIG_SPL
+#define CONFIG_BUILD_TARGET "u-boot-spl.kwb"
+#else
#define CONFIG_BUILD_TARGET "u-boot.kwb"
+#endif
/* end of 16M scrubbed by training in bootrom */
#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000
diff --git a/arch/arm/include/asm/arch-armada-xp/cpu.h b/arch/arm/include/asm/arch-armada-xp/cpu.h
index 6b60c21..4f5ff96 100644
--- a/arch/arm/include/asm/arch-armada-xp/cpu.h
+++ b/arch/arm/include/asm/arch-armada-xp/cpu.h
@@ -96,6 +96,9 @@ struct kwgpio_registers {
u32 irq_level;
};
+/* Needed for dynamic (board-specific) mbus configuration */
+extern struct mvebu_mbus_state mbus_state;
+
/*
* functions
*/
@@ -103,5 +106,18 @@ unsigned int mvebu_sdram_bar(enum memory_bank bank);
unsigned int mvebu_sdram_bs(enum memory_bank bank);
void mvebu_sdram_size_adjust(enum memory_bank bank);
int mvebu_mbus_probe(struct mbus_win windows[], int count);
+
+/*
+ * Highspeed SERDES PHY config init, ported from bin_hdr
+ * to mainline U-Boot
+ */
+int serdes_phy_config(void);
+
+/*
+ * DDR3 init / training code ported from Marvell bin_hdr. Now
+ * available in mainline U-Boot in:
+ * drivers/ddr/mvebu/
+ */
+int ddr3_init(void);
#endif /* __ASSEMBLY__ */
#endif /* _ARMADA_XP_CPU_H */
diff --git a/arch/arm/include/asm/arch-at91/at91cap9.h b/arch/arm/include/asm/arch-at91/at91cap9.h
deleted file mode 100644
index 63870bc..0000000
--- a/arch/arm/include/asm/arch-at91/at91cap9.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9.h]
- *
- * Copyright (C) 2007 Stelian Pop <stelian@popies.net>
- * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Common definitions.
- * Based on AT91CAP9 datasheet revision B (Preliminary).
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91CAP9_H
-#define AT91CAP9_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Peripherals */
-#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
-#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
-#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
-#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
-#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
-#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
-#define AT91CAP9_ID_US0 8 /* USART 0 */
-#define AT91CAP9_ID_US1 9 /* USART 1 */
-#define AT91CAP9_ID_US2 10 /* USART 2 */
-#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
-#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
-#define AT91CAP9_ID_CAN 13 /* CAN */
-#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
-#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
-#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
-#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
-#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
-#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
-#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
-#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
-#define AT91CAP9_ID_EMAC 22 /* Ethernet */
-#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
-#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */
-#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
-#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
-#define AT91CAP9_ID_DMA 27 /* DMA Controller */
-#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
-#define AT91CAP9_ID_UHP 29 /* USB Host Port */
-#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
-#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
-
-#define AT91_PIO_BASE 0xfffff200
-#define AT91_PMC_BASE 0xfffffc00
-#define AT91_RSTC_BASE 0xfffffd00
-#define AT91_PIT_BASE 0xfffffd30
-
-/*
- * Internal Memory.
- */
-#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
-#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
-
-#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
-#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
-
-#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
-#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */
-#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
-
-#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
-
-/*
- * Cpu Name
- */
-#define CONFIG_SYS_AT91_CPU_NAME "AT91CAP9"
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91cap9_matrix.h b/arch/arm/include/asm/arch-at91/at91cap9_matrix.h
deleted file mode 100644
index 009a19d..0000000
--- a/arch/arm/include/asm/arch-at91/at91cap9_matrix.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9_matrix.h]
- *
- * Copyright (C) 2007 Stelian Pop <stelian@popies.net>
- * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- * Copyright (C) 2006 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91CAP9 datasheet revision B (Preliminary).
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91CAP9_MATRIX_H
-#define AT91CAP9_MATRIX_H
-
-#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
-#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
-
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
-#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
-#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */
-#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
-#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
-#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
-#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-
-#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
-#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
-#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
-#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */
-#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */
-#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
-#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
-#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
-#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
-#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
-#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
-#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
-#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
-#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
-#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
-#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
-#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
-
-#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
-#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_RCB2 (1 << 2)
-#define AT91_MATRIX_RCB3 (1 << 3)
-#define AT91_MATRIX_RCB4 (1 << 4)
-#define AT91_MATRIX_RCB5 (1 << 5)
-#define AT91_MATRIX_RCB6 (1 << 6)
-#define AT91_MATRIX_RCB7 (1 << 7)
-#define AT91_MATRIX_RCB8 (1 << 8)
-#define AT91_MATRIX_RCB9 (1 << 9)
-#define AT91_MATRIX_RCB10 (1 << 10)
-#define AT91_MATRIX_RCB11 (1 << 11)
-
-#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
-#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
-
-#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
-#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
-#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
-#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
-#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
-#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
-#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
-#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
-#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */
-#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
-#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
-
-#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */
-#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */
-#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */
-
-#endif
diff --git a/arch/arm/include/asm/arch-bcm2835/gpio.h b/arch/arm/include/asm/arch-bcm2835/gpio.h
index db42896..c8ef8f5 100644
--- a/arch/arm/include/asm/arch-bcm2835/gpio.h
+++ b/arch/arm/include/asm/arch-bcm2835/gpio.h
@@ -1,6 +1,7 @@
/*
* Copyright (C) 2012 Vikram Narayananan
* <vikram186@gmail.com>
+ * (C) Copyright 2012,2015 Stephen Warren
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -8,7 +9,11 @@
#ifndef _BCM2835_GPIO_H_
#define _BCM2835_GPIO_H_
+#ifdef CONFIG_BCM2836
+#define BCM2835_GPIO_BASE 0x3f200000
+#else
#define BCM2835_GPIO_BASE 0x20200000
+#endif
#define BCM2835_GPIO_COUNT 54
#define BCM2835_GPIO_FSEL_MASK 0x7
diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h
index 88d2ec1..04bf480 100644
--- a/arch/arm/include/asm/arch-bcm2835/mbox.h
+++ b/arch/arm/include/asm/arch-bcm2835/mbox.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2012 Stephen Warren
+ * (C) Copyright 2012,2015 Stephen Warren
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -38,7 +38,11 @@
/* Raw mailbox HW */
+#ifdef CONFIG_BCM2836
+#define BCM2835_MBOX_PHYSADDR 0x3f00b880
+#else
#define BCM2835_MBOX_PHYSADDR 0x2000b880
+#endif
struct bcm2835_mbox_regs {
u32 read;
@@ -121,6 +125,9 @@ struct bcm2835_mbox_tag_hdr {
#define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002
+#ifdef CONFIG_BCM2836
+#define BCM2836_BOARD_REV_2_B 0x4
+#else
/*
* 0x2..0xf from:
* http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/
@@ -141,6 +148,7 @@ struct bcm2835_mbox_tag_hdr {
#define BCM2835_BOARD_REV_B_PLUS 0x10
#define BCM2835_BOARD_REV_CM 0x11
#define BCM2835_BOARD_REV_A_PLUS 0x12
+#endif
struct bcm2835_mbox_tag_get_board_rev {
struct bcm2835_mbox_tag_hdr tag_hdr;
diff --git a/arch/arm/include/asm/arch-bcm2835/sdhci.h b/arch/arm/include/asm/arch-bcm2835/sdhci.h
index a4f867b..2a21ccb 100644
--- a/arch/arm/include/asm/arch-bcm2835/sdhci.h
+++ b/arch/arm/include/asm/arch-bcm2835/sdhci.h
@@ -1,23 +1,17 @@
/*
- * (C) Copyright 2012 Stephen Warren
+ * (C) Copyright 2012,2015 Stephen Warren
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _BCM2835_SDHCI_H_
#define _BCM2835_SDHCI_H_
+#ifdef CONFIG_BCM2836
+#define BCM2835_SDHCI_BASE 0x3f300000
+#else
#define BCM2835_SDHCI_BASE 0x20300000
+#endif
int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq);
diff --git a/arch/arm/include/asm/arch-bcm2835/timer.h b/arch/arm/include/asm/arch-bcm2835/timer.h
index c2001b6..fc7aec7 100644
--- a/arch/arm/include/asm/arch-bcm2835/timer.h
+++ b/arch/arm/include/asm/arch-bcm2835/timer.h
@@ -1,23 +1,17 @@
/*
- * (C) Copyright 2012 Stephen Warren
+ * (C) Copyright 2012,2015 Stephen Warren
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _BCM2835_TIMER_H
#define _BCM2835_TIMER_H
+#ifdef CONFIG_BCM2836
+#define BCM2835_TIMER_PHYSADDR 0x3f003000
+#else
#define BCM2835_TIMER_PHYSADDR 0x20003000
+#endif
struct bcm2835_timer_regs {
u32 cs;
diff --git a/arch/arm/include/asm/arch-bcm2835/wdog.h b/arch/arm/include/asm/arch-bcm2835/wdog.h
index 303a65f..beb6a08 100644
--- a/arch/arm/include/asm/arch-bcm2835/wdog.h
+++ b/arch/arm/include/asm/arch-bcm2835/wdog.h
@@ -1,23 +1,17 @@
/*
- * (C) Copyright 2012 Stephen Warren
+ * (C) Copyright 2012,2015 Stephen Warren
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _BCM2835_TIMER_H
#define _BCM2835_TIMER_H
+#ifdef CONFIG_BCM2836
+#define BCM2835_WDOG_PHYSADDR 0x3f100000
+#else
#define BCM2835_WDOG_PHYSADDR 0x20100000
+#endif
struct bcm2835_wdog_regs {
u32 unknown0[7];
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index db24dc0..2a17dfc 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -26,6 +26,10 @@ enum pll_src_bit {
EXYNOS_SRC_MPLL = 6,
EXYNOS_SRC_EPLL,
EXYNOS_SRC_VPLL,
+ EXYNOS542X_SRC_MPLL = 3,
+ EXYNOS542X_SRC_SPLL,
+ EXYNOS542X_SRC_EPLL = 6,
+ EXYNOS542X_SRC_RPLL,
};
unsigned long get_pll_clk(int pllreg);
diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h b/arch/arm/include/asm/arch-exynos/pinmux.h
index 0b91ef6..d0ae757 100644
--- a/arch/arm/include/asm/arch-exynos/pinmux.h
+++ b/arch/arm/include/asm/arch-exynos/pinmux.h
@@ -23,6 +23,9 @@ enum {
/* Flags for SROM controller */
PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */
PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
+
+ /* Flags for I2C */
+ PINMUX_FLAG_HS_MODE = 1 << 1, /* I2C High Speed Mode */
};
/**
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index 8f6426b..564441c 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -1,7 +1,7 @@
/*
* Common definitions for LPC32XX board configurations
*
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -9,6 +9,8 @@
#ifndef _LPC32XX_CONFIG_H
#define _LPC32XX_CONFIG_H
+#define CONFIG_SYS_GENERIC_BOARD
+
/* Basic CPU architecture */
#define CONFIG_ARCH_CPU_INIT
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index c968600..ae88b6e 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -88,8 +88,8 @@
#define AIPS2_ARB_BASE_ADDR 0x02100000
#define AIPS2_ARB_END_ADDR 0x021FFFFF
#ifdef CONFIG_MX6SX
-#define AIPS3_BASE_ADDR 0x02200000
-#define AIPS3_END_ADDR 0x022FFFFF
+#define AIPS3_ARB_BASE_ADDR 0x02200000
+#define AIPS3_ARB_END_ADDR 0x022FFFFF
#define WEIM_ARB_BASE_ADDR 0x50000000
#define WEIM_ARB_END_ADDR 0x57FFFFFF
#define QSPI0_AMBA_BASE 0x60000000
@@ -624,12 +624,16 @@ struct fuse_bank0_regs {
u32 rsvd1[3];
u32 uid_high;
u32 rsvd2[3];
- u32 rsvd3[4];
- u32 rsvd4[4];
- u32 rsvd5[4];
+ u32 cfg2;
+ u32 rsvd3[3];
+ u32 cfg3;
+ u32 rsvd4[3];
+ u32 cfg4;
+ u32 rsvd5[3];
u32 cfg5;
u32 rsvd6[3];
- u32 rsvd7[4];
+ u32 cfg6;
+ u32 rsvd7[3];
};
#ifdef CONFIG_MX6SX
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 5ebabfa..8e0d7d1 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -62,6 +62,49 @@ struct mmdc_p_regs {
u32 mpmur0;
};
+#define MX6SX_IOM_DDR_BASE 0x020e0200
+struct mx6sx_iomux_ddr_regs {
+ u32 res1[59];
+ u32 dram_dqm0;
+ u32 dram_dqm1;
+ u32 dram_dqm2;
+ u32 dram_dqm3;
+ u32 dram_ras;
+ u32 dram_cas;
+ u32 res2[2];
+ u32 dram_sdwe_b;
+ u32 dram_odt0;
+ u32 dram_odt1;
+ u32 dram_sdba0;
+ u32 dram_sdba1;
+ u32 dram_sdba2;
+ u32 dram_sdcke0;
+ u32 dram_sdcke1;
+ u32 dram_sdclk_0;
+ u32 dram_sdqs0;
+ u32 dram_sdqs1;
+ u32 dram_sdqs2;
+ u32 dram_sdqs3;
+ u32 dram_reset;
+};
+
+#define MX6SX_IOM_GRP_BASE 0x020e0500
+struct mx6sx_iomux_grp_regs {
+ u32 res1[61];
+ u32 grp_addds;
+ u32 grp_ddrmode_ctl;
+ u32 grp_ddrpke;
+ u32 grp_ddrpk;
+ u32 grp_ddrhys;
+ u32 grp_ddrmode;
+ u32 grp_b0ds;
+ u32 grp_b1ds;
+ u32 grp_ctlds;
+ u32 grp_ddr_type;
+ u32 grp_b2ds;
+ u32 grp_b3ds;
+};
+
/*
* MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
*/
@@ -243,6 +286,9 @@ void mx6dq_dram_iocfg(unsigned width,
void mx6sdl_dram_iocfg(unsigned width,
const struct mx6sdl_iomux_ddr_regs *,
const struct mx6sdl_iomux_grp_regs *);
+void mx6sx_dram_iocfg(unsigned width,
+ const struct mx6sx_iomux_ddr_regs *,
+ const struct mx6sx_iomux_grp_regs *);
/* configure mx6 mmdc registers */
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h
index 062f3de..4678723 100644
--- a/arch/arm/include/asm/arch-mxs/sys_proto.h
+++ b/arch/arm/include/asm/arch-mxs/sys_proto.h
@@ -74,6 +74,23 @@ static const struct mxs_pair mxs_boot_modes[] = {
#endif
};
+#define MXS_BM_USB 0x00
+#define MXS_BM_I2C_MASTER_3V3 0x01
+#define MXS_BM_I2C_MASTER_1V8 0x11
+#define MXS_BM_SPI2_MASTER_3V3_NOR 0x02
+#define MXS_BM_SPI2_MASTER_1V8_NOR 0x12
+#define MXS_BM_SPI3_MASTER_3V3_NOR 0x03
+#define MXS_BM_SPI3_MASTER_1V8_NOR 0x13
+#define MXS_BM_NAND_3V3 0x04
+#define MXS_BM_NAND_1V8 0x14
+#define MXS_BM_JTAG 0x06
+#define MXS_BM_SPI3_MASTER_3V3_EEPROM 0x08
+#define MXS_BM_SPI3_MASTER_1V8_EEPROM 0x18
+#define MXS_BM_SDMMC0_3V3 0x09
+#define MXS_BM_SDMMC0_1V8 0x19
+#define MXS_BM_SDMMC1_3V3 0x0a
+#define MXS_BM_SDMMC1_1V8 0x1a
+
struct mxs_spl_data {
uint8_t boot_mode_idx;
uint32_t mem_dram_size;
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index 0b78c1c..3ce270c 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -249,6 +249,49 @@ enum {
#define MICRON_RASWIDTH_200 14
#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200)
+/* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */
+#define SAMSUNG_TDAL_165 5
+#define SAMSUNG_TDPL_165 2
+#define SAMSUNG_TRRD_165 2
+#define SAMSUNG_TRCD_165 3
+#define SAMSUNG_TRP_165 3
+#define SAMSUNG_TRAS_165 7
+#define SAMSUNG_TRC_165 10
+#define SAMSUNG_TRFC_165 12
+
+#define SAMSUNG_V_ACTIMA_165 \
+ ACTIM_CTRLA(SAMSUNG_TRFC_165, SAMSUNG_TRC_165, \
+ SAMSUNG_TRAS_165, SAMSUNG_TRP_165, \
+ SAMSUNG_TRCD_165, SAMSUNG_TRRD_165, \
+ SAMSUNG_TDPL_165, SAMSUNG_TDAL_165)
+
+#define SAMSUNG_TWTR_165 1
+#define SAMSUNG_TCKE_165 2
+#define SAMSUNG_XSR_165 20
+#define SAMSUNG_TXP_165 5
+
+#define SAMSUNG_V_ACTIMB_165 \
+ ACTIM_CTRLB(SAMSUNG_TWTR_165, SAMSUNG_TCKE_165, \
+ SAMSUNG_TXP_165, SAMSUNG_XSR_165)
+
+#define SAMSUNG_RASWIDTH_165 14
+#define SAMSUNG_V_MCFG_165(size) \
+ V_MCFG_RASWIDTH(SAMSUNG_RASWIDTH_165) | V_MCFG_CASWIDTH_10B | \
+ V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(size) | \
+ V_MCFG_BANKALLOCATION_RBC | V_MCFG_RAMTYPE_DDR
+
+/* TODO: find which register these were taken from */
+
+#define SAMSUNG_BL_165 0x2
+#define SAMSUNG_SIL_165 0x0
+#define SAMSUNG_CASL_165 0x3
+#define SAMSUNG_WBST_165 0x0
+#define SAMSUNG_V_MR_165 ((SAMSUNG_WBST_165 << 9) | \
+ (SAMSUNG_CASL_165 << 4) | (SAMSUNG_SIL_165 << 3) | \
+ (SAMSUNG_BL_165))
+
+#define SAMSUNG_SHARING 0x00003700
+
/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
/* 15/6 + 18/6 = 5.5 -> 6 */
diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
index 0ba621a..9f2896c 100644
--- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
@@ -51,6 +51,7 @@ typedef struct t2 {
#define PBIASLITEPWRDNZ0 (1 << 1)
#define PBIASSPEEDCTRL0 (1 << 2)
#define PBIASLITEPWRDNZ1 (1 << 9)
+#define PBIASLITEVMODE0 (1 << 0)
#define CTLPROGIO1SPEEDCTRL (1 << 20)
diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h
index eba4a5c..3277b40 100644
--- a/arch/arm/include/asm/arch-omap3/mux.h
+++ b/arch/arm/include/asm/arch-omap3/mux.h
@@ -15,6 +15,12 @@
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
+ * SB_LOW - Standby mode configuration: Output low-level
+ * SB_HI - Standby mode configuration: Output high-level
+ * SB_HIZ - Standby mode configuration: Output hi-impedence
+ * SB_PD - Standby mode pull-down enabled
+ * SB_PU - Standby mode pull-up enabled
+ * WKEN - Wakeup input enabled
* M0 - Mode 0
*/
@@ -26,6 +32,13 @@
#define EN (1 << 3)
#define DIS (0 << 3)
+#define SB_LOW (1 << 9)
+#define SB_HI (5 << 9)
+#define SB_HIZ (2 << 9)
+#define SB_PD (1 << 12)
+#define SB_PU (3 << 12)
+#define WKEN (1 << 14)
+
#define M0 0
#define M1 1
#define M2 2
@@ -36,8 +49,8 @@
#define M7 7
/*
- * To get the actual address the offset has to added
- * with OMAP34XX_CTRL_BASE to get the actual address
+ * To get the actual address the offset has to be added
+ * to OMAP34XX_CTRL_BASE
*/
/*SDRC*/
@@ -78,6 +91,33 @@
#define CONTROL_PADCONF_SDRC_DQS1 0x0074
#define CONTROL_PADCONF_SDRC_DQS2 0x0076
#define CONTROL_PADCONF_SDRC_DQS3 0x0078
+#define CONTROL_PADCONF_SDRC_BA0 0x05A0
+#define CONTROL_PADCONF_SDRC_BA1 0x05A2
+#define CONTROL_PADCONF_SDRC_A0 0x05A4
+#define CONTROL_PADCONF_SDRC_A1 0x05A6
+#define CONTROL_PADCONF_SDRC_A2 0x05A8
+#define CONTROL_PADCONF_SDRC_A3 0x05AA
+#define CONTROL_PADCONF_SDRC_A4 0x05AC
+#define CONTROL_PADCONF_SDRC_A5 0x05AE
+#define CONTROL_PADCONF_SDRC_A6 0x05B0
+#define CONTROL_PADCONF_SDRC_A7 0x05B2
+#define CONTROL_PADCONF_SDRC_A8 0x05B4
+#define CONTROL_PADCONF_SDRC_A9 0x05B6
+#define CONTROL_PADCONF_SDRC_A10 0x05B8
+#define CONTROL_PADCONF_SDRC_A11 0x05BA
+#define CONTROL_PADCONF_SDRC_A12 0x05BC
+#define CONTROL_PADCONF_SDRC_A13 0x05BE
+#define CONTROL_PADCONF_SDRC_A14 0x05C0
+#define CONTROL_PADCONF_SDRC_NCS0 0x05C2
+#define CONTROL_PADCONF_SDRC_NCS1 0x05C4
+#define CONTROL_PADCONF_SDRC_NCLK 0x05C6
+#define CONTROL_PADCONF_SDRC_NRAS 0x05C8
+#define CONTROL_PADCONF_SDRC_NCAS 0x05CA
+#define CONTROL_PADCONF_SDRC_NWE 0x05CC
+#define CONTROL_PADCONF_SDRC_DM0 0x05CE
+#define CONTROL_PADCONF_SDRC_DM1 0x05D0
+#define CONTROL_PADCONF_SDRC_DM2 0x05D2
+#define CONTROL_PADCONF_SDRC_DM3 0x05D4
/*GPMC*/
#define CONTROL_PADCONF_GPMC_A1 0x007A
#define CONTROL_PADCONF_GPMC_A2 0x007C
@@ -89,6 +129,7 @@
#define CONTROL_PADCONF_GPMC_A8 0x0088
#define CONTROL_PADCONF_GPMC_A9 0x008A
#define CONTROL_PADCONF_GPMC_A10 0x008C
+#define CONTROL_PADCONF_GPMC_A11 0x0264
#define CONTROL_PADCONF_GPMC_D0 0x008E
#define CONTROL_PADCONF_GPMC_D1 0x0090
#define CONTROL_PADCONF_GPMC_D2 0x0092
@@ -323,6 +364,8 @@
#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6
#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8
#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA
+#define CONTROL_PADCONF_JTAG_RTCK 0x0A4E
+#define CONTROL_PADCONF_JTAG_TDO 0x0A50
/*Die to Die */
#define CONTROL_PADCONF_D2D_MCAD0 0x01E4
#define CONTROL_PADCONF_D2D_MCAD1 0x01E6
@@ -433,6 +476,10 @@
#define CONTROL_PADCONF_SYS_BOOT8 0x0226
/* AM/DM37xx specific */
+#define CONTROL_PADCONF_GPIO112 0x0134
+#define CONTROL_PADCONF_GPIO113 0x0136
+#define CONTROL_PADCONF_GPIO114 0x0138
+#define CONTROL_PADCONF_GPIO115 0x013A
#define CONTROL_PADCONF_GPIO127 0x0A54
#define CONTROL_PADCONF_GPIO126 0x0A56
#define CONTROL_PADCONF_GPIO128 0x0A58
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 34bd8c5..bcf92fb 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -23,6 +23,7 @@ struct emu_hal_params {
/* Board SDRC timing values */
struct board_sdrc_timings {
+ u32 sharing;
u32 mcfg;
u32 ctrla;
u32 ctrlb;
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 0dc584b..f8e5630 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -236,13 +236,20 @@
#define VDD_MPU_ES2_LOW 880
#define VDD_MM_ES2_LOW 880
-/* TPS659038 Voltage settings in mv for OPP_NOMINAL */
-#define VDD_MPU_DRA752 1090
+/* DRA74x/75x voltage settings in mv for OPP_NOM per DM */
+#define VDD_MPU_DRA752 1100
#define VDD_EVE_DRA752 1060
#define VDD_GPU_DRA752 1060
-#define VDD_CORE_DRA752 1030
+#define VDD_CORE_DRA752 1060
#define VDD_IVA_DRA752 1060
+/* DRA72x voltage settings in mv for OPP_NOM per DM */
+#define VDD_MPU_DRA72x 1100
+#define VDD_EVE_DRA72x 1060
+#define VDD_GPU_DRA72x 1060
+#define VDD_CORE_DRA72x 1060
+#define VDD_IVA_DRA72x 1060
+
/* Efuse register offsets for DRA7xx platform */
#define DRA752_EFUSE_BASE 0x4A002000
#define DRA752_EFUSE_REGBITS 16
@@ -284,6 +291,13 @@
#define TPS659038_REG_ADDR_SMPS7 0x33
#define TPS659038_REG_ADDR_SMPS8 0x37
+/* TPS65917 */
+#define TPS65917_I2C_SLAVE_ADDR 0x58
+#define TPS65917_REG_ADDR_SMPS1 0x23
+#define TPS65917_REG_ADDR_SMPS2 0x27
+#define TPS65917_REG_ADDR_SMPS3 0x2F
+
+
/* TPS */
#define TPS62361_I2C_SLAVE_ADDR 0x60
#define TPS62361_REG_ADDR_SET0 0x0
diff --git a/arch/arm/include/asm/arch-pantheon/gpio.h b/arch/arm/include/asm/arch-pantheon/gpio.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/arm/include/asm/arch-pantheon/gpio.h
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 05fbad3..c28ee05 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -144,7 +144,16 @@ struct sunxi_ccm_reg {
#define PLL1_CFG_DEFAULT 0xa1005000
+#if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I
+/*
+ * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
+ * halving the mbus frequency, so set it to 300 MHz ourselves and base the
+ * mbus divider on that.
+ */
+#define PLL6_CFG_DEFAULT 0xa1009900
+#else
#define PLL6_CFG_DEFAULT 0xa1009911
+#endif
/* nand clock */
#define NAND_CLK_SRC_OSC24 0
@@ -305,6 +314,8 @@ struct sunxi_ccm_reg {
#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
+#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5)
+#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10)
#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index e101c54..8a80385 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -243,6 +243,8 @@ struct sunxi_ccm_reg {
#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
+#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5)
+#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10)
#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index a2a7839..04889c5 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -73,7 +73,6 @@
#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000)
#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400)
#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800)
-#define SUNXI_R_PIO_BASE (0x08002C00)
#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00)
#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400)
#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800)
@@ -92,8 +91,10 @@
#define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800)
/* RCPUS Module */
-#define SUNXI_RPRCM_BASE (REGS_RCPUS_BASE + 0x1400)
+#define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400)
#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800)
+#define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00)
+#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400)
/* Misc. */
#define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
index 7ff43e6..aedd194 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -25,31 +25,7 @@
#endif
unsigned long sunxi_dram_init(void);
-
-/*
- * Wait up to 1s for value to be set in given part of reg.
- */
-static inline void mctl_await_completion(u32 *reg, u32 mask, u32 val)
-{
- unsigned long tmo = timer_get_us() + 1000000;
-
- while ((readl(reg) & mask) != val) {
- if (timer_get_us() > tmo)
- panic("Timeout initialising DRAM\n");
- }
-}
-
-/*
- * Test if memory at offset offset matches memory at begin of DRAM
- */
-static inline bool mctl_mem_matches(u32 offset)
-{
- /* Try to write different values to RAM at two addresses */
- writel(0, CONFIG_SYS_SDRAM_BASE);
- writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset);
- /* Check if the same value is actually observed when reading back */
- return readl(CONFIG_SYS_SDRAM_BASE) ==
- readl(CONFIG_SYS_SDRAM_BASE + offset);
-}
+void mctl_await_completion(u32 *reg, u32 mask, u32 val);
+bool mctl_mem_matches(u32 offset);
#endif /* _SUNXI_DRAM_H */
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 71cc879..f2c247d 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -45,9 +45,13 @@
*
* sun8i has 1 bank:
* PL0 - PL11
+ *
+ * sun9i has 3 banks:
+ * PL0 - PL9 | PM0 - PM15 | PN0 - PN1
*/
#define SUNXI_GPIO_L 11
#define SUNXI_GPIO_M 12
+#define SUNXI_GPIO_N 13
struct sunxi_gpio {
u32 cfg[4];
@@ -114,6 +118,7 @@ enum sunxi_gpio_number {
SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
SUNXI_GPIO_L_START = 352,
SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
+ SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
SUNXI_GPIO_AXP0_START = 1024,
};
@@ -129,6 +134,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
+#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr))
#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr))
@@ -187,6 +193,9 @@ enum sunxi_gpio_number {
#define SUN8I_GPL2_R_UART_TX 2
#define SUN8I_GPL3_R_UART_RX 2
+#define SUN9I_GPN0_R_RSB_SCK 3
+#define SUN9I_GPN1_R_RSB_SDA 3
+
/* GPIO pin pull-up/down config */
#define SUNXI_GPIO_PULL_DISABLE 0
#define SUNXI_GPIO_PULL_UP 1
diff --git a/arch/arm/include/asm/arch-sunxi/rsb.h b/arch/arm/include/asm/arch-sunxi/rsb.h
index 95a595a..a893466 100644
--- a/arch/arm/include/asm/arch-sunxi/rsb.h
+++ b/arch/arm/include/asm/arch-sunxi/rsb.h
@@ -37,6 +37,7 @@ struct sunxi_rsb_reg {
#define RSB_STAT_TERR_INT (1 << 1)
#define RSB_STAT_LBSY_INT (1 << 2)
+#define RSB_DMCR_DEVICE_MODE_DATA 0x7c3e00
#define RSB_DMCR_DEVICE_MODE_START (1 << 31)
#define RSB_CMD_BYTE_WRITE 0x4e
@@ -46,8 +47,7 @@ struct sunxi_rsb_reg {
#define RSB_DEVADDR_RUNTIME_ADDR(x) ((x) << 16)
#define RSB_DEVADDR_DEVICE_ADDR(x) ((x) << 0)
-void rsb_init(void);
-int rsb_set_device_mode(u32 device_mode_data);
+int rsb_init(void);
int rsb_set_device_address(u16 device_addr, u16 runtime_addr);
int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data);
int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data);
diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h
index c3e636e..60a5bd8 100644
--- a/arch/arm/include/asm/arch-sunxi/sys_proto.h
+++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h
@@ -13,4 +13,14 @@
void sdelay(unsigned long);
+/* return_to_fel() - Return to BROM from SPL
+ *
+ * This returns back into the BROM after U-Boot SPL has performed its initial
+ * init. It uses the provided lr and sp to do so.
+ *
+ * @lr: BROM link register value (return address)
+ * @sp: BROM stack pointer
+ */
+void return_to_fel(uint32_t lr, uint32_t sp);
+
#endif
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index 84e7b55..a20bdaa 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -10,6 +10,7 @@
#define __TEGRA_MMC_H_
#include <fdtdec.h>
+#include <asm/gpio.h>
/* for mmc_config definition */
#include <mmc.h>
@@ -134,9 +135,9 @@ struct mmc_host {
int enabled; /* 1 to enable, 0 to disable */
int width; /* Bus Width, 1, 4 or 8 */
enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
- struct fdt_gpio_state cd_gpio; /* Change Detect GPIO */
- struct fdt_gpio_state pwr_gpio; /* Power GPIO */
- struct fdt_gpio_state wp_gpio; /* Write Protect GPIO */
+ struct gpio_desc cd_gpio; /* Change Detect GPIO */
+ struct gpio_desc pwr_gpio; /* Power GPIO */
+ struct gpio_desc wp_gpio; /* Write Protect GPIO */
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
struct mmc_config cfg; /* mmc configuration */
diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra20/display.h
index a04c84e..6feeda3 100644
--- a/arch/arm/include/asm/arch-tegra20/display.h
+++ b/arch/arm/include/asm/arch-tegra20/display.h
@@ -10,6 +10,7 @@
#include <asm/arch/dc.h>
#include <fdtdec.h>
+#include <asm/gpio.h>
/* This holds information about a window which can be displayed */
struct disp_ctl_win {
@@ -72,10 +73,10 @@ struct fdt_panel_config {
int pwm_channel; /* PWM channel to use for backlight */
enum lcd_cache_t cache_type;
- struct fdt_gpio_state backlight_en; /* GPIO for backlight enable */
- struct fdt_gpio_state lvds_shutdown; /* GPIO for lvds shutdown */
- struct fdt_gpio_state backlight_vdd; /* GPIO for backlight vdd */
- struct fdt_gpio_state panel_vdd; /* GPIO for panel vdd */
+ struct gpio_desc backlight_en; /* GPIO for backlight enable */
+ struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */
+ struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */
+ struct gpio_desc panel_vdd; /* GPIO for panel vdd */
/*
* Panel required timings
* Timing 1: delay between panel_vdd-rise and data-rise
diff --git a/arch/arm/include/asm/arch-uniphier/boot-device.h b/arch/arm/include/asm/arch-uniphier/boot-device.h
index 6987f57..7a10f1c 100644
--- a/arch/arm/include/asm/arch-uniphier/boot-device.h
+++ b/arch/arm/include/asm/arch-uniphier/boot-device.h
@@ -8,7 +8,7 @@
#ifndef _ASM_BOOT_DEVICE_H_
#define _ASM_BOOT_DEVICE_H_
-u32 get_boot_mode_sel(void);
+int get_boot_mode_sel(void);
struct boot_device_info {
u32 type;
diff --git a/arch/arm/include/asm/arch-uniphier/gpio.h b/arch/arm/include/asm/arch-uniphier/gpio.h
deleted file mode 100644
index 1fc4e19..0000000
--- a/arch/arm/include/asm/arch-uniphier/gpio.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/*
- * Dummy header file to enable CONFIG_OF_CONTROL.
- * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
- * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
- * OF_CONTROL must have arch/gpio.h even if GPIO is not supported.
- */
diff --git a/arch/arm/include/asm/arch-zynq/gpio.h b/arch/arm/include/asm/arch-zynq/gpio.h
index 2dbba75..a26ae87 100644
--- a/arch/arm/include/asm/arch-zynq/gpio.h
+++ b/arch/arm/include/asm/arch-zynq/gpio.h
@@ -7,19 +7,4 @@
#ifndef _ZYNQ_GPIO_H
#define _ZYNQ_GPIO_H
-inline int gpio_get_value(unsigned gpio)
-{
- return 0;
-}
-
-inline int gpio_set_value(unsigned gpio, int val)
-{
- return 0;
-}
-
-inline int gpio_request(unsigned gpio, const char *label)
-{
- return 0;
-}
-
#endif /* _ZYNQ_GPIO_H */
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 342f045..7a545ea 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -1149,6 +1149,7 @@ struct emif_regs {
u32 sdram_config;
u32 sdram_config2;
u32 ref_ctrl;
+ u32 ref_ctrl_final;
u32 sdram_tim1;
u32 sdram_tim2;
u32 sdram_tim3;
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index 8acd7cd..17b6f54 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -26,10 +26,14 @@ enum {
BOOT_DEVICE_SPI,
BOOT_DEVICE_SATA,
BOOT_DEVICE_I2C,
+ BOOT_DEVICE_BOARD,
BOOT_DEVICE_NONE
};
#endif
+/* Board-specific load method */
+void spl_board_load_image(void);
+
/* Linker symbols. */
extern char __bss_start[], __bss_end[];
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 89f2294..7820486 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -142,6 +142,21 @@ void flush_l3_cache(void);
#ifndef __ASSEMBLY__
+/**
+ * save_boot_params() - Save boot parameters before starting reset sequence
+ *
+ * If you provide this function it will be called immediately U-Boot starts,
+ * both for SPL and U-Boot proper.
+ *
+ * All registers are unchanged from U-Boot entry. No registers need be
+ * preserved.
+ *
+ * This is not a normal C function. There is no stack. Return by branching to
+ * save_boot_params_ret.
+ *
+ * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
+ */
+
#define isb() __asm__ __volatile__ ("" : : : "memory")
#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h
index f97f3dd..414042d 100644
--- a/arch/arm/include/asm/u-boot-arm.h
+++ b/arch/arm/include/asm/u-boot-arm.h
@@ -36,7 +36,6 @@ int arch_early_init_r(void);
/* board/.../... */
int board_init(void);
-int dram_init (void);
void dram_init_banksize (void);
/* cpu/.../interrupt.c */
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index d74e4b8..da8ed72 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -35,6 +35,7 @@ endif
obj-$(CONFIG_SEMIHOSTING) += semihosting.o
obj-y += sections.o
+obj-y += stack.o
ifdef CONFIG_ARM64
obj-y += gic_64.o
obj-y += interrupts_64.o
diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c
new file mode 100644
index 0000000..cf10a53
--- /dev/null
+++ b/arch/arm/lib/stack.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2015 Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_reserve_stacks(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */
+ gd->irq_sp = gd->start_addr_sp;
+#else
+ /* setup stack pointer for exceptions */
+ gd->irq_sp = gd->start_addr_sp;
+
+# if !defined(CONFIG_ARM64)
+# ifdef CONFIG_USE_IRQ
+ gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
+ debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
+ CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->start_addr_sp);
+
+ /* 8-byte alignment for ARM ABI compliance */
+ gd->start_addr_sp &= ~0x07;
+# endif
+ /* leave 3 words for abort-stack, plus 1 for alignment */
+ gd->start_addr_sp -= 16;
+# endif
+#endif
+
+ return 0;
+}
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
new file mode 100644
index 0000000..30945c1
--- /dev/null
+++ b/arch/arm/mach-at91/Kconfig
@@ -0,0 +1,168 @@
+if ARCH_AT91
+
+choice
+ prompt "Atmel AT91 board select"
+
+config TARGET_AT91RM9200EK
+ bool "Atmel AT91RM9200 evaluation kit"
+ select CPU_ARM920T
+
+config TARGET_EB_CPUX9K2
+ bool "Support eb_cpux9k2"
+ select CPU_ARM920T
+
+config TARGET_CPUAT91
+ bool "Support cpuat91"
+ select CPU_ARM920T
+
+config TARGET_AT91SAM9260EK
+ bool "Atmel at91sam9260 reference board"
+ select CPU_ARM926EJS
+
+config TARGET_ETHERNUT5
+ bool "Ethernut5 board"
+ select CPU_ARM926EJS
+
+config TARGET_TNY_A9260
+ bool "Caloa TNY A9260 board"
+ select CPU_ARM926EJS
+
+config TARGET_SNAPPER9260
+ bool "Support snapper9260"
+ select CPU_ARM926EJS
+
+config TARGET_AFEB9260
+ bool "Support afeb9260"
+ select CPU_ARM926EJS
+
+config TARGET_AT91SAM9261EK
+ bool "Atmel at91sam9261 reference board"
+ select CPU_ARM926EJS
+
+config TARGET_PM9261
+ bool "Ronetix pm9261 board"
+ select CPU_ARM926EJS
+
+config TARGET_AT91SAM9263EK
+ bool "Atmel at91sam9263 reference board"
+ select CPU_ARM926EJS
+
+config TARGET_USB_A9263
+ bool "Caloa USB A9260 board"
+ select CPU_ARM926EJS
+
+config TARGET_PM9263
+ bool "Ronetix pm9263 board"
+ select CPU_ARM926EJS
+
+config TARGET_SBC35_A9G20
+ bool "Support sbc35_a9g20"
+ select CPU_ARM926EJS
+
+config TARGET_STAMP9G20
+ bool "Support stamp9g20"
+ select CPU_ARM926EJS
+
+config TARGET_AT91SAM9M10G45EK
+ bool "Atmel AT91SAM9M10G45-EK board"
+ select CPU_ARM926EJS
+
+config TARGET_PM9G45
+ bool "Ronetix pm9g45 board"
+ select CPU_ARM926EJS
+
+config TARGET_AT91SAM9N12EK
+ bool "Atmel AT91SAM9N12-EK board"
+ select CPU_ARM926EJS
+
+config TARGET_AT91SAM9RLEK
+ bool "Atmel at91sam9rl reference board"
+ select CPU_ARM926EJS
+
+config TARGET_AT91SAM9X5EK
+ bool "Atmel AT91SAM9X5-EK board"
+ select CPU_ARM926EJS
+
+config TARGET_SAMA5D3_XPLAINED
+ bool "SAMA5D3 Xplained board"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_SAMA5D3XEK
+ bool "SAMA5D3X-EK board"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_SAMA5D4_XPLAINED
+ bool "SAMA5D4 Xplained board"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_SAMA5D4EK
+ bool "SAMA5D4 Evaluation Kit"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_VL_MA2SC
+ bool "Support vl_ma2sc"
+ select CPU_ARM926EJS
+
+config TARGET_MEESC
+ bool "Support meesc"
+ select CPU_ARM926EJS
+
+config TARGET_OTC570
+ bool "Support otc570"
+ select CPU_ARM926EJS
+
+config TARGET_CPU9260
+ bool "Support cpu9260"
+ select CPU_ARM926EJS
+
+config TARGET_CORVUS
+ bool "Support corvus"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
+config TARGET_TAURUS
+ bool "Support taurus"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
+endchoice
+
+config SYS_SOC
+ default "at91"
+
+source "board/atmel/at91rm9200ek/Kconfig"
+source "board/atmel/at91sam9260ek/Kconfig"
+source "board/atmel/at91sam9261ek/Kconfig"
+source "board/atmel/at91sam9263ek/Kconfig"
+source "board/atmel/at91sam9m10g45ek/Kconfig"
+source "board/atmel/at91sam9n12ek/Kconfig"
+source "board/atmel/at91sam9rlek/Kconfig"
+source "board/atmel/at91sam9x5ek/Kconfig"
+source "board/atmel/sama5d3_xplained/Kconfig"
+source "board/atmel/sama5d3xek/Kconfig"
+source "board/atmel/sama5d4_xplained/Kconfig"
+source "board/atmel/sama5d4ek/Kconfig"
+source "board/BuS/eb_cpux9k2/Kconfig"
+source "board/eukrea/cpuat91/Kconfig"
+source "board/afeb9260/Kconfig"
+source "board/bluewater/snapper9260/Kconfig"
+source "board/BuS/vl_ma2sc/Kconfig"
+source "board/calao/sbc35_a9g20/Kconfig"
+source "board/calao/tny_a9260/Kconfig"
+source "board/calao/usb_a9263/Kconfig"
+source "board/egnite/ethernut5/Kconfig"
+source "board/esd/meesc/Kconfig"
+source "board/esd/otc570/Kconfig"
+source "board/eukrea/cpu9260/Kconfig"
+source "board/ronetix/pm9261/Kconfig"
+source "board/ronetix/pm9263/Kconfig"
+source "board/ronetix/pm9g45/Kconfig"
+source "board/siemens/corvus/Kconfig"
+source "board/siemens/taurus/Kconfig"
+source "board/taskit/stamp9g20/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/at91-common/Makefile b/arch/arm/mach-at91/Makefile
index 89e1577..e596ba6 100644
--- a/arch/arm/cpu/at91-common/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,17 +1,12 @@
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2013 Atmel Corporation
-# Bo Shen <voice.shen@atmel.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
ifneq ($(CONFIG_SPL_BUILD),)
obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
+obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
obj-y += spl.o
endif
+
+obj-$(CONFIG_CPU_ARM920T) += arm920t/
+obj-$(CONFIG_CPU_ARM926EJS) += arm926ejs/
+obj-$(CONFIG_CPU_V7) += armv7/
diff --git a/arch/arm/cpu/arm920t/at91/Makefile b/arch/arm/mach-at91/arm920t/Makefile
index 561b4b4..561b4b4 100644
--- a/arch/arm/cpu/arm920t/at91/Makefile
+++ b/arch/arm/mach-at91/arm920t/Makefile
diff --git a/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c
index fc54327..fc54327 100644
--- a/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c
diff --git a/arch/arm/cpu/arm920t/at91/clock.c b/arch/arm/mach-at91/arm920t/clock.c
index 2813bf7..2813bf7 100644
--- a/arch/arm/cpu/arm920t/at91/clock.c
+++ b/arch/arm/mach-at91/arm920t/clock.c
diff --git a/arch/arm/cpu/arm920t/at91/cpu.c b/arch/arm/mach-at91/arm920t/cpu.c
index b0f411b..b0f411b 100644
--- a/arch/arm/cpu/arm920t/at91/cpu.c
+++ b/arch/arm/mach-at91/arm920t/cpu.c
diff --git a/arch/arm/cpu/arm920t/at91/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S
index d2934a3..d2934a3 100644
--- a/arch/arm/cpu/arm920t/at91/lowlevel_init.S
+++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S
diff --git a/arch/arm/cpu/arm920t/at91/reset.c b/arch/arm/mach-at91/arm920t/reset.c
index d47777a..d47777a 100644
--- a/arch/arm/cpu/arm920t/at91/reset.c
+++ b/arch/arm/mach-at91/arm920t/reset.c
diff --git a/arch/arm/cpu/arm920t/at91/timer.c b/arch/arm/mach-at91/arm920t/timer.c
index 6aa2994..6aa2994 100644
--- a/arch/arm/cpu/arm920t/at91/timer.c
+++ b/arch/arm/mach-at91/arm920t/timer.c
diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile
index 698a28d..ddc323f 100644
--- a/arch/arm/cpu/arm926ejs/at91/Makefile
+++ b/arch/arm/mach-at91/arm926ejs/Makefile
@@ -5,7 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_AT91CAP9) += at91cap9_devices.o
obj-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o
obj-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o
obj-$(CONFIG_AT91SAM9XE) += at91sam9260_devices.o
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c
index efb53d6..efb53d6 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c
index a445c75..a445c75 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c
index 6b51d5f..6b51d5f 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c
index 0e6c0da..0e6c0da 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
+++ b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c
index 39f17a1..39f17a1 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c
+++ b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c
index 0ec32c3..0ec32c3 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c
index 6d94572..6d94572 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
+++ b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c
index f363982..f363982 100644
--- a/arch/arm/cpu/arm926ejs/at91/clock.c
+++ b/arch/arm/mach-at91/arm926ejs/clock.c
diff --git a/arch/arm/cpu/arm926ejs/at91/cpu.c b/arch/arm/mach-at91/arm926ejs/cpu.c
index da1d359..da1d359 100644
--- a/arch/arm/cpu/arm926ejs/at91/cpu.c
+++ b/arch/arm/mach-at91/arm926ejs/cpu.c
diff --git a/arch/arm/cpu/arm926ejs/at91/eflash.c b/arch/arm/mach-at91/arm926ejs/eflash.c
index 3f39264..3f39264 100644
--- a/arch/arm/cpu/arm926ejs/at91/eflash.c
+++ b/arch/arm/mach-at91/arm926ejs/eflash.c
diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/mach-at91/arm926ejs/led.c
index b8d5c78..b8d5c78 100644
--- a/arch/arm/cpu/arm926ejs/at91/led.c
+++ b/arch/arm/mach-at91/arm926ejs/led.c
diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S
index a9ec81a..a9ec81a 100644
--- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
+++ b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S
diff --git a/arch/arm/cpu/arm926ejs/at91/reset.c b/arch/arm/mach-at91/arm926ejs/reset.c
index e67f47b..e67f47b 100644
--- a/arch/arm/cpu/arm926ejs/at91/reset.c
+++ b/arch/arm/mach-at91/arm926ejs/reset.c
diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/mach-at91/arm926ejs/timer.c
index b0b7fb9..b0b7fb9 100644
--- a/arch/arm/cpu/arm926ejs/at91/timer.c
+++ b/arch/arm/mach-at91/arm926ejs/timer.c
diff --git a/arch/arm/cpu/armv7/at91/Makefile b/arch/arm/mach-at91/armv7/Makefile
index f4f35a4..f4f35a4 100644
--- a/arch/arm/cpu/armv7/at91/Makefile
+++ b/arch/arm/mach-at91/armv7/Makefile
diff --git a/arch/arm/cpu/armv7/at91/clock.c b/arch/arm/mach-at91/armv7/clock.c
index 2cdddb2..0bf453e 100644
--- a/arch/arm/cpu/armv7/at91/clock.c
+++ b/arch/arm/mach-at91/armv7/clock.c
@@ -130,10 +130,18 @@ void at91_mck_init(u32 mckr)
AT91_PMC_MCKR_PRES_MASK |
AT91_PMC_MCKR_MDIV_MASK |
AT91_PMC_MCKR_PLLADIV_2);
+#ifdef CPU_HAS_H32MXDIV
+ tmp &= ~AT91_PMC_MCKR_H32MXDIV;
+#endif
+
tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK |
AT91_PMC_MCKR_PRES_MASK |
AT91_PMC_MCKR_MDIV_MASK |
AT91_PMC_MCKR_PLLADIV_2);
+#ifdef CPU_HAS_H32MXDIV
+ tmp |= mckr & AT91_PMC_MCKR_H32MXDIV;
+#endif
+
writel(tmp, &pmc->mckr);
while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/mach-at91/armv7/cpu.c
index 8d86f97..8d86f97 100644
--- a/arch/arm/cpu/armv7/at91/cpu.c
+++ b/arch/arm/mach-at91/armv7/cpu.c
diff --git a/arch/arm/cpu/armv7/at91/reset.c b/arch/arm/mach-at91/armv7/reset.c
index b30e79b..b30e79b 100644
--- a/arch/arm/cpu/armv7/at91/reset.c
+++ b/arch/arm/mach-at91/armv7/reset.c
diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/mach-at91/armv7/sama5d3_devices.c
index 78ecfc8..78ecfc8 100644
--- a/arch/arm/cpu/armv7/at91/sama5d3_devices.c
+++ b/arch/arm/mach-at91/armv7/sama5d3_devices.c
diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c b/arch/arm/mach-at91/armv7/sama5d4_devices.c
new file mode 100644
index 0000000..ef39cb7
--- /dev/null
+++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2014 Atmel
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sama5_matrix.h>
+#include <asm/arch/sama5_sfr.h>
+#include <asm/arch/sama5d4.h>
+
+char *get_cpu_name()
+{
+ unsigned int extension_id = get_extension_chip_id();
+
+ if (cpu_is_sama5d4())
+ switch (extension_id) {
+ case ARCH_EXID_SAMA5D41:
+ return "SAMA5D41";
+ case ARCH_EXID_SAMA5D42:
+ return "SAMA5D42";
+ case ARCH_EXID_SAMA5D43:
+ return "SAMA5D43";
+ case ARCH_EXID_SAMA5D44:
+ return "SAMA5D44";
+ default:
+ return "Unknown CPU type";
+ }
+ else
+ return "Unknown CPU type";
+}
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+void at91_udp_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable UPLL clock */
+ writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
+ /* Enable UDPHS clock */
+ at91_periph_clk_enable(ATMEL_ID_UDPHS);
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+void matrix_init(void)
+{
+ struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0;
+ struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
+ int i;
+
+ /* Disable the write protect */
+ writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
+ writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
+
+ /* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
+ for (i = 4; i <= 10; i++) {
+ writel(0x000f0f0f, &h64mx->ssr[i]);
+ writel(0x0000ffff, &h64mx->sassr[i]);
+ writel(0x0000000f, &h64mx->srtsr[i]);
+ }
+
+ /* CS3 */
+ writel(0x00c0c0c0, &h32mx->ssr[3]);
+ writel(0xff000000, &h32mx->sassr[3]);
+ writel(0xff000000, &h32mx->srtsr[3]);
+
+ /* NFC SRAM */
+ writel(0x00010101, &h32mx->ssr[4]);
+ writel(0x00000001, &h32mx->sassr[4]);
+ writel(0x00000001, &h32mx->srtsr[4]);
+
+ /* Enable the write protect */
+ writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
+ writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
+}
+
+void redirect_int_from_saic_to_aic(void)
+{
+ struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+ u32 key32;
+
+ if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
+ key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
+ writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
+ }
+}
+#endif
diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/mach-at91/armv7/timer.c
index 19bf80b..19bf80b 100644
--- a/arch/arm/cpu/armv7/at91/timer.c
+++ b/arch/arm/mach-at91/armv7/timer.c
diff --git a/arch/arm/mach-at91/config.mk b/arch/arm/mach-at91/config.mk
new file mode 100644
index 0000000..7168abb
--- /dev/null
+++ b/arch/arm/mach-at91/config.mk
@@ -0,0 +1,9 @@
+ifeq ($(CONFIG_CPU_ARM926EJS),y)
+PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)
+endif
+
+ifeq ($(CONFIG_CPU_V7),y)
+ifndef CONFIG_SPL_BUILD
+ALL-y += u-boot.img
+endif
+endif
diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/mach-at91/include/mach/at91_common.h
index 912e55c..efcd74e 100644
--- a/arch/arm/include/asm/arch-at91/at91_common.h
+++ b/arch/arm/mach-at91/include/mach/at91_common.h
@@ -33,5 +33,6 @@ void at91_mck_init(u32 mckr);
void at91_spl_board_init(void);
void at91_disable_wdt(void);
void matrix_init(void);
+void redirect_int_from_saic_to_aic(void);
#endif /* AT91_COMMON_H */
diff --git a/arch/arm/include/asm/arch-at91/at91_dbu.h b/arch/arm/mach-at91/include/mach/at91_dbu.h
index 7346fc0..7346fc0 100644
--- a/arch/arm/include/asm/arch-at91/at91_dbu.h
+++ b/arch/arm/mach-at91/include/mach/at91_dbu.h
diff --git a/arch/arm/include/asm/arch-at91/at91_eefc.h b/arch/arm/mach-at91/include/mach/at91_eefc.h
index 7ffbaee..7ffbaee 100644
--- a/arch/arm/include/asm/arch-at91/at91_eefc.h
+++ b/arch/arm/mach-at91/include/mach/at91_eefc.h
diff --git a/arch/arm/include/asm/arch-at91/at91_emac.h b/arch/arm/mach-at91/include/mach/at91_emac.h
index a0d74ab..a0d74ab 100644
--- a/arch/arm/include/asm/arch-at91/at91_emac.h
+++ b/arch/arm/mach-at91/include/mach/at91_emac.h
diff --git a/arch/arm/include/asm/arch-at91/at91_gpbr.h b/arch/arm/mach-at91/include/mach/at91_gpbr.h
index e781481..e781481 100644
--- a/arch/arm/include/asm/arch-at91/at91_gpbr.h
+++ b/arch/arm/mach-at91/include/mach/at91_gpbr.h
diff --git a/arch/arm/include/asm/arch-at91/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h
index 2379dd4..2379dd4 100644
--- a/arch/arm/include/asm/arch-at91/at91_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91_matrix.h
diff --git a/arch/arm/include/asm/arch-at91/at91_mc.h b/arch/arm/mach-at91/include/mach/at91_mc.h
index 2ace779..2ace779 100644
--- a/arch/arm/include/asm/arch-at91/at91_mc.h
+++ b/arch/arm/mach-at91/include/mach/at91_mc.h
diff --git a/arch/arm/include/asm/arch-at91/at91_pdc.h b/arch/arm/mach-at91/include/mach/at91_pdc.h
index 832ebb5..832ebb5 100644
--- a/arch/arm/include/asm/arch-at91/at91_pdc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pdc.h
diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h
index 50464ff..3012278 100644
--- a/arch/arm/include/asm/arch-at91/at91_pio.h
+++ b/arch/arm/mach-at91/include/mach/at91_pio.h
@@ -114,14 +114,10 @@ typedef union at91_pio {
at91_port_t pioa;
at91_port_t piob;
at91_port_t pioc;
- #if (ATMEL_PIO_PORTS > 3)
- at91_port_t piod;
- #endif
- #if (ATMEL_PIO_PORTS > 4)
- at91_port_t pioe;
- #endif
- } ;
- at91_port_t port[ATMEL_PIO_PORTS];
+ at91_port_t piod; /* not present in all hardware */
+ at91_port_t pioe;/* not present in all hardware */
+ };
+ at91_port_t port[5];
} at91_pio_t;
#ifdef CONFIG_AT91_GPIO
diff --git a/arch/arm/include/asm/arch-at91/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h
index 56724f1..56724f1 100644
--- a/arch/arm/include/asm/arch-at91/at91_pit.h
+++ b/arch/arm/mach-at91/include/mach/at91_pit.h
diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 53b5b2e..65691ab 100644
--- a/arch/arm/include/asm/arch-at91/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -157,10 +157,8 @@ typedef struct at91_pmc {
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
-#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
-#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
@@ -175,7 +173,7 @@ typedef struct at91_pmc {
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
-#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
+#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
@@ -210,7 +208,7 @@ typedef struct at91_pmc {
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
#define AT91RM9200_PMC_MDIV_3 (2 << 8)
#define AT91RM9200_PMC_MDIV_4 (3 << 8)
-#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
+#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
@@ -230,8 +228,7 @@ typedef struct at91_pmc {
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
-#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */
-#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
+#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock */
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
diff --git a/arch/arm/include/asm/arch-at91/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h
index a942342..e4eb3da 100644
--- a/arch/arm/include/asm/arch-at91/at91_rstc.h
+++ b/arch/arm/mach-at91/include/mach/at91_rstc.h
@@ -13,6 +13,8 @@
#ifndef AT91_RSTC_H
#define AT91_RSTC_H
+/* Reset Controller Status Register */
+#define AT91_ASM_RSTC_SR (ATMEL_BASE_RSTC + 0x04)
#define AT91_ASM_RSTC_MR (ATMEL_BASE_RSTC + 0x08)
#ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/arch-at91/at91_rtt.h b/arch/arm/mach-at91/include/mach/at91_rtt.h
index fe7619a..fe7619a 100644
--- a/arch/arm/include/asm/arch-at91/at91_rtt.h
+++ b/arch/arm/mach-at91/include/mach/at91_rtt.h
diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h b/arch/arm/mach-at91/include/mach/at91_spi.h
index b18665b..b18665b 100644
--- a/arch/arm/include/asm/arch-at91/at91_spi.h
+++ b/arch/arm/mach-at91/include/mach/at91_spi.h
diff --git a/arch/arm/include/asm/arch-at91/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h
index b1ee147..b1ee147 100644
--- a/arch/arm/include/asm/arch-at91/at91_st.h
+++ b/arch/arm/mach-at91/include/mach/at91_st.h
diff --git a/arch/arm/include/asm/arch-at91/at91_tc.h b/arch/arm/mach-at91/include/mach/at91_tc.h
index de0e266..de0e266 100644
--- a/arch/arm/include/asm/arch-at91/at91_tc.h
+++ b/arch/arm/mach-at91/include/mach/at91_tc.h
diff --git a/arch/arm/include/asm/arch-at91/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h
index 0644bbf..0644bbf 100644
--- a/arch/arm/include/asm/arch-at91/at91_wdt.h
+++ b/arch/arm/mach-at91/include/mach/at91_wdt.h
diff --git a/arch/arm/include/asm/arch-at91/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index d177bdc..d177bdc 100644
--- a/arch/arm/include/asm/arch-at91/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 8950d67..8950d67 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
diff --git a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
index dc61f48..dc61f48 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 6dfcf4c..6dfcf4c 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
diff --git a/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
index fc5f083..fc5f083 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 64a3888..64a3888 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
diff --git a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
index 54d8622..54d8622 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9_matrix.h
index 1b59cc6..d0bf0c2 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_matrix.h
@@ -15,8 +15,6 @@
#include <asm/arch/at91sam9263_matrix.h>
#elif defined(CONFIG_AT91SAM9RL)
#include <asm/arch/at91sam9rl_matrix.h>
-#elif defined(CONFIG_AT91CAP9)
-#include <asm/arch/at91cap9_matrix.h>
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
#include <asm/arch/at91sam9g45_matrix.h>
#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 3a076c6..3a076c6 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index d29e98e..d29e98e 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 6df8cdb..6df8cdb 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
index 80e49e3..80e49e3 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index 3a8e6d6..3a8e6d6 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
index 295f768..295f768 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 36a5cdf..36a5cdf 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
index bd0b25a..bd0b25a 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
diff --git a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
index 130a85a..130a85a 100644
--- a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h
+++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
diff --git a/arch/arm/include/asm/arch-at91/atmel_serial.h b/arch/arm/mach-at91/include/mach/atmel_serial.h
index 5bc094b..5bc094b 100644
--- a/arch/arm/include/asm/arch-at91/atmel_serial.h
+++ b/arch/arm/mach-at91/include/mach/atmel_serial.h
diff --git a/arch/arm/include/asm/arch-at91/atmel_usba_udc.h b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h
index 38b5012..38b5012 100644
--- a/arch/arm/include/asm/arch-at91/atmel_usba_udc.h
+++ b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h
diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/mach-at91/include/mach/clk.h
index 1d45e2d..1d45e2d 100644
--- a/arch/arm/include/asm/arch-at91/clk.h
+++ b/arch/arm/mach-at91/include/mach/clk.h
diff --git a/arch/arm/include/asm/arch-at91/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index 6d2a7b7..6d2a7b7 100644
--- a/arch/arm/include/asm/arch-at91/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index bf0a1bd..ff6b71b 100644
--- a/arch/arm/include/asm/arch-at91/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -23,8 +23,6 @@
# include <asm/arch/at91sam9g45.h>
#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
# include <asm/arch/at91sam9x5.h>
-#elif defined(CONFIG_AT91CAP9)
-# include <asm/arch/at91cap9.h>
#elif defined(CONFIG_SAMA5D3)
# include <asm/arch/sama5d3.h>
#elif defined(CONFIG_SAMA5D4)
diff --git a/arch/arm/mach-at91/include/mach/sama5_matrix.h b/arch/arm/mach-at91/include/mach/sama5_matrix.h
new file mode 100644
index 0000000..e324766
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama5_matrix.h
@@ -0,0 +1,37 @@
+/*
+ * Bus Matrix header file for the SAMA5 family
+ *
+ * Copyright (C) 2014 Atmel
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SAMA5_MATRIX_H
+#define __SAMA5_MATRIX_H
+
+struct atmel_matrix {
+ u32 mcfg[16]; /* 0x00 ~ 0x3c: Master Configuration Register */
+ u32 scfg[16]; /* 0x40 ~ 0x7c: Slave Configuration Register */
+ u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */
+ u32 res1[20]; /* 0x100 ~ 0x14c */
+ u32 meier; /* 0x150: Master Error Interrupt Enable Register */
+ u32 meidr; /* 0x154: Master Error Interrupt Disable Register */
+ u32 meimr; /* 0x158: Master Error Interrupt Mask Register */
+ u32 mesr; /* 0x15c: Master Error Status Register */
+ u32 mear[16]; /* 0x160 ~ 0x19c: Master Error Address Register */
+ u32 res2[17]; /* 0x1A0 ~ 0x1E0 */
+ u32 wpmr; /* 0x1E4: Write Protection Mode Register */
+ u32 wpsr; /* 0x1E8: Write Protection Status Register */
+ u32 res3[5]; /* 0x1EC ~ 0x1FC */
+ u32 ssr[16]; /* 0x200 ~ 0x23c: Security Slave Register */
+ u32 sassr[16]; /* 0x240 ~ 0x27c: Security Areas Split Slave Register */
+ u32 srtsr[16]; /* 0x280 ~ 0x2bc: Security Region Top Slave */
+ u32 spselr[3]; /* 0x2c0 ~ 0x2c8: Security Peripheral Select Register */
+};
+
+/* Bit field in WPMR */
+#define ATMEL_MATRIX_WPMR_WPKEY 0x4D415400
+#define ATMEL_MATRIX_WPMR_WPEN 0x00000001
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h
new file mode 100644
index 0000000..3081d37
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h
@@ -0,0 +1,38 @@
+/*
+ * Special Function Register (SFR)
+ *
+ * Copyright (C) 2014 Atmel
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SAMA5_SFR_H
+#define __SAMA5_SFR_H
+
+struct atmel_sfr {
+ u32 reserved1; /* 0x00 */
+ u32 ddrcfg; /* 0x04: DDR Configuration Register */
+ u32 reserved2; /* 0x08 */
+ u32 reserved3; /* 0x0c */
+ u32 ohciicr; /* 0x10: OHCI Interrupt Configuration Register */
+ u32 ohciisr; /* 0x14: OHCI Interrupt Status Register */
+ u32 reserved4[4]; /* 0x18 ~ 0x24 */
+ u32 secure; /* 0x28: Security Configuration Register */
+ u32 reserved5[5]; /* 0x2c ~ 0x3c */
+ u32 ebicfg; /* 0x40: EBI Configuration Register */
+ u32 reserved6[2]; /* 0x44 ~ 0x48 */
+ u32 sn0; /* 0x4c */
+ u32 sn1; /* 0x50 */
+ u32 aicredir; /* 0x54 */
+};
+
+/* Bit field in DDRCFG */
+#define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000
+#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000
+
+/* Bit field in AICREDIR */
+#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102
+#define ATMEL_SFR_AICREDIR_NSAIC 0x00000001
+
+#endif
diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index 227ba80..227ba80 100644
--- a/arch/arm/include/asm/arch-at91/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
diff --git a/arch/arm/include/asm/arch-at91/sama5d3_smc.h b/arch/arm/mach-at91/include/mach/sama5d3_smc.h
index a859b6d..a859b6d 100644
--- a/arch/arm/include/asm/arch-at91/sama5d3_smc.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3_smc.h
diff --git a/arch/arm/include/asm/arch-at91/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
index d851568..f30cb5f 100644
--- a/arch/arm/include/asm/arch-at91/sama5d4.h
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -126,6 +126,8 @@
#define ATMEL_BASE_ADC 0xfc034000
#define ATMEL_BASE_TWI3 0xfc038000
+#define ATMEL_BASE_MATRIX1 0xfc054000
+
#define ATMEL_BASE_SMC 0xfc05c000
#define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070)
#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500)
diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/mach-at91/mpddrc.c
index 44798e6..beec13d 100644
--- a/arch/arm/cpu/at91-common/mpddrc.c
+++ b/arch/arm/mach-at91/mpddrc.c
@@ -19,7 +19,7 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
static int ddr2_decodtype_is_seq(u32 cr)
{
-#if defined(CONFIG_SAMA5D3)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
return 0;
#endif
diff --git a/arch/arm/cpu/at91-common/phy.c b/arch/arm/mach-at91/phy.c
index 2cba716..2cba716 100644
--- a/arch/arm/cpu/at91-common/phy.c
+++ b/arch/arm/mach-at91/phy.c
diff --git a/arch/arm/cpu/at91-common/sdram.c b/arch/arm/mach-at91/sdram.c
index 5758b06..5758b06 100644
--- a/arch/arm/cpu/at91-common/sdram.c
+++ b/arch/arm/mach-at91/sdram.c
diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/mach-at91/spl.c
index 6473320..aaa5eec 100644
--- a/arch/arm/cpu/at91-common/spl.c
+++ b/arch/arm/mach-at91/spl.c
@@ -12,12 +12,16 @@
#include <asm/arch/clk.h>
#include <spl.h>
+#if defined(CONFIG_AT91SAM9_WATCHDOG)
+void at91_disable_wdt(void) { }
+#else
void at91_disable_wdt(void)
{
struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT;
writel(AT91_WDT_MR_WDDIS, &wdt->mr);
}
+#endif
u32 spl_boot_device(void)
{
diff --git a/arch/arm/cpu/at91-common/spl_at91.c b/arch/arm/mach-at91/spl_at91.c
index 89f588b..89f588b 100644
--- a/arch/arm/cpu/at91-common/spl_at91.c
+++ b/arch/arm/mach-at91/spl_at91.c
diff --git a/arch/arm/cpu/at91-common/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c
index 7297530..9cc1111 100644
--- a/arch/arm/cpu/at91-common/spl_atmel.c
+++ b/arch/arm/mach-at91/spl_atmel.c
@@ -51,11 +51,23 @@ static void switch_to_main_crystal_osc(void)
while (!(readl(&pmc->mcfr) & AT91_PMC_MAINRDY))
;
+#ifndef CONFIG_SAMA5D4
tmp = readl(&pmc->mor);
tmp &= ~AT91_PMC_MOR_MOSCRCEN;
tmp &= ~AT91_PMC_MOR_KEY(0xff);
tmp |= AT91_PMC_MOR_KEY(0x37);
writel(tmp, &pmc->mor);
+#endif
+}
+
+__weak void matrix_init(void)
+{
+ /* This only be used for sama5d4 soc now */
+}
+
+__weak void redirect_int_from_saic_to_aic(void)
+{
+ /* This only be used for sama5d4 soc now */
}
void s_init(void)
@@ -70,6 +82,10 @@ void s_init(void)
at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+ matrix_init();
+
+ redirect_int_from_saic_to_aic();
+
timer_init();
board_early_init_f();
diff --git a/arch/arm/cpu/at91-common/u-boot-spl.lds b/arch/arm/mach-at91/u-boot-spl.lds
index eccca43..eccca43 100644
--- a/arch/arm/cpu/at91-common/u-boot-spl.lds
+++ b/arch/arm/mach-at91/u-boot-spl.lds
diff --git a/arch/arm/cpu/arm926ejs/davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 613f04d..613f04d 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 7d67191..7d67191 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
diff --git a/arch/arm/cpu/arm926ejs/davinci/config.mk b/arch/arm/mach-davinci/config.mk
index 69e9d5a..69e9d5a 100644
--- a/arch/arm/cpu/arm926ejs/davinci/config.mk
+++ b/arch/arm/mach-davinci/config.mk
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/mach-davinci/cpu.c
index ff61147..ff61147 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/mach-davinci/cpu.c
diff --git a/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c b/arch/arm/mach-davinci/da830_pinmux.c
index edaab45..edaab45 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c
+++ b/arch/arm/mach-davinci/da830_pinmux.c
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c
index 19730ce..19730ce 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/mach-davinci/da850_lowlevel.c
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/arch/arm/mach-davinci/da850_pinmux.c
index 6105f63..6105f63 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
+++ b/arch/arm/mach-davinci/da850_pinmux.c
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index f9550a1..f9550a1 100644
--- a/arch/arm/cpu/arm926ejs/davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index f6ca527..f6ca527 100644
--- a/arch/arm/cpu/arm926ejs/davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/arch/arm/mach-davinci/dm365_lowlevel.c
index c8b4498..c8b4498 100644
--- a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
+++ b/arch/arm/mach-davinci/dm365_lowlevel.c
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index c58e271..c58e271 100644
--- a/arch/arm/cpu/arm926ejs/davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index cfea830..cfea830 100644
--- a/arch/arm/cpu/arm926ejs/davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
diff --git a/arch/arm/cpu/arm926ejs/davinci/dp83848.c b/arch/arm/mach-davinci/dp83848.c
index 603d507..6387e95 100644
--- a/arch/arm/cpu/arm926ejs/davinci/dp83848.c
+++ b/arch/arm/mach-davinci/dp83848.c
@@ -13,7 +13,7 @@
#include <net.h>
#include <dp83848.h>
#include <asm/arch/emac_defs.h>
-#include "../../../../../drivers/net/davinci_emac.h"
+#include "../../../drivers/net/davinci_emac.h"
#ifdef CONFIG_DRIVER_TI_EMAC
diff --git a/arch/arm/cpu/arm926ejs/davinci/et1011c.c b/arch/arm/mach-davinci/et1011c.c
index 9d53875..151020d 100644
--- a/arch/arm/cpu/arm926ejs/davinci/et1011c.c
+++ b/arch/arm/mach-davinci/et1011c.c
@@ -10,7 +10,7 @@
#include <net.h>
#include <miiphy.h>
#include <asm/arch/emac_defs.h>
-#include "../../../../../drivers/net/davinci_emac.h"
+#include "../../../drivers/net/davinci_emac.h"
#ifdef CONFIG_DRIVER_TI_EMAC
diff --git a/arch/arm/include/asm/arch-davinci/aintc_defs.h b/arch/arm/mach-davinci/include/mach/aintc_defs.h
index 5063e39..5063e39 100644
--- a/arch/arm/include/asm/arch-davinci/aintc_defs.h
+++ b/arch/arm/mach-davinci/include/mach/aintc_defs.h
diff --git a/arch/arm/include/asm/arch-davinci/da850_lowlevel.h b/arch/arm/mach-davinci/include/mach/da850_lowlevel.h
index 45a325c..45a325c 100644
--- a/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
+++ b/arch/arm/mach-davinci/include/mach/da850_lowlevel.h
diff --git a/arch/arm/include/asm/arch-davinci/da8xx-usb.h b/arch/arm/mach-davinci/include/mach/da8xx-usb.h
index f091e49..f091e49 100644
--- a/arch/arm/include/asm/arch-davinci/da8xx-usb.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx-usb.h
diff --git a/arch/arm/include/asm/arch-davinci/davinci_misc.h b/arch/arm/mach-davinci/include/mach/davinci_misc.h
index 03be388..03be388 100644
--- a/arch/arm/include/asm/arch-davinci/davinci_misc.h
+++ b/arch/arm/mach-davinci/include/mach/davinci_misc.h
diff --git a/arch/arm/include/asm/arch-davinci/ddr2_defs.h b/arch/arm/mach-davinci/include/mach/ddr2_defs.h
index 24afd9d..24afd9d 100644
--- a/arch/arm/include/asm/arch-davinci/ddr2_defs.h
+++ b/arch/arm/mach-davinci/include/mach/ddr2_defs.h
diff --git a/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h b/arch/arm/mach-davinci/include/mach/dm365_lowlevel.h
index 6c0275e..6c0275e 100644
--- a/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h
+++ b/arch/arm/mach-davinci/include/mach/dm365_lowlevel.h
diff --git a/arch/arm/include/asm/arch-davinci/emac_defs.h b/arch/arm/mach-davinci/include/mach/emac_defs.h
index c3f046e..c3f046e 100644
--- a/arch/arm/include/asm/arch-davinci/emac_defs.h
+++ b/arch/arm/mach-davinci/include/mach/emac_defs.h
diff --git a/arch/arm/include/asm/arch-davinci/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index 7da0060..7da0060 100644
--- a/arch/arm/include/asm/arch-davinci/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index a4eb0bd..a4eb0bd 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
diff --git a/arch/arm/include/asm/arch-davinci/i2c_defs.h b/arch/arm/mach-davinci/include/mach/i2c_defs.h
index 06da894..06da894 100644
--- a/arch/arm/include/asm/arch-davinci/i2c_defs.h
+++ b/arch/arm/mach-davinci/include/mach/i2c_defs.h
diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/arch/arm/mach-davinci/include/mach/pinmux_defs.h
index 2d82af5..2d82af5 100644
--- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
+++ b/arch/arm/mach-davinci/include/mach/pinmux_defs.h
diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/mach-davinci/include/mach/pll_defs.h
index d083ccc..d083ccc 100644
--- a/arch/arm/include/asm/arch-davinci/pll_defs.h
+++ b/arch/arm/mach-davinci/include/mach/pll_defs.h
diff --git a/arch/arm/include/asm/arch-davinci/psc_defs.h b/arch/arm/mach-davinci/include/mach/psc_defs.h
index bcb5580..bcb5580 100644
--- a/arch/arm/include/asm/arch-davinci/psc_defs.h
+++ b/arch/arm/mach-davinci/include/mach/psc_defs.h
diff --git a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h b/arch/arm/mach-davinci/include/mach/sdmmc_defs.h
index 9aa3f4a..9aa3f4a 100644
--- a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h
+++ b/arch/arm/mach-davinci/include/mach/sdmmc_defs.h
diff --git a/arch/arm/include/asm/arch-davinci/syscfg_defs.h b/arch/arm/mach-davinci/include/mach/syscfg_defs.h
index 812088f..812088f 100644
--- a/arch/arm/include/asm/arch-davinci/syscfg_defs.h
+++ b/arch/arm/mach-davinci/include/mach/syscfg_defs.h
diff --git a/arch/arm/include/asm/arch-davinci/timer_defs.h b/arch/arm/mach-davinci/include/mach/timer_defs.h
index 94d1832..94d1832 100644
--- a/arch/arm/include/asm/arch-davinci/timer_defs.h
+++ b/arch/arm/mach-davinci/include/mach/timer_defs.h
diff --git a/arch/arm/cpu/arm926ejs/davinci/ksz8873.c b/arch/arm/mach-davinci/ksz8873.c
index 4af5dd2..75af135 100644
--- a/arch/arm/cpu/arm926ejs/davinci/ksz8873.c
+++ b/arch/arm/mach-davinci/ksz8873.c
@@ -20,7 +20,7 @@
#include <net.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
-#include "../../../../../drivers/net/davinci_emac.h"
+#include "../../../drivers/net/davinci_emac.h"
int ksz8873_is_phy_connected(int phy_addr)
{
diff --git a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S b/arch/arm/mach-davinci/lowlevel_init.S
index e916234..e916234 100644
--- a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
+++ b/arch/arm/mach-davinci/lowlevel_init.S
diff --git a/arch/arm/cpu/arm926ejs/davinci/lxt972.c b/arch/arm/mach-davinci/lxt972.c
index c482fd9..a7356f9 100644
--- a/arch/arm/cpu/arm926ejs/davinci/lxt972.c
+++ b/arch/arm/mach-davinci/lxt972.c
@@ -14,7 +14,7 @@
#include <miiphy.h>
#include <lxt971a.h>
#include <asm/arch/emac_defs.h>
-#include "../../../../../drivers/net/davinci_emac.h"
+#include "../../../drivers/net/davinci_emac.h"
#ifdef CONFIG_DRIVER_TI_EMAC
diff --git a/arch/arm/cpu/arm926ejs/davinci/misc.c b/arch/arm/mach-davinci/misc.c
index e18bdfc..e18bdfc 100644
--- a/arch/arm/cpu/arm926ejs/davinci/misc.c
+++ b/arch/arm/mach-davinci/misc.c
diff --git a/arch/arm/cpu/arm926ejs/davinci/pinmux.c b/arch/arm/mach-davinci/pinmux.c
index e9d8c87..e9d8c87 100644
--- a/arch/arm/cpu/arm926ejs/davinci/pinmux.c
+++ b/arch/arm/mach-davinci/pinmux.c
diff --git a/arch/arm/cpu/arm926ejs/davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 8d99e2e..8d99e2e 100644
--- a/arch/arm/cpu/arm926ejs/davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
diff --git a/arch/arm/cpu/arm926ejs/davinci/reset.c b/arch/arm/mach-davinci/reset.c
index 6b0f154..6b0f154 100644
--- a/arch/arm/cpu/arm926ejs/davinci/reset.c
+++ b/arch/arm/mach-davinci/reset.c
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/mach-davinci/spl.c
index 59b304e..49349da 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/mach-davinci/spl.c
@@ -34,29 +34,14 @@ void putc(char c)
}
#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
-void board_init_f(ulong dummy)
+void spl_board_init(void)
{
- /* First, setup our stack pointer. */
- asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
-
- /* Second, perform our low-level init. */
#ifdef CONFIG_SOC_DM365
dm36x_lowlevel_init(0);
#endif
#ifdef CONFIG_SOC_DA8XX
arch_cpu_init();
#endif
-
- /* Third, we clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* Finally, setup gd and move to the next step. */
- gd = &gdata;
- board_init_r(NULL, 0);
-}
-
-void spl_board_init(void)
-{
preloader_console_init();
}
diff --git a/arch/arm/cpu/arm926ejs/davinci/timer.c b/arch/arm/mach-davinci/timer.c
index c7d0652..c7d0652 100644
--- a/arch/arm/cpu/arm926ejs/davinci/timer.c
+++ b/arch/arm/mach-davinci/timer.c
diff --git a/arch/arm/cpu/armv7/highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 0e73c04..0e73c04 100644
--- a/arch/arm/cpu/armv7/highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
diff --git a/arch/arm/cpu/armv7/highbank/Makefile b/arch/arm/mach-highbank/Makefile
index 876099d..876099d 100644
--- a/arch/arm/cpu/armv7/highbank/Makefile
+++ b/arch/arm/mach-highbank/Makefile
diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/mach-highbank/timer.c
index d56bf21..d56bf21 100644
--- a/arch/arm/cpu/armv7/highbank/timer.c
+++ b/arch/arm/mach-highbank/timer.c
diff --git a/arch/arm/cpu/armv7/keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index 134ae87..134ae87 100644
--- a/arch/arm/cpu/armv7/keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/mach-keystone/Makefile
index ed030db..ed030db 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/mach-keystone/Makefile
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/mach-keystone/clock-k2e.c
index 31f6661..31f6661 100644
--- a/arch/arm/cpu/armv7/keystone/clock-k2e.c
+++ b/arch/arm/mach-keystone/clock-k2e.c
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2hk.c b/arch/arm/mach-keystone/clock-k2hk.c
index 1591960..1591960 100644
--- a/arch/arm/cpu/armv7/keystone/clock-k2hk.c
+++ b/arch/arm/mach-keystone/clock-k2hk.c
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2l.c b/arch/arm/mach-keystone/clock-k2l.c
index 1c5e4d5..1c5e4d5 100644
--- a/arch/arm/cpu/armv7/keystone/clock-k2l.c
+++ b/arch/arm/mach-keystone/clock-k2l.c
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/mach-keystone/clock.c
index d13fbc1..d13fbc1 100644
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/mach-keystone/cmd_clock.c
index af1b701..af1b701 100644
--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
+++ b/arch/arm/mach-keystone/cmd_clock.c
diff --git a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c b/arch/arm/mach-keystone/cmd_ddr3.c
index ea78ad8..ea78ad8 100644
--- a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
+++ b/arch/arm/mach-keystone/cmd_ddr3.c
diff --git a/arch/arm/cpu/armv7/keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c
index f9f58a3..f9f58a3 100644
--- a/arch/arm/cpu/armv7/keystone/cmd_mon.c
+++ b/arch/arm/mach-keystone/cmd_mon.c
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index 923906a..dfb27b5 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -263,17 +263,14 @@ static void ddr3_map_ecc_cic2_irq(u32 base)
}
#endif
-void ddr3_init_ecc(u32 base)
+void ddr3_init_ecc(u32 base, u32 ddr3_size)
{
- u32 ddr3_size;
-
if (!ddr3_ecc_support_rmw(base)) {
ddr3_disable_ecc(base);
return;
}
ddr3_ecc_init_range(base);
- ddr3_size = ddr3_get_size();
ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
/* mapping DDR3 ECC system interrupt from CIC2 to GIC */
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h
index d013b83..d013b83 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2e.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
index f28d5f0..f28d5f0 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h
index bb9a5c4..bb9a5c4 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h
diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index 9f6cfb2..9f6cfb2 100644
--- a/arch/arm/include/asm/arch-keystone/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
diff --git a/arch/arm/include/asm/arch-keystone/clock_defs.h b/arch/arm/mach-keystone/include/mach/clock_defs.h
index 85a046b..85a046b 100644
--- a/arch/arm/include/asm/arch-keystone/clock_defs.h
+++ b/arch/arm/mach-keystone/include/mach/clock_defs.h
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/mach-keystone/include/mach/ddr3.h
index b044d6f..a22c237 100644
--- a/arch/arm/include/asm/arch-keystone/ddr3.h
+++ b/arch/arm/mach-keystone/include/mach/ddr3.h
@@ -48,10 +48,9 @@ struct ddr3_emif_config {
unsigned int sdrfc;
};
-void ddr3_init(void);
-int ddr3_get_size(void);
+u32 ddr3_init(void);
void ddr3_reset_ddrphy(void);
-void ddr3_init_ecc(u32 base);
+void ddr3_init_ecc(u32 base, u32 ddr3_size);
void ddr3_disable_ecc(u32 base);
void ddr3_check_ecc_int(u32 base);
int ddr3_ecc_support_rmw(u32 base);
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/mach-keystone/include/mach/hardware-k2e.h
index df49995..df49995 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2e.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2e.h
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h
index 195c0d3..195c0d3 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/mach-keystone/include/mach/hardware-k2l.h
index 4f1197e..4f1197e 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2l.h
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index 16cbcee..16cbcee 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
diff --git a/arch/arm/include/asm/arch-keystone/i2c_defs.h b/arch/arm/mach-keystone/include/mach/i2c_defs.h
index d425652..d425652 100644
--- a/arch/arm/include/asm/arch-keystone/i2c_defs.h
+++ b/arch/arm/mach-keystone/include/mach/i2c_defs.h
diff --git a/arch/arm/include/asm/arch-keystone/mon.h b/arch/arm/mach-keystone/include/mach/mon.h
index 33a2876..33a2876 100644
--- a/arch/arm/include/asm/arch-keystone/mon.h
+++ b/arch/arm/mach-keystone/include/mach/mon.h
diff --git a/arch/arm/include/asm/arch-keystone/msmc.h b/arch/arm/mach-keystone/include/mach/msmc.h
index 083f5ba..083f5ba 100644
--- a/arch/arm/include/asm/arch-keystone/msmc.h
+++ b/arch/arm/mach-keystone/include/mach/msmc.h
diff --git a/arch/arm/include/asm/arch-keystone/psc_defs.h b/arch/arm/mach-keystone/include/mach/psc_defs.h
index 70d22cf..70d22cf 100644
--- a/arch/arm/include/asm/arch-keystone/psc_defs.h
+++ b/arch/arm/mach-keystone/include/mach/psc_defs.h
diff --git a/arch/arm/include/asm/arch-keystone/xhci-keystone.h b/arch/arm/mach-keystone/include/mach/xhci-keystone.h
index 3aab4e0..3aab4e0 100644
--- a/arch/arm/include/asm/arch-keystone/xhci-keystone.h
+++ b/arch/arm/mach-keystone/include/mach/xhci-keystone.h
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/mach-keystone/init.c
index c96845c..c96845c 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/mach-keystone/init.c
diff --git a/arch/arm/cpu/armv7/keystone/keystone.c b/arch/arm/mach-keystone/keystone.c
index 11a9357..11a9357 100644
--- a/arch/arm/cpu/armv7/keystone/keystone.c
+++ b/arch/arm/mach-keystone/keystone.c
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/mach-keystone/msmc.c
index 7899141..7899141 100644
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ b/arch/arm/mach-keystone/msmc.c
diff --git a/arch/arm/cpu/armv7/keystone/psc.c b/arch/arm/mach-keystone/psc.c
index 237e776..237e776 100644
--- a/arch/arm/cpu/armv7/keystone/psc.c
+++ b/arch/arm/mach-keystone/psc.c
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 45c6687..45c6687 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index df4756e..df4756e 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cache.c b/arch/arm/mach-kirkwood/cache.c
index e18a309..e18a309 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cache.c
+++ b/arch/arm/mach-kirkwood/cache.c
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c
index 4c9d3fd..4c9d3fd 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/mach-kirkwood/cpu.c
diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index e77ac40..e77ac40 100644
--- a/arch/arm/include/asm/arch-kirkwood/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h
index 926d347..926d347 100644
--- a/arch/arm/include/asm/arch-kirkwood/cpu.h
+++ b/arch/arm/mach-kirkwood/include/mach/cpu.h
diff --git a/arch/arm/include/asm/arch-kirkwood/gpio.h b/arch/arm/mach-kirkwood/include/mach/gpio.h
index aa8c5da..aa8c5da 100644
--- a/arch/arm/include/asm/arch-kirkwood/gpio.h
+++ b/arch/arm/mach-kirkwood/include/mach/gpio.h
diff --git a/arch/arm/include/asm/arch-kirkwood/kw88f6192.h b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h
index de220d5..de220d5 100644
--- a/arch/arm/include/asm/arch-kirkwood/kw88f6192.h
+++ b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h
diff --git a/arch/arm/include/asm/arch-kirkwood/kw88f6281.h b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
index ca88a30..ca88a30 100644
--- a/arch/arm/include/asm/arch-kirkwood/kw88f6281.h
+++ b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
diff --git a/arch/arm/include/asm/arch-kirkwood/mpp.h b/arch/arm/mach-kirkwood/include/mach/mpp.h
index 7c8f6eb..7c8f6eb 100644
--- a/arch/arm/include/asm/arch-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/include/mach/mpp.h
diff --git a/arch/arm/include/asm/arch-kirkwood/soc.h b/arch/arm/mach-kirkwood/include/mach/soc.h
index 58ed71b..58ed71b 100644
--- a/arch/arm/include/asm/arch-kirkwood/soc.h
+++ b/arch/arm/mach-kirkwood/include/mach/soc.h
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 7222504..7222504 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
diff --git a/arch/arm/cpu/arm926ejs/nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 265f336..265f336 100644
--- a/arch/arm/cpu/arm926ejs/nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
diff --git a/arch/arm/cpu/arm926ejs/nomadik/Makefile b/arch/arm/mach-nomadik/Makefile
index cdf1345..cdf1345 100644
--- a/arch/arm/cpu/arm926ejs/nomadik/Makefile
+++ b/arch/arm/mach-nomadik/Makefile
diff --git a/arch/arm/cpu/arm926ejs/nomadik/gpio.c b/arch/arm/mach-nomadik/gpio.c
index eff5b2b..eff5b2b 100644
--- a/arch/arm/cpu/arm926ejs/nomadik/gpio.c
+++ b/arch/arm/mach-nomadik/gpio.c
diff --git a/arch/arm/include/asm/arch-nomadik/gpio.h b/arch/arm/mach-nomadik/include/mach/gpio.h
index 311758a..311758a 100644
--- a/arch/arm/include/asm/arch-nomadik/gpio.h
+++ b/arch/arm/mach-nomadik/include/mach/gpio.h
diff --git a/arch/arm/include/asm/arch-nomadik/mtu.h b/arch/arm/mach-nomadik/include/mach/mtu.h
index f89f242..f89f242 100644
--- a/arch/arm/include/asm/arch-nomadik/mtu.h
+++ b/arch/arm/mach-nomadik/include/mach/mtu.h
diff --git a/arch/arm/cpu/arm926ejs/nomadik/reset.S b/arch/arm/mach-nomadik/reset.S
index ec95472..ec95472 100644
--- a/arch/arm/cpu/arm926ejs/nomadik/reset.S
+++ b/arch/arm/mach-nomadik/reset.S
diff --git a/arch/arm/cpu/arm926ejs/nomadik/timer.c b/arch/arm/mach-nomadik/timer.c
index 775d0b7..775d0b7 100644
--- a/arch/arm/cpu/arm926ejs/nomadik/timer.c
+++ b/arch/arm/mach-nomadik/timer.c
diff --git a/arch/arm/cpu/arm926ejs/orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 5a54262..5a54262 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
diff --git a/arch/arm/cpu/arm926ejs/orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 546ebcb..546ebcb 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c
index f88db3b..f88db3b 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
+++ b/arch/arm/mach-orion5x/cpu.c
diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/mach-orion5x/dram.c
index 9ed93d2..9ed93d2 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/dram.c
+++ b/arch/arm/mach-orion5x/dram.c
diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/mach-orion5x/include/mach/cpu.h
index 08a450f..08a450f 100644
--- a/arch/arm/include/asm/arch-orion5x/cpu.h
+++ b/arch/arm/mach-orion5x/include/mach/cpu.h
diff --git a/arch/arm/include/asm/arch-orion5x/mv88f5182.h b/arch/arm/mach-orion5x/include/mach/mv88f5182.h
index e6c71ae..e6c71ae 100644
--- a/arch/arm/include/asm/arch-orion5x/mv88f5182.h
+++ b/arch/arm/mach-orion5x/include/mach/mv88f5182.h
diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index fbb1de8..fbb1de8 100644
--- a/arch/arm/include/asm/arch-orion5x/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
diff --git a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S
index 4dacc29..4dacc29 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S
+++ b/arch/arm/mach-orion5x/lowlevel_init.S
diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/mach-orion5x/timer.c
index ec4f6be..ec4f6be 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/timer.c
+++ b/arch/arm/mach-orion5x/timer.c
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
new file mode 100644
index 0000000..3a8e2b1
--- /dev/null
+++ b/arch/arm/mach-tegra/Kconfig
@@ -0,0 +1,52 @@
+if TEGRA
+
+choice
+ prompt "Tegra SoC select"
+
+config TEGRA20
+ bool "Tegra20 family"
+
+config TEGRA30
+ bool "Tegra30 family"
+
+config TEGRA114
+ bool "Tegra114 family"
+
+config TEGRA124
+ bool "Tegra124 family"
+
+endchoice
+
+config SYS_MALLOC_F
+ default y
+
+config SYS_MALLOC_F_LEN
+ default 0x1800
+
+config USE_PRIVATE_LIBGCC
+ default y if SPL_BUILD
+
+config DM
+ default y if !SPL_BUILD
+
+config DM_SERIAL
+ default y if !SPL_BUILD
+
+config DM_SPI
+ default y if !SPL_BUILD
+
+config DM_SPI_FLASH
+ default y if !SPL_BUILD
+
+config DM_I2C
+ default y if !SPL_BUILD
+
+config DM_GPIO
+ default y if !SPL_BUILD
+
+source "arch/arm/mach-tegra/tegra20/Kconfig"
+source "arch/arm/mach-tegra/tegra30/Kconfig"
+source "arch/arm/mach-tegra/tegra114/Kconfig"
+source "arch/arm/mach-tegra/tegra124/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/mach-tegra/Makefile
index a78869e..04cef0a 100644
--- a/arch/arm/cpu/tegra-common/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -7,6 +7,13 @@
# SPDX-License-Identifier: GPL-2.0+
#
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += cpu.o
+else
+obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
+endif
+
obj-y += ap.o
obj-y += board.o
obj-y += cache.o
@@ -17,3 +24,8 @@ obj-y += powergate.o
obj-y += xusb-padctl.o
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
obj-$(CONFIG_TEGRA124) += vpr.o
+
+obj-$(CONFIG_TEGRA20) += tegra20/
+obj-$(CONFIG_TEGRA30) += tegra30/
+obj-$(CONFIG_TEGRA114) += tegra114/
+obj-$(CONFIG_TEGRA124) += tegra124/
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/mach-tegra/ap.c
index a17dfd1..a17dfd1 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/mach-tegra/ap.c
diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/mach-tegra/board.c
index b6a84a5..b6a84a5 100644
--- a/arch/arm/cpu/tegra-common/board.c
+++ b/arch/arm/mach-tegra/board.c
diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/mach-tegra/cache.c
index 94f5bce..94f5bce 100644
--- a/arch/arm/cpu/tegra-common/cache.c
+++ b/arch/arm/mach-tegra/cache.c
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/mach-tegra/clock.c
index 11c7435..11c7435 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/mach-tegra/clock.c
diff --git a/arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c b/arch/arm/mach-tegra/cmd_enterrcm.c
index a94ec93..a94ec93 100644
--- a/arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c
+++ b/arch/arm/mach-tegra/cmd_enterrcm.c
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/mach-tegra/cpu.c
index c6f3b02..c6f3b02 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/mach-tegra/cpu.c
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/mach-tegra/cpu.h
index b4ca44f..b4ca44f 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.h
+++ b/arch/arm/mach-tegra/cpu.h
diff --git a/arch/arm/cpu/tegra-common/lowlevel_init.S b/arch/arm/mach-tegra/lowlevel_init.S
index a211bb3..a211bb3 100644
--- a/arch/arm/cpu/tegra-common/lowlevel_init.S
+++ b/arch/arm/mach-tegra/lowlevel_init.S
diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c
index 6e3ab0c..6e3ab0c 100644
--- a/arch/arm/cpu/tegra-common/pinmux-common.c
+++ b/arch/arm/mach-tegra/pinmux-common.c
diff --git a/arch/arm/cpu/tegra-common/powergate.c b/arch/arm/mach-tegra/powergate.c
index 439cff3..439cff3 100644
--- a/arch/arm/cpu/tegra-common/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/mach-tegra/spl.c
index e0f9d5b..e0f9d5b 100644
--- a/arch/arm/cpu/arm720t/tegra-common/spl.c
+++ b/arch/arm/mach-tegra/spl.c
diff --git a/arch/arm/cpu/tegra-common/sys_info.c b/arch/arm/mach-tegra/sys_info.c
index 5933c35..5933c35 100644
--- a/arch/arm/cpu/tegra-common/sys_info.c
+++ b/arch/arm/mach-tegra/sys_info.c
diff --git a/arch/arm/cpu/armv7/tegra114/Kconfig b/arch/arm/mach-tegra/tegra114/Kconfig
index 31012bc..31012bc 100644
--- a/arch/arm/cpu/armv7/tegra114/Kconfig
+++ b/arch/arm/mach-tegra/tegra114/Kconfig
diff --git a/arch/arm/cpu/tegra114-common/Makefile b/arch/arm/mach-tegra/tegra114/Makefile
index d959b57..7489f5f 100644
--- a/arch/arm/cpu/tegra114-common/Makefile
+++ b/arch/arm/mach-tegra/tegra114/Makefile
@@ -1,9 +1,6 @@
#
# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2, as published by the Free Software Foundation.
@@ -17,4 +14,6 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
+obj-$(CONFIG_SPL_BUILD) += cpu.o
+
obj-y += clock.o funcmux.o pinmux.o
diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/mach-tegra/tegra114/clock.c
index d5194e1..d5194e1 100644
--- a/arch/arm/cpu/tegra114-common/clock.c
+++ b/arch/arm/mach-tegra/tegra114/clock.c
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/mach-tegra/tegra114/cpu.c
index 5ed3bb9..18dc1af 100644
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ b/arch/arm/mach-tegra/tegra114/cpu.c
@@ -22,7 +22,7 @@
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
-#include "../tegra-common/cpu.h"
+#include "../cpu.h"
/* Tegra114-specific CPU init code */
static void enable_cpu_power_rail(void)
diff --git a/arch/arm/cpu/tegra114-common/funcmux.c b/arch/arm/mach-tegra/tegra114/funcmux.c
index 52441c7..52441c7 100644
--- a/arch/arm/cpu/tegra114-common/funcmux.c
+++ b/arch/arm/mach-tegra/tegra114/funcmux.c
diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/mach-tegra/tegra114/pinmux.c
index 3e5acb9..3e5acb9 100644
--- a/arch/arm/cpu/tegra114-common/pinmux.c
+++ b/arch/arm/mach-tegra/tegra114/pinmux.c
diff --git a/arch/arm/cpu/armv7/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig
index 88f627c..88f627c 100644
--- a/arch/arm/cpu/armv7/tegra124/Kconfig
+++ b/arch/arm/mach-tegra/tegra124/Kconfig
diff --git a/arch/arm/cpu/tegra124-common/Makefile b/arch/arm/mach-tegra/tegra124/Makefile
index 7b59fb1..ef2da29 100644
--- a/arch/arm/cpu/tegra124-common/Makefile
+++ b/arch/arm/mach-tegra/tegra124/Makefile
@@ -5,6 +5,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_SPL_BUILD) += cpu.o
+
obj-y += clock.o
obj-y += funcmux.o
obj-y += pinmux.o
diff --git a/arch/arm/cpu/tegra124-common/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index fc8bd19..fc8bd19 100644
--- a/arch/arm/cpu/tegra124-common/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c
index 6ff6aeb..974f203 100644
--- a/arch/arm/cpu/arm720t/tegra124/cpu.c
+++ b/arch/arm/mach-tegra/tegra124/cpu.c
@@ -15,7 +15,7 @@
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/ap.h>
-#include "../tegra-common/cpu.h"
+#include "../cpu.h"
/* Tegra124-specific CPU init code */
diff --git a/arch/arm/cpu/tegra124-common/funcmux.c b/arch/arm/mach-tegra/tegra124/funcmux.c
index cced787..cced787 100644
--- a/arch/arm/cpu/tegra124-common/funcmux.c
+++ b/arch/arm/mach-tegra/tegra124/funcmux.c
diff --git a/arch/arm/cpu/tegra124-common/pinmux.c b/arch/arm/mach-tegra/tegra124/pinmux.c
index c6685ea..c6685ea 100644
--- a/arch/arm/cpu/tegra124-common/pinmux.c
+++ b/arch/arm/mach-tegra/tegra124/pinmux.c
diff --git a/arch/arm/cpu/tegra124-common/xusb-padctl.c b/arch/arm/mach-tegra/tegra124/xusb-padctl.c
index 43af883..43af883 100644
--- a/arch/arm/cpu/tegra124-common/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c
diff --git a/arch/arm/cpu/armv7/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig
index a354e2a..a354e2a 100644
--- a/arch/arm/cpu/armv7/tegra20/Kconfig
+++ b/arch/arm/mach-tegra/tegra20/Kconfig
diff --git a/arch/arm/cpu/tegra20-common/Makefile b/arch/arm/mach-tegra/tegra20/Makefile
index 0e4b3fc..d48f9bb 100644
--- a/arch/arm/cpu/tegra20-common/Makefile
+++ b/arch/arm/mach-tegra/tegra20/Makefile
@@ -1,12 +1,16 @@
#
# (C) Copyright 2010,2011 Nvidia Corporation.
#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
# SPDX-License-Identifier: GPL-2.0+
#
+ifdef CONFIG_SPL_BUILD
+obj-y += cpu.o
+else
+obj-$(CONFIG_PWM_TEGRA) += pwm.o
+obj-$(CONFIG_VIDEO_TEGRA) += display.o
+endif
+
# The AVP is ARMv4T architecture so we must use special compiler
# flags for any startup files it might use.
CFLAGS_warmboot_avp.o += -march=armv4t
diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/mach-tegra/tegra20/clock.c
index 7b9e10c..7b9e10c 100644
--- a/arch/arm/cpu/tegra20-common/clock.c
+++ b/arch/arm/mach-tegra/tegra20/clock.c
diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.c b/arch/arm/mach-tegra/tegra20/cpu.c
index 2533899..67f49d7 100644
--- a/arch/arm/cpu/arm720t/tegra20/cpu.c
+++ b/arch/arm/mach-tegra/tegra20/cpu.c
@@ -18,7 +18,7 @@
#include <asm/io.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/pmc.h>
-#include "../tegra-common/cpu.h"
+#include "../cpu.h"
static void enable_cpu_power_rail(void)
{
diff --git a/arch/arm/cpu/tegra20-common/crypto.c b/arch/arm/mach-tegra/tegra20/crypto.c
index ec95d7c..ec95d7c 100644
--- a/arch/arm/cpu/tegra20-common/crypto.c
+++ b/arch/arm/mach-tegra/tegra20/crypto.c
diff --git a/arch/arm/cpu/tegra20-common/crypto.h b/arch/arm/mach-tegra/tegra20/crypto.h
index f59b927..f59b927 100644
--- a/arch/arm/cpu/tegra20-common/crypto.h
+++ b/arch/arm/mach-tegra/tegra20/crypto.h
diff --git a/arch/arm/cpu/armv7/tegra20/display.c b/arch/arm/mach-tegra/tegra20/display.c
index 61efed6..61efed6 100644
--- a/arch/arm/cpu/armv7/tegra20/display.c
+++ b/arch/arm/mach-tegra/tegra20/display.c
diff --git a/arch/arm/cpu/tegra20-common/emc.c b/arch/arm/mach-tegra/tegra20/emc.c
index ed2462a..ed2462a 100644
--- a/arch/arm/cpu/tegra20-common/emc.c
+++ b/arch/arm/mach-tegra/tegra20/emc.c
diff --git a/arch/arm/cpu/tegra20-common/funcmux.c b/arch/arm/mach-tegra/tegra20/funcmux.c
index 0df4a07..0df4a07 100644
--- a/arch/arm/cpu/tegra20-common/funcmux.c
+++ b/arch/arm/mach-tegra/tegra20/funcmux.c
diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/mach-tegra/tegra20/pinmux.c
index e484f99..e484f99 100644
--- a/arch/arm/cpu/tegra20-common/pinmux.c
+++ b/arch/arm/mach-tegra/tegra20/pinmux.c
diff --git a/arch/arm/cpu/tegra20-common/pmu.c b/arch/arm/mach-tegra/tegra20/pmu.c
index 36a76a2..a774246 100644
--- a/arch/arm/cpu/tegra20-common/pmu.c
+++ b/arch/arm/mach-tegra/tegra20/pmu.c
@@ -52,7 +52,7 @@ int pmu_set_nominal(void)
debug("%s: Cannot find DVC I2C bus\n", __func__);
return ret;
}
- ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, &dev);
+ ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, 1, &dev);
if (ret) {
debug("%s: Cannot find DVC I2C chip\n", __func__);
return ret;
diff --git a/arch/arm/cpu/armv7/tegra20/pwm.c b/arch/arm/mach-tegra/tegra20/pwm.c
index 5b88636..5b88636 100644
--- a/arch/arm/cpu/armv7/tegra20/pwm.c
+++ b/arch/arm/mach-tegra/tegra20/pwm.c
diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c
index 5fdc4bb..5fdc4bb 100644
--- a/arch/arm/cpu/tegra20-common/warmboot.c
+++ b/arch/arm/mach-tegra/tegra20/warmboot.c
diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c
index 27ce5f4..27ce5f4 100644
--- a/arch/arm/cpu/tegra20-common/warmboot_avp.c
+++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c
diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.h b/arch/arm/mach-tegra/tegra20/warmboot_avp.h
index 7b86acb..7b86acb 100644
--- a/arch/arm/cpu/tegra20-common/warmboot_avp.h
+++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.h
diff --git a/arch/arm/cpu/armv7/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig
index 3abdc7b..3abdc7b 100644
--- a/arch/arm/cpu/armv7/tegra30/Kconfig
+++ b/arch/arm/mach-tegra/tegra30/Kconfig
diff --git a/arch/arm/cpu/tegra30-common/Makefile b/arch/arm/mach-tegra/tegra30/Makefile
index d2d616e..bc250de 100644
--- a/arch/arm/cpu/tegra30-common/Makefile
+++ b/arch/arm/mach-tegra/tegra30/Makefile
@@ -1,9 +1,6 @@
#
# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2, as published by the Free Software Foundation.
@@ -17,4 +14,6 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
+obj-$(CONFIG_SPL_BUILD) += cpu.o
+
obj-y += clock.o funcmux.o pinmux.o
diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/mach-tegra/tegra30/clock.c
index 0eb0f0a..0eb0f0a 100644
--- a/arch/arm/cpu/tegra30-common/clock.c
+++ b/arch/arm/mach-tegra/tegra30/clock.c
diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/mach-tegra/tegra30/cpu.c
index 9003902..c76e74c 100644
--- a/arch/arm/cpu/arm720t/tegra30/cpu.c
+++ b/arch/arm/mach-tegra/tegra30/cpu.c
@@ -22,7 +22,7 @@
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/tegra_i2c.h>
-#include "../tegra-common/cpu.h"
+#include "../cpu.h"
/* Tegra30-specific CPU init code */
void tegra_i2c_ll_write_addr(uint addr, uint config)
diff --git a/arch/arm/cpu/tegra30-common/funcmux.c b/arch/arm/mach-tegra/tegra30/funcmux.c
index 409335c..409335c 100644
--- a/arch/arm/cpu/tegra30-common/funcmux.c
+++ b/arch/arm/mach-tegra/tegra30/funcmux.c
diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/mach-tegra/tegra30/pinmux.c
index 7eb0574..7eb0574 100644
--- a/arch/arm/cpu/tegra30-common/pinmux.c
+++ b/arch/arm/mach-tegra/tegra30/pinmux.c
diff --git a/arch/arm/cpu/tegra-common/vpr.c b/arch/arm/mach-tegra/vpr.c
index f695811..f695811 100644
--- a/arch/arm/cpu/tegra-common/vpr.c
+++ b/arch/arm/mach-tegra/vpr.c
diff --git a/arch/arm/cpu/tegra-common/xusb-padctl.c b/arch/arm/mach-tegra/xusb-padctl.c
index 65f8d2e..65f8d2e 100644
--- a/arch/arm/cpu/tegra-common/xusb-padctl.c
+++ b/arch/arm/mach-tegra/xusb-padctl.c
diff --git a/arch/arm/cpu/arm926ejs/versatile/Kconfig b/arch/arm/mach-versatile/Kconfig
index d2e76f4..d2e76f4 100644
--- a/arch/arm/cpu/arm926ejs/versatile/Kconfig
+++ b/arch/arm/mach-versatile/Kconfig
diff --git a/arch/arm/cpu/arm926ejs/versatile/Makefile b/arch/arm/mach-versatile/Makefile
index 907f516..907f516 100644
--- a/arch/arm/cpu/arm926ejs/versatile/Makefile
+++ b/arch/arm/mach-versatile/Makefile
diff --git a/arch/arm/cpu/arm926ejs/versatile/reset.S b/arch/arm/mach-versatile/reset.S
index 1c557b0..1c557b0 100644
--- a/arch/arm/cpu/arm926ejs/versatile/reset.S
+++ b/arch/arm/mach-versatile/reset.S
diff --git a/arch/arm/cpu/arm926ejs/versatile/timer.c b/arch/arm/mach-versatile/timer.c
index 5d694d8..5d694d8 100644
--- a/arch/arm/cpu/arm926ejs/versatile/timer.c
+++ b/arch/arm/mach-versatile/timer.c
diff --git a/arch/arm/mvebu-common/Makefile b/arch/arm/mvebu-common/Makefile
index 9dcab69..de243fe 100644
--- a/arch/arm/mvebu-common/Makefile
+++ b/arch/arm/mvebu-common/Makefile
@@ -10,3 +10,5 @@ obj-y = dram.o
obj-y += gpio.o
obj-$(CONFIG_ARMADA_XP) += mbus.o
obj-y += timer.o
+
+obj-y += serdes/
diff --git a/arch/arm/mvebu-common/serdes/Makefile b/arch/arm/mvebu-common/serdes/Makefile
new file mode 100644
index 0000000..a380fee
--- /dev/null
+++ b/arch/arm/mvebu-common/serdes/Makefile
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD) = high_speed_env_lib.o
+obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec.o
diff --git a/arch/arm/mvebu-common/serdes/board_env_spec.h b/arch/arm/mvebu-common/serdes/board_env_spec.h
new file mode 100644
index 0000000..36e0ed8
--- /dev/null
+++ b/arch/arm/mvebu-common/serdes/board_env_spec.h
@@ -0,0 +1,262 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __BOARD_ENV_SPEC
+#define __BOARD_ENV_SPEC
+
+/* Board specific configuration */
+
+/* KW40 */
+#define MV_6710_DEV_ID 0x6710
+
+#define MV_6710_Z1_REV 0x0
+#define MV_6710_Z1_ID ((MV_6710_DEV_ID << 16) | MV_6710_Z1_REV)
+#define MV_6710_Z1_NAME "MV6710 Z1"
+
+/* Armada XP Family */
+#define MV_78130_DEV_ID 0x7813
+#define MV_78160_DEV_ID 0x7816
+#define MV_78230_DEV_ID 0x7823
+#define MV_78260_DEV_ID 0x7826
+#define MV_78460_DEV_ID 0x7846
+#define MV_78000_DEV_ID 0x7888
+
+#define MV_FPGA_DEV_ID 0x2107
+
+#define MV_78XX0_Z1_REV 0x0
+
+/* boards ID numbers */
+#define BOARD_ID_BASE 0x0
+
+/* New board ID numbers */
+#define DB_88F78XX0_BP_ID (BOARD_ID_BASE)
+#define RD_78460_SERVER_ID (DB_88F78XX0_BP_ID + 1)
+#define DB_78X60_PCAC_ID (RD_78460_SERVER_ID + 1)
+#define FPGA_88F78XX0_ID (DB_78X60_PCAC_ID + 1)
+#define DB_88F78XX0_BP_REV2_ID (FPGA_88F78XX0_ID + 1)
+#define RD_78460_NAS_ID (DB_88F78XX0_BP_REV2_ID + 1)
+#define DB_78X60_AMC_ID (RD_78460_NAS_ID + 1)
+#define DB_78X60_PCAC_REV2_ID (DB_78X60_AMC_ID + 1)
+#define RD_78460_SERVER_REV2_ID (DB_78X60_PCAC_REV2_ID + 1)
+#define DB_784MP_GP_ID (RD_78460_SERVER_REV2_ID + 1)
+#define RD_78460_CUSTOMER_ID (DB_784MP_GP_ID + 1)
+#define MV_MAX_BOARD_ID (RD_78460_CUSTOMER_ID + 1)
+#define INVALID_BAORD_ID 0xFFFFFFFF
+
+/* Sample at Reset */
+#define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4))
+
+/* BIOS Modes related defines */
+
+#define SAR0_BOOTWIDTH_OFFSET 3
+#define SAR0_BOOTWIDTH_MASK (0x3 << SAR0_BOOTWIDTH_OFFSET)
+#define SAR0_BOOTSRC_OFFSET 5
+#define SAR0_BOOTSRC_MASK (0xF << SAR0_BOOTSRC_OFFSET)
+
+#define SAR0_L2_SIZE_OFFSET 19
+#define SAR0_L2_SIZE_MASK (0x3 << SAR0_L2_SIZE_OFFSET)
+#define SAR0_CPU_FREQ_OFFSET 21
+#define SAR0_CPU_FREQ_MASK (0x7 << SAR0_CPU_FREQ_OFFSET)
+#define SAR0_FABRIC_FREQ_OFFSET 24
+#define SAR0_FABRIC_FREQ_MASK (0xF << SAR0_FABRIC_FREQ_OFFSET)
+#define SAR0_CPU0CORE_OFFSET 31
+#define SAR0_CPU0CORE_MASK (0x1 << SAR0_CPU0CORE_OFFSET)
+#define SAR1_CPU0CORE_OFFSET 0
+#define SAR1_CPU0CORE_MASK (0x1 << SAR1_CPU0CORE_OFFSET)
+
+#define PEX_CLK_100MHZ_OFFSET 2
+#define PEX_CLK_100MHZ_MASK (0x1 << PEX_CLK_100MHZ_OFFSET)
+
+#define SAR1_FABRIC_MODE_OFFSET 19
+#define SAR1_FABRIC_MODE_MASK (0x1 << SAR1_FABRIC_MODE_OFFSET)
+#define SAR1_CPU_MODE_OFFSET 20
+#define SAR1_CPU_MODE_MASK (0x1 << SAR1_CPU_MODE_OFFSET)
+
+#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24))
+
+
+#define CORE_AVS_CONTROL_0REG 0x18300
+#define CORE_AVS_CONTROL_2REG 0x18308
+#define CPU_AVS_CONTROL2_REG 0x20868
+#define CPU_AVS_CONTROL0_REG 0x20860
+#define GENERAL_PURPOSE_RESERVED0_REG 0x182E0
+
+#define MSAR_TCLK_OFFS 28
+#define MSAR_TCLK_MASK (0x1 << MSAR_TCLK_OFFS)
+
+
+/* Controler environment registers offsets */
+#define GEN_PURP_RES_1_REG 0x182F4
+#define GEN_PURP_RES_2_REG 0x182F8
+
+/* registers offsets */
+#define MV_GPP_REGS_OFFSET(unit) (0x18100 + ((unit) * 0x40))
+#define MPP_CONTROL_REG(id) (0x18000 + (id * 4))
+#define MV_GPP_REGS_BASE(unit) (MV_GPP_REGS_OFFSET(unit))
+#define MV_GPP_REGS_BASE_0 (MV_GPP_REGS_OFFSET_0)
+
+#define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00)
+#define GPP_DATA_OUT_REG_0 (MV_GPP_REGS_BASE_0 + 0x00) /* Used in .S files */
+#define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04)
+#define GPP_BLINK_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x08)
+#define GPP_DATA_IN_POL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x0C)
+#define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10)
+#define GPP_INT_CAUSE_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x14)
+#define GPP_INT_MASK_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x18)
+#define GPP_INT_LVL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x1C)
+#define GPP_OUT_SET_REG(grp) (0x18130 + ((grp) * 0x40))
+#define GPP_64_66_DATA_OUT_SET_REG 0x181A4
+#define GPP_OUT_CLEAR_REG(grp) (0x18134 + ((grp) * 0x40))
+#define GPP_64_66_DATA_OUT_CLEAR_REG 0x181B0
+#define GPP_FUNC_SELECT_REG (MV_GPP_REGS_BASE(0) + 0x40)
+
+#define MV_GPP66 (1 << 2)
+
+/* Relevant for MV78XX0 */
+#define GPP_DATA_OUT_SET_REG (MV_GPP_REGS_BASE(0) + 0x20)
+#define GPP_DATA_OUT_CLEAR_REG (MV_GPP_REGS_BASE(0) + 0x24)
+
+/* This define describes the maximum number of supported PEX Interfaces */
+#define MV_PEX_MAX_IF 10
+#define MV_PEX_MAX_UNIT 4
+
+#define MV_SERDES_NUM_TO_PEX_NUM(num) ((num < 8) ? (num) : (8 + (num / 12)))
+
+#define PEX_PHY_ACCESS_REG(unit) (0x40000 + ((unit) % 2 * 0x40000) + \
+ ((unit)/2 * 0x2000) + 0x1B00)
+
+#define SATA_BASE_REG(port) (0xA2000 + (port)*0x2000)
+
+#define SATA_PWR_PLL_CTRL_REG(port) (SATA_BASE_REG(port) + 0x804)
+#define SATA_DIG_LP_ENA_REG(port) (SATA_BASE_REG(port) + 0x88C)
+#define SATA_REF_CLK_SEL_REG(port) (SATA_BASE_REG(port) + 0x918)
+#define SATA_COMPHY_CTRL_REG(port) (SATA_BASE_REG(port) + 0x920)
+#define SATA_LP_PHY_EXT_CTRL_REG(port) (SATA_BASE_REG(port) + 0x058)
+#define SATA_LP_PHY_EXT_STAT_REG(port) (SATA_BASE_REG(port) + 0x05C)
+#define SATA_IMP_TX_SSC_CTRL_REG(port) (SATA_BASE_REG(port) + 0x810)
+#define SATA_GEN_1_SET_0_REG(port) (SATA_BASE_REG(port) + 0x834)
+#define SATA_GEN_1_SET_1_REG(port) (SATA_BASE_REG(port) + 0x838)
+#define SATA_GEN_2_SET_0_REG(port) (SATA_BASE_REG(port) + 0x83C)
+#define SATA_GEN_2_SET_1_REG(port) (SATA_BASE_REG(port) + 0x840)
+
+#define MV_ETH_BASE_ADDR (0x72000)
+#define MV_ETH_REGS_OFFSET(port) (MV_ETH_BASE_ADDR - ((port) / 2) * \
+ 0x40000 + ((port) % 2) * 0x4000)
+#define MV_ETH_REGS_BASE(port) MV_ETH_REGS_OFFSET(port)
+
+
+#define SGMII_PWR_PLL_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xE04)
+#define SGMII_DIG_LP_ENA_REG(port) (MV_ETH_REGS_BASE(port) + 0xE8C)
+#define SGMII_REF_CLK_SEL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF18)
+#define SGMII_SERDES_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4A0)
+#define SGMII_SERDES_STAT_REG(port) (MV_ETH_REGS_BASE(port) + 0x4A4)
+#define SGMII_COMPHY_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF20)
+#define QSGMII_GEN_1_SETTING_REG(port) (MV_ETH_REGS_BASE(port) + 0xE38)
+#define QSGMII_SERDES_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4a0)
+
+#define SERDES_LINE_MUX_REG_0_7 0x18270
+#define SERDES_LINE_MUX_REG_8_15 0x18274
+#define QSGMII_CONTROL_1_REG 0x18404
+
+/* SOC_CTRL_REG fields */
+#define SCR_PEX_ENA_OFFS(pex) ((pex) & 0x3)
+#define SCR_PEX_ENA_MASK(pex) (1 << pex)
+
+#define PCIE0_QUADX1_EN (1<<7)
+#define PCIE1_QUADX1_EN (1<<8)
+
+#define SCR_PEX_4BY1_OFFS(pex) ((pex) + 7)
+#define SCR_PEX_4BY1_MASK(pex) (1 << SCR_PEX_4BY1_OFFS(pex))
+
+#define PCIE1_CLK_OUT_EN_OFF 5
+#define PCIE1_CLK_OUT_EN_MASK (1 << PCIE1_CLK_OUT_EN_OFF)
+
+#define PCIE0_CLK_OUT_EN_OFF 4
+#define PCIE0_CLK_OUT_EN_MASK (1 << PCIE0_CLK_OUT_EN_OFF)
+
+#define SCR_PEX0_4BY1_OFFS 7
+#define SCR_PEX0_4BY1_MASK (1 << SCR_PEX0_4BY1_OFFS)
+
+#define SCR_PEX1_4BY1_OFFS 8
+#define SCR_PEX1_4BY1_MASK (1 << SCR_PEX1_4BY1_OFFS)
+
+
+#define MV_MISC_REGS_OFFSET (0x18200)
+#define MV_MISC_REGS_BASE (MV_MISC_REGS_OFFSET)
+#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4)
+
+/*
+ * PCI Express Control and Status Registers
+ */
+#define MAX_PEX_DEVICES 32
+#define MAX_PEX_FUNCS 8
+#define MAX_PEX_BUSSES 256
+
+#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */
+#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS)
+
+#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */
+#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS)
+
+#define PXSR_DL_DOWN 0x1 /* DL_Down indication. */
+#define PXCAR_CONFIG_EN (1 << 31)
+#define PEX_STATUS_AND_COMMAND 0x004
+#define PXSAC_MABORT (1 << 29) /* Recieved Master Abort */
+
+/* PCI Express Configuration Address Register */
+
+/* PEX_CFG_ADDR_REG (PXCAR) */
+#define PXCAR_REG_NUM_OFFS 2
+#define PXCAR_REG_NUM_MAX 0x3F
+#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS)
+#define PXCAR_FUNC_NUM_OFFS 8
+#define PXCAR_FUNC_NUM_MAX 0x7
+#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS)
+#define PXCAR_DEVICE_NUM_OFFS 11
+#define PXCAR_DEVICE_NUM_MAX 0x1F
+#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS)
+#define PXCAR_BUS_NUM_OFFS 16
+#define PXCAR_BUS_NUM_MAX 0xFF
+#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS)
+#define PXCAR_EXT_REG_NUM_OFFS 24
+#define PXCAR_EXT_REG_NUM_MAX 0xF
+
+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
+#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS)
+
+
+#define PEX_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x60)
+#define PEX_LINK_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x6C)
+#define PEX_LINK_CTRL_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x70)
+#define PEX_LINK_CTRL_STATUS2_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x90)
+#define PEX_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A00)
+#define PEX_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A04)
+#define PEX_COMPLT_TMEOUT_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A10)
+#define PEX_PWR_MNG_EXT_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A18)
+#define PEX_FLOW_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A20)
+#define PEX_DYNMC_WIDTH_MNG_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A30)
+#define PEX_ROOT_CMPLX_SSPL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A0C)
+#define PEX_RAM_PARITY_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A50)
+#define PEX_DBG_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A60)
+#define PEX_DBG_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A64)
+
+#define PXLCSR_NEG_LNK_GEN_OFFS 16 /* Negotiated Link GEN */
+#define PXLCSR_NEG_LNK_GEN_MASK (0xf << PXLCSR_NEG_LNK_GEN_OFFS)
+#define PXLCSR_NEG_LNK_GEN_1_1 (0x1 << PXLCSR_NEG_LNK_GEN_OFFS)
+#define PXLCSR_NEG_LNK_GEN_2_0 (0x2 << PXLCSR_NEG_LNK_GEN_OFFS)
+
+#define PEX_CFG_ADDR_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x18F8)
+#define PEX_CFG_DATA_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x18FC)
+#define PEX_CAUSE_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1900)
+
+#define PEX_CAPABILITY_REG 0x60
+#define PEX_DEV_CAPABILITY_REG 0x64
+#define PEX_DEV_CTRL_STAT_REG 0x68
+#define PEX_LINK_CAPABILITY_REG 0x6C
+#define PEX_LINK_CTRL_STAT_REG 0x70
+#define PEX_LINK_CTRL_STAT_2_REG 0x90
+
+#endif /* __BOARD_ENV_SPEC */
diff --git a/arch/arm/mvebu-common/serdes/high_speed_env_lib.c b/arch/arm/mvebu-common/serdes/high_speed_env_lib.c
new file mode 100644
index 0000000..702273a
--- /dev/null
+++ b/arch/arm/mvebu-common/serdes/high_speed_env_lib.c
@@ -0,0 +1,1572 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "high_speed_env_spec.h"
+#include "board_env_spec.h"
+
+#define SERDES_VERION "2.1.5"
+#define ENDED_OK "High speed PHY - Ended Successfully\n"
+
+static const u8 serdes_cfg[][SERDES_LAST_UNIT] = BIN_SERDES_CFG;
+
+extern MV_BIN_SERDES_CFG *serdes_info_tbl[];
+
+extern u8 rd78460gp_twsi_dev[];
+extern u8 db88f78xx0rev2_twsi_dev[];
+
+u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs);
+int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
+int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
+
+#define MV_BOARD_PEX_MODULE_ADDR 0x23
+#define MV_BOARD_PEX_MODULE_ID 1
+#define MV_BOARD_ETM_MODULE_ID 2
+
+#define PEX_MODULE_DETECT 1
+#define ETM_MODULE_DETECT 2
+
+#define PEX_MODE_GET(satr) ((satr & 0x6) >> 1)
+#define PEX_CAPABILITY_GET(satr) (satr & 1)
+#define MV_PEX_UNIT_TO_IF(pex_unit) ((pex_unit < 3) ? (pex_unit * 4) : 9)
+
+/* Static parametes */
+static int config_module;
+static int switch_module;
+
+/* Local function */
+static u32 board_id_get(void)
+{
+#if defined(CONFIG_DB_88F78X60)
+ return DB_88F78XX0_BP_ID;
+#elif defined(CONFIG_RD_88F78460_SERVER)
+ return RD_78460_SERVER_ID;
+#elif defined(CONFIG_RD_78460_SERVER_REV2)
+ return RD_78460_SERVER_REV2_ID;
+#elif defined(CONFIG_DB_78X60_PCAC)
+ return DB_78X60_PCAC_ID;
+#elif defined(CONFIG_DB_88F78X60_REV2)
+ return DB_88F78XX0_BP_REV2_ID;
+#elif defined(CONFIG_RD_78460_NAS)
+ return RD_78460_NAS_ID;
+#elif defined(CONFIG_DB_78X60_AMC)
+ return DB_78X60_AMC_ID;
+#elif defined(CONFIG_DB_78X60_PCAC_REV2)
+ return DB_78X60_PCAC_REV2_ID;
+#elif defined(CONFIG_DB_784MP_GP)
+ return DB_784MP_GP_ID;
+#elif defined(CONFIG_RD_78460_CUSTOMER)
+ return RD_78460_CUSTOMER_ID;
+#else
+ /*
+ * Return 0 here for custom board as this should not be used
+ * for custom boards.
+ */
+ return 0;
+#endif
+}
+
+static u8 board_sat_r_get(u8 dev_num, u8 reg)
+{
+ u8 data;
+ u8 *dev;
+ u32 board_id = board_id_get();
+ int ret;
+
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ switch (board_id) {
+ case DB_784MP_GP_ID:
+ dev = rd78460gp_twsi_dev;
+
+ break;
+ case DB_88F78XX0_BP_ID:
+ case DB_88F78XX0_BP_REV2_ID:
+ dev = db88f78xx0rev2_twsi_dev;
+ break;
+
+ case DB_78X60_PCAC_ID:
+ case FPGA_88F78XX0_ID:
+ case DB_78X60_PCAC_REV2_ID:
+ case RD_78460_SERVER_REV2_ID:
+ default:
+ return 0;
+ }
+
+ /* Read MPP module ID */
+ ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1);
+ if (ret)
+ return MV_ERROR;
+
+ return data;
+}
+
+static int board_modules_scan(void)
+{
+ u8 val;
+ u32 board_id = board_id_get();
+ int ret;
+
+ /* Perform scan only for DB board */
+ if ((board_id == DB_88F78XX0_BP_ID) ||
+ (board_id == DB_88F78XX0_BP_REV2_ID)) {
+ /* reset modules flags */
+ config_module = 0;
+
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ /* SERDES module (only PEX model is supported now) */
+ ret = i2c_read(MV_BOARD_PEX_MODULE_ADDR, 0, 1, (u8 *)&val, 1);
+ if (ret)
+ return MV_ERROR;
+
+ if (val == MV_BOARD_PEX_MODULE_ID)
+ config_module = PEX_MODULE_DETECT;
+ if (val == MV_BOARD_ETM_MODULE_ID)
+ config_module = ETM_MODULE_DETECT;
+ } else if (board_id == RD_78460_NAS_ID) {
+ switch_module = 0;
+ if ((reg_read(GPP_DATA_IN_REG(2)) & MV_GPP66) == 0x0)
+ switch_module = 1;
+ }
+
+ return MV_OK;
+}
+
+u32 pex_max_unit_get(void)
+{
+ /*
+ * TODO:
+ * Right now only MV78460 is supported. Other SoC's might need
+ * a different value here.
+ */
+ return MV_PEX_MAX_UNIT;
+}
+
+u32 pex_max_if_get(void)
+{
+ /*
+ * TODO:
+ * Right now only MV78460 is supported. Other SoC's might need
+ * a different value here.
+ */
+ return MV_PEX_MAX_IF;
+}
+
+u8 board_cpu_freq_get(void)
+{
+ u32 sar;
+ u32 sar_msb;
+
+ sar = reg_read(MPP_SAMPLE_AT_RESET(0));
+ sar_msb = reg_read(MPP_SAMPLE_AT_RESET(1));
+ return ((sar_msb & 0x100000) >> 17) | ((sar & 0xe00000) >> 21);
+}
+
+__weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
+{
+ u32 board_id;
+ u32 serdes_cfg_val = 0; /* default */
+
+ board_id = board_id_get();
+
+ switch (board_id) {
+ case DB_784MP_GP_ID:
+ serdes_cfg_val = 0;
+ break;
+ }
+
+ return &serdes_info_tbl[board_id - BOARD_ID_BASE][serdes_cfg_val];
+}
+
+u16 ctrl_model_get(void)
+{
+ /* Right now only MV78460 supported */
+ return MV_78460_DEV_ID;
+}
+
+u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info)
+{
+ if (line_num < 8)
+ return (info->line0_7 >> (line_num << 2)) & 0xF;
+ else
+ return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF;
+}
+
+int serdes_phy_config(void)
+{
+ int status = MV_OK;
+ u32 line_cfg;
+ u8 line_num;
+ /* addr/value for each line @ every setup step */
+ u32 addr[16][11], val[16][11];
+ u8 pex_unit, pex_line_num;
+ u8 sgmii_port = 0;
+ u32 tmp;
+ u32 in_direct;
+ u8 max_serdes_lines;
+ MV_BIN_SERDES_CFG *info;
+ u8 satr11;
+ u8 sata_port;
+ u8 freq;
+ u8 device_rev;
+ u32 rx_high_imp_mode;
+ u16 ctrl_mode;
+ u32 board_id = board_id_get();
+ u32 pex_if;
+ u32 pex_if_num;
+
+ /*
+ * TODO:
+ * Right now we only support the MV78460 with 16 serdes lines
+ */
+ max_serdes_lines = 16;
+ if (max_serdes_lines == 0)
+ return MV_OK;
+
+ switch (board_id) {
+ case DB_78X60_AMC_ID:
+ case DB_78X60_PCAC_REV2_ID:
+ case RD_78460_CUSTOMER_ID:
+ case RD_78460_SERVER_ID:
+ case RD_78460_SERVER_REV2_ID:
+ case DB_78X60_PCAC_ID:
+ satr11 = (0x1 << 1) | 1;
+ break;
+ case FPGA_88F78XX0_ID:
+ case RD_78460_NAS_ID:
+ satr11 = (0x0 << 1) | 1;
+ break;
+ case DB_88F78XX0_BP_REV2_ID:
+ case DB_784MP_GP_ID:
+ case DB_88F78XX0_BP_ID:
+ satr11 = board_sat_r_get(1, 1);
+ if ((u8) MV_ERROR == (u8) satr11)
+ return MV_ERROR;
+ break;
+ }
+
+ board_modules_scan();
+ memset(addr, 0, sizeof(addr));
+ memset(val, 0, sizeof(val));
+
+ /* Check if DRAM is already initialized */
+ if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
+ (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
+ DEBUG_INIT_S("High speed PHY - Version: ");
+ DEBUG_INIT_S(SERDES_VERION);
+ DEBUG_INIT_S(" - 2nd boot - Skip\n");
+ return MV_OK;
+ }
+ DEBUG_INIT_S("High speed PHY - Version: ");
+ DEBUG_INIT_S(SERDES_VERION);
+ DEBUG_INIT_S(" (COM-PHY-V20)\n");
+
+ /*
+ * AVS : disable AVS for frequency less than 1333
+ */
+ freq = board_cpu_freq_get();
+ device_rev = mv_ctrl_rev_get();
+
+ if (device_rev == 2) { /* for B0 only */
+ u32 cpu_avs;
+ u8 fabric_freq;
+ cpu_avs = reg_read(CPU_AVS_CONTROL2_REG);
+ DEBUG_RD_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
+ cpu_avs &= ~(1 << 9);
+
+ if ((0x4 == freq) || (0xB == freq)) {
+ u32 tmp2;
+
+ tmp2 = reg_read(CPU_AVS_CONTROL0_REG);
+ DEBUG_RD_REG(CPU_AVS_CONTROL0_REG, tmp2);
+ /* cpu upper limit = 1.1V cpu lower limit = 0.9125V */
+ tmp2 |= 0x0FF;
+ reg_write(CPU_AVS_CONTROL0_REG, tmp2);
+ DEBUG_WR_REG(CPU_AVS_CONTROL0_REG, tmp2);
+ cpu_avs |= (1 << 9); /* cpu avs enable */
+ cpu_avs |= (1 << 18); /* AvsAvddDetEn enable */
+ fabric_freq = (reg_read(MPP_SAMPLE_AT_RESET(0)) &
+ SAR0_FABRIC_FREQ_MASK) >> SAR0_FABRIC_FREQ_OFFSET;
+ if ((0xB == freq) && (5 == fabric_freq)) {
+ u32 core_avs;
+
+ core_avs = reg_read(CORE_AVS_CONTROL_0REG);
+ DEBUG_RD_REG(CORE_AVS_CONTROL_0REG, core_avs);
+
+ /*
+ * Set core lower limit = 0.9V &
+ * core upper limit = 0.9125V
+ */
+ core_avs &= ~(0xff);
+ core_avs |= 0x0E;
+ reg_write(CORE_AVS_CONTROL_0REG, core_avs);
+ DEBUG_WR_REG(CORE_AVS_CONTROL_0REG, core_avs);
+
+ core_avs = reg_read(CORE_AVS_CONTROL_2REG);
+ DEBUG_RD_REG(CORE_AVS_CONTROL_2REG, core_avs);
+ core_avs |= (1 << 9); /* core AVS enable */
+ reg_write(CORE_AVS_CONTROL_2REG, core_avs);
+ DEBUG_WR_REG(CORE_AVS_CONTROL_2REG, core_avs);
+
+ tmp2 = reg_read(GENERAL_PURPOSE_RESERVED0_REG);
+ DEBUG_RD_REG(GENERAL_PURPOSE_RESERVED0_REG,
+ tmp2);
+ tmp2 |= 0x1; /* AvsCoreAvddDetEn enable */
+ reg_write(GENERAL_PURPOSE_RESERVED0_REG, tmp2);
+ DEBUG_WR_REG(GENERAL_PURPOSE_RESERVED0_REG,
+ tmp2);
+ }
+ }
+ reg_write(CPU_AVS_CONTROL2_REG, cpu_avs);
+ DEBUG_WR_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
+ }
+
+ info = board_serdes_cfg_get(PEX_MODE_GET(satr11));
+ DEBUG_INIT_FULL_S("info->line0_7= 0x");
+ DEBUG_INIT_FULL_D(info->line0_7, 8);
+ DEBUG_INIT_FULL_S(" info->line8_15= 0x");
+ DEBUG_INIT_FULL_D(info->line8_15, 8);
+ DEBUG_INIT_FULL_S("\n");
+
+ if (info == NULL) {
+ DEBUG_INIT_S("Hight speed PHY Error #1\n");
+ return MV_ERROR;
+ }
+
+ if (config_module & ETM_MODULE_DETECT) { /* step 0.9 ETM */
+ DEBUG_INIT_FULL_S("ETM module detect Step 0.9:\n");
+ reg_write(SERDES_LINE_MUX_REG_0_7, 0x11111111);
+ DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x11111111);
+ info->pex_mode[1] = PEX_BUS_DISABLED; /* pex unit 1 is configure for ETM */
+ mdelay(100);
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF); /* SETM0 - G3 full swing AMP */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF); /* SETM0 - G3 full swing AMP */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF); /* SETM1 - G3 full swing AMP */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF); /* SETM1 - G3 full swing AMP */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800); /* SETM0 - 40 data bit width */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800); /* SETM0 - 40 data bit width */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800); /* SETM1 - 40 data bit width */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800); /* SETM1 - 40 data bit width */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400); /* lane3(serdes7) */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400); /* lane3(serdes7) */
+ }
+
+ /* STEP -1 [PEX-Only] First phase of PEX-PIPE Configuration: */
+ DEBUG_INIT_FULL_S("Step 1: First phase of PEX-PIPE Configuration\n");
+ for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+
+ /* 1. GLOB_CLK_CTRL Reset and Clock Control */
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
+
+ /* 2. GLOB_TEST_CTRL Test Mode Control */
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) {
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC2 << 16) | 0x200);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC2 << 16) | 0x200);
+ }
+
+ /* 3. GLOB_CLK_SRC_LO Clock Source Low */
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC3 << 16) | 0x0F);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC3 << 16) | 0x0F);
+ }
+
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC5 << 16) | 0x11F);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC5 << 16) | 0x11F);
+ }
+
+ /*
+ * 2 Configure the desire PIN_PHY_GEN and do power down to the PU_PLL,
+ * PU_RX,PU_TX. (bits[12:5])
+ */
+ DEBUG_INIT_FULL_S("Step 2: Configure the desire PIN_PHY_GEN\n");
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
+ continue;
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
+ continue;
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
+ switch (line_num) {
+ case 4:
+ case 6:
+ sata_port = 0;
+ break;
+ case 5:
+ sata_port = 1;
+ break;
+ default:
+ DEBUG_INIT_C
+ ("SATA port error for serdes line: ",
+ line_num, 2);
+ return MV_ERROR;
+ }
+ tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
+ DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+ tmp &= ~((0x1ff << 5) | 0x7);
+ tmp |= ((info->bus_speed & (1 << line_num)) != 0) ?
+ (0x11 << 5) : 0x0;
+
+ reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+ DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
+ /*
+ * 4) Configure the desire PIN_PHY_GEN and do power
+ * down to the PU_PLL,PU_RX,PU_TX. (bits[12:5])
+ */
+ tmp = reg_read(SGMII_SERDES_CFG_REG(0));
+ DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
+ tmp &= ~((0x1ff << 5) | 0x7);
+ tmp |= 0x660;
+ reg_write(SGMII_SERDES_CFG_REG(0), tmp);
+ DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
+ sgmii_port = 0;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
+ sgmii_port = 1;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
+ sgmii_port = 2;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
+ sgmii_port = 3;
+ else
+ continue;
+
+ tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
+ DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+ tmp &= ~((0x1ff << 5) | 0x7);
+ tmp |= (((info->bus_speed & (1 << line_num)) != 0) ?
+ (0x88 << 5) : (0x66 << 5));
+ reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+ DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+ }
+
+ /* Step 3 - QSGMII enable */
+ DEBUG_INIT_FULL_S("Step 3 QSGMII enable\n");
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
+ /* QSGMII Active bit set to true */
+ tmp = reg_read(QSGMII_CONTROL_1_REG);
+ DEBUG_RD_REG(QSGMII_CONTROL_1_REG, tmp);
+ tmp |= (1 << 30);
+#ifdef ERRATA_GL_6572255
+ tmp |= (1 << 27);
+#endif
+ reg_write(QSGMII_CONTROL_1_REG, tmp);
+ DEBUG_WR_REG(QSGMII_CONTROL_1_REG, tmp);
+ }
+ }
+
+ /* Step 4 - configure SERDES MUXes */
+ DEBUG_INIT_FULL_S("Step 4: Configure SERDES MUXes\n");
+ if (config_module & ETM_MODULE_DETECT) {
+ reg_write(SERDES_LINE_MUX_REG_0_7, 0x40041111);
+ DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x40041111);
+ } else {
+ reg_write(SERDES_LINE_MUX_REG_0_7, info->line0_7);
+ DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, info->line0_7);
+ }
+ reg_write(SERDES_LINE_MUX_REG_8_15, info->line8_15);
+ DEBUG_WR_REG(SERDES_LINE_MUX_REG_8_15, info->line8_15);
+
+ /* Step 5: Activate the RX High Impedance Mode */
+ DEBUG_INIT_FULL_S("Step 5: Activate the RX High Impedance Mode\n");
+ rx_high_imp_mode = 0x8080;
+ if (device_rev == 2) /* for B0 only */
+ rx_high_imp_mode |= 4;
+
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ /* for each serdes lane */
+ DEBUG_INIT_FULL_S("SERDES ");
+ DEBUG_INIT_FULL_D_10(line_num, 2);
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED]) {
+ DEBUG_INIT_FULL_S(" unconnected ***\n");
+ continue;
+ }
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
+ pex_unit = line_num >> 2;
+ pex_line_num = line_num % 4;
+ DEBUG_INIT_FULL_S(" - PEX unit ");
+ DEBUG_INIT_FULL_D_10(pex_unit, 1);
+ DEBUG_INIT_FULL_S(" line= ");
+ DEBUG_INIT_FULL_D_10(pex_line_num, 1);
+ DEBUG_INIT_FULL_S("\n");
+
+ /* Needed for PEX_PHY_ACCESS_REG macro */
+ if ((line_num > 7) &&
+ (info->pex_mode[3] == PEX_BUS_MODE_X8))
+ /* lines 8 - 15 are belong to PEX3 in x8 mode */
+ pex_unit = 3;
+
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+
+ /*
+ * 8) Activate the RX High Impedance Mode field
+ * (bit [2]) in register /PCIe_USB Control (Each MAC
+ * contain different Access to reach its
+ * Serdes-Regfile).
+ * [PEX-Only] Set bit[12]: The analog part latches idle
+ * if PU_TX = 1 and PU_PLL =1.
+ */
+
+ /* Termination enable */
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
+ in_direct = (0x48 << 16) | (pex_line_num << 24) |
+ 0x1000 | rx_high_imp_mode; /* x1 */
+ } else if ((info->pex_mode[pex_unit] ==
+ PEX_BUS_MODE_X4) && (pex_line_num == 0))
+ in_direct = (0x48 << 16) | (pex_line_num << 24) |
+ 0x1000 | (rx_high_imp_mode & 0xff); /* x4 */
+ else
+ in_direct = 0;
+
+ if (in_direct) {
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ in_direct);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ in_direct);
+ }
+
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
+ /*
+ * port 0 for serdes lines 4,6, and port 1 for
+ * serdes lines 5
+ */
+ sata_port = line_num & 1;
+ DEBUG_INIT_FULL_S(" - SATA port ");
+ DEBUG_INIT_FULL_D_10(sata_port, 2);
+ DEBUG_INIT_FULL_S("\n");
+ reg_write(SATA_COMPHY_CTRL_REG(sata_port),
+ rx_high_imp_mode);
+ DEBUG_WR_REG(SATA_COMPHY_CTRL_REG(sata_port),
+ rx_high_imp_mode);
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
+ DEBUG_INIT_FULL_S(" - QSGMII\n");
+ reg_write(SGMII_COMPHY_CTRL_REG(0), rx_high_imp_mode);
+ DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(0),
+ rx_high_imp_mode);
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
+ sgmii_port = 0;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
+ sgmii_port = 1;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
+ sgmii_port = 2;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
+ sgmii_port = 3;
+ else
+ continue;
+ DEBUG_INIT_FULL_S(" - SGMII port ");
+ DEBUG_INIT_FULL_D_10(sgmii_port, 2);
+ DEBUG_INIT_FULL_S("\n");
+ reg_write(SGMII_COMPHY_CTRL_REG(sgmii_port), rx_high_imp_mode);
+ DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(sgmii_port),
+ rx_high_imp_mode);
+ } /* for each serdes lane */
+
+ /* Step 6 [PEX-Only] PEX-Main configuration (X4 or X1): */
+ DEBUG_INIT_FULL_S("Step 6: [PEX-Only] PEX-Main configuration (X4 or X1)\n");
+ tmp = reg_read(SOC_CTRL_REG);
+ DEBUG_RD_REG(SOC_CTRL_REG, tmp);
+ tmp &= 0x200;
+ if (info->pex_mode[0] == PEX_BUS_MODE_X1)
+ tmp |= PCIE0_QUADX1_EN;
+ if (info->pex_mode[1] == PEX_BUS_MODE_X1)
+ tmp |= PCIE1_QUADX1_EN;
+ if (((reg_read(MPP_SAMPLE_AT_RESET(0)) & PEX_CLK_100MHZ_MASK) >>
+ PEX_CLK_100MHZ_OFFSET) == 0x1)
+ tmp |= (PCIE0_CLK_OUT_EN_MASK | PCIE1_CLK_OUT_EN_MASK);
+
+ reg_write(SOC_CTRL_REG, tmp);
+ DEBUG_WR_REG(SOC_CTRL_REG, tmp);
+
+ /* 6.2 PCI Express Link Capabilities */
+ DEBUG_INIT_FULL_S("Step 6.2: [PEX-Only] PCI Express Link Capabilities\n");
+
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ line_cfg = get_line_cfg(line_num, info);
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
+ /*
+ * PCI Express Control
+ * 0xX1A00 [0]:
+ * 0x0 X4-Link.
+ * 0x1 X1-Link
+ */
+ pex_unit = line_num >> 2;
+ pex_if = MV_SERDES_NUM_TO_PEX_NUM(line_num);
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+
+ /* set Common Clock Configuration */
+ tmp = reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
+ DEBUG_RD_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
+ tmp |= (1 << 6);
+ reg_write(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
+ DEBUG_WR_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
+
+ tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
+ DEBUG_RD_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
+ tmp &= ~(0x3FF);
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1)
+ tmp |= (0x1 << 4);
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
+ tmp |= (0x4 << 4);
+ if (0 == PEX_CAPABILITY_GET(satr11))
+ tmp |= 0x1;
+ else
+ tmp |= 0x2;
+ DEBUG_INIT_FULL_S("Step 6.2: PEX ");
+ DEBUG_INIT_FULL_D(pex_if, 1);
+ DEBUG_INIT_FULL_C(" set GEN", (tmp & 3), 1);
+ reg_write(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
+ DEBUG_WR_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
+
+ /*
+ * If pex is X4, no need to pass thru the other
+ * 3X1 serdes lines
+ */
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
+ line_num += 3;
+ }
+ }
+
+ /*
+ * Step 7 [PEX-X4 Only] To create PEX-Link that contain 4-lanes you
+ * need to config the register SOC_Misc/General Purpose2
+ * (Address= 182F8)
+ */
+ DEBUG_INIT_FULL_S("Step 7: [PEX-X4 Only] To create PEX-Link\n");
+ tmp = reg_read(GEN_PURP_RES_2_REG);
+ DEBUG_RD_REG(GEN_PURP_RES_2_REG, tmp);
+
+ tmp &= 0xFFFF0000;
+ if (info->pex_mode[0] == PEX_BUS_MODE_X4)
+ tmp |= 0x0000000F;
+
+ if (info->pex_mode[1] == PEX_BUS_MODE_X4)
+ tmp |= 0x000000F0;
+
+ if (info->pex_mode[2] == PEX_BUS_MODE_X4)
+ tmp |= 0x00000F00;
+
+ if (info->pex_mode[3] == PEX_BUS_MODE_X4)
+ tmp |= 0x0000F000;
+
+ reg_write(GEN_PURP_RES_2_REG, tmp);
+ DEBUG_WR_REG(GEN_PURP_RES_2_REG, tmp);
+
+ /* Steps 8 , 9 ,10 - use prepared REG addresses and values */
+ DEBUG_INIT_FULL_S("Steps 7,8,9,10 and 11\n");
+
+ /* Prepare PHY parameters for each step according to MUX selection */
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ /* for each serdes lane */
+
+ line_cfg = get_line_cfg(line_num, info);
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
+ continue;
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
+ pex_unit = line_num >> 2;
+ pex_line_num = line_num % 4;
+
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+ /*
+ * 8) Configure the desire PHY_MODE (bits [7:5])
+ * and REF_FREF_SEL (bits[4:0]) in the register Power
+ * and PLL Control (Each MAC contain different Access
+ * to reach its Serdes-Regfile).
+ */
+ if (((info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) &&
+ (0 == pex_line_num))
+ || ((info->pex_mode[pex_unit] == PEX_BUS_MODE_X1))) {
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x01 << 16) | (pex_line_num << 24) |
+ 0xFC60);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x01 << 16) | (pex_line_num << 24)
+ | 0xFC60);
+ /*
+ * Step 8.1: [PEX-Only] Configure Max PLL Rate
+ * (bit 8 in KVCO Calibration Control and
+ * bits[10:9] in
+ */
+ /* Use Maximum PLL Rate(Bit 8) */
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x02 << 16) | (1 << 31) |
+ (pex_line_num << 24)); /* read command */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x02 << 16) | (1 << 31) |
+ (pex_line_num << 24));
+ tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
+ DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+ tmp &= ~(1 << 31);
+ tmp |= (1 << 8);
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+
+ /* Use Maximum PLL Rate(Bits [10:9]) */
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x81 << 16) | (1 << 31) |
+ (pex_line_num << 24)); /* read command */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x81 << 16) | (1 << 31) |
+ (pex_line_num << 24));
+ tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
+ DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+ tmp &= ~(1 << 31);
+ tmp |= (3 << 9);
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+ }
+
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
+ /*
+ * Port 0 for serdes lines 4,6, and port 1 for serdes
+ * lines 5
+ */
+ sata_port = line_num & 1;
+
+ /*
+ * 8) Configure the desire PHY_MODE (bits [7:5]) and
+ * REF_FREF_SEL (bits[4:0]) in the register Power
+ * and PLL Control (Each MAC contain different Access
+ * to reach its Serdes-Regfile).
+ */
+ reg_write(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
+ DEBUG_WR_REG(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
+
+ /* 9) Configure the desire SEL_BITS */
+ reg_write(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
+ DEBUG_WR_REG(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
+
+ /* 10) Configure the desire REFCLK_SEL */
+
+ reg_write(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
+ DEBUG_WR_REG(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
+
+ /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
+ tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
+ DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+ tmp |= 7;
+ reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+ DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
+ /*
+ * 8) Configure the desire PHY_MODE (bits [7:5])
+ * and REF_FREF_SEL (bits[4:0]) in the register
+ */
+ reg_write(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
+ DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
+
+ /*
+ * 9) Configure the desire SEL_BITS (bits [11:0]
+ * in register
+ */
+ reg_write(SGMII_DIG_LP_ENA_REG(0), 0x400);
+ DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(0), 0x400);
+
+ /*
+ * 10) Configure the desire REFCLK_SEL (bit [10])
+ * in register
+ */
+ reg_write(SGMII_REF_CLK_SEL_REG(0), 0x400);
+ DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(0), 0x400);
+
+ /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
+ tmp = reg_read(SGMII_SERDES_CFG_REG(0));
+ DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
+ tmp |= 7;
+ reg_write(SGMII_SERDES_CFG_REG(0), tmp);
+ DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
+ sgmii_port = 0;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
+ sgmii_port = 1;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
+ sgmii_port = 2;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
+ sgmii_port = 3;
+ else
+ continue;
+
+ /*
+ * 8) Configure the desire PHY_MODE (bits [7:5]) and
+ * REF_FREF_SEL (bits[4:0]) in the register
+ */
+ reg_write(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
+ DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
+
+ /* 9) Configure the desire SEL_BITS (bits [11:0] in register */
+ reg_write(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
+ DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
+
+ /* 10) Configure the desire REFCLK_SEL (bit [10]) in register */
+ reg_write(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
+ DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
+
+ /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
+ tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
+ DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+ tmp |= 7;
+ reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+ DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+
+ } /* for each serdes lane */
+
+ /* Step 12 [PEX-Only] Last phase of PEX-PIPE Configuration */
+ DEBUG_INIT_FULL_S("Steps 12: [PEX-Only] Last phase of PEX-PIPE Configuration\n");
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ /* for each serdes lane */
+
+ line_cfg = get_line_cfg(line_num, info);
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
+ continue;
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
+ pex_unit = line_num >> 2;
+ pex_line_num = line_num % 4;
+ if (0 == pex_line_num) {
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC1 << 16) | 0x24);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC1 << 16) | 0x24);
+ }
+ }
+ }
+
+ /*--------------------------------------------------------------*/
+ /* Step 13: Wait 15ms before checking results */
+ DEBUG_INIT_FULL_S("Steps 13: Wait 15ms before checking results");
+ mdelay(15);
+ tmp = 20;
+ while (tmp) {
+ status = MV_OK;
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ u32 tmp;
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
+ continue;
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
+ continue;
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
+ /*
+ * Port 0 for serdes lines 4,6, and port 1
+ * for serdes lines 5
+ */
+ sata_port = line_num & 1;
+
+ tmp =
+ reg_read(SATA_LP_PHY_EXT_STAT_REG
+ (sata_port));
+ DEBUG_RD_REG(SATA_LP_PHY_EXT_STAT_REG
+ (sata_port), tmp);
+ if ((tmp & 0x7) != 0x7)
+ status = MV_ERROR;
+ continue;
+ }
+
+ if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
+ tmp = reg_read(SGMII_SERDES_STAT_REG(0));
+ DEBUG_RD_REG(SGMII_SERDES_STAT_REG(0), tmp);
+ if ((tmp & 0x7) != 0x7)
+ status = MV_ERROR;
+ continue;
+ }
+
+ if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_SGMII0])
+ sgmii_port = 0;
+ else if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_SGMII1])
+ sgmii_port = 1;
+ else if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_SGMII2])
+ sgmii_port = 2;
+ else if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_SGMII3])
+ sgmii_port = 3;
+ else
+ continue;
+
+ tmp = reg_read(SGMII_SERDES_STAT_REG(sgmii_port));
+ DEBUG_RD_REG(SGMII_SERDES_STAT_REG(sgmii_port), tmp);
+ if ((tmp & 0x7) != 0x7)
+ status = MV_ERROR;
+ }
+
+ if (status == MV_OK)
+ break;
+ mdelay(5);
+ tmp--;
+ }
+
+ /*
+ * Step14 [PEX-Only] In order to configure RC/EP mode please write
+ * to register 0x0060 bits
+ */
+ DEBUG_INIT_FULL_S("Steps 14: [PEX-Only] In order to configure\n");
+ for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+ tmp =
+ reg_read(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)));
+ DEBUG_RD_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
+ tmp);
+ tmp &= ~(0xf << 20);
+ if (info->pex_type == MV_PEX_ROOT_COMPLEX)
+ tmp |= (0x4 << 20);
+ else
+ tmp |= (0x1 << 20);
+ reg_write(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
+ tmp);
+ DEBUG_WR_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
+ tmp);
+ }
+
+ /*
+ * Step 15 [PEX-Only] Only for EP mode set to Zero bits 19 and 16 of
+ * register 0x1a60
+ */
+ DEBUG_INIT_FULL_S("Steps 15: [PEX-Only] In order to configure\n");
+ for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+ if (info->pex_type == MV_PEX_END_POINT) {
+ tmp =
+ reg_read(PEX_DBG_CTRL_REG
+ (MV_PEX_UNIT_TO_IF(pex_unit)));
+ DEBUG_RD_REG(PEX_DBG_CTRL_REG
+ (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
+ tmp &= 0xfff6ffff;
+ reg_write(PEX_DBG_CTRL_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
+ tmp);
+ DEBUG_WR_REG(PEX_DBG_CTRL_REG
+ (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
+ }
+ }
+
+ if (info->serdes_m_phy_change) {
+ MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
+ u32 bus_speed;
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
+ continue;
+ serdes_m_phy_change = info->serdes_m_phy_change;
+ bus_speed = info->bus_speed & (1 << line_num);
+ while (serdes_m_phy_change->type !=
+ SERDES_UNIT_UNCONNECTED) {
+ switch (serdes_m_phy_change->type) {
+ case SERDES_UNIT_PEX:
+ if (line_cfg != SERDES_UNIT_PEX)
+ break;
+ pex_unit = line_num >> 2;
+ pex_line_num = line_num % 4;
+ if (info->pex_mode[pex_unit] ==
+ PEX_BUS_DISABLED)
+ break;
+ if ((info->pex_mode[pex_unit] ==
+ PEX_BUS_MODE_X4) && pex_line_num)
+ break;
+
+ if (bus_speed) {
+ reg_write(PEX_PHY_ACCESS_REG
+ (pex_unit),
+ (pex_line_num << 24) |
+ serdes_m_phy_change->val_hi_speed);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG
+ (pex_unit),
+ (pex_line_num <<
+ 24) |
+ serdes_m_phy_change->val_hi_speed);
+ } else {
+ reg_write(PEX_PHY_ACCESS_REG
+ (pex_unit),
+ (pex_line_num << 24) |
+ serdes_m_phy_change->val_low_speed);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG
+ (pex_unit),
+ (pex_line_num <<
+ 24) |
+ serdes_m_phy_change->val_low_speed);
+ }
+ break;
+ case SERDES_UNIT_SATA:
+ if (line_cfg != SERDES_UNIT_SATA)
+ break;
+ /*
+ * Port 0 for serdes lines 4,6, and
+ * port 1 for serdes lines 5
+ */
+ sata_port = line_num & 1;
+ if (bus_speed) {
+ reg_write(SATA_BASE_REG
+ (sata_port) |
+ serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ DEBUG_WR_REG(SATA_BASE_REG
+ (sata_port) |
+ serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ } else {
+ reg_write(SATA_BASE_REG
+ (sata_port) |
+ serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ DEBUG_WR_REG(SATA_BASE_REG
+ (sata_port) |
+ serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ }
+ break;
+ case SERDES_UNIT_SGMII0:
+ case SERDES_UNIT_SGMII1:
+ case SERDES_UNIT_SGMII2:
+ case SERDES_UNIT_SGMII3:
+ if (line_cfg == serdes_cfg[line_num]
+ [SERDES_UNIT_SGMII0])
+ sgmii_port = 0;
+ else if (line_cfg ==
+ serdes_cfg[line_num]
+ [SERDES_UNIT_SGMII1])
+ sgmii_port = 1;
+ else if (line_cfg ==
+ serdes_cfg[line_num]
+ [SERDES_UNIT_SGMII2])
+ sgmii_port = 2;
+ else if (line_cfg ==
+ serdes_cfg[line_num]
+ [SERDES_UNIT_SGMII3])
+ sgmii_port = 3;
+ else
+ break;
+ if (bus_speed) {
+ reg_write(MV_ETH_REGS_BASE
+ (sgmii_port) |
+ serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ DEBUG_WR_REG(MV_ETH_REGS_BASE
+ (sgmii_port) |
+ serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ } else {
+ reg_write(MV_ETH_REGS_BASE
+ (sgmii_port) |
+ serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ DEBUG_WR_REG(MV_ETH_REGS_BASE
+ (sgmii_port) |
+ serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ }
+ break;
+ case SERDES_UNIT_QSGMII:
+ if (line_cfg != SERDES_UNIT_QSGMII)
+ break;
+ if (bus_speed) {
+ reg_write
+ (serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ DEBUG_WR_REG
+ (serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ } else {
+ reg_write
+ (serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ DEBUG_WR_REG
+ (serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ }
+ break;
+ default:
+ break;
+ }
+ serdes_m_phy_change++;
+ }
+ }
+ }
+
+ /* Step 16 [PEX-Only] Training Enable */
+ DEBUG_INIT_FULL_S("Steps 16: [PEX-Only] Training Enable");
+ tmp = reg_read(SOC_CTRL_REG);
+ DEBUG_RD_REG(SOC_CTRL_REG, tmp);
+ tmp &= ~(0x0F);
+ for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
+ reg_write(PEX_CAUSE_REG(pex_unit), 0);
+ DEBUG_WR_REG(PEX_CAUSE_REG(pex_unit), 0);
+ if (info->pex_mode[pex_unit] != PEX_BUS_DISABLED)
+ tmp |= (0x1 << pex_unit);
+ }
+ reg_write(SOC_CTRL_REG, tmp);
+ DEBUG_WR_REG(SOC_CTRL_REG, tmp);
+
+ /* Step 17: Speed change to target speed and width */
+ {
+ u32 tmp_reg, tmp_pex_reg;
+ u32 addr;
+ u32 first_busno, next_busno;
+ u32 max_link_width = 0;
+ u32 neg_link_width = 0;
+ pex_if_num = pex_max_if_get();
+ mdelay(150);
+ DEBUG_INIT_FULL_C("step 17: max_if= 0x", pex_if_num, 1);
+ next_busno = 0;
+ for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
+ line_num = (pex_if <= 8) ? pex_if : 12;
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg != serdes_cfg[line_num][SERDES_UNIT_PEX])
+ continue;
+ pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
+ DEBUG_INIT_FULL_S("step 17: PEX");
+ DEBUG_INIT_FULL_D(pex_if, 1);
+ DEBUG_INIT_FULL_C(" pex_unit= ", pex_unit, 1);
+
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
+ DEBUG_INIT_FULL_C("PEX disabled interface ",
+ pex_if, 1);
+ if (pex_if < 8)
+ pex_if += 3;
+ continue;
+ }
+ first_busno = next_busno;
+ if ((info->pex_type == MV_PEX_END_POINT) &&
+ (0 == pex_if)) {
+ if ((pex_if < 8) && (info->pex_mode[pex_unit] ==
+ PEX_BUS_MODE_X4))
+ pex_if += 3;
+ continue;
+ }
+
+ tmp = reg_read(PEX_DBG_STATUS_REG(pex_if));
+ DEBUG_RD_REG(PEX_DBG_STATUS_REG(pex_if), tmp);
+ if ((tmp & 0x7f) == 0x7e) {
+ next_busno++;
+ tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
+ max_link_width = tmp;
+ DEBUG_RD_REG((PEX_LINK_CAPABILITIES_REG
+ (pex_if)), tmp);
+ max_link_width = ((max_link_width >> 4) & 0x3F);
+ neg_link_width =
+ reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
+ DEBUG_RD_REG((PEX_LINK_CTRL_STATUS_REG(pex_if)),
+ neg_link_width);
+ neg_link_width = ((neg_link_width >> 20) & 0x3F);
+ if (max_link_width > neg_link_width) {
+ tmp &= ~(0x3F << 4);
+ tmp |= (neg_link_width << 4);
+ reg_write(PEX_LINK_CAPABILITIES_REG
+ (pex_if), tmp);
+ DEBUG_WR_REG((PEX_LINK_CAPABILITIES_REG
+ (pex_if)), tmp);
+ mdelay(1); /* wait 1ms before reading capability for speed */
+ DEBUG_INIT_S("PEX");
+ DEBUG_INIT_D(pex_if, 1);
+ DEBUG_INIT_C(": change width to X",
+ neg_link_width, 1);
+ }
+ tmp_pex_reg =
+ reg_read((PEX_CFG_DIRECT_ACCESS
+ (pex_if,
+ PEX_LINK_CAPABILITY_REG)));
+ DEBUG_RD_REG((PEX_CFG_DIRECT_ACCESS
+ (pex_if,
+ PEX_LINK_CAPABILITY_REG)),
+ tmp_pex_reg);
+ tmp_pex_reg &= (0xF);
+ if (tmp_pex_reg == 0x2) {
+ tmp_reg =
+ (reg_read
+ (PEX_CFG_DIRECT_ACCESS
+ (pex_if,
+ PEX_LINK_CTRL_STAT_REG)) &
+ 0xF0000) >> 16;
+ DEBUG_RD_REG(PEX_CFG_DIRECT_ACCESS
+ (pex_if,
+ PEX_LINK_CTRL_STAT_REG),
+ tmp_pex_reg);
+ /* check if the link established is GEN1 */
+ if (tmp_reg == 0x1) {
+ pex_local_bus_num_set(pex_if,
+ first_busno);
+ pex_local_dev_num_set(pex_if,
+ 1);
+
+ DEBUG_INIT_FULL_S("** Link is Gen1, check the EP capability\n");
+ /* link is Gen1, check the EP capability */
+ addr =
+ pex_cfg_read(pex_if,
+ first_busno, 0,
+ 0,
+ 0x34) & 0xFF;
+ DEBUG_INIT_FULL_C("pex_cfg_read: return addr=0x%x",
+ addr, 4);
+ if (addr == 0xff) {
+ DEBUG_INIT_FULL_C("pex_cfg_read: return 0xff -->PEX (%d): Detected No Link.",
+ pex_if, 1);
+ continue;
+ }
+ while ((pex_cfg_read
+ (pex_if, first_busno, 0,
+ 0,
+ addr) & 0xFF) !=
+ 0x10) {
+ addr =
+ (pex_cfg_read
+ (pex_if,
+ first_busno, 0, 0,
+ addr) & 0xFF00) >>
+ 8;
+ }
+ if ((pex_cfg_read
+ (pex_if, first_busno, 0, 0,
+ addr + 0xC) & 0xF) >=
+ 0x2) {
+ tmp =
+ reg_read
+ (PEX_LINK_CTRL_STATUS2_REG
+ (pex_if));
+ DEBUG_RD_REG
+ (PEX_LINK_CTRL_STATUS2_REG
+ (pex_if), tmp);
+ tmp &= ~(0x1 | 1 << 1);
+ tmp |= (1 << 1);
+ reg_write
+ (PEX_LINK_CTRL_STATUS2_REG
+ (pex_if), tmp);
+ DEBUG_WR_REG
+ (PEX_LINK_CTRL_STATUS2_REG
+ (pex_if), tmp);
+
+ tmp =
+ reg_read
+ (PEX_CTRL_REG
+ (pex_if));
+ DEBUG_RD_REG
+ (PEX_CTRL_REG
+ (pex_if), tmp);
+ tmp |= (1 << 10);
+ reg_write(PEX_CTRL_REG
+ (pex_if),
+ tmp);
+ DEBUG_WR_REG
+ (PEX_CTRL_REG
+ (pex_if), tmp);
+ mdelay(10); /* We need to wait 10ms before reading the PEX_DBG_STATUS_REG in order not to read the status of the former state */
+ DEBUG_INIT_FULL_S
+ ("Gen2 client!\n");
+ } else {
+ DEBUG_INIT_FULL_S
+ ("GEN1 client!\n");
+ }
+ }
+ }
+ } else {
+ DEBUG_INIT_FULL_S("PEX");
+ DEBUG_INIT_FULL_D(pex_if, 1);
+ DEBUG_INIT_FULL_S(" : Detected No Link. Status Reg(0x");
+ DEBUG_INIT_FULL_D(PEX_DBG_STATUS_REG(pex_if),
+ 8);
+ DEBUG_INIT_FULL_C(") = 0x", tmp, 8);
+ }
+
+ if ((pex_if < 8) &&
+ (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
+ pex_if += 3;
+ }
+ }
+
+ /* Step 18: update pex DEVICE ID */
+ {
+ u32 devId;
+ pex_if_num = pex_max_if_get();
+ ctrl_mode = ctrl_model_get();
+ for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
+ pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
+ if ((pex_if < 8) &&
+ (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
+ pex_if += 3;
+ continue;
+ }
+
+ devId = reg_read(PEX_CFG_DIRECT_ACCESS(
+ pex_if, PEX_DEVICE_AND_VENDOR_ID));
+ devId &= 0xFFFF;
+ devId |= ((ctrl_mode << 16) & 0xffff0000);
+ DEBUG_INIT_S("Update Device ID PEX");
+ DEBUG_INIT_D(pex_if, 1);
+ DEBUG_INIT_D(devId, 8);
+ DEBUG_INIT_S("\n");
+ reg_write(PEX_CFG_DIRECT_ACCESS
+ (pex_if, PEX_DEVICE_AND_VENDOR_ID), devId);
+ if ((pex_if < 8) &&
+ (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
+ pex_if += 3;
+ }
+ DEBUG_INIT_S("Update PEX Device ID 0x");
+ DEBUG_INIT_D(ctrl_mode, 4);
+ DEBUG_INIT_S("0\n");
+ }
+ tmp = reg_read(PEX_DBG_STATUS_REG(0));
+ DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp);
+
+ DEBUG_INIT_S(ENDED_OK);
+ return MV_OK;
+}
+
+/* PEX configuration space read write */
+
+/*
+ * pex_cfg_read - Read from configuration space
+ *
+ * DESCRIPTION:
+ * This function performs a 32 bit read from PEX configuration space.
+ * It supports both type 0 and type 1 of Configuration Transactions
+ * (local and over bridge). In order to read from local bus segment, use
+ * bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers
+ * will result configuration transaction of type 1 (over bridge).
+ *
+ * INPUT:
+ * pex_if - PEX interface number.
+ * bus - PEX segment bus number.
+ * dev - PEX device number.
+ * func - Function number.
+ * offss - Register offset.
+ *
+ * OUTPUT:
+ * None.
+ *
+ * RETURN:
+ * 32bit register data, 0xffffffff on error
+ *
+ */
+u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs)
+{
+ u32 pex_data = 0;
+ u32 local_dev, local_bus;
+ u32 val;
+
+ if (pex_if >= MV_PEX_MAX_IF)
+ return 0xFFFFFFFF;
+
+ if (dev >= MAX_PEX_DEVICES) {
+ DEBUG_INIT_C("pex_cfg_read: ERR. device number illigal ", dev,
+ 1);
+ return 0xFFFFFFFF;
+ }
+
+ if (func >= MAX_PEX_FUNCS) {
+ DEBUG_INIT_C("pex_cfg_read: ERR. function num illigal ", func,
+ 1);
+ return 0xFFFFFFFF;
+ }
+
+ if (bus >= MAX_PEX_BUSSES) {
+ DEBUG_INIT_C("pex_cfg_read: ERR. bus number illigal ", bus, 1);
+ return MV_ERROR;
+ }
+ val = reg_read(PEX_STATUS_REG(pex_if));
+
+ local_dev =
+ ((val & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS);
+ local_bus =
+ ((val & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS);
+
+ /* Speed up the process. In case on no link, return MV_ERROR */
+ if ((dev != local_dev) || (bus != local_bus)) {
+ pex_data = reg_read(PEX_STATUS_REG(pex_if));
+
+ if ((pex_data & PXSR_DL_DOWN))
+ return MV_ERROR;
+ }
+
+ /*
+ * In PCI Express we have only one device number
+ * and this number is the first number we encounter else that the
+ * local_dev spec pex define return on config read/write on any device
+ */
+ if (bus == local_bus) {
+ if (local_dev == 0) {
+ /*
+ * If local dev is 0 then the first number we encounter
+ * after 0 is 1
+ */
+ if ((dev != 1) && (dev != local_dev))
+ return MV_ERROR;
+ } else {
+ /*
+ * If local dev is not 0 then the first number we
+ * encounter is 0
+ */
+ if ((dev != 0) && (dev != local_dev))
+ return MV_ERROR;
+ }
+ }
+
+ /* Creating PEX address to be passed */
+ pex_data = (bus << PXCAR_BUS_NUM_OFFS);
+ pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS);
+ pex_data |= (func << PXCAR_FUNC_NUM_OFFS);
+ pex_data |= (offs & PXCAR_REG_NUM_MASK); /* lgacy register space */
+ /* extended register space */
+ pex_data |= (((offs & PXCAR_REAL_EXT_REG_NUM_MASK) >>
+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
+
+ pex_data |= PXCAR_CONFIG_EN;
+
+ /* Write the address to the PEX configuration address register */
+ reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data);
+
+ /*
+ * In order to let the PEX controller absorbed the address of the read
+ * transaction we perform a validity check that the address was written
+ */
+ if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if)))
+ return MV_ERROR;
+
+ /* cleaning Master Abort */
+ reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND),
+ PXSAC_MABORT);
+ /* Read the Data returned in the PEX Data register */
+ pex_data = reg_read(PEX_CFG_DATA_REG(pex_if));
+
+ DEBUG_INIT_FULL_C(" --> ", pex_data, 4);
+
+ return pex_data;
+}
+
+/*
+ * pex_local_bus_num_set - Set PEX interface local bus number.
+ *
+ * DESCRIPTION:
+ * This function sets given PEX interface its local bus number.
+ * Note: In case the PEX interface is PEX-X, the information is read-only.
+ *
+ * INPUT:
+ * pex_if - PEX interface number.
+ * bus_num - Bus number.
+ *
+ * OUTPUT:
+ * None.
+ *
+ * RETURN:
+ * MV_NOT_ALLOWED in case PEX interface is PEX-X.
+ * MV_BAD_PARAM on bad parameters ,
+ * otherwise MV_OK
+ *
+ */
+int pex_local_bus_num_set(u32 pex_if, u32 bus_num)
+{
+ u32 val;
+
+ if (bus_num >= MAX_PEX_BUSSES) {
+ DEBUG_INIT_C("pex_local_bus_num_set: ERR. bus number illigal %d\n",
+ bus_num, 4);
+ return MV_ERROR;
+ }
+
+ val = reg_read(PEX_STATUS_REG(pex_if));
+ val &= ~PXSR_PEX_BUS_NUM_MASK;
+ val |= (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
+ reg_write(PEX_STATUS_REG(pex_if), val);
+
+ return MV_OK;
+}
+
+/*
+ * pex_local_dev_num_set - Set PEX interface local device number.
+ *
+ * DESCRIPTION:
+ * This function sets given PEX interface its local device number.
+ * Note: In case the PEX interface is PEX-X, the information is read-only.
+ *
+ * INPUT:
+ * pex_if - PEX interface number.
+ * dev_num - Device number.
+ *
+ * OUTPUT:
+ * None.
+ *
+ * RETURN:
+ * MV_NOT_ALLOWED in case PEX interface is PEX-X.
+ * MV_BAD_PARAM on bad parameters ,
+ * otherwise MV_OK
+ *
+ */
+int pex_local_dev_num_set(u32 pex_if, u32 dev_num)
+{
+ u32 val;
+
+ if (pex_if >= MV_PEX_MAX_IF)
+ return MV_BAD_PARAM;
+
+ val = reg_read(PEX_STATUS_REG(pex_if));
+ val &= ~PXSR_PEX_DEV_NUM_MASK;
+ val |= (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
+ reg_write(PEX_STATUS_REG(pex_if), val);
+
+ return MV_OK;
+}
diff --git a/arch/arm/mvebu-common/serdes/high_speed_env_spec.c b/arch/arm/mvebu-common/serdes/high_speed_env_spec.c
new file mode 100644
index 0000000..115ec2c
--- /dev/null
+++ b/arch/arm/mvebu-common/serdes/high_speed_env_spec.c
@@ -0,0 +1,185 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "high_speed_env_spec.h"
+
+MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[] = {
+ /* SERDES TYPE, Low REG OFFS, Low REG VALUE, Hi REG OFS, Hi REG VALUE */
+ {
+ /* PEX: Change of Slew Rate port0 */
+ SERDES_UNIT_PEX, 0x0,
+ (0x0F << 16) | 0x2a21, 0x0, (0x0F << 16) | 0x2a21
+ }, {
+ /* PEX: Change PLL BW port0 */
+ SERDES_UNIT_PEX, 0x0,
+ (0x4F << 16) | 0x6219, 0x0, (0x4F << 16) | 0x6219
+ }, {
+ /* SATA: Slew rate change port 0 */
+ SERDES_UNIT_SATA, 0x0083C, 0x8a31, 0x0083C, 0x8a31
+ }, {
+ /* SATA: Slew rate change port 0 */
+ SERDES_UNIT_SATA, 0x00834, 0xc928, 0x00834, 0xc928
+ }, {
+ /* SATA: Slew rate change port 0 */
+ SERDES_UNIT_SATA, 0x00838, 0x30f0, 0x00838, 0x30f0
+ }, {
+ /* SATA: Slew rate change port 0 */
+ SERDES_UNIT_SATA, 0x00840, 0x30f5, 0x00840, 0x30f5
+ }, {
+ /* SGMII: FFE setting Port0 */
+ SERDES_UNIT_SGMII0, 0x00E18, 0x989F, 0x00E18, 0x989F
+ }, {
+ /* SGMII: SELMUP and SELMUF Port0 */
+ SERDES_UNIT_SGMII0, 0x00E38, 0x10FA, 0x00E38, 0x10FA
+ }, {
+ /* SGMII: Amplitude new setting gen2 Port3 */
+ SERDES_UNIT_SGMII0, 0x00E34, 0xC968, 0x00E34, 0xC66C
+ }, {
+ /* QSGMII: Amplitude and slew rate change */
+ SERDES_UNIT_QSGMII, 0x72E34, 0xaa58, 0x72E34, 0xaa58
+ }, {
+ /* QSGMII: SELMUP and SELMUF */
+ SERDES_UNIT_QSGMII, 0x72e38, 0x10aF, 0x72e38, 0x10aF
+ }, {
+ /* QSGMII: 0x72e18 */
+ SERDES_UNIT_QSGMII, 0x72e18, 0x98AC, 0x72e18, 0x98AC
+ }, {
+ /* Null terminated */
+ SERDES_UNIT_UNCONNECTED, 0, 0
+ }
+};
+
+MV_BIN_SERDES_CFG db88f78xx0_serdes_cfg[] = {
+ /* Z1B */
+ {MV_PEX_ROOT_COMPLEX, 0x32221111, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Default */
+ {MV_PEX_ROOT_COMPLEX, 0x31211111, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* PEX module */
+ /* Z1A */
+ {MV_PEX_ROOT_COMPLEX, 0x32220000, 0x00000000,
+ {PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED,
+ PEX_BUS_DISABLED}, 0x0030, serdes_change_m_phy}, /* Default - Z1A */
+ {MV_PEX_ROOT_COMPLEX, 0x31210000, 0x00000000,
+ {PEX_BUS_DISABLED, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0030, serdes_change_m_phy} /* PEX module - Z1A */
+};
+
+MV_BIN_SERDES_CFG db88f78xx0rev2_serdes_cfg[] = {
+ /* A0 */
+ {MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Default: No Pex module, PEX0 x1, disabled */
+ {MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x1 */
+ {MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* no Pex module, PEX0 x4, PEX1 disabled */
+ {MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111,
+ {PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x1 */
+ {MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x4 */
+ {MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111,
+ {PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x4 */
+};
+
+MV_BIN_SERDES_CFG rd78460nas_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Default */
+ {MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x00f4, serdes_change_m_phy}, /* Switch module */
+};
+
+MV_BIN_SERDES_CFG rd78460_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x22321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy}, /* CPU0 */
+ {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy} /* CPU1-3 */
+};
+
+MV_BIN_SERDES_CFG rd78460server_rev2_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy}, /* CPU0 */
+ {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy} /* CPU1-3 */
+};
+
+MV_BIN_SERDES_CFG db78X60pcac_serdes_cfg[] = {
+ {MV_PEX_END_POINT, 0x22321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy} /* Default */
+};
+
+MV_BIN_SERDES_CFG db78X60pcacrev2_serdes_cfg[] = {
+ {MV_PEX_END_POINT, 0x23321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy} /* Default */
+};
+
+MV_BIN_SERDES_CFG fpga88f78xx0_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x00000000, 0x00000000,
+ {PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0000, serdes_change_m_phy} /* No PEX in FPGA */
+};
+
+MV_BIN_SERDES_CFG db78X60amc_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x33111111, 0x00010001,
+ {PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1},
+ 0x0030, serdes_change_m_phy} /* Default */
+};
+
+/*
+ * ARMADA-XP CUSTOMER BOARD
+ */
+MV_BIN_SERDES_CFG rd78460customer_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x00000030, serdes_change_m_phy}, /* Default */
+ {MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x00000030, serdes_change_m_phy}, /* Switch module */
+};
+
+MV_BIN_SERDES_CFG rd78460AXP_GP_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy} /* Default */
+};
+
+MV_BIN_SERDES_CFG *serdes_info_tbl[] = {
+ db88f78xx0_serdes_cfg,
+ rd78460_serdes_cfg,
+ db78X60pcac_serdes_cfg,
+ fpga88f78xx0_serdes_cfg,
+ db88f78xx0rev2_serdes_cfg,
+ rd78460nas_serdes_cfg,
+ db78X60amc_serdes_cfg,
+ db78X60pcacrev2_serdes_cfg,
+ rd78460server_rev2_serdes_cfg,
+ rd78460AXP_GP_serdes_cfg,
+ rd78460customer_serdes_cfg
+};
+
+u8 rd78460gp_twsi_dev[] = { 0x4C, 0x4D, 0x4E };
+u8 db88f78xx0rev2_twsi_dev[] = { 0x4C, 0x4D, 0x4E, 0x4F };
diff --git a/arch/arm/mvebu-common/serdes/high_speed_env_spec.h b/arch/arm/mvebu-common/serdes/high_speed_env_spec.h
new file mode 100644
index 0000000..e5aa1b0
--- /dev/null
+++ b/arch/arm/mvebu-common/serdes/high_speed_env_spec.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __HIGHSPEED_ENV_SPEC_H
+#define __HIGHSPEED_ENV_SPEC_H
+
+#include "../../../drivers/ddr/mvebu/ddr3_hw_training.h"
+
+typedef enum {
+ SERDES_UNIT_UNCONNECTED = 0x0,
+ SERDES_UNIT_PEX = 0x1,
+ SERDES_UNIT_SATA = 0x2,
+ SERDES_UNIT_SGMII0 = 0x3,
+ SERDES_UNIT_SGMII1 = 0x4,
+ SERDES_UNIT_SGMII2 = 0x5,
+ SERDES_UNIT_SGMII3 = 0x6,
+ SERDES_UNIT_QSGMII = 0x7,
+ SERDES_UNIT_SETM = 0x8,
+ SERDES_LAST_UNIT
+} MV_BIN_SERDES_UNIT_INDX;
+
+
+typedef enum {
+ PEX_BUS_DISABLED = 0,
+ PEX_BUS_MODE_X1 = 1,
+ PEX_BUS_MODE_X4 = 2,
+ PEX_BUS_MODE_X8 = 3
+} MV_PEX_UNIT_CFG;
+
+typedef enum pex_type {
+ MV_PEX_ROOT_COMPLEX, /* root complex device */
+ MV_PEX_END_POINT /* end point device */
+} MV_PEX_TYPE;
+
+typedef struct serdes_change_m_phy {
+ MV_BIN_SERDES_UNIT_INDX type;
+ u32 reg_low_speed;
+ u32 val_low_speed;
+ u32 reg_hi_speed;
+ u32 val_hi_speed;
+} MV_SERDES_CHANGE_M_PHY;
+
+/*
+ * Configuration per SERDES line. Each nibble is MV_SERDES_LINE_TYPE
+ */
+typedef struct board_serdes_conf {
+ MV_PEX_TYPE pex_type; /* MV_PEX_ROOT_COMPLEX MV_PEX_END_POINT */
+ u32 line0_7; /* Lines 0 to 7 SERDES MUX one nibble per line */
+ u32 line8_15; /* Lines 8 to 15 SERDES MUX one nibble per line */
+ MV_PEX_UNIT_CFG pex_mode[4];
+
+ /*
+ * Bus speed - one bit per SERDES line:
+ * Low speed (0) High speed (1)
+ * PEX 2.5 G (10 bit) 5 G (20 bit)
+ * SATA 1.5 G 3 G
+ * SGMII 1.25 Gbps 3.125 Gbps
+ */
+ u32 bus_speed;
+
+ MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
+} MV_BIN_SERDES_CFG;
+
+
+#define BIN_SERDES_CFG { \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
+ {0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
+ {0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
+ {0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
+ {0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
+ {0, 1, 2 , 4, -1, 3, -1, -1, -1}, /* Lane 6 */ \
+ {0, 1, -1 , 2, -1, -1, 3, -1, 4}, /* Lane 7*/ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 8 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 9 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 10 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 11 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 12 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 13 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 14 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 15 */ \
+}
+
+#endif /* __HIGHSPEED_ENV_SPEC_H */
diff --git a/arch/arm/mvebu-common/u-boot-spl.lds b/arch/arm/mvebu-common/u-boot-spl.lds
new file mode 100644
index 0000000..eee1db4
--- /dev/null
+++ b/arch/arm/mvebu-common/u-boot-spl.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ arch/arm/cpu/armv7/start.o (.text*)
+ *(.text*)
+ *(.vectors)
+ } >.sram
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*_i2c_*)));
+ } >.sram
+
+ . = ALIGN(4);
+ __image_copy_end = .;
+
+ .end :
+ {
+ *(.__end)
+ }
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } >.sdram
+}
diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk
index 469185e..8252f59 100644
--- a/arch/avr32/config.mk
+++ b/arch/avr32/config.mk
@@ -9,6 +9,9 @@ ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := avr32-linux-
endif
+# avr32 has generic board support
+__HAVE_ARCH_GENERIC_BOARD := y
+
CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000
PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax
diff --git a/arch/avr32/cpu/Makefile b/arch/avr32/cpu/Makefile
index 00cede3..e111db3 100644
--- a/arch/avr32/cpu/Makefile
+++ b/arch/avr32/cpu/Makefile
@@ -16,5 +16,6 @@ obj-y += cache.o
obj-y += interrupts.o
obj-$(CONFIG_PORTMUX_PIO) += portmux-pio.o
obj-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o
+obj-y += mmc.o
obj-$(if $(filter at32ap700x,$(SOC)),y) += at32ap700x/
diff --git a/arch/avr32/cpu/at32ap700x/mmu.c b/arch/avr32/cpu/at32ap700x/mmu.c
index 0e28b21..f5e62f2 100644
--- a/arch/avr32/cpu/at32ap700x/mmu.c
+++ b/arch/avr32/cpu/at32ap700x/mmu.c
@@ -7,7 +7,7 @@ void mmu_init_r(unsigned long dest_addr)
uintptr_t vmr_table_addr;
/* Round monitor address down to the nearest page boundary */
- dest_addr &= PAGE_ADDR_MASK;
+ dest_addr &= MMU_PAGE_ADDR_MASK;
/* Initialize TLB entry 0 to cover the monitor, and lock it */
sysreg_write(TLBEHI, dest_addr | SYSREG_BIT(TLBEHI_V));
@@ -36,7 +36,7 @@ int mmu_handle_tlb_miss(void)
unsigned int fault_pgno;
int first, last;
- fault_pgno = sysreg_read(TLBEAR) >> PAGE_SHIFT;
+ fault_pgno = sysreg_read(TLBEAR) >> MMU_PAGE_SHIFT;
vmr_table = (const struct mmu_vm_range *)sysreg_read(PTBR);
/* Do a binary search through the VM ranges */
@@ -60,8 +60,8 @@ int mmu_handle_tlb_miss(void)
/* Got it; let's slam it into the TLB */
uint32_t tlbelo;
- tlbelo = vmr->phys & ~PAGE_ADDR_MASK;
- tlbelo |= fault_pgno << PAGE_SHIFT;
+ tlbelo = vmr->phys & ~MMU_PAGE_ADDR_MASK;
+ tlbelo |= fault_pgno << MMU_PAGE_SHIFT;
sysreg_write(TLBELO, tlbelo);
__builtin_tlbw();
diff --git a/arch/avr32/cpu/cpu.c b/arch/avr32/cpu/cpu.c
index cef630e..cd226a6 100644
--- a/arch/avr32/cpu/cpu.c
+++ b/arch/avr32/cpu/cpu.c
@@ -27,7 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int cpu_init(void)
+int arch_cpu_init(void)
{
extern void _evba(void);
diff --git a/arch/avr32/cpu/exception.c b/arch/avr32/cpu/exception.c
index 5d1bc68..d6991f6 100644
--- a/arch/avr32/cpu/exception.c
+++ b/arch/avr32/cpu/exception.c
@@ -96,11 +96,11 @@ void do_unknown_exception(unsigned int ecr, struct pt_regs *regs)
printf("CPU Mode: %s\n", cpu_modes[mode]);
/* Avoid exception loops */
- if (regs->sp < (gd->arch.stack_end - CONFIG_STACKSIZE)
- || regs->sp >= gd->arch.stack_end)
+ if (regs->sp < (gd->start_addr_sp - CONFIG_STACKSIZE) ||
+ regs->sp >= gd->start_addr_sp)
printf("\nStack pointer seems bogus, won't do stack dump\n");
else
- dump_mem("\nStack: ", regs->sp, gd->arch.stack_end);
+ dump_mem("\nStack: ", regs->sp, gd->start_addr_sp);
panic("Unhandled exception\n");
}
diff --git a/arch/avr32/cpu/mmc.c b/arch/avr32/cpu/mmc.c
new file mode 100644
index 0000000..b7213e4
--- /dev/null
+++ b/arch/avr32/cpu/mmc.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ * Copyright (C) 2015 Andreas Bießmann <andreas.devel@googlmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <atmel_mci.h>
+#include <asm/arch/hardware.h>
+
+/* provide cpu_mmc_init, to overwrite provide board_mmc_init */
+int cpu_mmc_init(bd_t *bd)
+{
+ /* This calls the atmel_mci_init in gen_atmel_mci.c */
+ return atmel_mci_init((void *)ATMEL_BASE_MMCI);
+}
diff --git a/arch/avr32/cpu/u-boot.lds b/arch/avr32/cpu/u-boot.lds
index cb29a22..b0180e3 100644
--- a/arch/avr32/cpu/u-boot.lds
+++ b/arch/avr32/cpu/u-boot.lds
@@ -48,9 +48,11 @@ SECTIONS
_edata = .;
.bss (NOLOAD) : {
+ __bss_start = .;
*(.bss)
*(.bss.*)
}
. = ALIGN(8);
__bss_end = .;
+ __init_end = .;
}
diff --git a/arch/avr32/include/asm/arch-at32ap700x/mmu.h b/arch/avr32/include/asm/arch-at32ap700x/mmu.h
index fcd9a05..4736312 100644
--- a/arch/avr32/include/asm/arch-at32ap700x/mmu.h
+++ b/arch/avr32/include/asm/arch-at32ap700x/mmu.h
@@ -13,9 +13,9 @@
#include <asm/sysreg.h>
-#define PAGE_SHIFT 20
-#define PAGE_SIZE (1UL << PAGE_SHIFT)
-#define PAGE_ADDR_MASK (~(PAGE_SIZE - 1))
+#define MMU_PAGE_SHIFT 20
+#define MMU_PAGE_SIZE (1UL << MMU_PAGE_SHIFT)
+#define MMU_PAGE_ADDR_MASK (~(MMU_PAGE_SIZE - 1))
#define MMU_VMR_CACHE_NONE \
(SYSREG_BF(AP, 3) | SYSREG_BF(SZ, 3) | SYSREG_BIT(TLBELO_D))
diff --git a/arch/avr32/include/asm/config.h b/arch/avr32/include/asm/config.h
index 63056a4..529fe22 100644
--- a/arch/avr32/include/asm/config.h
+++ b/arch/avr32/include/asm/config.h
@@ -8,5 +8,6 @@
#define _ASM_CONFIG_H_
#define CONFIG_NEEDS_MANUAL_RELOC
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#endif
diff --git a/arch/avr32/include/asm/dma-mapping.h b/arch/avr32/include/asm/dma-mapping.h
index dbdd2fe..1cde827 100644
--- a/arch/avr32/include/asm/dma-mapping.h
+++ b/arch/avr32/include/asm/dma-mapping.h
@@ -14,7 +14,12 @@ enum dma_data_direction {
DMA_TO_DEVICE = 1,
DMA_FROM_DEVICE = 2,
};
-extern void *dma_alloc_coherent(size_t len, unsigned long *handle);
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+ *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+ return (void *)*handle;
+}
static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
enum dma_data_direction dir)
diff --git a/arch/avr32/include/asm/global_data.h b/arch/avr32/include/asm/global_data.h
index d82fb7c..60abd00 100644
--- a/arch/avr32/include/asm/global_data.h
+++ b/arch/avr32/include/asm/global_data.h
@@ -8,7 +8,6 @@
/* Architecture-specific global data */
struct arch_global_data {
- unsigned long stack_end; /* highest stack address */
unsigned long cpu_hz; /* cpu core clock frequency */
};
diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h
index 6aef808..8b047ec 100644
--- a/arch/avr32/include/asm/u-boot.h
+++ b/arch/avr32/include/asm/u-boot.h
@@ -6,6 +6,11 @@
#ifndef __ASM_U_BOOT_H__
#define __ASM_U_BOOT_H__ 1
+#ifdef CONFIG_SYS_GENERIC_BOARD
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+#else
+
typedef struct bd_info {
unsigned char bi_phy_id[4];
unsigned long bi_board_number;
@@ -22,7 +27,12 @@ typedef struct bd_info {
#define bi_memstart bi_dram[0].start
#define bi_memsize bi_dram[0].size
+#endif
+
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_AVR32
+int arch_cpu_init(void);
+int dram_init(void);
+
#endif /* __ASM_U_BOOT_H__ */
diff --git a/arch/avr32/lib/Makefile b/arch/avr32/lib/Makefile
index bb45cbe..6750913 100644
--- a/arch/avr32/lib/Makefile
+++ b/arch/avr32/lib/Makefile
@@ -8,6 +8,9 @@
#
obj-y += memset.o
+ifndef CONFIG_SYS_GENERIC_BOARD
obj-y += board.o
+endif
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += interrupts.o
+obj-y += dram_init.o
diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c
index bf0997f..99aa96e 100644
--- a/arch/avr32/lib/board.c
+++ b/arch/avr32/lib/board.c
@@ -9,7 +9,6 @@
#include <stdio_dev.h>
#include <version.h>
#include <net.h>
-#include <atmel_mci.h>
#ifdef CONFIG_BITBANGMII
#include <miiphy.h>
@@ -30,6 +29,12 @@ DECLARE_GLOBAL_DATA_PTR;
unsigned long monitor_flash_len;
+__weak void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
/* Weak aliases for optional board functions */
static int __do_nothing(void)
{
@@ -38,57 +43,6 @@ static int __do_nothing(void)
int board_postclk_init(void) __attribute__((weak, alias("__do_nothing")));
int board_early_init_r(void) __attribute__((weak, alias("__do_nothing")));
-/* provide cpu_mmc_init, to overwrite provide board_mmc_init */
-int cpu_mmc_init(bd_t *bd)
-{
- /* This calls the atmel_mci_init in gen_atmel_mci.c */
- return atmel_mci_init((void *)ATMEL_BASE_MMCI);
-}
-
-#ifdef CONFIG_SYS_DMA_ALLOC_LEN
-#include <asm/arch/cacheflush.h>
-#include <asm/io.h>
-
-static unsigned long dma_alloc_start;
-static unsigned long dma_alloc_end;
-static unsigned long dma_alloc_brk;
-
-static void dma_alloc_init(void)
-{
- unsigned long monitor_addr;
-
- monitor_addr = CONFIG_SYS_MONITOR_BASE + gd->reloc_off;
- dma_alloc_end = monitor_addr - CONFIG_SYS_MALLOC_LEN;
- dma_alloc_start = dma_alloc_end - CONFIG_SYS_DMA_ALLOC_LEN;
- dma_alloc_brk = dma_alloc_start;
-
- printf("DMA: Using memory from 0x%08lx to 0x%08lx\n",
- dma_alloc_start, dma_alloc_end);
-
- invalidate_dcache_range((unsigned long)cached(dma_alloc_start),
- dma_alloc_end);
-}
-
-void *dma_alloc_coherent(size_t len, unsigned long *handle)
-{
- unsigned long paddr = dma_alloc_brk;
-
- if (dma_alloc_brk + len > dma_alloc_end)
- return NULL;
-
- dma_alloc_brk = ((paddr + len + CONFIG_SYS_DCACHE_LINESZ - 1)
- & ~(CONFIG_SYS_DCACHE_LINESZ - 1));
-
- *handle = paddr;
- return uncached(paddr);
-}
-#else
-static inline void dma_alloc_init(void)
-{
-
-}
-#endif
-
static int init_baudrate(void)
{
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
@@ -134,7 +88,6 @@ void board_init_f(ulong board_type)
unsigned long monitor_len;
unsigned long monitor_addr;
unsigned long addr;
- long sdram_size;
/* Initialize the global data pointer */
memset(&gd_data, 0, sizeof(gd_data));
@@ -142,17 +95,17 @@ void board_init_f(ulong board_type)
/* Perform initialization sequence */
board_early_init_f();
- cpu_init();
+ arch_cpu_init();
board_postclk_init();
env_init();
init_baudrate();
serial_init();
console_init_f();
display_banner();
- sdram_size = initdram(board_type);
+ dram_init();
/* If we have no SDRAM, we can't go on */
- if (sdram_size <= 0)
+ if (gd->ram_size <= 0)
panic("No working SDRAM available\n");
/*
@@ -166,7 +119,7 @@ void board_init_f(ulong board_type)
* - global data struct
* - stack
*/
- addr = CONFIG_SYS_SDRAM_BASE + sdram_size;
+ addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
monitor_len = (char *)(&__bss_end) - _text;
/*
@@ -180,12 +133,6 @@ void board_init_f(ulong board_type)
/* Reserve memory for malloc() */
addr -= CONFIG_SYS_MALLOC_LEN;
-#ifdef CONFIG_SYS_DMA_ALLOC_LEN
- /* Reserve DMA memory (must be cache aligned) */
- addr &= ~(CONFIG_SYS_DCACHE_LINESZ - 1);
- addr -= CONFIG_SYS_DMA_ALLOC_LEN;
-#endif
-
#ifdef CONFIG_LCD
#ifdef CONFIG_FB_ADDR
printf("LCD: Frame buffer allocated at preset 0x%08x\n",
@@ -210,16 +157,11 @@ void board_init_f(ulong board_type)
/* And finally, a new, bigger stack. */
new_sp = (unsigned long *)addr;
- gd->arch.stack_end = addr;
+ gd->start_addr_sp = addr;
*(--new_sp) = 0;
*(--new_sp) = 0;
- /*
- * Initialize the board information struct with the
- * information we have.
- */
- bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- bd->bi_dram[0].size = sdram_size;
+ dram_init_banksize();
memcpy(new_gd, gd, sizeof(gd_t));
@@ -264,7 +206,6 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
/* The malloc area is right below the monitor image in RAM */
mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN);
- dma_alloc_init();
enable_interrupts();
diff --git a/arch/avr32/lib/dram_init.c b/arch/avr32/lib/dram_init.c
new file mode 100644
index 0000000..5078e77
--- /dev/null
+++ b/arch/avr32/lib/dram_init.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2015 Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ /* check for the maximum amount of memory possible on AP7000 devices */
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ (256<<20));
+ return 0;
+}
diff --git a/arch/avr32/lib/interrupts.c b/arch/avr32/lib/interrupts.c
index bacb2d1..5f3a49e 100644
--- a/arch/avr32/lib/interrupts.c
+++ b/arch/avr32/lib/interrupts.c
@@ -7,6 +7,11 @@
#include <asm/sysreg.h>
+int interrupt_init(void)
+{
+ return 0;
+}
+
void enable_interrupts(void)
{
asm volatile("csrf %0" : : "n"(SYSREG_GM_OFFSET));
diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c
index b7f1188..91aa5cc 100644
--- a/arch/blackfin/cpu/cpu.c
+++ b/arch/blackfin/cpu/cpu.c
@@ -24,6 +24,7 @@
#include "cpu.h"
#include "initcode.h"
+#include "exports.h"
ulong bfin_poweron_retx;
DECLARE_GLOBAL_DATA_PTR;
@@ -121,7 +122,7 @@ static void display_global_data(void)
printf(" |-ram_size: %lx\n", gd->ram_size);
printf(" |-env_addr: %lx\n", gd->env_addr);
printf(" |-env_valid: %lx\n", gd->env_valid);
- printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt));
+ printf(" |-jt(%p): %p\n", gd->jt, gd->jt->get_version);
printf(" \\-bd: %p\n", gd->bd);
printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params);
printf(" |-bi_memstart: %lx\n", bd->bi_memstart);
diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk
index 98bbf79..2b817be 100644
--- a/arch/microblaze/config.mk
+++ b/arch/microblaze/config.mk
@@ -15,3 +15,8 @@ endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000
PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__
+
+ifeq ($(CONFIG_SPL_BUILD),)
+PLATFORM_CPPFLAGS += -fPIC
+endif
+__HAVE_ARCH_GENERIC_BOARD := y
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index 227842f..aa34f45 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -13,49 +13,52 @@ void _hw_exception_handler (void)
{
int address = 0;
int state = 0;
+
/* loading address of exception EAR */
- MFS (address, rear);
+ MFS(address, rear);
/* loading excetpion state register ESR */
- MFS (state, resr);
- printf ("Hardware exception at 0x%x address\n", address);
+ MFS(state, resr);
+ printf("Hardware exception at 0x%x address\n", address);
+ R17(address);
+ printf("Return address from exception 0x%x\n", address);
switch (state & 0x1f) { /* mask on exception cause */
case 0x1:
- puts ("Unaligned data access exception\n");
+ puts("Unaligned data access exception\n");
break;
case 0x2:
- puts ("Illegal op-code exception\n");
+ puts("Illegal op-code exception\n");
break;
case 0x3:
- puts ("Instruction bus error exception\n");
+ puts("Instruction bus error exception\n");
break;
case 0x4:
- puts ("Data bus error exception\n");
+ puts("Data bus error exception\n");
break;
case 0x5:
- puts ("Divide by zero exception\n");
+ puts("Divide by zero exception\n");
break;
#ifdef MICROBLAZE_V5
case 0x7:
puts("Priviledged or stack protection violation exception\n");
break;
case 0x1000:
- puts ("Exception in delay slot\n");
+ puts("Exception in delay slot\n");
break;
#endif
default:
- puts ("Undefined cause\n");
+ puts("Undefined cause\n");
break;
}
- printf ("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
- printf ("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
- printf ("Register R%x\n", (state & 0x3E) >> 5);
- hang ();
+ printf("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
+ printf("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
+ printf("Register R%x\n", (state & 0x3E) >> 5);
+ hang();
}
#ifdef CONFIG_SYS_USR_EXCEP
void _exception_handler (void)
{
- puts ("User vector_exception\n");
- hang ();
+ puts("User vector_exception\n");
+ hang();
}
#endif
diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c
index 9364e2f..b6d6610 100644
--- a/arch/microblaze/cpu/interrupts.c
+++ b/arch/microblaze/cpu/interrupts.c
@@ -14,10 +14,9 @@
#include <asm/microblaze_intc.h>
#include <asm/asm.h>
-#undef DEBUG_INT
-
void enable_interrupts(void)
{
+ debug("Enable interrupts for the whole CPU\n");
MSRSET(0x2);
}
@@ -50,12 +49,11 @@ static void enable_one_interrupt(int irq)
offset <<= irq;
mask = intc->ier;
intc->ier = (mask | offset);
-#ifdef DEBUG_INT
- printf("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask,
- intc->ier);
- printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
- intc->iar, intc->mer);
-#endif
+
+ debug("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask,
+ intc->ier);
+ debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ intc->iar, intc->mer);
}
static void disable_one_interrupt(int irq)
@@ -66,12 +64,11 @@ static void disable_one_interrupt(int irq)
offset <<= irq;
mask = intc->ier;
intc->ier = (mask & ~offset);
-#ifdef DEBUG_INT
- printf("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask,
- intc->ier);
- printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
- intc->iar, intc->mer);
-#endif
+
+ debug("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask,
+ intc->ier);
+ debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ intc->iar, intc->mer);
}
int install_interrupt_handler(int irq, interrupt_handler_t *hdlr, void *arg)
@@ -88,12 +85,12 @@ int install_interrupt_handler(int irq, interrupt_handler_t *hdlr, void *arg)
act->handler = hdlr;
act->arg = arg;
act->count = 0;
- enable_one_interrupt (irq);
+ enable_one_interrupt(irq);
return 0;
}
/* Disable */
- act->handler = (interrupt_handler_t *) def_hdlr;
+ act->handler = (interrupt_handler_t *)def_hdlr;
act->arg = (void *)irq;
disable_one_interrupt(irq);
return 1;
@@ -107,18 +104,17 @@ static void intc_init(void)
intc->iar = 0xFFFFFFFF;
/* XIntc_Start - hw_interrupt enable and all interrupt enable */
intc->mer = 0x3;
-#ifdef DEBUG_INT
- printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
- intc->iar, intc->mer);
-#endif
+
+ debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ intc->iar, intc->mer);
}
-int interrupts_init(void)
+int interrupt_init(void)
{
int i;
#if defined(CONFIG_SYS_INTC_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM)
- intc = (microblaze_intc_t *) (CONFIG_SYS_INTC_0_ADDR);
+ intc = (microblaze_intc_t *)CONFIG_SYS_INTC_0_ADDR;
irq_no = CONFIG_SYS_INTC_0_NUM;
#endif
if (irq_no) {
@@ -130,7 +126,7 @@ int interrupts_init(void)
/* initialize irq list */
for (i = 0; i < irq_no; i++) {
- vecs[i].handler = (interrupt_handler_t *) def_hdlr;
+ vecs[i].handler = (interrupt_handler_t *)def_hdlr;
vecs[i].arg = (void *)i;
vecs[i].count = 0;
}
@@ -147,31 +143,29 @@ void interrupt_handler(void)
{
int irqs = intc->ivr; /* find active interrupt */
int mask = 1;
-#ifdef DEBUG_INT
int value;
- printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
- intc->iar, intc->mer);
- R14(value);
- printf ("Interrupt handler on %x line, r14 %x\n", irqs, value);
-#endif
struct irq_action *act = vecs + irqs;
-#ifdef DEBUG_INT
- printf
- ("Jumping to interrupt handler rutine addr %x,count %x,arg %x\n",
- act->handler, act->count, act->arg);
+ debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ intc->iar, intc->mer);
+#ifdef DEBUG
+ R14(value);
#endif
- act->handler (act->arg);
+ debug("Interrupt handler on %x line, r14 %x\n", irqs, value);
+
+ debug("Jumping to interrupt handler rutine addr %x,count %x,arg %x\n",
+ (u32)act->handler, act->count, (u32)act->arg);
+ act->handler(act->arg);
act->count++;
intc->iar = mask << irqs;
-#ifdef DEBUG_INT
- printf ("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr,
- intc->ier, intc->iar, intc->mer);
+ debug("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr,
+ intc->ier, intc->iar, intc->mer);
+#ifdef DEBUG
R14(value);
- printf ("Interrupt handler on %x line, r14 %x\n", irqs, value);
#endif
+ debug("Interrupt handler on %x line, r14 %x\n", irqs, value);
}
#if defined(CONFIG_CMD_IRQ)
@@ -186,10 +180,10 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, const char *argv[])
"-----------------------------\n");
for (i = 0; i < irq_no; i++) {
- if (act->handler != (interrupt_handler_t *) def_hdlr) {
+ if (act->handler != (interrupt_handler_t *)def_hdlr) {
printf("%02d %08x %08x %d\n", i,
- (int)act->handler, (int)act->arg,
- act->count);
+ (int)act->handler, (int)act->arg,
+ act->count);
}
act++;
}
diff --git a/arch/microblaze/cpu/irq.S b/arch/microblaze/cpu/irq.S
index 2401589..5cfe151 100644
--- a/arch/microblaze/cpu/irq.S
+++ b/arch/microblaze/cpu/irq.S
@@ -11,71 +11,70 @@
.text
.global _interrupt_handler
_interrupt_handler:
- swi r2, r1, -4
- swi r3, r1, -8
- swi r4, r1, -12
- swi r5, r1, -16
- swi r6, r1, -20
- swi r7, r1, -24
- swi r8, r1, -28
- swi r9, r1, -32
- swi r10, r1, -36
- swi r11, r1, -40
- swi r12, r1, -44
- swi r13, r1, -48
- swi r14, r1, -52
- swi r15, r1, -56
- swi r16, r1, -60
- swi r17, r1, -64
- swi r18, r1, -68
- swi r19, r1, -72
- swi r20, r1, -76
- swi r21, r1, -80
- swi r22, r1, -84
- swi r23, r1, -88
- swi r24, r1, -92
- swi r25, r1, -96
- swi r26, r1, -100
- swi r27, r1, -104
- swi r28, r1, -108
- swi r29, r1, -112
- swi r30, r1, -116
- swi r31, r1, -120
addik r1, r1, -124
+ swi r2, r1, 4
+ swi r3, r1, 8
+ swi r4, r1, 12
+ swi r5, r1, 16
+ swi r6, r1, 20
+ swi r7, r1, 24
+ swi r8, r1, 28
+ swi r9, r1, 32
+ swi r10, r1, 36
+ swi r11, r1, 40
+ swi r12, r1, 44
+ swi r13, r1, 48
+ swi r14, r1, 52
+ swi r15, r1, 56
+ swi r16, r1, 60
+ swi r17, r1, 64
+ swi r18, r1, 68
+ swi r19, r1, 72
+ swi r20, r1, 76
+ swi r21, r1, 80
+ swi r22, r1, 84
+ swi r23, r1, 88
+ swi r24, r1, 92
+ swi r25, r1, 96
+ swi r26, r1, 100
+ swi r27, r1, 104
+ swi r28, r1, 108
+ swi r29, r1, 112
+ swi r30, r1, 116
+ swi r31, r1, 120
brlid r15, interrupt_handler
nop
+ lwi r31, r1, 120
+ lwi r30, r1, 116
+ lwi r29, r1, 112
+ lwi r28, r1, 108
+ lwi r27, r1, 104
+ lwi r26, r1, 100
+ lwi r25, r1, 96
+ lwi r24, r1, 92
+ lwi r23, r1, 88
+ lwi r22, r1, 84
+ lwi r21, r1, 80
+ lwi r20, r1, 76
+ lwi r19, r1, 72
+ lwi r18, r1, 68
+ lwi r17, r1, 64
+ lwi r16, r1, 60
+ lwi r15, r1, 56
+ lwi r14, r1, 52
+ lwi r13, r1, 48
+ lwi r12, r1, 44
+ lwi r11, r1, 40
+ lwi r10, r1, 36
+ lwi r9, r1, 32
+ lwi r8, r1, 28
+ lwi r7, r1, 24
+ lwi r6, r1, 20
+ lwi r5, r1, 16
+ lwi r4, r1, 12
+ lwi r3, r1, 8
+ lwi r2, r1, 4
addik r1, r1, 124
- lwi r31, r1, -120
- lwi r30, r1, -116
- lwi r29, r1, -112
- lwi r28, r1, -108
- lwi r27, r1, -104
- lwi r26, r1, -100
- lwi r25, r1, -96
- lwi r24, r1, -92
- lwi r23, r1, -88
- lwi r22, r1, -84
- lwi r21, r1, -80
- lwi r20, r1, -76
- lwi r19, r1, -72
- lwi r18, r1, -68
- lwi r17, r1, -64
- lwi r16, r1, -60
- lwi r15, r1, -56
- lwi r14, r1, -52
- lwi r13, r1, -48
- lwi r12, r1, -44
- lwi r11, r1, -40
- lwi r10, r1, -36
- lwi r9, r1, -32
- lwi r8, r1, -28
- lwi r7, r1, -24
- lwi r6, r1, -20
- lwi r5, r1, -16
- lwi r4, r1, -12
- lwi r3, r1, -8
- lwi r2, r1, -4
-
rtid r14, 0
nop
.size _interrupt_handler,.-_interrupt_handler
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
index 0912261..2cc0a2d 100644
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@@ -25,8 +25,6 @@ u32 spl_boot_device(void)
/* Board initialization after bss clearance */
void spl_board_init(void)
{
- gd = (gd_t *)CONFIG_SPL_STACK_ADDR;
-
/* enable console uart printing */
preloader_console_init();
}
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 84c29e5..953d3a1 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -30,7 +30,11 @@ _start:
mts rshr, r1
addi r1, r1, -4 /* Decrement SP to top of memory */
#else
+#if defined(CONFIG_SYS_MALLOC_F_LEN)
+ addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET - CONFIG_SYS_MALLOC_F_LEN
+#else
addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
+#endif
mts rshr, r1
addi r1, r1, -4 /* Decrement SP to top of memory */
@@ -129,7 +133,7 @@ _start:
/* Flush cache before enable cache */
addik r5, r0, 0
addik r6, r0, XILINX_DCACHE_BYTE_SIZE
-flush: bralid r15, flush_cache
+ bralid r15, flush_cache
nop
/* enable instruction and data cache */
@@ -150,12 +154,28 @@ clear_bss:
bnei r6, 2b
3: /* jumping to board_init */
#ifndef CONFIG_SPL_BUILD
+ or r5, r0, r0 /* flags - empty */
+ addi r31, r0, _gd
+#if defined(CONFIG_SYS_MALLOC_F_LEN)
+ addi r6, r0, CONFIG_SYS_INIT_SP_OFFSET
+ swi r6, r31, GD_MALLOC_BASE
+#endif
brai board_init_f
#else
+ addi r31, r0, _gd
+#if defined(CONFIG_SYS_MALLOC_F_LEN)
+ addi r6, r0, CONFIG_SPL_STACK_ADDR
+ swi r6, r31, GD_MALLOC_BASE
+#endif
brai board_init_r
#endif
1: bri 1b
+ .section .bss
+.align 4
+_gd:
+ .space GENERATED_GBL_DATA_SIZE
+
#ifndef CONFIG_SPL_BUILD
/*
* Read 16bit little endian
@@ -189,4 +209,108 @@ out16: bslli r3, r6, 8
rtsd r15, 8
or r0, r0, r0
.end out16
+
+/*
+ * Relocate u-boot
+ */
+ .text
+ .global relocate_code
+ .ent relocate_code
+ .align 2
+relocate_code:
+ /*
+ * r5 - start_addr_sp
+ * r6 - new_gd
+ * r7 - reloc_addr
+ */
+ addi r1, r5, 0 /* Start to use new SP */
+ addi r31, r6, 0 /* Start to use new GD */
+
+ add r23, r0, r7 /* Move reloc addr to r23 */
+ /* Relocate text and data - r12 temp value */
+ addi r21, r0, _start
+ addi r22, r0, __end - 4 /* Include BSS too */
+
+ rsub r6, r21, r22
+ or r5, r0, r0
+1: lw r12, r21, r5 /* Load u-boot data */
+ sw r12, r23, r5 /* Write zero to loc */
+ cmp r12, r5, r6 /* Check if we have reach the end */
+ bneid r12, 1b
+ addi r5, r5, 4 /* Increment to next loc - relocate code */
+
+ /* R23 points to the base address. */
+ add r23, r0, r7 /* Move reloc addr to r23 */
+ addi r24, r0, CONFIG_SYS_TEXT_BASE /* Get reloc offset */
+ rsub r23, r24, r23 /* keep - this is already here gd->reloc_off */
+
+ addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
+ lwi r7, r0, 0x28
+ swi r6, r0, 0x28 /* used first unused MB vector */
+ lbui r10, r0, 0x28 /* used first unused MB vector */
+ swi r7, r0, 0x28
+
+#ifdef CONFIG_SYS_USR_EXCEP
+ addik r6, r0, _exception_handler
+ addk r6, r6, r23 /* add offset */
+ sw r6, r1, r0
+ lhu r7, r1, r10
+ rsubi r8, r10, 0xa
+ sh r7, r0, r8
+ rsubi r8, r10, 0xe
+ sh r6, r0, r8
+#endif
+ addik r6, r0, _hw_exception_handler
+ addk r6, r6, r23 /* add offset */
+ sw r6, r1, r0
+ lhu r7, r1, r10
+ rsubi r8, r10, 0x22
+ sh r7, r0, r8
+ rsubi r8, r10, 0x26
+ sh r6, r0, r8
+
+ addik r6, r0, _interrupt_handler
+ addk r6, r6, r23 /* add offset */
+ sw r6, r1, r0
+ lhu r7, r1, r10
+ rsubi r8, r10, 0x12
+ sh r7, r0, r8
+ rsubi r8, r10, 0x16
+ sh r6, r0, r8
+
+ /* Check if GOT exist */
+ addik r21, r23, _got_start
+ addik r22, r23, _got_end
+ cmpu r12, r21, r22
+ beqi r12, 2f /* No GOT table - jump over */
+
+ /* Skip last 3 entries plus 1 because of loop boundary below */
+ addik r22, r22, -0x10
+
+ /* Relocate the GOT. */
+3: lw r12, r21, r0 /* Load entry */
+ addk r12, r12, r23 /* Add reloc offset */
+ sw r12, r21, r0 /* Save entry back */
+
+ cmpu r12, r21, r22 /* Check if this cross boundary */
+ bneid r12, 3b
+ addik r21. r21, 4
+
+ /* Update pointer to GOT */
+ mfs r20, rpc
+ addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8
+ addk r20, r20, r23
+
+ /* Flush caches to ensure consistency */
+ addik r5, r0, 0
+ addik r6, r0, XILINX_DCACHE_BYTE_SIZE
+ bralid r15, flush_cache
+ nop
+
+2: addi r5, r31, 0 /* gd is initialized in board_r.c */
+ addi r6, r0, CONFIG_SYS_TEXT_BASE
+ addi r12, r23, board_init_r
+ bra r12 /* Jump to relocated code */
+
+ .end relocate_code
#endif
diff --git a/arch/microblaze/cpu/u-boot-spl.lds b/arch/microblaze/cpu/u-boot-spl.lds
index 96353cd..c60336c 100644
--- a/arch/microblaze/cpu/u-boot-spl.lds
+++ b/arch/microblaze/cpu/u-boot-spl.lds
@@ -37,6 +37,12 @@ SECTIONS
__data_end = .;
}
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+ __init_end = . ;
+
.bss ALIGN(0x4):
{
__bss_start = .;
diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds
index fdad207..2502a0d 100644
--- a/arch/microblaze/cpu/u-boot.lds
+++ b/arch/microblaze/cpu/u-boot.lds
@@ -29,17 +29,23 @@ SECTIONS
.data ALIGN(0x4):
{
__data_start = .;
-#ifdef CONFIG_OF_EMBED
- dts/built-in.o (.data)
-#endif
*(.data)
__data_end = .;
}
+ .got ALIGN(4):
+ {
+ _got_start = .;
+ *(.got*)
+ . = ALIGN(4);
+ _got_end = .;
+ }
+
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
+ __init_end = . ;
.bss ALIGN(0x4):
{
diff --git a/arch/microblaze/include/asm/asm.h b/arch/microblaze/include/asm/asm.h
index c1c3b03..11f3dd0 100644
--- a/arch/microblaze/include/asm/asm.h
+++ b/arch/microblaze/include/asm/asm.h
@@ -43,6 +43,10 @@
#define R14(val) \
__asm__ __volatile__ ("addi %0, r14, 0":"=r" (val));
+/* get return address from interrupt */
+#define R17(val) \
+ __asm__ __volatile__ ("addi %0, r17, 0" : "=r" (val));
+
#define NOP __asm__ __volatile__ ("nop");
/* use machine status registe USE_MSR_REG */
diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h
index cd29734..32fd636 100644
--- a/arch/microblaze/include/asm/config.h
+++ b/arch/microblaze/include/asm/config.h
@@ -7,4 +7,11 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_NEEDS_MANUAL_RELOC
+#endif
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_GENERIC_BOARD
+
#endif
diff --git a/arch/microblaze/include/asm/microblaze_intc.h b/arch/microblaze/include/asm/microblaze_intc.h
index 0fb9207..6586838 100644
--- a/arch/microblaze/include/asm/microblaze_intc.h
+++ b/arch/microblaze/include/asm/microblaze_intc.h
@@ -34,5 +34,3 @@ struct irq_action {
*/
int install_interrupt_handler(int irq, interrupt_handler_t *hdlr,
void *arg);
-
-int interrupts_init(void);
diff --git a/arch/microblaze/include/asm/u-boot.h b/arch/microblaze/include/asm/u-boot.h
index 54d415e..66f8f95 100644
--- a/arch/microblaze/include/asm/u-boot.h
+++ b/arch/microblaze/include/asm/u-boot.h
@@ -16,16 +16,7 @@
#ifndef _U_BOOT_H_
#define _U_BOOT_H_
-typedef struct bd_info {
- unsigned long bi_memstart; /* start of DRAM memory */
- phys_size_t bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
- unsigned long bi_sramstart; /* start of SRAM memory */
- unsigned long bi_sramsize; /* size of SRAM memory */
- ulong bi_boot_params; /* where this board expects params */
-} bd_t;
+#include <asm-generic/u-boot.h>
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_MICROBLAZE
diff --git a/arch/microblaze/lib/Makefile b/arch/microblaze/lib/Makefile
index 339dd15..0289d0c 100644
--- a/arch/microblaze/lib/Makefile
+++ b/arch/microblaze/lib/Makefile
@@ -5,6 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += board.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += muldi3.o
diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c
deleted file mode 100644
index 600c80a..0000000
--- a/arch/microblaze/lib/board.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- * (C) Copyright 2004 Atmark Techno, Inc.
- *
- * Michal SIMEK <monstr@monstr.eu>
- * Yasushi SHOJI <yashi@atmark-techno.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <version.h>
-#include <watchdog.h>
-#include <stdio_dev.h>
-#include <serial.h>
-#include <net.h>
-#include <spi.h>
-#include <linux/compiler.h>
-#include <asm/processor.h>
-#include <asm/microblaze_intc.h>
-#include <fdtdec.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int display_banner(void)
-{
- printf("\n\n%s\n\n", version_string);
- return 0;
-}
-
-/*
- * All attempts to come up with a "common" initialization sequence
- * that works for all boards and architectures failed: some of the
- * requirements are just _too_ different. To get rid of the resulting
- * mess of board dependend #ifdef'ed code we now make the whole
- * initialization sequence configurable to the user.
- *
- * The requirements for any new initalization function is simple: it
- * receives a pointer to the "global data" structure as it's only
- * argument, and returns an integer return code, where 0 means
- * "continue" and != 0 means "fatal error, hang the system".
- */
-typedef int (init_fnc_t) (void);
-
-init_fnc_t *init_sequence[] = {
- env_init,
-#ifdef CONFIG_OF_CONTROL
- fdtdec_check_fdt,
-#endif
- serial_init,
-#ifndef CONFIG_SPL_BUILD
- console_init_f,
-#endif
- display_banner,
-#ifndef CONFIG_SPL_BUILD
- interrupts_init,
- timer_init,
-#endif
- NULL,
-};
-
-unsigned long monitor_flash_len;
-
-void board_init_f(ulong not_used)
-{
- bd_t *bd;
- init_fnc_t **init_fnc_ptr;
- gd = (gd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET);
- bd = (bd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET
- - GENERATED_BD_INFO_SIZE);
-#if defined(CONFIG_CMD_FLASH) && !defined(CONFIG_SPL_BUILD)
- ulong flash_size = 0;
-#endif
- asm ("nop"); /* FIXME gd is not initialize - wait */
- memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
- memset((void *)bd, 0, GENERATED_BD_INFO_SIZE);
- gd->bd = bd;
- gd->baudrate = CONFIG_BAUDRATE;
- bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
-
- monitor_flash_len = __end - __text_start;
-
-#ifdef CONFIG_OF_EMBED
- /* Get a pointer to the FDT */
- gd->fdt_blob = __dtb_dt_begin;
-#elif defined CONFIG_OF_SEPARATE
- /* FDT is at end of image */
- gd->fdt_blob = (void *)__end;
-#endif
-
-#ifndef CONFIG_SPL_BUILD
- /* Allow the early environment to override the fdt address */
- gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
- (uintptr_t)gd->fdt_blob);
-#endif
-
- /*
- * The Malloc area is immediately below the monitor copy in DRAM
- * aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off
- * as our monitory code is run from SDRAM
- */
- mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
-
- serial_initialize();
-
-#ifdef CONFIG_XILINX_TB_WATCHDOG
- hw_watchdog_init();
-#endif
- for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
- WATCHDOG_RESET();
- if ((*init_fnc_ptr) () != 0)
- hang();
- }
-
-#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_OF_CONTROL
- /* For now, put this check after the console is ready */
- if (fdtdec_prepare_fdt())
- panic("** No FDT - please see doc/README.fdt-control");
- else
- printf("DTB: 0x%x\n", (u32)gd->fdt_blob);
-#endif
-
- puts("SDRAM :\n");
- printf("\t\tIcache:%s\n", icache_status() ? "ON" : "OFF");
- printf("\t\tDcache:%s\n", dcache_status() ? "ON" : "OFF");
- printf("\tU-Boot Start:0x%08x\n", CONFIG_SYS_TEXT_BASE);
-
-#if defined(CONFIG_CMD_FLASH)
- puts("Flash: ");
- bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
- flash_size = flash_init();
- if (bd->bi_flashstart && flash_size > 0) {
-# ifdef CONFIG_SYS_FLASH_CHECKSUM
- print_size(flash_size, "");
- /*
- * Compute and print flash CRC if flashchecksum is set to 'y'
- *
- * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
- */
- if (getenv_yesno("flashchecksum") == 1) {
- printf(" CRC: %08X",
- crc32(0, (const u8 *)bd->bi_flashstart,
- flash_size)
- );
- }
- putc('\n');
-# else /* !CONFIG_SYS_FLASH_CHECKSUM */
- print_size(flash_size, "\n");
-# endif /* CONFIG_SYS_FLASH_CHECKSUM */
- bd->bi_flashsize = flash_size;
- bd->bi_flashoffset = bd->bi_flashstart + flash_size;
- } else {
- puts("Flash init FAILED");
- bd->bi_flashstart = 0;
- bd->bi_flashsize = 0;
- bd->bi_flashoffset = 0;
- }
-#endif
-
-#ifdef CONFIG_SPI
- spi_init();
-#endif
-
- /* relocate environment function pointers etc. */
- env_relocate();
-
- /* Initialize stdio devices */
- stdio_init();
-
- /* Initialize the jump table for applications */
- jumptable_init();
-
- /* Initialize the console (after the relocation and devices init) */
- console_init_r();
-
- board_init();
-
- /* Initialize from environment */
- load_addr = getenv_ulong("loadaddr", 16, load_addr);
-
-#if defined(CONFIG_CMD_NET)
- printf("Net: ");
- eth_initialize(gd->bd);
-
- uchar enetaddr[6];
- eth_getenv_enetaddr("ethaddr", enetaddr);
- printf("MAC: %pM\n", enetaddr);
-#endif
-
- /* main_loop */
- for (;;) {
- WATCHDOG_RESET();
- main_loop();
- }
-#endif /* CONFIG_SPL_BUILD */
-}
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ef78929..bc4283d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -36,6 +36,7 @@ config TARGET_VCT
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select SYS_MIPS_CACHE_INIT_RAM_LOAD
config TARGET_DBAU1X00
bool "Support dbau1x00"
@@ -43,12 +44,14 @@ config TARGET_DBAU1X00
select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select SYS_MIPS_CACHE_INIT_RAM_LOAD
config TARGET_PB1X00
bool "Support pb1x00"
select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select SYS_MIPS_CACHE_INIT_RAM_LOAD
endchoice
@@ -185,6 +188,9 @@ config 64BIT
config SWAP_IO_SPACE
bool
+config SYS_MIPS_CACHE_INIT_RAM_LOAD
+ bool
+
endif
endmenu
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 0a9e7e6..43f0f5c 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -2,9 +2,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
-head-$(CONFIG_CPU_MIPS32) := arch/mips/cpu/mips32/start.o
-head-$(CONFIG_CPU_MIPS64) := arch/mips/cpu/mips64/start.o
+head-y := arch/mips/cpu/start.o
-libs-$(CONFIG_CPU_MIPS32) += arch/mips/cpu/mips32/
-libs-$(CONFIG_CPU_MIPS64) += arch/mips/cpu/mips64/
+libs-y += arch/mips/cpu/
libs-y += arch/mips/lib/
+
+libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/
diff --git a/arch/mips/cpu/Makefile b/arch/mips/cpu/Makefile
new file mode 100644
index 0000000..fc6b455
--- /dev/null
+++ b/arch/mips/cpu/Makefile
@@ -0,0 +1,9 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+extra-y = start.o
+
+obj-y += time.o
+obj-y += interrupts.o
+obj-y += cpu.o
diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
new file mode 100644
index 0000000..8d3b2f5
--- /dev/null
+++ b/arch/mips/cpu/cpu.c
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+
+void __weak _machine_restart(void)
+{
+ fprintf(stderr, "*** reset failed ***\n");
+
+ while (1)
+ /* NOP */;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ _machine_restart();
+
+ return 0;
+}
+
+void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
+{
+ write_c0_entrylo0(low0);
+ write_c0_pagemask(pagemask);
+ write_c0_entrylo1(low1);
+ write_c0_entryhi(hi);
+ write_c0_index(index);
+ tlb_write_indexed();
+}
diff --git a/arch/mips/cpu/mips32/interrupts.c b/arch/mips/cpu/interrupts.c
index 275fcf5..275fcf5 100644
--- a/arch/mips/cpu/mips32/interrupts.c
+++ b/arch/mips/cpu/interrupts.c
diff --git a/arch/mips/cpu/mips32/Makefile b/arch/mips/cpu/mips32/Makefile
deleted file mode 100644
index fa82dd3..0000000
--- a/arch/mips/cpu/mips32/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y = start.o
-obj-y = cache.o
-obj-y += cpu.o interrupts.o time.o
-
-obj-$(CONFIG_SOC_AU1X00) += au1x00/
diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile
deleted file mode 100644
index 899c319..0000000
--- a/arch/mips/cpu/mips64/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y = start.o
-obj-y = cpu.o interrupts.o time.o cache.o
diff --git a/arch/mips/cpu/mips64/cache.S b/arch/mips/cpu/mips64/cache.S
deleted file mode 100644
index 36d8688..0000000
--- a/arch/mips/cpu/mips64/cache.S
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * Cache-handling routined for MIPS CPUs
- *
- * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/asm.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <asm/cacheops.h>
-
-#define RA t9
-
-/*
- * 16kB is the maximum size of instruction and data caches on MIPS 4K,
- * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
- *
- * Note that the above size is the maximum size of primary cache. U-Boot
- * doesn't have L2 cache support for now.
- */
-#define MIPS_MAX_CACHE_SIZE 0x10000
-
-#define INDEX_BASE CKSEG0
-
- .macro cache_op op addr
- .set push
- .set noreorder
- .set mips3
- cache \op, 0(\addr)
- .set pop
- .endm
-
- .macro f_fill64 dst, offset, val
- LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
- LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
- LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
- LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
- LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
- LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
- LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
- LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
-#if LONGSIZE == 4
- LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
- LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
- LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
- LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
- LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
- LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
- LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
- LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
-#endif
- .endm
-
-/*
- * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
- */
-LEAF(mips_init_icache)
- blez a1, 9f
- mtc0 zero, CP0_TAGLO
- /* clear tag to invalidate */
- PTR_LI t0, INDEX_BASE
- PTR_ADDU t1, t0, a1
-1: cache_op INDEX_STORE_TAG_I t0
- PTR_ADDU t0, a2
- bne t0, t1, 1b
- /* fill once, so data field parity is correct */
- PTR_LI t0, INDEX_BASE
-2: cache_op FILL t0
- PTR_ADDU t0, a2
- bne t0, t1, 2b
- /* invalidate again - prudent but not strictly neccessary */
- PTR_LI t0, INDEX_BASE
-1: cache_op INDEX_STORE_TAG_I t0
- PTR_ADDU t0, a2
- bne t0, t1, 1b
-9: jr ra
- END(mips_init_icache)
-
-/*
- * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
- */
-LEAF(mips_init_dcache)
- blez a1, 9f
- mtc0 zero, CP0_TAGLO
- /* clear all tags */
- PTR_LI t0, INDEX_BASE
- PTR_ADDU t1, t0, a1
-1: cache_op INDEX_STORE_TAG_D t0
- PTR_ADDU t0, a2
- bne t0, t1, 1b
- /* load from each line (in cached space) */
- PTR_LI t0, INDEX_BASE
-2: LONG_L zero, 0(t0)
- PTR_ADDU t0, a2
- bne t0, t1, 2b
- /* clear all tags */
- PTR_LI t0, INDEX_BASE
-1: cache_op INDEX_STORE_TAG_D t0
- PTR_ADDU t0, a2
- bne t0, t1, 1b
-9: jr ra
- END(mips_init_dcache)
-
-/*
- * mips_cache_reset - low level initialisation of the primary caches
- *
- * This routine initialises the primary caches to ensure that they have good
- * parity. It must be called by the ROM before any cached locations are used
- * to prevent the possibility of data with bad parity being written to memory.
- *
- * To initialise the instruction cache it is essential that a source of data
- * with good parity is available. This routine will initialise an area of
- * memory starting at location zero to be used as a source of parity.
- *
- * RETURNS: N/A
- *
- */
-NESTED(mips_cache_reset, 0, ra)
- move RA, ra
- li t2, CONFIG_SYS_ICACHE_SIZE
- li t3, CONFIG_SYS_DCACHE_SIZE
- li t8, CONFIG_SYS_CACHELINE_SIZE
-
- li v0, MIPS_MAX_CACHE_SIZE
-
- /*
- * Now clear that much memory starting from zero.
- */
- PTR_LI a0, CKSEG1
- PTR_ADDU a1, a0, v0
-2: PTR_ADDIU a0, 64
- f_fill64 a0, -64, zero
- bne a0, a1, 2b
-
- /*
- * The caches are probably in an indeterminate state,
- * so we force good parity into them by doing an
- * invalidate, load/fill, invalidate for each line.
- */
-
- /*
- * Assume bottom of RAM will generate good parity for the cache.
- */
-
- /*
- * Initialize the I-cache first,
- */
- move a1, t2
- move a2, t8
- PTR_LA v1, mips_init_icache
- jalr v1
-
- /*
- * then initialize D-cache.
- */
- move a1, t3
- move a2, t8
- PTR_LA v1, mips_init_dcache
- jalr v1
-
- jr RA
- END(mips_cache_reset)
-
-/*
- * dcache_status - get cache status
- *
- * RETURNS: 0 - cache disabled; 1 - cache enabled
- *
- */
-LEAF(dcache_status)
- mfc0 t0, CP0_CONFIG
- li t1, CONF_CM_UNCACHED
- andi t0, t0, CONF_CM_CMASK
- move v0, zero
- beq t0, t1, 2f
- li v0, 1
-2: jr ra
- END(dcache_status)
-
-/*
- * dcache_disable - disable cache
- *
- * RETURNS: N/A
- *
- */
-LEAF(dcache_disable)
- mfc0 t0, CP0_CONFIG
- li t1, -8
- and t0, t0, t1
- ori t0, t0, CONF_CM_UNCACHED
- mtc0 t0, CP0_CONFIG
- jr ra
- END(dcache_disable)
-
-/*
- * dcache_enable - enable cache
- *
- * RETURNS: N/A
- *
- */
-LEAF(dcache_enable)
- mfc0 t0, CP0_CONFIG
- ori t0, CONF_CM_CMASK
- xori t0, CONF_CM_CMASK
- ori t0, CONF_CM_CACHABLE_NONCOHERENT
- mtc0 t0, CP0_CONFIG
- jr ra
- END(dcache_enable)
diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c
deleted file mode 100644
index 9f45cfc..0000000
--- a/arch/mips/cpu/mips64/cpu.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/mipsregs.h>
-#include <asm/cacheops.h>
-#include <asm/reboot.h>
-
-#define cache_op(op, addr) \
- __asm__ __volatile__( \
- " .set push\n" \
- " .set noreorder\n" \
- " .set mips64\n" \
- " cache %0, %1\n" \
- " .set pop\n" \
- : \
- : "i" (op), "R" (*(unsigned char *)(addr)))
-
-void __attribute__((weak)) _machine_restart(void)
-{
- fprintf(stderr, "*** reset failed ***\n");
-
- while (1)
- /* NOP */;
-}
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- _machine_restart();
-
- return 0;
-}
-
-void flush_cache(ulong start_addr, ulong size)
-{
- unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
- unsigned long addr = start_addr & ~(lsize - 1);
- unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
-
- /* aend will be miscalculated when size is zero, so we return here */
- if (size == 0)
- return;
-
- while (1) {
- cache_op(HIT_WRITEBACK_INV_D, addr);
- cache_op(HIT_INVALIDATE_I, addr);
- if (addr == aend)
- break;
- addr += lsize;
- }
-}
-
-void flush_dcache_range(ulong start_addr, ulong stop)
-{
- unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
- unsigned long addr = start_addr & ~(lsize - 1);
- unsigned long aend = (stop - 1) & ~(lsize - 1);
-
- while (1) {
- cache_op(HIT_WRITEBACK_INV_D, addr);
- if (addr == aend)
- break;
- addr += lsize;
- }
-}
-
-void invalidate_dcache_range(ulong start_addr, ulong stop)
-{
- unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
- unsigned long addr = start_addr & ~(lsize - 1);
- unsigned long aend = (stop - 1) & ~(lsize - 1);
-
- while (1) {
- cache_op(HIT_INVALIDATE_D, addr);
- if (addr == aend)
- break;
- addr += lsize;
- }
-}
-
-void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
-{
- write_c0_entrylo0(low0);
- write_c0_pagemask(pagemask);
- write_c0_entrylo1(low1);
- write_c0_entryhi(hi);
- write_c0_index(index);
- tlb_write_indexed();
-}
diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c
deleted file mode 100644
index 275fcf5..0000000
--- a/arch/mips/cpu/mips64/interrupts.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-int interrupt_init(void)
-{
- return 0;
-}
-
-void enable_interrupts(void)
-{
-}
-
-int disable_interrupts(void)
-{
- return 0;
-}
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
deleted file mode 100644
index 471bc1e..0000000
--- a/arch/mips/cpu/mips64/start.S
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * Startup Code for MIPS64 CPU-core
- *
- * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-
-#ifndef CONFIG_SYS_MIPS_CACHE_MODE
-#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
-#endif
-
-#ifndef CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_SP_OFFSET)
-#endif
-
-#ifdef CONFIG_SYS_LITTLE_ENDIAN
-#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
- (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
-#else
-#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
- ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
-#endif
-
- /*
- * For the moment disable interrupts, mark the kernel mode and
- * set ST0_KX so that the CPU does not spit fire when using
- * 64-bit addresses.
- */
- .macro setup_c0_status set clr
- .set push
- mfc0 t0, CP0_STATUS
- or t0, ST0_CU0 | \set | 0x1f | \clr
- xor t0, 0x1f | \clr
- mtc0 t0, CP0_STATUS
- .set noreorder
- sll zero, 3 # ehb
- .set pop
- .endm
-
- .set noreorder
-
- .globl _start
- .text
-_start:
- /* U-boot entry point */
- b reset
- nop
-
- .org 0x200
- /* TLB refill, 32 bit task */
-1: b 1b
- nop
-
- .org 0x280
- /* XTLB refill, 64 bit task */
-1: b 1b
- nop
-
- .org 0x300
- /* Cache error exception */
-1: b 1b
- nop
-
- .org 0x380
- /* General exception */
-1: b 1b
- nop
-
- .org 0x400
- /* Catch interrupt exceptions */
-1: b 1b
- nop
-
- .org 0x480
- /* EJTAG debug exception */
-1: b 1b
- nop
-
- .align 4
-reset:
-
- /* Clear watch registers */
- dmtc0 zero, CP0_WATCHLO
- dmtc0 zero, CP0_WATCHHI
-
- /* WP(Watch Pending), SW0/1 should be cleared */
- mtc0 zero, CP0_CAUSE
-
- setup_c0_status ST0_KX 0
-
- /* Init Timer */
- mtc0 zero, CP0_COUNT
- mtc0 zero, CP0_COMPARE
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- /* CONFIG0 register */
- dli t0, CONF_CM_UNCACHED
- mtc0 t0, CP0_CONFIG
-#endif
-
- /*
- * Initialize $gp, force 8 byte alignment of bal instruction to forbid
- * the compiler to put nop's between bal and _gp. This is required to
- * keep _gp and ra aligned to 8 byte.
- */
- .align 3
- bal 1f
- nop
- .dword _gp
-1:
- ld gp, 0(ra)
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- /* Initialize any external memory */
- dla t9, lowlevel_init
- jalr t9
- nop
-
- /* Initialize caches... */
- dla t9, mips_cache_reset
- jalr t9
- nop
-
- /* ... and enable them */
- dli t0, CONFIG_SYS_MIPS_CACHE_MODE
- mtc0 t0, CP0_CONFIG
-#endif
-
- /* Set up temporary stack */
- dli t0, -16
- dli t1, CONFIG_SYS_INIT_SP_ADDR
- and sp, t1, t0 # force 16 byte alignment
- dsub sp, sp, GD_SIZE # reserve space for gd
- and sp, sp, t0 # force 16 byte alignment
- move k0, sp # save gd pointer
-#ifdef CONFIG_SYS_MALLOC_F_LEN
- dli t2, CONFIG_SYS_MALLOC_F_LEN
- dsub sp, sp, t2 # reserve space for early malloc
- and sp, sp, t0 # force 16 byte alignment
-#endif
- move fp, sp
-
- /* Clear gd */
- move t0, k0
-1:
- sw zero, 0(t0)
- blt t0, t1, 1b
- daddi t0, 4
-
-#ifdef CONFIG_SYS_MALLOC_F_LEN
- daddu t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
- sw sp, 0(t0)
-#endif
-
- dla t9, board_init_f
- jr t9
- move ra, zero
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * a0 = addr_sp
- * a1 = gd
- * a2 = destination address
- */
- .globl relocate_code
- .ent relocate_code
-relocate_code:
- move sp, a0 # set new stack pointer
- move fp, sp
-
- move s0, a1 # save gd in s0
- move s2, a2 # save destination address in s2
-
- dli t0, CONFIG_SYS_MONITOR_BASE
- dsub s1, s2, t0 # s1 <-- relocation offset
-
- dla t3, in_ram
- ld t2, -24(t3) # t2 <-- __image_copy_end
- move t1, a2
-
- dadd gp, s1 # adjust gp
-
- /*
- * t0 = source address
- * t1 = target address
- * t2 = source end address
- */
-1:
- lw t3, 0(t0)
- sw t3, 0(t1)
- daddu t0, 4
- blt t0, t2, 1b
- daddu t1, 4
-
- /* If caches were enabled, we would have to flush them here. */
- dsub a1, t1, s2 # a1 <-- size
- dla t9, flush_cache
- jalr t9
- move a0, s2 # a0 <-- destination address
-
- /* Jump to where we've relocated ourselves */
- daddi t0, s2, in_ram - _start
- jr t0
- nop
-
- .dword __rel_dyn_end
- .dword __rel_dyn_start
- .dword __image_copy_end
- .dword _GLOBAL_OFFSET_TABLE_
- .dword num_got_entries
-
-in_ram:
- /*
- * Now we want to update GOT.
- *
- * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
- * generated by GNU ld. Skip these reserved entries from relocation.
- */
- ld t3, -8(t0) # t3 <-- num_got_entries
- ld t8, -16(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
- dadd t8, s1 # t8 now holds relocated _G_O_T_
- daddi t8, t8, 16 # skipping first two entries
- dli t2, 2
-1:
- ld t1, 0(t8)
- beqz t1, 2f
- dadd t1, s1
- sd t1, 0(t8)
-2:
- daddi t2, 1
- blt t2, t3, 1b
- daddi t8, 8
-
- /* Update dynamic relocations */
- ld t1, -32(t0) # t1 <-- __rel_dyn_start
- ld t2, -40(t0) # t2 <-- __rel_dyn_end
-
- b 2f # skip first reserved entry
- daddi t1, 16
-
-1:
- lw t8, -4(t1) # t8 <-- relocation info
-
- dli t3, MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
- bne t8, t3, 2f # skip non R_MIPS_REL32 entries
- nop
-
- ld t3, -16(t1) # t3 <-- location to fix up in FLASH
-
- ld t8, 0(t3) # t8 <-- original pointer
- dadd t8, s1 # t8 <-- adjusted pointer
-
- dadd t3, s1 # t3 <-- location to fix up in RAM
- sd t8, 0(t3)
-
-2:
- blt t1, t2, 1b
- daddi t1, 16 # each rel.dyn entry is 16 bytes
-
- /*
- * Clear BSS
- *
- * GOT is now relocated. Thus __bss_start and __bss_end can be
- * accessed directly via $gp.
- */
- dla t1, __bss_start # t1 <-- __bss_start
- dla t2, __bss_end # t2 <-- __bss_end
-
-1:
- sd zero, 0(t1)
- blt t1, t2, 1b
- daddi t1, 8
-
- move a0, s0 # a0 <-- gd
- move a1, s2
- dla t9, board_init_r
- jr t9
- move ra, zero
-
- .end relocate_code
diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c
deleted file mode 100644
index 553da5f..0000000
--- a/arch/mips/cpu/mips64/time.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mipsregs.h>
-
-unsigned long notrace timer_read_counter(void)
-{
- return read_c0_count();
-}
-
-ulong notrace get_tbclk(void)
-{
- return CONFIG_SYS_MIPS_TIMER_FREQ;
-}
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/start.S
index 36b92cc..3b5b622 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/start.S
@@ -8,6 +8,7 @@
#include <asm-offsets.h>
#include <config.h>
+#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
@@ -20,6 +21,23 @@
CONFIG_SYS_INIT_SP_OFFSET)
#endif
+#ifdef CONFIG_32BIT
+# define MIPS_RELOC 3
+# define STATUS_SET 0
+#endif
+
+#ifdef CONFIG_64BIT
+# ifdef CONFIG_SYS_LITTLE_ENDIAN
+# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
+ (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
+# else
+# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
+ ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
+# endif
+# define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
+# define STATUS_SET ST0_KX
+#endif
+
/*
* For the moment disable interrupts, mark the kernel mode and
* set ST0_KX so that the CPU does not spit fire when using
@@ -98,13 +116,13 @@ _start:
reset:
/* Clear watch registers */
- mtc0 zero, CP0_WATCHLO
- mtc0 zero, CP0_WATCHHI
+ MTC0 zero, CP0_WATCHLO
+ MTC0 zero, CP0_WATCHHI
/* WP(Watch Pending), SW0/1 should be cleared */
mtc0 zero, CP0_CAUSE
- setup_c0_status 0 0
+ setup_c0_status STATUS_SET 0
/* Init Timer */
mtc0 zero, CP0_COUNT
@@ -116,21 +134,26 @@ reset:
mtc0 t0, CP0_CONFIG
#endif
- /* Initialize $gp */
+ /*
+ * Initialize $gp, force pointer sized alignment of bal instruction to
+ * forbid the compiler to put nop's between bal and _gp. This is
+ * required to keep _gp and ra aligned to 8 byte.
+ */
+ .align PTRLOG
bal 1f
nop
- .word _gp
+ PTR _gp
1:
- lw gp, 0(ra)
+ PTR_L gp, 0(ra)
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/* Initialize any external memory */
- la t9, lowlevel_init
+ PTR_LA t9, lowlevel_init
jalr t9
nop
/* Initialize caches... */
- la t9, mips_cache_reset
+ PTR_LA t9, mips_cache_reset
jalr t9
nop
@@ -140,15 +163,15 @@ reset:
#endif
/* Set up temporary stack */
- li t0, -16
- li t1, CONFIG_SYS_INIT_SP_ADDR
+ PTR_LI t0, -16
+ PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
and sp, t1, t0 # force 16 byte alignment
- sub sp, sp, GD_SIZE # reserve space for gd
+ PTR_SUB sp, sp, GD_SIZE # reserve space for gd
and sp, sp, t0 # force 16 byte alignment
move k0, sp # save gd pointer
#ifdef CONFIG_SYS_MALLOC_F_LEN
- li t2, CONFIG_SYS_MALLOC_F_LEN
- sub sp, sp, t2 # reserve space for early malloc
+ PTR_LI t2, CONFIG_SYS_MALLOC_F_LEN
+ PTR_SUB sp, sp, t2 # reserve space for early malloc
and sp, sp, t0 # force 16 byte alignment
#endif
move fp, sp
@@ -158,14 +181,14 @@ reset:
1:
sw zero, 0(t0)
blt t0, t1, 1b
- addi t0, 4
+ PTR_ADDI t0, 4
#ifdef CONFIG_SYS_MALLOC_F_LEN
- addu t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
+ PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
sw sp, 0(t0)
#endif
- la t9, board_init_f
+ PTR_LA t9, board_init_f
jr t9
move ra, zero
@@ -188,14 +211,14 @@ relocate_code:
move s0, a1 # save gd in s0
move s2, a2 # save destination address in s2
- li t0, CONFIG_SYS_MONITOR_BASE
- sub s1, s2, t0 # s1 <-- relocation offset
+ PTR_LI t0, CONFIG_SYS_MONITOR_BASE
+ PTR_SUB s1, s2, t0 # s1 <-- relocation offset
- la t3, in_ram
- lw t2, -12(t3) # t2 <-- __image_copy_end
+ PTR_LA t3, in_ram
+ PTR_L t2, -(3 * PTRSIZE)(t3) # t2 <-- __image_copy_end
move t1, a2
- add gp, s1 # adjust gp
+ PTR_ADD gp, s1 # adjust gp
/*
* t0 = source address
@@ -205,26 +228,26 @@ relocate_code:
1:
lw t3, 0(t0)
sw t3, 0(t1)
- addu t0, 4
+ PTR_ADDU t0, 4
blt t0, t2, 1b
- addu t1, 4
+ PTR_ADDU t1, 4
/* If caches were enabled, we would have to flush them here. */
- sub a1, t1, s2 # a1 <-- size
- la t9, flush_cache
+ PTR_SUB a1, t1, s2 # a1 <-- size
+ PTR_LA t9, flush_cache
jalr t9
move a0, s2 # a0 <-- destination address
/* Jump to where we've relocated ourselves */
- addi t0, s2, in_ram - _start
+ PTR_ADDI t0, s2, in_ram - _start
jr t0
nop
- .word __rel_dyn_end
- .word __rel_dyn_start
- .word __image_copy_end
- .word _GLOBAL_OFFSET_TABLE_
- .word num_got_entries
+ PTR __rel_dyn_end
+ PTR __rel_dyn_start
+ PTR __image_copy_end
+ PTR _GLOBAL_OFFSET_TABLE_
+ PTR num_got_entries
in_ram:
/*
@@ -233,46 +256,46 @@ in_ram:
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
* generated by GNU ld. Skip these reserved entries from relocation.
*/
- lw t3, -4(t0) # t3 <-- num_got_entries
- lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
- add t8, s1 # t8 now holds relocated _G_O_T_
- addi t8, t8, 8 # skipping first two entries
- li t2, 2
+ PTR_L t3, -(1 * PTRSIZE)(t0) # t3 <-- num_got_entries
+ PTR_L t8, -(2 * PTRSIZE)(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
+ PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_
+ PTR_ADDI t8, t8, 2 * PTRSIZE # skipping first two entries
+ PTR_LI t2, 2
1:
- lw t1, 0(t8)
+ PTR_L t1, 0(t8)
beqz t1, 2f
- add t1, s1
- sw t1, 0(t8)
+ PTR_ADD t1, s1
+ PTR_S t1, 0(t8)
2:
- addi t2, 1
+ PTR_ADDI t2, 1
blt t2, t3, 1b
- addi t8, 4
+ PTR_ADDI t8, PTRSIZE
/* Update dynamic relocations */
- lw t1, -16(t0) # t1 <-- __rel_dyn_start
- lw t2, -20(t0) # t2 <-- __rel_dyn_end
+ PTR_L t1, -(4 * PTRSIZE)(t0) # t1 <-- __rel_dyn_start
+ PTR_L t2, -(5 * PTRSIZE)(t0) # t2 <-- __rel_dyn_end
b 2f # skip first reserved entry
- addi t1, 8
+ PTR_ADDI t1, 2 * PTRSIZE
1:
lw t8, -4(t1) # t8 <-- relocation info
- li t3, 3
- bne t8, t3, 2f # skip non R_MIPS_REL32 entries
+ PTR_LI t3, MIPS_RELOC
+ bne t8, t3, 2f # skip non-MIPS_RELOC entries
nop
- lw t3, -8(t1) # t3 <-- location to fix up in FLASH
+ PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH
- lw t8, 0(t3) # t8 <-- original pointer
- add t8, s1 # t8 <-- adjusted pointer
+ PTR_L t8, 0(t3) # t8 <-- original pointer
+ PTR_ADD t8, s1 # t8 <-- adjusted pointer
- add t3, s1 # t3 <-- location to fix up in RAM
- sw t8, 0(t3)
+ PTR_ADD t3, s1 # t3 <-- location to fix up in RAM
+ PTR_S t8, 0(t3)
2:
blt t1, t2, 1b
- addi t1, 8 # each rel.dyn entry is 8 bytes
+ PTR_ADDI t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
/*
* Clear BSS
@@ -280,17 +303,17 @@ in_ram:
* GOT is now relocated. Thus __bss_start and __bss_end can be
* accessed directly via $gp.
*/
- la t1, __bss_start # t1 <-- __bss_start
- la t2, __bss_end # t2 <-- __bss_end
+ PTR_LA t1, __bss_start # t1 <-- __bss_start
+ PTR_LA t2, __bss_end # t2 <-- __bss_end
1:
- sw zero, 0(t1)
+ PTR_S zero, 0(t1)
blt t1, t2, 1b
- addi t1, 4
+ PTR_ADDI t1, PTRSIZE
move a0, s0 # a0 <-- gd
move a1, s2
- la t9, board_init_r
+ PTR_LA t9, board_init_r
jr t9
move ra, zero
diff --git a/arch/mips/cpu/mips32/time.c b/arch/mips/cpu/time.c
index 553da5f..553da5f 100644
--- a/arch/mips/cpu/mips32/time.c
+++ b/arch/mips/cpu/time.c
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 6464250..75ec380 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -11,6 +11,19 @@
#ifndef __ASM_CACHEOPS_H
#define __ASM_CACHEOPS_H
+#ifndef __ASSEMBLY__
+
+static inline void mips_cache(int op, const volatile void *addr)
+{
+#ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
+ __builtin_mips_cache(op, addr);
+#else
+ __asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr))
+#endif
+}
+
+#endif /* !__ASSEMBLY__ */
+
/*
* Cache Operations available on all MIPS processors with R4000-style caches
*/
diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h
index 9e7c045..d9ffc15 100644
--- a/arch/mips/include/asm/malta.h
+++ b/arch/mips/include/asm/malta.h
@@ -64,4 +64,9 @@
#define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16)
+#define PCI_CFG_PIIX4_IDETIM_PRI 0x40
+#define PCI_CFG_PIIX4_IDETIM_SEC 0x42
+
+#define PCI_CFG_PIIX4_IDETIM_IDE (1 << 15)
+
#endif /* _MIPS_ASM_MALTA_H */
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 7f9b653..ac536da 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -5,6 +5,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += cache.o
+obj-y += cache_init.o
obj-y += io.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/lib/cache.c
index 278865b..e245614 100644
--- a/arch/mips/cpu/mips32/cpu.c
+++ b/arch/mips/lib/cache.c
@@ -6,33 +6,8 @@
*/
#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/mipsregs.h>
#include <asm/cacheops.h>
-#include <asm/reboot.h>
-
-#define cache_op(op,addr) \
- __asm__ __volatile__( \
- " .set push \n" \
- " .set noreorder \n" \
- " .set mips3\n\t \n" \
- " cache %0, %1 \n" \
- " .set pop \n" \
- : \
- : "i" (op), "R" (*(unsigned char *)(addr)))
-
-void __attribute__((weak)) _machine_restart(void)
-{
-}
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- _machine_restart();
-
- fprintf(stderr, "*** reset failed ***\n");
- return 0;
-}
+#include <asm/mipsregs.h>
#ifdef CONFIG_SYS_CACHELINE_SIZE
@@ -74,20 +49,20 @@ void flush_cache(ulong start_addr, ulong size)
{
unsigned long ilsize = icache_line_size();
unsigned long dlsize = dcache_line_size();
- unsigned long addr, aend;
+ const void *addr, *aend;
/* aend will be miscalculated when size is zero, so we return here */
if (size == 0)
return;
- addr = start_addr & ~(dlsize - 1);
- aend = (start_addr + size - 1) & ~(dlsize - 1);
+ addr = (const void *)(start_addr & ~(dlsize - 1));
+ aend = (const void *)((start_addr + size - 1) & ~(dlsize - 1));
if (ilsize == dlsize) {
/* flush I-cache & D-cache simultaneously */
while (1) {
- cache_op(HIT_WRITEBACK_INV_D, addr);
- cache_op(HIT_INVALIDATE_I, addr);
+ mips_cache(HIT_WRITEBACK_INV_D, addr);
+ mips_cache(HIT_INVALIDATE_I, addr);
if (addr == aend)
break;
addr += dlsize;
@@ -97,17 +72,17 @@ void flush_cache(ulong start_addr, ulong size)
/* flush D-cache */
while (1) {
- cache_op(HIT_WRITEBACK_INV_D, addr);
+ mips_cache(HIT_WRITEBACK_INV_D, addr);
if (addr == aend)
break;
addr += dlsize;
}
/* flush I-cache */
- addr = start_addr & ~(ilsize - 1);
- aend = (start_addr + size - 1) & ~(ilsize - 1);
+ addr = (const void *)(start_addr & ~(ilsize - 1));
+ aend = (const void *)((start_addr + size - 1) & ~(ilsize - 1));
while (1) {
- cache_op(HIT_INVALIDATE_I, addr);
+ mips_cache(HIT_INVALIDATE_I, addr);
if (addr == aend)
break;
addr += ilsize;
@@ -117,11 +92,11 @@ void flush_cache(ulong start_addr, ulong size)
void flush_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = dcache_line_size();
- unsigned long addr = start_addr & ~(lsize - 1);
- unsigned long aend = (stop - 1) & ~(lsize - 1);
+ const void *addr = (const void *)(start_addr & ~(lsize - 1));
+ const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
while (1) {
- cache_op(HIT_WRITEBACK_INV_D, addr);
+ mips_cache(HIT_WRITEBACK_INV_D, addr);
if (addr == aend)
break;
addr += lsize;
@@ -131,31 +106,13 @@ void flush_dcache_range(ulong start_addr, ulong stop)
void invalidate_dcache_range(ulong start_addr, ulong stop)
{
unsigned long lsize = dcache_line_size();
- unsigned long addr = start_addr & ~(lsize - 1);
- unsigned long aend = (stop - 1) & ~(lsize - 1);
+ const void *addr = (const void *)(start_addr & ~(lsize - 1));
+ const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
while (1) {
- cache_op(HIT_INVALIDATE_D, addr);
+ mips_cache(HIT_INVALIDATE_D, addr);
if (addr == aend)
break;
addr += lsize;
}
}
-
-void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
-{
- write_c0_entrylo0(low0);
- write_c0_pagemask(pagemask);
- write_c0_entrylo1(low1);
- write_c0_entryhi(hi);
- write_c0_index(index);
- tlb_write_indexed();
-}
-
-int cpu_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_SOC_AU1X00
- au1x00_enet_initialize(bis);
-#endif
- return 0;
-}
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/lib/cache_init.S
index 22bd844..137d728 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/lib/cache_init.S
@@ -18,18 +18,8 @@
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
#endif
-#define RA t9
-
#define INDEX_BASE CKSEG0
- .macro cache_op op addr
- .set push
- .set noreorder
- .set mips3
- cache \op, 0(\addr)
- .set pop
- .endm
-
.macro f_fill64 dst, offset, val
LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
@@ -51,56 +41,49 @@
#endif
.endm
-/*
- * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
- */
-LEAF(mips_init_icache)
- blez a1, 9f
- mtc0 zero, CP0_TAGLO
- /* clear tag to invalidate */
- PTR_LI t0, INDEX_BASE
- PTR_ADDU t1, t0, a1
-1: cache_op INDEX_STORE_TAG_I t0
- PTR_ADDU t0, a2
- bne t0, t1, 1b
- /* fill once, so data field parity is correct */
- PTR_LI t0, INDEX_BASE
-2: cache_op FILL t0
- PTR_ADDU t0, a2
- bne t0, t1, 2b
- /* invalidate again - prudent but not strictly neccessary */
- PTR_LI t0, INDEX_BASE
-1: cache_op INDEX_STORE_TAG_I t0
- PTR_ADDU t0, a2
- bne t0, t1, 1b
-9: jr ra
- END(mips_init_icache)
-
-/*
- * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
- */
-LEAF(mips_init_dcache)
- blez a1, 9f
- mtc0 zero, CP0_TAGLO
- /* clear all tags */
- PTR_LI t0, INDEX_BASE
- PTR_ADDU t1, t0, a1
-1: cache_op INDEX_STORE_TAG_D t0
- PTR_ADDU t0, a2
- bne t0, t1, 1b
- /* load from each line (in cached space) */
- PTR_LI t0, INDEX_BASE
-2: LONG_L zero, 0(t0)
- PTR_ADDU t0, a2
- bne t0, t1, 2b
- /* clear all tags */
- PTR_LI t0, INDEX_BASE
-1: cache_op INDEX_STORE_TAG_D t0
- PTR_ADDU t0, a2
- bne t0, t1, 1b
-9: jr ra
- END(mips_init_dcache)
+ .macro cache_loop curr, end, line_sz, op
+10: cache \op, 0(\curr)
+ PTR_ADDU \curr, \curr, \line_sz
+ bne \curr, \end, 10b
+ .endm
+ .macro l1_info sz, line_sz, off
+ .set push
+ .set noat
+
+ mfc0 $1, CP0_CONFIG, 1
+
+ /* detect line size */
+ srl \line_sz, $1, \off + MIPS_CONF1_DL_SHIFT - MIPS_CONF1_DA_SHIFT
+ andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
+ move \sz, zero
+ beqz \line_sz, 10f
+ li \sz, 2
+ sllv \line_sz, \sz, \line_sz
+
+ /* detect associativity */
+ srl \sz, $1, \off + MIPS_CONF1_DA_SHIFT - MIPS_CONF1_DA_SHIFT
+ andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
+ addi \sz, \sz, 1
+
+ /* sz *= line_sz */
+ mul \sz, \sz, \line_sz
+
+ /* detect log32(sets) */
+ srl $1, $1, \off + MIPS_CONF1_DS_SHIFT - MIPS_CONF1_DA_SHIFT
+ andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
+ addiu $1, $1, 1
+ andi $1, $1, 0x7
+
+ /* sz <<= log32(sets) */
+ sllv \sz, \sz, $1
+
+ /* sz *= 32 */
+ li $1, 32
+ mul \sz, \sz, $1
+10:
+ .set pop
+ .endm
/*
* mips_cache_reset - low level initialisation of the primary caches
*
@@ -115,75 +98,23 @@ LEAF(mips_init_dcache)
* RETURNS: N/A
*
*/
-NESTED(mips_cache_reset, 0, ra)
- move RA, ra
-
-#if !defined(CONFIG_SYS_ICACHE_SIZE) || !defined(CONFIG_SYS_DCACHE_SIZE) || \
- !defined(CONFIG_SYS_CACHELINE_SIZE)
- /* read Config1 for use below */
- mfc0 t5, CP0_CONFIG, 1
-#endif
-
-#ifdef CONFIG_SYS_CACHELINE_SIZE
- li t7, CONFIG_SYS_CACHELINE_SIZE
- li t8, CONFIG_SYS_CACHELINE_SIZE
-#else
- /* Detect I-cache line size. */
- srl t8, t5, MIPS_CONF1_IL_SHIFT
- andi t8, t8, (MIPS_CONF1_IL >> MIPS_CONF1_IL_SHIFT)
- beqz t8, 1f
- li t6, 2
- sllv t8, t6, t8
-
-1: /* Detect D-cache line size. */
- srl t7, t5, MIPS_CONF1_DL_SHIFT
- andi t7, t7, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
- beqz t7, 1f
- li t6, 2
- sllv t7, t6, t7
-1:
-#endif
-
+LEAF(mips_cache_reset)
#ifdef CONFIG_SYS_ICACHE_SIZE
li t2, CONFIG_SYS_ICACHE_SIZE
+ li t8, CONFIG_SYS_CACHELINE_SIZE
#else
- /* Detect I-cache size. */
- srl t6, t5, MIPS_CONF1_IS_SHIFT
- andi t6, t6, (MIPS_CONF1_IS >> MIPS_CONF1_IS_SHIFT)
- li t4, 32
- xori t2, t6, 0x7
- beqz t2, 1f
- addi t6, t6, 1
- sllv t4, t4, t6
-1: /* At this point t4 == I-cache sets. */
- mul t2, t4, t8
- srl t6, t5, MIPS_CONF1_IA_SHIFT
- andi t6, t6, (MIPS_CONF1_IA >> MIPS_CONF1_IA_SHIFT)
- addi t6, t6, 1
- /* At this point t6 == I-cache ways. */
- mul t2, t2, t6
+ l1_info t2, t8, MIPS_CONF1_IA_SHIFT
#endif
#ifdef CONFIG_SYS_DCACHE_SIZE
li t3, CONFIG_SYS_DCACHE_SIZE
+ li t9, CONFIG_SYS_CACHELINE_SIZE
#else
- /* Detect D-cache size. */
- srl t6, t5, MIPS_CONF1_DS_SHIFT
- andi t6, t6, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
- li t4, 32
- xori t3, t6, 0x7
- beqz t3, 1f
- addi t6, t6, 1
- sllv t4, t4, t6
-1: /* At this point t4 == I-cache sets. */
- mul t3, t4, t7
- srl t6, t5, MIPS_CONF1_DA_SHIFT
- andi t6, t6, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
- addi t6, t6, 1
- /* At this point t6 == I-cache ways. */
- mul t3, t3, t6
+ l1_info t3, t9, MIPS_CONF1_DA_SHIFT
#endif
+#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
+
/* Determine the largest L1 cache size */
#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
@@ -205,33 +136,62 @@ NESTED(mips_cache_reset, 0, ra)
f_fill64 a0, -64, zero
bne a0, a1, 2b
+#endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */
+
/*
- * The caches are probably in an indeterminate state,
- * so we force good parity into them by doing an
- * invalidate, load/fill, invalidate for each line.
+ * The TagLo registers used depend upon the CPU implementation, but the
+ * architecture requires that it is safe for software to write to both
+ * TagLo selects 0 & 2 covering supported cases.
*/
+ mtc0 zero, CP0_TAGLO
+ mtc0 zero, CP0_TAGLO, 2
/*
- * Assume bottom of RAM will generate good parity for the cache.
+ * The caches are probably in an indeterminate state, so we force good
+ * parity into them by doing an invalidate for each line. If
+ * CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is set then we'll proceed to
+ * perform a load/fill & a further invalidate for each line, assuming
+ * that the bottom of RAM (having just been cleared) will generate good
+ * parity for the cache.
*/
/*
* Initialize the I-cache first,
*/
- move a1, t2
- move a2, t8
- PTR_LA v1, mips_init_icache
- jalr v1
+ blez t2, 1f
+ PTR_LI t0, INDEX_BASE
+ PTR_ADDU t1, t0, t2
+ /* clear tag to invalidate */
+ cache_loop t0, t1, t8, INDEX_STORE_TAG_I
+#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
+ /* fill once, so data field parity is correct */
+ PTR_LI t0, INDEX_BASE
+ cache_loop t0, t1, t8, FILL
+ /* invalidate again - prudent but not strictly neccessary */
+ PTR_LI t0, INDEX_BASE
+ cache_loop t0, t1, t8, INDEX_STORE_TAG_I
+#endif
/*
* then initialize D-cache.
*/
- move a1, t3
- move a2, t7
- PTR_LA v1, mips_init_dcache
- jalr v1
+1: blez t3, 3f
+ PTR_LI t0, INDEX_BASE
+ PTR_ADDU t1, t0, t3
+ /* clear all tags */
+ cache_loop t0, t1, t9, INDEX_STORE_TAG_D
+#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
+ /* load from each line (in cached space) */
+ PTR_LI t0, INDEX_BASE
+2: LONG_L zero, 0(t0)
+ PTR_ADDU t0, t9
+ bne t0, t1, 2b
+ /* clear all tags */
+ PTR_LI t0, INDEX_BASE
+ cache_loop t0, t1, t9, INDEX_STORE_TAG_D
+#endif
- jr RA
+3: jr ra
END(mips_cache_reset)
/*
diff --git a/arch/mips/cpu/mips32/au1x00/Makefile b/arch/mips/mach-au1x00/Makefile
index c5643e7..c5643e7 100644
--- a/arch/mips/cpu/mips32/au1x00/Makefile
+++ b/arch/mips/mach-au1x00/Makefile
diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_eth.c b/arch/mips/mach-au1x00/au1x00_eth.c
index 4770f56..39c5b6b 100644
--- a/arch/mips/cpu/mips32/au1x00/au1x00_eth.c
+++ b/arch/mips/mach-au1x00/au1x00_eth.c
@@ -294,3 +294,9 @@ int au1x00_enet_initialize(bd_t *bis){
return 1;
}
+
+int cpu_eth_init(bd_t *bis)
+{
+ au1x00_enet_initialize(bis);
+ return 0;
+}
diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_ide.c b/arch/mips/mach-au1x00/au1x00_ide.c
index ba0b35d..ba0b35d 100644
--- a/arch/mips/cpu/mips32/au1x00/au1x00_ide.c
+++ b/arch/mips/mach-au1x00/au1x00_ide.c
diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_serial.c b/arch/mips/mach-au1x00/au1x00_serial.c
index 0463508..0463508 100644
--- a/arch/mips/cpu/mips32/au1x00/au1x00_serial.c
+++ b/arch/mips/mach-au1x00/au1x00_serial.c
diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c b/arch/mips/mach-au1x00/au1x00_usb_ohci.c
index 74bdb77..74bdb77 100644
--- a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c
+++ b/arch/mips/mach-au1x00/au1x00_usb_ohci.c
diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h b/arch/mips/mach-au1x00/au1x00_usb_ohci.h
index bb9f351..bb9f351 100644
--- a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h
+++ b/arch/mips/mach-au1x00/au1x00_usb_ohci.h
diff --git a/arch/mips/cpu/mips32/au1x00/config.mk b/arch/mips/mach-au1x00/config.mk
index 5c89129..5c89129 100644
--- a/arch/mips/cpu/mips32/au1x00/config.mk
+++ b/arch/mips/mach-au1x00/config.mk
diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h
index b079086..dee5f43 100644
--- a/arch/nds32/include/asm/u-boot-nds32.h
+++ b/arch/nds32/include/asm/u-boot-nds32.h
@@ -22,7 +22,6 @@ int cleanup_before_linux(void);
/* board/.../... */
int board_init(void);
-int dram_init(void);
/* cpu/.../interrupt.c */
void reset_timer_masked(void);
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index 71bb9d7..7202c3f 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -424,6 +424,14 @@ phys_size_t initdram(int board_type)
int write_recovery;
phys_size_t dram_size = 0;
+ if (IS_ENABLED(CONFIG_SYS_RAMBOOT)) {
+ /*
+ * Reduce RAM size to avoid overwriting memory used by
+ * current stack? Not sure what is happening.
+ */
+ return sdram_memsize() / 2;
+ }
+
num_dimm_banks = sizeof(iic0_dimm_addr);
/*------------------------------------------------------------------
diff --git a/arch/powerpc/cpu/ppc4xx/config.mk b/arch/powerpc/cpu/ppc4xx/config.mk
index f87c9dc..9cb41bb 100644
--- a/arch/powerpc/cpu/ppc4xx/config.mk
+++ b/arch/powerpc/cpu/ppc4xx/config.mk
@@ -7,10 +7,7 @@
PLATFORM_CPPFLAGS += -mstring -msoft-float
-cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h
-is440:=$(shell grep CONFIG_440 $(cfg))
-
-ifneq (,$(findstring CONFIG_440,$(is440)))
+ifneq (,$(CONFIG_440))
PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440
else
PLATFORM_CPPFLAGS += -Wa,-m405 -mcpu=405
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index e5a0e21..5f5c720 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -450,10 +450,12 @@ cpu_init_f (void)
PLB4Ax_ACR_RDP_4DEEP);
#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
+#ifndef CONFIG_SYS_GENERIC_BOARD
gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset((void *)gd, 0, sizeof(gd_t));
+#endif
}
/*
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 09a02d7..7a0f0d2 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -760,6 +760,15 @@ _start:
#endif
bl cpu_init_f /* run low-level CPU init code (from Flash) */
+#ifdef CONFIG_SYS_GENERIC_BOARD
+ mr r3, r1
+ bl board_init_f_mem
+ mr r1, r3
+ li r0,0
+ stwu r0, -4(r1)
+ stwu r0, -4(r1)
+#endif
+ li r3, 0
bl board_init_f
/* NOTREACHED - board_init_f() does not return */
@@ -1027,7 +1036,14 @@ _start:
GET_GOT /* initialize GOT access */
bl cpu_init_f /* run low-level CPU init code (from Flash) */
-
+#ifdef CONFIG_SYS_GENERIC_BOARD
+ mr r3, r1
+ bl board_init_f_mem
+ mr r1, r3
+ stwu r0, -4(r1)
+ stwu r0, -4(r1)
+#endif
+ li r3, 0
bl board_init_f /* run first part of init code (from Flash) */
/* NOTREACHED - board_init_f() does not return */
diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds
index 8773178..1980508 100644
--- a/arch/powerpc/cpu/ppc4xx/u-boot.lds
+++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds
@@ -76,9 +76,13 @@ SECTIONS
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
+ .data.init : {
+ *(.data.init)
+ . = ALIGN(256);
+ LONG(0) LONG(0) /* Extend u-boot.bin to here */
+ }
__init_end = .;
+ _end = .;
#ifndef CONFIG_SPL
#ifdef CONFIG_440
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
new file mode 100644
index 0000000..ad104b9
--- /dev/null
+++ b/arch/powerpc/dts/Makefile
@@ -0,0 +1,11 @@
+dtb-$(CONFIG_TARGET_CANYONLANDS) += arches.dtb canyonlands.dtb glacier.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
diff --git a/arch/powerpc/dts/arches.dts b/arch/powerpc/dts/arches.dts
new file mode 100644
index 0000000..bd5ebfd
--- /dev/null
+++ b/arch/powerpc/dts/arches.dts
@@ -0,0 +1,339 @@
+/*
+ * Device Tree Source for AMCC Arches (dual 460GT board)
+ *
+ * (C) Copyright 2008 Applied Micro Circuits Corporation
+ * Victor Gallardo <vgallardo@amcc.com>
+ * Adam Graham <agraham@amcc.com>
+ *
+ * Based on the glacier.dts file
+ * Stefan Roese <sr@denx.de>
+ * Copyright 2008 DENX Software Engineering
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "amcc,arches";
+ compatible = "amcc,arches";
+ dcr-parent = <&{/cpus/cpu@0}>;
+
+ aliases {
+ ethernet0 = &EMAC0;
+ ethernet1 = &EMAC1;
+ ethernet2 = &EMAC2;
+ serial0 = &UART0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ model = "PowerPC,460GT";
+ reg = <0x00000000>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ timebase-frequency = <0>; /* Filled in by U-Boot */
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ dcr-controller;
+ dcr-access-method = "native";
+ next-level-cache = <&L2C0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
+ };
+
+ UIC0: interrupt-controller0 {
+ compatible = "ibm,uic-460gt","ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0x0c0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = "ibm,uic-460gt","ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0x0d0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC2: interrupt-controller2 {
+ compatible = "ibm,uic-460gt","ibm,uic";
+ interrupt-controller;
+ cell-index = <2>;
+ dcr-reg = <0x0e0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC3: interrupt-controller3 {
+ compatible = "ibm,uic-460gt","ibm,uic";
+ interrupt-controller;
+ cell-index = <3>;
+ dcr-reg = <0x0f0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ SDR0: sdr {
+ compatible = "ibm,sdr-460gt";
+ dcr-reg = <0x00e 0x002>;
+ };
+
+ CPR0: cpr {
+ compatible = "ibm,cpr-460gt";
+ dcr-reg = <0x00c 0x002>;
+ };
+
+ L2C0: l2c {
+ compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
+ dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
+ 0x030 0x008>; /* L2 cache DCR's */
+ cache-line-size = <32>; /* 32 bytes */
+ cache-size = <262144>; /* L2, 256K */
+ interrupt-parent = <&UIC1>;
+ interrupts = <11 1>;
+ };
+
+ plb {
+ compatible = "ibm,plb-460gt", "ibm,plb4";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ SDRAM0: sdram {
+ compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
+ dcr-reg = <0x010 0x002>;
+ };
+
+ CRYPTO: crypto@180000 {
+ compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
+ reg = <4 0x00180000 0x80400>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x1d 0x4>;
+ };
+
+ MAL0: mcmal {
+ compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
+ dcr-reg = <0x180 0x062>;
+ num-tx-chans = <3>;
+ num-rx-chans = <24>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-parent = <&UIC2>;
+ interrupts = < /*TXEOB*/ 0x6 0x4
+ /*RXEOB*/ 0x7 0x4
+ /*SERR*/ 0x3 0x4
+ /*TXDE*/ 0x4 0x4
+ /*RXDE*/ 0x5 0x4>;
+ desc-base-addr-high = <0x8>;
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-460gt", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-460gt", "ibm,ebc";
+ dcr-reg = <0x012 0x002>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ /* ranges property is supplied by U-Boot */
+ interrupts = <0x6 0x4>;
+ interrupt-parent = <&UIC1>;
+
+ nor_flash@0,0 {
+ compatible = "amd,s29gl256n", "cfi-flash";
+ bank-width = <2>;
+ reg = <0x00000000 0x00000000 0x02000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "kernel";
+ reg = <0x00000000 0x001e0000>;
+ };
+ partition@1e0000 {
+ label = "dtb";
+ reg = <0x001e0000 0x00020000>;
+ };
+ partition@200000 {
+ label = "root";
+ reg = <0x00200000 0x00200000>;
+ };
+ partition@400000 {
+ label = "user";
+ reg = <0x00400000 0x01b60000>;
+ };
+ partition@1f60000 {
+ label = "env";
+ reg = <0x01f60000 0x00040000>;
+ };
+ partition@1fa0000 {
+ label = "u-boot";
+ reg = <0x01fa0000 0x00060000>;
+ };
+ };
+ };
+
+ UART0: serial@ef600300 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0xef600300 0x00000008>;
+ virtual-reg = <0xef600300>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC1>;
+ interrupts = <0x1 0x4>;
+ };
+
+ IIC0: i2c@ef600700 {
+ compatible = "ibm,iic-460gt", "ibm,iic";
+ reg = <0xef600700 0x00000014>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x2 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sttm@4a {
+ compatible = "ad,ad7414";
+ reg = <0x4a>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <0x0 0x8>;
+ };
+ };
+
+ IIC1: i2c@ef600800 {
+ compatible = "ibm,iic-460gt", "ibm,iic";
+ reg = <0xef600800 0x00000014>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x3 0x4>;
+ };
+
+ TAH0: emac-tah@ef601350 {
+ compatible = "ibm,tah-460gt", "ibm,tah";
+ reg = <0xef601350 0x00000030>;
+ };
+
+ TAH1: emac-tah@ef601450 {
+ compatible = "ibm,tah-460gt", "ibm,tah";
+ reg = <0xef601450 0x00000030>;
+ };
+
+ EMAC0: ethernet@ef600e00 {
+ device_type = "network";
+ compatible = "ibm,emac-460gt", "ibm,emac4sync";
+ interrupt-parent = <&EMAC0>;
+ interrupts = <0x0 0x1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
+ /*Wake*/ 0x1 &UIC2 0x14 0x4>;
+ reg = <0xef600e00 0x000000c4>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <9000>;
+ rx-fifo-size = <4096>;
+ tx-fifo-size = <2048>;
+ rx-fifo-size-gige = <16384>;
+ phy-mode = "sgmii";
+ phy-map = <0xffffffff>;
+ gpcs-address = <0x0000000a>;
+ tah-device = <&TAH0>;
+ tah-channel = <0>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ };
+
+ EMAC1: ethernet@ef600f00 {
+ device_type = "network";
+ compatible = "ibm,emac-460gt", "ibm,emac4sync";
+ interrupt-parent = <&EMAC1>;
+ interrupts = <0x0 0x1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
+ /*Wake*/ 0x1 &UIC2 0x15 0x4>;
+ reg = <0xef600f00 0x000000c4>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <1>;
+ mal-rx-channel = <8>;
+ cell-index = <1>;
+ max-frame-size = <9000>;
+ rx-fifo-size = <4096>;
+ tx-fifo-size = <2048>;
+ rx-fifo-size-gige = <16384>;
+ phy-mode = "sgmii";
+ phy-map = <0x00000000>;
+ gpcs-address = <0x0000000b>;
+ tah-device = <&TAH1>;
+ tah-channel = <1>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ mdio-device = <&EMAC0>;
+ };
+
+ EMAC2: ethernet@ef601100 {
+ device_type = "network";
+ compatible = "ibm,emac-460gt", "ibm,emac4sync";
+ interrupt-parent = <&EMAC2>;
+ interrupts = <0x0 0x1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
+ /*Wake*/ 0x1 &UIC2 0x16 0x4>;
+ reg = <0xef601100 0x000000c4>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <2>;
+ mal-rx-channel = <16>;
+ cell-index = <2>;
+ max-frame-size = <9000>;
+ rx-fifo-size = <4096>;
+ tx-fifo-size = <2048>;
+ rx-fifo-size-gige = <16384>;
+ tx-fifo-size-gige = <16384>; /* emac2&3 only */
+ phy-mode = "sgmii";
+ phy-map = <0x00000001>;
+ gpcs-address = <0x0000000C>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ mdio-device = <&EMAC0>;
+ };
+ };
+ };
+};
diff --git a/arch/powerpc/dts/canyonlands.dts b/arch/powerpc/dts/canyonlands.dts
new file mode 100644
index 0000000..0a2f5d7
--- /dev/null
+++ b/arch/powerpc/dts/canyonlands.dts
@@ -0,0 +1,561 @@
+/*
+ * Device Tree Source for AMCC Canyonlands (460EX)
+ *
+ * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "amcc,canyonlands";
+ compatible = "amcc,canyonlands";
+ dcr-parent = <&{/cpus/cpu@0}>;
+
+ aliases {
+ ethernet0 = &EMAC0;
+ ethernet1 = &EMAC1;
+ serial0 = &UART0;
+ serial1 = &UART1;
+ };
+
+ chosen {
+ stdout-path = &UART0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ model = "PowerPC,460EX";
+ reg = <0x00000000>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ timebase-frequency = <0>; /* Filled in by U-Boot */
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ dcr-controller;
+ dcr-access-method = "native";
+ next-level-cache = <&L2C0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
+ };
+
+ UIC0: interrupt-controller0 {
+ compatible = "ibm,uic-460ex","ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0x0c0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = "ibm,uic-460ex","ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0x0d0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC2: interrupt-controller2 {
+ compatible = "ibm,uic-460ex","ibm,uic";
+ interrupt-controller;
+ cell-index = <2>;
+ dcr-reg = <0x0e0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC3: interrupt-controller3 {
+ compatible = "ibm,uic-460ex","ibm,uic";
+ interrupt-controller;
+ cell-index = <3>;
+ dcr-reg = <0x0f0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ SDR0: sdr {
+ compatible = "ibm,sdr-460ex";
+ dcr-reg = <0x00e 0x002>;
+ };
+
+ CPR0: cpr {
+ compatible = "ibm,cpr-460ex";
+ dcr-reg = <0x00c 0x002>;
+ };
+
+ CPM0: cpm {
+ compatible = "ibm,cpm";
+ dcr-access-method = "native";
+ dcr-reg = <0x160 0x003>;
+ unused-units = <0x00000100>;
+ idle-doze = <0x02000000>;
+ standby = <0xfeff791d>;
+ };
+
+ L2C0: l2c {
+ compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
+ dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
+ 0x030 0x008>; /* L2 cache DCR's */
+ cache-line-size = <32>; /* 32 bytes */
+ cache-size = <262144>; /* L2, 256K */
+ interrupt-parent = <&UIC1>;
+ interrupts = <11 1>;
+ };
+
+ plb {
+ compatible = "ibm,plb-460ex", "ibm,plb4";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ SDRAM0: sdram {
+ compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
+ dcr-reg = <0x010 0x002>;
+ };
+
+ CRYPTO: crypto@180000 {
+ compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
+ reg = <4 0x00180000 0x80400>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x1d 0x4>;
+ };
+
+ HWRNG: hwrng@110000 {
+ compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
+ reg = <4 0x00110000 0x50>;
+ };
+
+ MAL0: mcmal {
+ compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
+ dcr-reg = <0x180 0x062>;
+ num-tx-chans = <2>;
+ num-rx-chans = <16>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-parent = <&UIC2>;
+ interrupts = < /*TXEOB*/ 0x6 0x4
+ /*RXEOB*/ 0x7 0x4
+ /*SERR*/ 0x3 0x4
+ /*TXDE*/ 0x4 0x4
+ /*RXDE*/ 0x5 0x4>;
+ };
+
+ USB0: ehci@bffd0400 {
+ compatible = "ibm,usb-ehci-460ex", "usb-ehci";
+ interrupt-parent = <&UIC2>;
+ interrupts = <0x1d 4>;
+ reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
+ };
+
+ USB1: usb@bffd0000 {
+ compatible = "ohci-le";
+ reg = <4 0xbffd0000 0x60>;
+ interrupt-parent = <&UIC2>;
+ interrupts = <0x1e 4>;
+ };
+
+ USBOTG0: usbotg@bff80000 {
+ compatible = "amcc,dwc-otg";
+ reg = <0x4 0xbff80000 0x10000>;
+ interrupt-parent = <&USBOTG0>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x1 0x2>;
+ interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
+ /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
+ /* DMA */ 0x2 &UIC0 0xc 0x4>;
+ };
+
+ SATA0: sata@bffd1000 {
+ compatible = "amcc,sata-460ex";
+ reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>;
+ interrupt-parent = <&UIC3>;
+ interrupts = <0x0 0x4 /* SATA */
+ 0x5 0x4>; /* AHBDMA */
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-460ex", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-460ex", "ibm,ebc";
+ dcr-reg = <0x012 0x002>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ /* ranges property is supplied by U-Boot */
+ interrupts = <0x6 0x4>;
+ interrupt-parent = <&UIC1>;
+
+ nor_flash@0,0 {
+ compatible = "amd,s29gl512n", "cfi-flash";
+ bank-width = <2>;
+ reg = <0x00000000 0x00000000 0x04000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "kernel";
+ reg = <0x00000000 0x001e0000>;
+ };
+ partition@1e0000 {
+ label = "dtb";
+ reg = <0x001e0000 0x00020000>;
+ };
+ partition@200000 {
+ label = "ramdisk";
+ reg = <0x00200000 0x01400000>;
+ };
+ partition@1600000 {
+ label = "jffs2";
+ reg = <0x01600000 0x00400000>;
+ };
+ partition@1a00000 {
+ label = "user";
+ reg = <0x01a00000 0x02560000>;
+ };
+ partition@3f60000 {
+ label = "env";
+ reg = <0x03f60000 0x00040000>;
+ };
+ partition@3fa0000 {
+ label = "u-boot";
+ reg = <0x03fa0000 0x00060000>;
+ };
+ };
+
+ cpld@2,0 {
+ compatible = "amcc,ppc460ex-bcsr";
+ reg = <2 0x0 0x9>;
+ };
+
+ ndfc@3,0 {
+ compatible = "ibm,ndfc";
+ reg = <0x00000003 0x00000000 0x00002000>;
+ ccr = <0x00001000>;
+ bank-settings = <0x80002222>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x00000000 0x00100000>;
+ };
+ partition@100000 {
+ label = "user";
+ reg = <0x00000000 0x03f00000>;
+ };
+ };
+ };
+ };
+
+ UART0: serial@ef600300 {
+ device_type = "serial";
+ reg-shift = <0>;
+ compatible = "ns16550";
+ reg = <0xef600300 0x00000008>;
+ virtual-reg = <0xef600300>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC1>;
+ interrupts = <0x1 0x4>;
+ };
+
+ UART1: serial@ef600400 {
+ device_type = "serial";
+ reg-shift = <0>;
+ compatible = "ns16550";
+ reg = <0xef600400 0x00000008>;
+ virtual-reg = <0xef600400>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x1 0x4>;
+ };
+
+ IIC0: i2c@ef600700 {
+ compatible = "ibm,iic-460ex", "ibm,iic";
+ reg = <0xef600700 0x00000014>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x2 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rtc@68 {
+ compatible = "stm,m41t80";
+ reg = <0x68>;
+ interrupt-parent = <&UIC2>;
+ interrupts = <0x19 0x8>;
+ };
+ sttm@48 {
+ compatible = "ad,ad7414";
+ reg = <0x48>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <0x14 0x8>;
+ };
+ };
+
+ IIC1: i2c@ef600800 {
+ compatible = "ibm,iic-460ex", "ibm,iic";
+ reg = <0xef600800 0x00000014>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x3 0x4>;
+ };
+
+ GPIO0: gpio@ef600b00 {
+ compatible = "ibm,ppc4xx-gpio";
+ reg = <0xef600b00 0x00000048>;
+ gpio-controller;
+ };
+
+ ZMII0: emac-zmii@ef600d00 {
+ compatible = "ibm,zmii-460ex", "ibm,zmii";
+ reg = <0xef600d00 0x0000000c>;
+ };
+
+ RGMII0: emac-rgmii@ef601500 {
+ compatible = "ibm,rgmii-460ex", "ibm,rgmii";
+ reg = <0xef601500 0x00000008>;
+ has-mdio;
+ };
+
+ TAH0: emac-tah@ef601350 {
+ compatible = "ibm,tah-460ex", "ibm,tah";
+ reg = <0xef601350 0x00000030>;
+ };
+
+ TAH1: emac-tah@ef601450 {
+ compatible = "ibm,tah-460ex", "ibm,tah";
+ reg = <0xef601450 0x00000030>;
+ };
+
+ EMAC0: ethernet@ef600e00 {
+ device_type = "network";
+ compatible = "ibm,emac-460ex", "ibm,emac4sync";
+ interrupt-parent = <&EMAC0>;
+ interrupts = <0x0 0x1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
+ /*Wake*/ 0x1 &UIC2 0x14 0x4>;
+ reg = <0xef600e00 0x000000c4>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <9000>;
+ rx-fifo-size = <4096>;
+ tx-fifo-size = <2048>;
+ rx-fifo-size-gige = <16384>;
+ phy-mode = "rgmii";
+ phy-map = <0x00000000>;
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <0>;
+ tah-device = <&TAH0>;
+ tah-channel = <0>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ };
+
+ EMAC1: ethernet@ef600f00 {
+ device_type = "network";
+ compatible = "ibm,emac-460ex", "ibm,emac4sync";
+ interrupt-parent = <&EMAC1>;
+ interrupts = <0x0 0x1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
+ /*Wake*/ 0x1 &UIC2 0x15 0x4>;
+ reg = <0xef600f00 0x000000c4>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <1>;
+ mal-rx-channel = <8>;
+ cell-index = <1>;
+ max-frame-size = <9000>;
+ rx-fifo-size = <4096>;
+ tx-fifo-size = <2048>;
+ rx-fifo-size-gige = <16384>;
+ phy-mode = "rgmii";
+ phy-map = <0x00000000>;
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <1>;
+ tah-device = <&TAH1>;
+ tah-channel = <1>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ mdio-device = <&EMAC0>;
+ };
+ };
+
+ PCIX0: pci@c0ec00000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
+ primary;
+ large-inbound-windows;
+ enable-msi-hole;
+ reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
+ 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
+ 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
+ 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
+ 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
+ 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
+ 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+ /* This drives busses 0 to 0x3f */
+ bus-range = <0x0 0x3f>;
+
+ /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
+ };
+
+ PCIE0: pciex@d00000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+ primary;
+ port = <0x0>; /* port number */
+ reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
+ 0x0000000c 0x08010000 0x00001000>; /* Registers */
+ dcr-reg = <0x100 0x020>;
+ sdr-base = <0x300>;
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
+ 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
+ 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+ /* This drives busses 40 to 0x7f */
+ bus-range = <0x40 0x7f>;
+
+ /* Legacy interrupts (note the weird polarity, the bridge seems
+ * to invert PCIe legacy interrupts).
+ * We are de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers.
+ * The real slot is on idsel 0, so the swizzling is 1:1
+ */
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <
+ 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
+ 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
+ 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
+ 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
+ };
+
+ PCIE1: pciex@d20000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+ primary;
+ port = <0x1>; /* port number */
+ reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
+ 0x0000000c 0x08011000 0x00001000>; /* Registers */
+ dcr-reg = <0x120 0x020>;
+ sdr-base = <0x340>;
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
+ 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
+ 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+ /* This drives busses 80 to 0xbf */
+ bus-range = <0x80 0xbf>;
+
+ /* Legacy interrupts (note the weird polarity, the bridge seems
+ * to invert PCIe legacy interrupts).
+ * We are de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers.
+ * The real slot is on idsel 0, so the swizzling is 1:1
+ */
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <
+ 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
+ 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
+ 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
+ 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
+ };
+
+ MSI: ppc4xx-msi@C10000000 {
+ compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
+ reg = < 0xC 0x10000000 0x100>;
+ sdr-base = <0x36C>;
+ msi-data = <0x00000000>;
+ msi-mask = <0x44440000>;
+ interrupt-count = <3>;
+ interrupts = <0 1 2 3>;
+ interrupt-parent = <&UIC3>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0 &UIC3 0x18 1
+ 1 &UIC3 0x19 1
+ 2 &UIC3 0x1A 1
+ 3 &UIC3 0x1B 1>;
+ };
+ };
+};
diff --git a/arch/powerpc/dts/glacier.dts b/arch/powerpc/dts/glacier.dts
new file mode 100644
index 0000000..bb4e819
--- /dev/null
+++ b/arch/powerpc/dts/glacier.dts
@@ -0,0 +1,582 @@
+/*
+ * Device Tree Source for AMCC Glacier (460GT)
+ *
+ * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "amcc,glacier";
+ compatible = "amcc,glacier";
+ dcr-parent = <&{/cpus/cpu@0}>;
+
+ aliases {
+ ethernet0 = &EMAC0;
+ ethernet1 = &EMAC1;
+ ethernet2 = &EMAC2;
+ ethernet3 = &EMAC3;
+ serial0 = &UART0;
+ serial1 = &UART1;
+ };
+
+ chosen {
+ stdout-path = &UART0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ model = "PowerPC,460GT";
+ reg = <0x00000000>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ timebase-frequency = <0>; /* Filled in by U-Boot */
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ dcr-controller;
+ dcr-access-method = "native";
+ next-level-cache = <&L2C0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
+ };
+
+ UIC0: interrupt-controller0 {
+ compatible = "ibm,uic-460gt","ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0x0c0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = "ibm,uic-460gt","ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0x0d0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC2: interrupt-controller2 {
+ compatible = "ibm,uic-460gt","ibm,uic";
+ interrupt-controller;
+ cell-index = <2>;
+ dcr-reg = <0x0e0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC3: interrupt-controller3 {
+ compatible = "ibm,uic-460gt","ibm,uic";
+ interrupt-controller;
+ cell-index = <3>;
+ dcr-reg = <0x0f0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ SDR0: sdr {
+ compatible = "ibm,sdr-460gt";
+ dcr-reg = <0x00e 0x002>;
+ };
+
+ CPR0: cpr {
+ compatible = "ibm,cpr-460gt";
+ dcr-reg = <0x00c 0x002>;
+ };
+
+ L2C0: l2c {
+ compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
+ dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
+ 0x030 0x008>; /* L2 cache DCR's */
+ cache-line-size = <32>; /* 32 bytes */
+ cache-size = <262144>; /* L2, 256K */
+ interrupt-parent = <&UIC1>;
+ interrupts = <11 1>;
+ };
+
+ plb {
+ compatible = "ibm,plb-460gt", "ibm,plb4";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ SDRAM0: sdram {
+ compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
+ dcr-reg = <0x010 0x002>;
+ };
+
+ CRYPTO: crypto@180000 {
+ compatible = "amcc,ppc460gt-crypto", "amcc,ppc460ex-crypto",
+ "amcc,ppc4xx-crypto";
+ reg = <4 0x00180000 0x80400>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x1d 0x4>;
+ };
+
+ HWRNG: hwrng@110000 {
+ compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
+ reg = <4 0x00110000 0x50>;
+ };
+
+ MAL0: mcmal {
+ compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
+ dcr-reg = <0x180 0x062>;
+ num-tx-chans = <4>;
+ num-rx-chans = <32>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-parent = <&UIC2>;
+ interrupts = < /*TXEOB*/ 0x6 0x4
+ /*RXEOB*/ 0x7 0x4
+ /*SERR*/ 0x3 0x4
+ /*TXDE*/ 0x4 0x4
+ /*RXDE*/ 0x5 0x4>;
+ desc-base-addr-high = <0x8>;
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-460gt", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-460gt", "ibm,ebc";
+ dcr-reg = <0x012 0x002>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ /* ranges property is supplied by U-Boot */
+ interrupts = <0x6 0x4>;
+ interrupt-parent = <&UIC1>;
+
+ nor_flash@0,0 {
+ compatible = "amd,s29gl512n", "cfi-flash";
+ bank-width = <2>;
+ reg = <0x00000000 0x00000000 0x04000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "kernel";
+ reg = <0x00000000 0x001e0000>;
+ };
+ partition@1e0000 {
+ label = "dtb";
+ reg = <0x001e0000 0x00020000>;
+ };
+ partition@200000 {
+ label = "ramdisk";
+ reg = <0x00200000 0x01400000>;
+ };
+ partition@1600000 {
+ label = "jffs2";
+ reg = <0x01600000 0x00400000>;
+ };
+ partition@1a00000 {
+ label = "user";
+ reg = <0x01a00000 0x02560000>;
+ };
+ partition@3f60000 {
+ label = "env";
+ reg = <0x03f60000 0x00040000>;
+ };
+ partition@3fa0000 {
+ label = "u-boot";
+ reg = <0x03fa0000 0x00060000>;
+ };
+ };
+
+ ndfc@3,0 {
+ compatible = "ibm,ndfc";
+ reg = <0x00000003 0x00000000 0x00002000>;
+ ccr = <0x00001000>;
+ bank-settings = <0x80002222>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x00000000 0x00100000>;
+ };
+ partition@100000 {
+ label = "user";
+ reg = <0x00000000 0x03f00000>;
+ };
+ };
+ };
+ };
+
+ UART0: serial@ef600300 {
+ device_type = "serial";
+ reg-shift = <0>;
+ compatible = "ns16550";
+ reg = <0xef600300 0x00000008>;
+ virtual-reg = <0xef600300>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC1>;
+ interrupts = <0x1 0x4>;
+ };
+
+ UART1: serial@ef600400 {
+ device_type = "serial";
+ reg-shift = <0>;
+ compatible = "ns16550";
+ reg = <0xef600400 0x00000008>;
+ virtual-reg = <0xef600400>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x1 0x4>;
+ };
+
+ UART2: serial@ef600500 {
+ device_type = "serial";
+ reg-shift = <0>;
+ compatible = "ns16550";
+ reg = <0xef600500 0x00000008>;
+ virtual-reg = <0xef600500>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC1>;
+ interrupts = <28 0x4>;
+ };
+
+ UART3: serial@ef600600 {
+ device_type = "serial";
+ reg-shift = <0>;
+ compatible = "ns16550";
+ reg = <0xef600600 0x00000008>;
+ virtual-reg = <0xef600600>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC1>;
+ interrupts = <29 0x4>;
+ };
+
+ IIC0: i2c@ef600700 {
+ compatible = "ibm,iic-460gt", "ibm,iic";
+ reg = <0xef600700 0x00000014>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x2 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rtc@68 {
+ compatible = "stm,m41t80";
+ reg = <0x68>;
+ interrupt-parent = <&UIC2>;
+ interrupts = <0x19 0x8>;
+ };
+ sttm@48 {
+ compatible = "ad,ad7414";
+ reg = <0x48>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <0x14 0x8>;
+ };
+ };
+
+ IIC1: i2c@ef600800 {
+ compatible = "ibm,iic-460gt", "ibm,iic";
+ reg = <0xef600800 0x00000014>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x3 0x4>;
+ };
+
+ ZMII0: emac-zmii@ef600d00 {
+ compatible = "ibm,zmii-460gt", "ibm,zmii";
+ reg = <0xef600d00 0x0000000c>;
+ };
+
+ RGMII0: emac-rgmii@ef601500 {
+ compatible = "ibm,rgmii-460gt", "ibm,rgmii";
+ reg = <0xef601500 0x00000008>;
+ has-mdio;
+ };
+
+ RGMII1: emac-rgmii@ef601600 {
+ compatible = "ibm,rgmii-460gt", "ibm,rgmii";
+ reg = <0xef601600 0x00000008>;
+ has-mdio;
+ };
+
+ TAH0: emac-tah@ef601350 {
+ compatible = "ibm,tah-460gt", "ibm,tah";
+ reg = <0xef601350 0x00000030>;
+ };
+
+ TAH1: emac-tah@ef601450 {
+ compatible = "ibm,tah-460gt", "ibm,tah";
+ reg = <0xef601450 0x00000030>;
+ };
+
+ EMAC0: ethernet@ef600e00 {
+ device_type = "network";
+ compatible = "ibm,emac-460gt", "ibm,emac4sync";
+ interrupt-parent = <&EMAC0>;
+ interrupts = <0x0 0x1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
+ /*Wake*/ 0x1 &UIC2 0x14 0x4>;
+ reg = <0xef600e00 0x000000c4>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <9000>;
+ rx-fifo-size = <4096>;
+ tx-fifo-size = <2048>;
+ rx-fifo-size-gige = <16384>;
+ phy-mode = "rgmii";
+ phy-map = <0x00000000>;
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <0>;
+ tah-device = <&TAH0>;
+ tah-channel = <0>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ };
+
+ EMAC1: ethernet@ef600f00 {
+ device_type = "network";
+ compatible = "ibm,emac-460gt", "ibm,emac4sync";
+ interrupt-parent = <&EMAC1>;
+ interrupts = <0x0 0x1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
+ /*Wake*/ 0x1 &UIC2 0x15 0x4>;
+ reg = <0xef600f00 0x000000c4>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <1>;
+ mal-rx-channel = <8>;
+ cell-index = <1>;
+ max-frame-size = <9000>;
+ rx-fifo-size = <4096>;
+ tx-fifo-size = <2048>;
+ rx-fifo-size-gige = <16384>;
+ phy-mode = "rgmii";
+ phy-map = <0x00000000>;
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <1>;
+ tah-device = <&TAH1>;
+ tah-channel = <1>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ mdio-device = <&EMAC0>;
+ };
+
+ EMAC2: ethernet@ef601100 {
+ device_type = "network";
+ compatible = "ibm,emac-460gt", "ibm,emac4sync";
+ interrupt-parent = <&EMAC2>;
+ interrupts = <0x0 0x1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
+ /*Wake*/ 0x1 &UIC2 0x16 0x4>;
+ reg = <0xef601100 0x000000c4>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <2>;
+ mal-rx-channel = <16>;
+ cell-index = <2>;
+ max-frame-size = <9000>;
+ rx-fifo-size = <4096>;
+ tx-fifo-size = <2048>;
+ rx-fifo-size-gige = <16384>;
+ tx-fifo-size-gige = <16384>; /* emac2&3 only */
+ phy-mode = "rgmii";
+ phy-map = <0x00000000>;
+ rgmii-device = <&RGMII1>;
+ rgmii-channel = <0>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ mdio-device = <&EMAC0>;
+ };
+
+ EMAC3: ethernet@ef601200 {
+ device_type = "network";
+ compatible = "ibm,emac-460gt", "ibm,emac4sync";
+ interrupt-parent = <&EMAC3>;
+ interrupts = <0x0 0x1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4
+ /*Wake*/ 0x1 &UIC2 0x17 0x4>;
+ reg = <0xef601200 0x000000c4>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <3>;
+ mal-rx-channel = <24>;
+ cell-index = <3>;
+ max-frame-size = <9000>;
+ rx-fifo-size = <4096>;
+ tx-fifo-size = <2048>;
+ rx-fifo-size-gige = <16384>;
+ tx-fifo-size-gige = <16384>; /* emac2&3 only */
+ phy-mode = "rgmii";
+ phy-map = <0x00000000>;
+ rgmii-device = <&RGMII1>;
+ rgmii-channel = <1>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ mdio-device = <&EMAC0>;
+ };
+ };
+
+ PCIX0: pci@c0ec00000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
+ primary;
+ large-inbound-windows;
+ enable-msi-hole;
+ reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
+ 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
+ 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
+ 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
+ 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
+ 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
+ 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+ /* This drives busses 0 to 0x3f */
+ bus-range = <0x0 0x3f>;
+
+ /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
+ };
+
+ PCIE0: pciex@d00000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+ primary;
+ port = <0x0>; /* port number */
+ reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
+ 0x0000000c 0x08010000 0x00001000>; /* Registers */
+ dcr-reg = <0x100 0x020>;
+ sdr-base = <0x300>;
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
+ 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
+ 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+ /* This drives busses 40 to 0x7f */
+ bus-range = <0x40 0x7f>;
+
+ /* Legacy interrupts (note the weird polarity, the bridge seems
+ * to invert PCIe legacy interrupts).
+ * We are de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers.
+ * The real slot is on idsel 0, so the swizzling is 1:1
+ */
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <
+ 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
+ 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
+ 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
+ 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
+ };
+
+ PCIE1: pciex@d20000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+ primary;
+ port = <0x1>; /* port number */
+ reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
+ 0x0000000c 0x08011000 0x00001000>; /* Registers */
+ dcr-reg = <0x120 0x020>;
+ sdr-base = <0x340>;
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
+ 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
+ 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+ /* This drives busses 80 to 0xbf */
+ bus-range = <0x80 0xbf>;
+
+ /* Legacy interrupts (note the weird polarity, the bridge seems
+ * to invert PCIe legacy interrupts).
+ * We are de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers.
+ * The real slot is on idsel 0, so the swizzling is 1:1
+ */
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <
+ 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
+ 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
+ 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
+ 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
+ };
+ };
+};
diff --git a/arch/powerpc/include/asm/arch-ppc4xx/gpio.h b/arch/powerpc/include/asm/arch-ppc4xx/gpio.h
new file mode 100644
index 0000000..3d960c3
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-ppc4xx/gpio.h
@@ -0,0 +1,7 @@
+/*
+ * (C) Copyright 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* This is empty for now as we don't support the generic GPIO interface */
diff --git a/arch/powerpc/include/asm/linkage.h b/arch/powerpc/include/asm/linkage.h
new file mode 100644
index 0000000..559b42e
--- /dev/null
+++ b/arch/powerpc/include/asm/linkage.h
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* We don't need anything here at present */
diff --git a/arch/powerpc/include/asm/ppc460ex_gt.h b/arch/powerpc/include/asm/ppc460ex_gt.h
index f41df0d..ea019aa 100644
--- a/arch/powerpc/include/asm/ppc460ex_gt.h
+++ b/arch/powerpc/include/asm/ppc460ex_gt.h
@@ -19,10 +19,12 @@
/* Memory mapped registers */
#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
+#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
+#endif
#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 0f62982..05b22bb 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -40,6 +40,7 @@ obj-y += extable.o
obj-y += interrupts.o
obj-$(CONFIG_CMD_KGDB) += kgdb.o
obj-$(CONFIG_CMD_IDE) += ide.o
+obj-y += stack.o
obj-y += time.o
# Don't include the MPC5xxx special memcpy into the
diff --git a/arch/powerpc/lib/stack.c b/arch/powerpc/lib/stack.c
new file mode 100644
index 0000000..1985f03
--- /dev/null
+++ b/arch/powerpc/lib/stack.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2015 Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_reserve_stacks(void)
+{
+ ulong *s;
+
+ /* setup stack pointer for exceptions */
+ gd->irq_sp = gd->start_addr_sp;
+
+ /* Clear initial stack frame */
+ s = (ulong *)gd->start_addr_sp;
+ *s = 0; /* Terminate back chain */
+ *++s = 0; /* NULL return address */
+
+ return 0;
+}
diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig
index 3057325..2098b9c 100644
--- a/arch/sandbox/Kconfig
+++ b/arch/sandbox/Kconfig
@@ -10,4 +10,28 @@ config SYS_BOARD
config SYS_CONFIG_NAME
default "sandbox"
+config DM
+ default y
+
+config DM_GPIO
+ default y
+
+config DM_SERIAL
+ default y
+
+config DM_CROS_EC
+ default y
+
+config DM_SPI
+ default y
+
+config DM_SPI_FLASH
+ default y
+
+config DM_I2C
+ default y
+
+config DM_TEST
+ default y
+
endmenu
diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index e38a44b..7b84f02 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -5,10 +5,16 @@ PLATFORM_CPPFLAGS += -D__SANDBOX__ -U_FORTIFY_SOURCE
PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM -DCONFIG_SYS_GENERIC_BOARD
PLATFORM_LIBS += -lrt
+# Define this to avoid linking with SDL, which requires SDL libraries
+# This can solve 'sdl-config: Command not found' errors
+ifneq ($(NO_SDL),)
+PLATFORM_CPPFLAGS += -DSANDBOX_NO_SDL
+else
ifdef CONFIG_SANDBOX_SDL
PLATFORM_LIBS += $(shell sdl-config --libs)
PLATFORM_CPPFLAGS += $(shell sdl-config --cflags)
endif
+endif
# Support generic board on sandbox
__HAVE_ARCH_GENERIC_BOARD := y
@@ -18,9 +24,3 @@ cmd_u-boot__ = $(CC) -o $@ -T u-boot.lds \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
CONFIG_ARCH_DEVICE_TREE := sandbox
-
-# Define this to avoid linking with SDL, which requires SDL libraries
-# This can solve 'sdl-config: Command not found' errors
-ifneq ($(NO_SDL),)
-PLATFORM_CPPFLAGS += -DSANDBOX_NO_SDL
-endif
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index 42353d8..ec01040 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <os.h>
#include <cli.h>
+#include <malloc.h>
#include <asm/getopt.h>
#include <asm/io.h>
#include <asm/sections.h>
@@ -77,11 +78,13 @@ int sandbox_main_loop_init(void)
/* Execute command if required */
if (state->cmd) {
+ int retval;
+
cli_init();
- run_command_list(state->cmd, -1, 0);
+ retval = run_command_list(state->cmd, -1, 0);
if (!state->interactive)
- os_exit(state->exit_type);
+ os_exit(retval);
}
return 0;
@@ -102,6 +105,25 @@ static int sandbox_cmdline_cb_fdt(struct sandbox_state *state, const char *arg)
}
SANDBOX_CMDLINE_OPT_SHORT(fdt, 'd', 1, "Specify U-Boot's control FDT");
+static int sandbox_cmdline_cb_default_fdt(struct sandbox_state *state,
+ const char *arg)
+{
+ const char *fmt = "%s.dtb";
+ char *fname;
+ int len;
+
+ len = strlen(state->argv[0]) + strlen(fmt) + 1;
+ fname = os_malloc(len);
+ if (!fname)
+ return -ENOMEM;
+ snprintf(fname, len, fmt, state->argv[0]);
+ state->fdt_fname = fname;
+
+ return 0;
+}
+SANDBOX_CMDLINE_OPT_SHORT(default_fdt, 'D', 0,
+ "Use the default u-boot.dtb control FDT in U-Boot directory");
+
static int sandbox_cmdline_cb_interactive(struct sandbox_state *state,
const char *arg)
{
diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index ba73b7e..033958c 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -13,11 +13,6 @@
static struct sandbox_state main_state;
static struct sandbox_state *state; /* Pointer to current state record */
-void state_record_exit(enum exit_type_id exit_type)
-{
- state->exit_type = exit_type;
-}
-
static int state_ensure_space(int extra_size)
{
void *blob = state->state_fdt;
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 11748ae..9ce31bf 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -19,6 +19,7 @@
colour = "cyan";
sides = <3>;
character = <83>;
+ light-gpios = <&gpio_a 2>, <&gpio_b 6 0>;
};
square {
compatible = "demo-shape";
@@ -73,10 +74,8 @@
cros-ec-keyb {
compatible = "google,cros-ec-keyb";
- google,key-rows = <8>;
- google,key-columns = <13>;
- google,repeat-delay-ms = <240>;
- google,repeat-rate-ms = <30>;
+ keypad,num-rows = <8>;
+ keypad,num-columns = <13>;
google,ghost-filter;
/*
* Keymap entries take the form of 0xRRCCKKKK where
@@ -126,7 +125,7 @@
0x070b0067 0x070c0069>;
};
- gpio_a: gpios {
+ gpio_a: gpios@0 {
gpio-controller;
compatible = "sandbox,gpio";
#gpio-cells = <1>;
@@ -134,6 +133,14 @@
num-gpios = <20>;
};
+ gpio_b: gpios@1 {
+ gpio-controller;
+ compatible = "sandbox,gpio";
+ #gpio-cells = <2>;
+ gpio-bank-name = "b";
+ num-gpios = <10>;
+ };
+
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
index 32d55cc..a0c24ba 100644
--- a/arch/sandbox/include/asm/state.h
+++ b/arch/sandbox/include/asm/state.h
@@ -10,13 +10,6 @@
#include <stdbool.h>
#include <linux/stringify.h>
-/* How we exited U-Boot */
-enum exit_type_id {
- STATE_EXIT_NORMAL,
- STATE_EXIT_COLD_REBOOT,
- STATE_EXIT_POWER_OFF,
-};
-
/**
* Selects the behavior of the serial terminal.
*
@@ -50,7 +43,6 @@ struct sandbox_state {
const char *cmd; /* Command to execute */
bool interactive; /* Enable cmdline after execute */
const char *fdt_fname; /* Filename of FDT binary */
- enum exit_type_id exit_type; /* How we exited U-Boot */
const char *parse_err; /* Error to report from parsing */
int argc; /* Program arguments */
char **argv; /* Command line arguments */
@@ -139,13 +131,6 @@ struct sandbox_state_io {
}
/**
- * Record the exit type to be reported by the test program.
- *
- * @param exit_type Exit type to record
- */
-void state_record_exit(enum exit_type_id exit_type);
-
-/**
* Gets a pointer to the current state.
*
* @return pointer to state
diff --git a/arch/sandbox/include/asm/u-boot-sandbox.h b/arch/sandbox/include/asm/u-boot-sandbox.h
index d2f1b65..770ab5c 100644
--- a/arch/sandbox/include/asm/u-boot-sandbox.h
+++ b/arch/sandbox/include/asm/u-boot-sandbox.h
@@ -17,7 +17,6 @@
/* board/.../... */
int board_init(void);
-int dram_init(void);
/* start.c */
int sandbox_early_getopt_check(void);
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 90e828a..35d24e4 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -41,8 +41,47 @@ config TARGET_CROWNBAY
Intel Platform Controller Hub EG20T, other system components and
peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
+config TARGET_MINNOWMAX
+ bool "Support Intel Minnowboard MAX"
+ help
+ This is the Intel Minnowboard MAX. It contains an Atom E3800
+ processor in a small form factor with Ethernet, micro-SD, USB 2,
+ USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
+ It requires some binary blobs - see README.x86 for details.
+
+ Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+ by U-Boot matches that value.
+
+config TARGET_GALILEO
+ bool "Support Intel Galileo"
+ help
+ This is the Intel Galileo board, which is the first in a family of
+ Arduino-certified development and prototyping boards based on Intel
+ architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
+ single-core, single-thread, Intel Pentium processor instrunction set
+ architecture (ISA) compatible, operating at speeds up to 400Mhz,
+ along with 256MB DDR3 memory. It supports a wide range of industry
+ standard I/O interfaces, including a full-sized mini-PCIe slot,
+ one 100Mb Ethernet port, a microSD card slot, a USB host port and
+ a USB client port.
+
endchoice
+config DM
+ default y
+
+config DM_GPIO
+ default y
+
+config DM_SERIAL
+ default y
+
+config SYS_MALLOC_F
+ default y
+
+config SYS_MALLOC_F_LEN
+ default 0x800
+
config RAMBASE
hex
default 0x100000
@@ -324,6 +363,54 @@ config FRAMEBUFFER_VESA_MODE
endmenu
+config HAVE_FSP
+ bool "Add an Firmware Support Package binary"
+ help
+ Select this option to add an Firmware Support Package binary to
+ the resulting U-Boot image. It is a binary blob which U-Boot uses
+ to set up SDRAM and other chipset specific initialization.
+
+ Note: Without this binary U-Boot will not be able to set up its
+ SDRAM so will not boot.
+
+config FSP_FILE
+ string "Firmware Support Package binary filename"
+ depends on HAVE_FSP
+ default "fsp.bin"
+ help
+ The filename of the file to use as Firmware Support Package binary
+ in the board directory.
+
+config FSP_ADDR
+ hex "Firmware Support Package binary location"
+ depends on HAVE_FSP
+ default 0xfffc0000
+ help
+ FSP is not Position Independent Code (PIC) and the whole FSP has to
+ be rebased if it is placed at a location which is different from the
+ perferred base address specified during the FSP build. Use Intel's
+ Binary Configuration Tool (BCT) to do the rebase.
+
+ The default base address of 0xfffc0000 indicates that the binary must
+ be located at offset 0xc0000 from the beginning of a 1MB flash device.
+
+config FSP_TEMP_RAM_ADDR
+ hex
+ default 0x2000000
+ help
+ Stack top address which is used in FspInit after DRAM is ready and
+ CAR is disabled.
+
+source "arch/x86/cpu/baytrail/Kconfig"
+
+source "arch/x86/cpu/coreboot/Kconfig"
+
+source "arch/x86/cpu/ivybridge/Kconfig"
+
+source "arch/x86/cpu/quark/Kconfig"
+
+source "arch/x86/cpu/queensbay/Kconfig"
+
config TSC_CALIBRATION_BYPASS
bool "Bypass Time-Stamp Counter (TSC) calibration"
default n
@@ -344,16 +431,28 @@ config TSC_FREQ_IN_MHZ
help
The running frequency in MHz of Time-Stamp Counter (TSC).
-source "arch/x86/cpu/coreboot/Kconfig"
-
-source "arch/x86/cpu/ivybridge/Kconfig"
-
-source "arch/x86/cpu/queensbay/Kconfig"
-
source "board/coreboot/coreboot/Kconfig"
source "board/google/chromebook_link/Kconfig"
source "board/intel/crownbay/Kconfig"
+source "board/intel/minnowmax/Kconfig"
+
+source "board/intel/galileo/Kconfig"
+
+config PCIE_ECAM_BASE
+ hex
+ default 0xe0000000
+ help
+ This is the memory-mapped address of PCI configuration space, which
+ is only available through the Enhanced Configuration Access
+ Mechanism (ECAM) with PCI Express. It can be set up almost
+ anywhere. Before it is set up, it is possible to access PCI
+ configuration space through I/O access, but memory access is more
+ convenient. Using this, PCI can be scanned and configured. This
+ should be set to a region that does not conflict with memory
+ assigned to PCI devices - i.e. the memory and prefetch regions, as
+ passed to pci_set_region().
+
endmenu
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 62e43c0..6ded0a7 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -12,9 +12,11 @@ extra-y = start.o
obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
obj-y += interrupts.o cpu.o call64.o
+obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
obj-$(CONFIG_SYS_COREBOOT) += coreboot/
obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
+obj-$(CONFIG_INTEL_QUARK) += quark/
obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
obj-y += lapic.o
obj-y += mtrr.o
diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig
new file mode 100644
index 0000000..e86cc01
--- /dev/null
+++ b/arch/x86/cpu/baytrail/Kconfig
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2015 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+config INTEL_BAYTRAIL
+ bool
+ select HAVE_FSP
diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
new file mode 100644
index 0000000..8914e8b
--- /dev/null
+++ b/arch/x86/cpu/baytrail/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2015 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += early_uart.o
+obj-y += fsp_configs.o
+obj-y += pci.o
+obj-y += valleyview.o
diff --git a/arch/x86/cpu/baytrail/early_uart.c b/arch/x86/cpu/baytrail/early_uart.c
new file mode 100644
index 0000000..4199210
--- /dev/null
+++ b/arch/x86/cpu/baytrail/early_uart.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+
+#define PCI_DEV_CONFIG(segbus, dev, fn) ( \
+ (((segbus) & 0xfff) << 20) | \
+ (((dev) & 0x1f) << 15) | \
+ (((fn) & 0x07) << 12))
+
+/* Platform Controller Unit */
+#define LPC_DEV 0x1f
+#define LPC_FUNC 0
+
+/* Enable UART */
+#define UART_CONT 0x80
+
+/* SCORE Pad definitions */
+#define UART_RXD_PAD 82
+#define UART_TXD_PAD 83
+
+/* Pad base: PAD_CONF0[n]= PAD_BASE + 16 * n */
+#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE)
+
+/* IO Memory */
+#define IO_BASE_ADDRESS 0xfed0c000
+#define IO_BASE_OFFSET_GPSCORE 0x0000
+#define IO_BASE_OFFSET_GPNCORE 0x1000
+#define IO_BASE_OFFSET_GPSSUS 0x2000
+#define IO_BASE_SIZE 0x4000
+
+static inline unsigned int score_pconf0(int pad_num)
+{
+ return GPSCORE_PAD_BASE + pad_num * 16;
+}
+
+static void score_select_func(int pad, int func)
+{
+ uint32_t reg;
+ uint32_t pconf0_addr = score_pconf0(pad);
+
+ reg = readl(pconf0_addr);
+ reg &= ~0x7;
+ reg |= func & 0x7;
+ writel(reg, pconf0_addr);
+}
+
+static void pci_write_config32(int dev, unsigned int where, u32 value)
+{
+ unsigned long addr;
+
+ addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
+ writel(value, addr);
+}
+
+/* This can be called after memory-mapped PCI is working */
+int setup_early_uart(void)
+{
+ /* Enable the legacy UART hardware. */
+ pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, 1);
+
+ /*
+ * Set up the pads to the UART function. This allows the signals to
+ * leave the chip
+ */
+ score_select_func(UART_RXD_PAD, 1);
+ score_select_func(UART_TXD_PAD, 1);
+
+ /* TODO(sjg@chromium.org): Call debug_uart_init() */
+
+ return 0;
+}
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
new file mode 100644
index 0000000..86b6926
--- /dev/null
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#include <common.h>
+#include <asm/arch/fsp/azalia.h>
+#include <asm/fsp/fsp_support.h>
+
+/* ALC262 Verb Table - 10EC0262 */
+static const uint32_t verb_table_data13[] = {
+ /* Pin Complex (NID 0x11) */
+ 0x01171cf0,
+ 0x01171d11,
+ 0x01171e11,
+ 0x01171f41,
+ /* Pin Complex (NID 0x12) */
+ 0x01271cf0,
+ 0x01271d11,
+ 0x01271e11,
+ 0x01271f41,
+ /* Pin Complex (NID 0x14) */
+ 0x01471c10,
+ 0x01471d40,
+ 0x01471e01,
+ 0x01471f01,
+ /* Pin Complex (NID 0x15) */
+ 0x01571cf0,
+ 0x01571d11,
+ 0x01571e11,
+ 0x01571f41,
+ /* Pin Complex (NID 0x16) */
+ 0x01671cf0,
+ 0x01671d11,
+ 0x01671e11,
+ 0x01671f41,
+ /* Pin Complex (NID 0x18) */
+ 0x01871c20,
+ 0x01871d98,
+ 0x01871ea1,
+ 0x01871f01,
+ /* Pin Complex (NID 0x19) */
+ 0x01971c21,
+ 0x01971d98,
+ 0x01971ea1,
+ 0x01971f02,
+ /* Pin Complex (NID 0x1A) */
+ 0x01a71c2f,
+ 0x01a71d30,
+ 0x01a71e81,
+ 0x01a71f01,
+ /* Pin Complex */
+ 0x01b71c1f,
+ 0x01b71d40,
+ 0x01b71e21,
+ 0x01b71f02,
+ /* Pin Complex */
+ 0x01c71cf0,
+ 0x01c71d11,
+ 0x01c71e11,
+ 0x01c71f41,
+ /* Pin Complex */
+ 0x01d71c01,
+ 0x01d71dc6,
+ 0x01d71e14,
+ 0x01d71f40,
+ /* Pin Complex */
+ 0x01e71cf0,
+ 0x01e71d11,
+ 0x01e71e11,
+ 0x01e71f41,
+ /* Pin Complex */
+ 0x01f71cf0,
+ 0x01f71d11,
+ 0x01f71e11,
+ 0x01f71f41,
+};
+
+/*
+ * This needs to be in ROM since if we put it in CAR, FSP init loses it when
+ * it drops CAR.
+ *
+ * TODO(sjg@chromium.org): Move to device tree when FSP allows it
+ *
+ * VerbTable: (RealTek ALC262)
+ * Revision ID = 0xFF, support all steps
+ * Codec Verb Table For AZALIA
+ * Codec Address: CAd value (0/1/2)
+ * Codec Vendor: 0x10EC0262
+ */
+static const struct pch_azalia_verb_table azalia_verb_table[] = {
+ {
+ {
+ 0x10ec0262,
+ 0x0000,
+ 0xff,
+ 0x01,
+ 0x000b,
+ 0x0002,
+ },
+ verb_table_data13
+ }
+};
+
+const struct pch_azalia_config azalia_config = {
+ .pme_enable = 1,
+ .docking_supported = 1,
+ .docking_attached = 0,
+ .hdmi_codec_enable = 1,
+ .azalia_v_ci_enable = 1,
+ .rsvdbits = 0,
+ .azalia_verb_table_num = 1,
+ .azalia_verb_table = azalia_verb_table,
+ .reset_wait_timer_us = 300
+};
+
+void update_fsp_upd(struct upd_region *fsp_upd)
+{
+ struct memory_down_data *mem;
+
+ /*
+ * Configure everything here to avoid the poor hard-pressed user
+ * needing to run Intel's binary configuration tool. It may also allow
+ * us to support the 1GB single core variant easily.
+ *
+ * TODO(sjg@chromium.org): Move to device tree
+ */
+ fsp_upd->mrc_init_tseg_size = 8;
+ fsp_upd->mrc_init_mmio_size = 0x800;
+ fsp_upd->emmc_boot_mode = 0xff;
+ fsp_upd->enable_sdio = 1;
+ fsp_upd->enable_sdcard = 1;
+ fsp_upd->enable_hsuart0 = 1;
+ fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
+ fsp_upd->enable_i2_c0 = 0;
+ fsp_upd->enable_i2_c2 = 0;
+ fsp_upd->enable_i2_c3 = 0;
+ fsp_upd->enable_i2_c4 = 0;
+ fsp_upd->enable_xhci = 0;
+ fsp_upd->igd_render_standby = 1;
+
+ mem = &fsp_upd->memory_params;
+ mem->enable_memory_down = 1;
+ mem->dram_speed = 1;
+ mem->dimm_width = 1;
+ mem->dimm_density = 2;
+ mem->dimm_tcl = 0xb;
+ mem->dimm_trpt_rcd = 0xb;
+ mem->dimm_twr = 0xc;
+ mem->dimm_twtr = 6;
+ mem->dimm_trrd = 6;
+ mem->dimm_trtp = 6;
+ mem->dimm_tfaw = 0x14;
+}
diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c
new file mode 100644
index 0000000..6c291f9
--- /dev/null
+++ b/arch/x86/cpu/baytrail/pci.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_pci_setup_hose(struct pci_controller *hose)
+{
+ hose->first_busno = 0;
+ hose->last_busno = 0;
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 0,
+ CONFIG_PCI_MEM_BUS,
+ CONFIG_PCI_MEM_PHYS,
+ CONFIG_PCI_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 1,
+ CONFIG_PCI_IO_BUS,
+ CONFIG_PCI_IO_PHYS,
+ CONFIG_PCI_IO_SIZE,
+ PCI_REGION_IO);
+
+ pci_set_region(hose->regions + 2,
+ CONFIG_PCI_PREF_BUS,
+ CONFIG_PCI_PREF_PHYS,
+ CONFIG_PCI_PREF_SIZE,
+ PCI_REGION_PREFETCH);
+
+ pci_set_region(hose->regions + 3,
+ 0,
+ 0,
+ gd->ram_size,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+ hose->region_count = 4;
+}
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
new file mode 100644
index 0000000..a3e837d
--- /dev/null
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <pci_ids.h>
+#include <asm/post.h>
+
+static struct pci_device_id mmc_supported[] = {
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
+};
+
+int cpu_mmc_init(bd_t *bis)
+{
+ printf("mmc init\n");
+ return pci_mmc_init("ValleyView SDHCI", mmc_supported,
+ ARRAY_SIZE(mmc_supported));
+}
+
+int arch_cpu_init(void)
+{
+ int ret;
+
+ post_code(POST_CPU_INIT);
+#ifdef CONFIG_SYS_X86_TSC_TIMER
+ timer_set_base(rdtsc());
+#endif
+
+ ret = x86_cpu_init_f();
+ if (ret)
+ return ret;
+
+ return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
index 6cf9654..821ea25 100644
--- a/arch/x86/cpu/ivybridge/gma.c
+++ b/arch/x86/cpu/ivybridge/gma.c
@@ -758,7 +758,8 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
#ifdef CONFIG_VIDEO
start = get_timer(0);
- ret = pci_run_vga_bios(dev, int15_handler, false);
+ ret = pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
+ PCI_ROM_ALLOW_FALLBACK);
debug("BIOS ran in %lums\n", get_timer(start));
#endif
/* Post VBIOS init */
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 4963448..766b385 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -757,7 +757,7 @@ int dram_init(void)
.mchbar = DEFAULT_MCHBAR,
.dmibar = DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .pciexbar = CONFIG_PCIE_ECAM_BASE,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig
new file mode 100644
index 0000000..bc961ef
--- /dev/null
+++ b/arch/x86/cpu/quark/Kconfig
@@ -0,0 +1,126 @@
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+config INTEL_QUARK
+ bool
+ select HAVE_RMU
+ select TSC_CALIBRATION_BYPASS
+
+if INTEL_QUARK
+
+config HAVE_RMU
+ bool "Add a Remote Management Unit (RMU) binary"
+ help
+ Select this option to add a Remote Management Unit (RMU) binary
+ to the resulting U-Boot image. It is a data block (up to 64K) of
+ machine-specific code which must be put in the flash for the RMU
+ within the Quark SoC processor to access when powered up before
+ system BIOS is executed.
+
+config RMU_FILE
+ string "Remote Management Unit (RMU) binary filename"
+ depends on HAVE_RMU
+ default "rmu.bin"
+ help
+ The filename of the file to use as Remote Management Unit (RMU)
+ binary in the board directory.
+
+config RMU_ADDR
+ hex "Remote Management Unit (RMU) binary location"
+ depends on HAVE_RMU
+ default 0xfff00000
+ help
+ The location of the RMU binary is determined by a strap. It must be
+ put in flash at a location matching the strap-determined base address.
+
+ The default base address of 0xfff00000 indicates that the binary must
+ be located at offset 0 from the beginning of a 1MB flash device.
+
+config HAVE_CMC
+ bool
+ default HAVE_RMU
+
+config CMC_FILE
+ string
+ depends on HAVE_CMC
+ default RMU_FILE
+
+config CMC_ADDR
+ hex
+ depends on HAVE_CMC
+ default RMU_ADDR
+
+config ESRAM_BASE
+ hex
+ default 0x80000000
+ help
+ Embedded SRAM (eSRAM) memory-mapped base address.
+
+config PCIE_ECAM_BASE
+ hex
+ default 0xe0000000
+
+config RCBA_BASE
+ hex
+ default 0xfed1c000
+ help
+ Root Complex register block memory-mapped base address.
+
+config ACPI_PM1_BASE
+ hex
+ default 0x1000
+ help
+ ACPI Power Managment 1 (PM1) i/o-mapped base address.
+ This device is defined in ACPI specification, with 16 bytes in size.
+
+config ACPI_PBLK_BASE
+ hex
+ default 0x1010
+ help
+ ACPI Processor Block (PBLK) i/o-mapped base address.
+ This device is defined in ACPI specification, with 16 bytes in size.
+
+config SPI_DMA_BASE
+ hex
+ default 0x1020
+ help
+ SPI DMA i/o-mapped base address.
+
+config GPIO_BASE
+ hex
+ default 0x1080
+ help
+ GPIO i/o-mapped base address.
+
+config ACPI_GPE0_BASE
+ hex
+ default 0x1100
+ help
+ ACPI General Purpose Event 0 (GPE0) i/o-mapped base address.
+ This device is defined in ACPI specification, with 64 bytes in size.
+
+config WDT_BASE
+ hex
+ default 0x1140
+ help
+ Watchdog timer i/o-mapped base address.
+
+config SYS_CAR_ADDR
+ hex
+ default ESRAM_BASE
+
+config SYS_CAR_SIZE
+ hex
+ default 0x8000
+ help
+ Space in bytes in eSRAM used as Cache-As-ARM (CAR).
+ Note this size must not exceed eSRAM's total size.
+
+config TSC_FREQ_IN_MHZ
+ int
+ default 400
+
+endif
diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile
new file mode 100644
index 0000000..e87b424
--- /dev/null
+++ b/arch/x86/cpu/quark/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += car.o dram.o msg_port.o quark.o
+obj-y += mrc.o mrc_util.o hte.o smc.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/x86/cpu/quark/car.S b/arch/x86/cpu/quark/car.S
new file mode 100644
index 0000000..3432ffa
--- /dev/null
+++ b/arch/x86/cpu/quark/car.S
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/pci.h>
+#include <asm/post.h>
+#include <asm/arch/quark.h>
+#include <asm/arch/msg_port.h>
+
+.globl car_init
+car_init:
+ post_code(POST_CAR_START)
+
+ /*
+ * Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is
+ * initialized by hardware. eSRAM is the ideal place to be used
+ * for Cache-As-RAM (CAR) before system memory is available.
+ *
+ * Relocate this eSRAM to a suitable location in the physical
+ * memory map and enable it.
+ */
+
+ /* Host Memory Bound Register P03h:R08h */
+ mov $((MSG_PORT_HOST_BRIDGE << 16) | (HM_BOUND << 8)), %eax
+ mov $(DRAM_BASE + DRAM_MAX_SIZE + ESRAM_SIZE), %edx
+ lea 1f, %esp
+ jmp msg_port_write
+1:
+
+ /* eSRAM Block Page Control Register P05h:R82h */
+ mov $((MSG_PORT_MEM_MGR << 16) | (ESRAM_BLK_CTRL << 8)), %eax
+ mov $(ESRAM_BLOCK_MODE | (CONFIG_ESRAM_BASE >> 24)), %edx
+ lea 2f, %esp
+ jmp msg_port_write
+2:
+
+ post_code(POST_CAR_CPU_CACHE)
+ jmp car_init_ret
+
+msg_port_read:
+ /*
+ * Parameter:
+ * eax[23:16] - Message Port ID
+ * eax[15:08] - Register Address
+ *
+ * Return Value:
+ * eax - Message Port Register value
+ *
+ * Return Address: esp
+ */
+
+ or $((MSG_OP_READ << 24) | MSG_BYTE_ENABLE), %eax
+ mov %eax, %ebx
+
+ /* Write MCR B0:D0:F0:RD0 */
+ mov $(PCI_CFG_EN | MSG_CTRL_REG), %eax
+ mov $PCI_REG_ADDR, %dx
+ out %eax, %dx
+ mov $PCI_REG_DATA, %dx
+ mov %ebx, %eax
+ out %eax, %dx
+
+ /* Read MDR B0:D0:F0:RD4 */
+ mov $(PCI_CFG_EN | MSG_DATA_REG), %eax
+ mov $PCI_REG_ADDR, %dx
+ out %eax, %dx
+ mov $PCI_REG_DATA, %dx
+ in %dx, %eax
+
+ jmp *%esp
+
+msg_port_write:
+ /*
+ * Parameter:
+ * eax[23:16] - Message Port ID
+ * eax[15:08] - Register Address
+ * edx - Message Port Register value to write
+ *
+ * Return Address: esp
+ */
+
+ or $((MSG_OP_WRITE << 24) | MSG_BYTE_ENABLE), %eax
+ mov %eax, %esi
+ mov %edx, %edi
+
+ /* Write MDR B0:D0:F0:RD4 */
+ mov $(PCI_CFG_EN | MSG_DATA_REG), %eax
+ mov $PCI_REG_ADDR, %dx
+ out %eax, %dx
+ mov $PCI_REG_DATA, %dx
+ mov %edi, %eax
+ out %eax, %dx
+
+ /* Write MCR B0:D0:F0:RD0 */
+ mov $(PCI_CFG_EN | MSG_CTRL_REG), %eax
+ mov $PCI_REG_ADDR, %dx
+ out %eax, %dx
+ mov $PCI_REG_DATA, %dx
+ mov %esi, %eax
+ out %eax, %dx
+
+ jmp *%esp
diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c
new file mode 100644
index 0000000..9cac846
--- /dev/null
+++ b/arch/x86/cpu/quark/dram.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <asm/post.h>
+#include <asm/arch/mrc.h>
+#include <asm/arch/quark.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int mrc_configure_params(struct mrc_params *mrc_params)
+{
+ const void *blob = gd->fdt_blob;
+ int node;
+ int mrc_flags;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_QRK_MRC);
+ if (node < 0) {
+ debug("%s: Cannot find MRC node\n", __func__);
+ return -EINVAL;
+ }
+
+ /*
+ * TODO:
+ *
+ * We need support fast boot (MRC cache) in the future.
+ *
+ * Set boot mode to cold boot for now
+ */
+ mrc_params->boot_mode = BM_COLD;
+
+ /*
+ * TODO:
+ *
+ * We need determine ECC by pin strap state
+ *
+ * Disable ECC by default for now
+ */
+ mrc_params->ecc_enables = 0;
+
+ mrc_flags = fdtdec_get_int(blob, node, "flags", 0);
+ if (mrc_flags & MRC_FLAG_SCRAMBLE_EN)
+ mrc_params->scrambling_enables = 1;
+ else
+ mrc_params->scrambling_enables = 0;
+
+ mrc_params->dram_width = fdtdec_get_int(blob, node, "dram-width", 0);
+ mrc_params->ddr_speed = fdtdec_get_int(blob, node, "dram-speed", 0);
+ mrc_params->ddr_type = fdtdec_get_int(blob, node, "dram-type", 0);
+
+ mrc_params->rank_enables = fdtdec_get_int(blob, node, "rank-mask", 0);
+ mrc_params->channel_enables = fdtdec_get_int(blob, node,
+ "chan-mask", 0);
+ mrc_params->channel_width = fdtdec_get_int(blob, node,
+ "chan-width", 0);
+ mrc_params->address_mode = fdtdec_get_int(blob, node, "addr-mode", 0);
+
+ mrc_params->refresh_rate = fdtdec_get_int(blob, node,
+ "refresh-rate", 0);
+ mrc_params->sr_temp_range = fdtdec_get_int(blob, node,
+ "sr-temp-range", 0);
+ mrc_params->ron_value = fdtdec_get_int(blob, node,
+ "ron-value", 0);
+ mrc_params->rtt_nom_value = fdtdec_get_int(blob, node,
+ "rtt-nom-value", 0);
+ mrc_params->rd_odt_value = fdtdec_get_int(blob, node,
+ "rd-odt-value", 0);
+
+ mrc_params->params.density = fdtdec_get_int(blob, node,
+ "dram-density", 0);
+ mrc_params->params.cl = fdtdec_get_int(blob, node, "dram-cl", 0);
+ mrc_params->params.ras = fdtdec_get_int(blob, node, "dram-ras", 0);
+ mrc_params->params.wtr = fdtdec_get_int(blob, node, "dram-wtr", 0);
+ mrc_params->params.rrd = fdtdec_get_int(blob, node, "dram-rrd", 0);
+ mrc_params->params.faw = fdtdec_get_int(blob, node, "dram-faw", 0);
+
+ debug("MRC dram_width %d\n", mrc_params->dram_width);
+ debug("MRC rank_enables %d\n", mrc_params->rank_enables);
+ debug("MRC ddr_speed %d\n", mrc_params->ddr_speed);
+ debug("MRC flags: %s\n",
+ (mrc_params->scrambling_enables) ? "SCRAMBLE_EN" : "");
+
+ debug("MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n",
+ mrc_params->params.density, mrc_params->params.cl,
+ mrc_params->params.ras, mrc_params->params.wtr,
+ mrc_params->params.rrd, mrc_params->params.faw);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct mrc_params mrc_params;
+ int ret;
+
+ memset(&mrc_params, 0, sizeof(struct mrc_params));
+ ret = mrc_configure_params(&mrc_params);
+ if (ret)
+ return ret;
+
+ /* Set up the DRAM by calling the memory reference code */
+ mrc_init(&mrc_params);
+ if (mrc_params.status)
+ return -EIO;
+
+ gd->ram_size = mrc_params.mem_size;
+ post_code(POST_DRAM);
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+/*
+ * This function looks for the highest region of memory lower than 4GB which
+ * has enough space for U-Boot where U-Boot is aligned on a page boundary.
+ * It overrides the default implementation found elsewhere which simply
+ * picks the end of ram, wherever that may be. The location of the stack,
+ * the relocation address, and how far U-Boot is moved by relocation are
+ * set in the global data structure.
+ */
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return gd->ram_size;
+}
diff --git a/arch/x86/cpu/quark/hte.c b/arch/x86/cpu/quark/hte.c
new file mode 100644
index 0000000..372815d
--- /dev/null
+++ b/arch/x86/cpu/quark/hte.c
@@ -0,0 +1,396 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Ported from Intel released Quark UEFI BIOS
+ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#include <common.h>
+#include <asm/arch/mrc.h>
+#include <asm/arch/msg_port.h>
+#include "mrc_util.h"
+#include "hte.h"
+
+/**
+ * Enable HTE to detect all possible errors for the given training parameters
+ * (per-bit or full byte lane).
+ */
+static void hte_enable_all_errors(void)
+{
+ msg_port_write(HTE, 0x000200A2, 0xFFFFFFFF);
+ msg_port_write(HTE, 0x000200A3, 0x000000FF);
+ msg_port_write(HTE, 0x000200A4, 0x00000000);
+}
+
+/**
+ * Go and read the HTE register in order to find any error
+ *
+ * @return: The errors detected in the HTE status register
+ */
+static u32 hte_check_errors(void)
+{
+ return msg_port_read(HTE, 0x000200A7);
+}
+
+/**
+ * Wait until HTE finishes
+ */
+static void hte_wait_for_complete(void)
+{
+ u32 tmp;
+
+ ENTERFN();
+
+ do {} while ((msg_port_read(HTE, 0x00020012) & BIT30) != 0);
+
+ tmp = msg_port_read(HTE, 0x00020011);
+ tmp |= BIT9;
+ tmp &= ~(BIT12 | BIT13);
+ msg_port_write(HTE, 0x00020011, tmp);
+
+ LEAVEFN();
+}
+
+/**
+ * Clear registers related with errors in the HTE
+ */
+static void hte_clear_error_regs(void)
+{
+ u32 tmp;
+
+ /*
+ * Clear all HTE errors and enable error checking
+ * for burst and chunk.
+ */
+ tmp = msg_port_read(HTE, 0x000200A1);
+ tmp |= BIT8;
+ msg_port_write(HTE, 0x000200A1, tmp);
+}
+
+/**
+ * Execute a basic single-cache-line memory write/read/verify test using simple
+ * constant pattern, different for READ_TRAIN and WRITE_TRAIN modes.
+ *
+ * See hte_basic_write_read() which is the external visible wrapper.
+ *
+ * @mrc_params: host structure for all MRC global data
+ * @addr: memory adress being tested (must hit specific channel/rank)
+ * @first_run: if set then the HTE registers are configured, otherwise it is
+ * assumed configuration is done and we just re-run the test
+ * @mode: READ_TRAIN or WRITE_TRAIN (the difference is in the pattern)
+ *
+ * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
+ */
+static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr,
+ u8 first_run, u8 mode)
+{
+ u32 pattern;
+ u32 offset;
+
+ if (first_run) {
+ msg_port_write(HTE, 0x00020020, 0x01B10021);
+ msg_port_write(HTE, 0x00020021, 0x06000000);
+ msg_port_write(HTE, 0x00020022, addr >> 6);
+ msg_port_write(HTE, 0x00020062, 0x00800015);
+ msg_port_write(HTE, 0x00020063, 0xAAAAAAAA);
+ msg_port_write(HTE, 0x00020064, 0xCCCCCCCC);
+ msg_port_write(HTE, 0x00020065, 0xF0F0F0F0);
+ msg_port_write(HTE, 0x00020061, 0x00030008);
+
+ if (mode == WRITE_TRAIN)
+ pattern = 0xC33C0000;
+ else /* READ_TRAIN */
+ pattern = 0xAA5555AA;
+
+ for (offset = 0x80; offset <= 0x8F; offset++)
+ msg_port_write(HTE, offset, pattern);
+ }
+
+ msg_port_write(HTE, 0x000200A1, 0xFFFF1000);
+ msg_port_write(HTE, 0x00020011, 0x00011000);
+ msg_port_write(HTE, 0x00020011, 0x00011100);
+
+ hte_wait_for_complete();
+
+ /*
+ * Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
+ * any bytelane errors.
+ */
+ return (hte_check_errors() >> 8) & 0xFF;
+}
+
+/**
+ * Examine a single-cache-line memory with write/read/verify test using multiple
+ * data patterns (victim-aggressor algorithm).
+ *
+ * See hte_write_stress_bit_lanes() which is the external visible wrapper.
+ *
+ * @mrc_params: host structure for all MRC global data
+ * @addr: memory adress being tested (must hit specific channel/rank)
+ * @loop_cnt: number of test iterations
+ * @seed_victim: victim data pattern seed
+ * @seed_aggressor: aggressor data pattern seed
+ * @victim_bit: should be 0 as auto-rotate feature is in use
+ * @first_run: if set then the HTE registers are configured, otherwise it is
+ * assumed configuration is done and we just re-run the test
+ *
+ * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
+ */
+static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr,
+ u8 loop_cnt, u32 seed_victim, u32 seed_aggressor,
+ u8 victim_bit, u8 first_run)
+{
+ u32 offset;
+ u32 tmp;
+
+ if (first_run) {
+ msg_port_write(HTE, 0x00020020, 0x00910024);
+ msg_port_write(HTE, 0x00020023, 0x00810024);
+ msg_port_write(HTE, 0x00020021, 0x06070000);
+ msg_port_write(HTE, 0x00020024, 0x06070000);
+ msg_port_write(HTE, 0x00020022, addr >> 6);
+ msg_port_write(HTE, 0x00020025, addr >> 6);
+ msg_port_write(HTE, 0x00020062, 0x0000002A);
+ msg_port_write(HTE, 0x00020063, seed_victim);
+ msg_port_write(HTE, 0x00020064, seed_aggressor);
+ msg_port_write(HTE, 0x00020065, seed_victim);
+
+ /*
+ * Write the pattern buffers to select the victim bit
+ *
+ * Start with bit0
+ */
+ for (offset = 0x80; offset <= 0x8F; offset++) {
+ if ((offset % 8) == victim_bit)
+ msg_port_write(HTE, offset, 0x55555555);
+ else
+ msg_port_write(HTE, offset, 0xCCCCCCCC);
+ }
+
+ msg_port_write(HTE, 0x00020061, 0x00000000);
+ msg_port_write(HTE, 0x00020066, 0x03440000);
+ msg_port_write(HTE, 0x000200A1, 0xFFFF1000);
+ }
+
+ tmp = 0x10001000 | (loop_cnt << 16);
+ msg_port_write(HTE, 0x00020011, tmp);
+ msg_port_write(HTE, 0x00020011, tmp | BIT8);
+
+ hte_wait_for_complete();
+
+ /*
+ * Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
+ * any bytelane errors.
+ */
+ return (hte_check_errors() >> 8) & 0xFF;
+}
+
+/**
+ * Use HW HTE engine to initialize or test all memory attached to a given DUNIT.
+ * If flag is MRC_MEM_INIT, this routine writes 0s to all memory locations to
+ * initialize ECC. If flag is MRC_MEM_TEST, this routine will send an 5AA55AA5
+ * pattern to all memory locations on the RankMask and then read it back.
+ * Then it sends an A55AA55A pattern to all memory locations on the RankMask
+ * and reads it back.
+ *
+ * @mrc_params: host structure for all MRC global data
+ * @flag: MRC_MEM_INIT or MRC_MEM_TEST
+ *
+ * @return: errors register showing HTE failures. Also prints out which rank
+ * failed the HTE test if failure occurs. For rank detection to work,
+ * the address map must be left in its default state. If MRC changes
+ * the address map, this function must be modified to change it back
+ * to default at the beginning, then restore it at the end.
+ */
+u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag)
+{
+ u32 offset;
+ int test_num;
+ int i;
+
+ /*
+ * Clear out the error registers at the start of each memory
+ * init or memory test run.
+ */
+ hte_clear_error_regs();
+
+ msg_port_write(HTE, 0x00020062, 0x00000015);
+
+ for (offset = 0x80; offset <= 0x8F; offset++)
+ msg_port_write(HTE, offset, ((offset & 1) ? 0xA55A : 0x5AA5));
+
+ msg_port_write(HTE, 0x00020021, 0x00000000);
+ msg_port_write(HTE, 0x00020022, (mrc_params->mem_size >> 6) - 1);
+ msg_port_write(HTE, 0x00020063, 0xAAAAAAAA);
+ msg_port_write(HTE, 0x00020064, 0xCCCCCCCC);
+ msg_port_write(HTE, 0x00020065, 0xF0F0F0F0);
+ msg_port_write(HTE, 0x00020066, 0x03000000);
+
+ switch (flag) {
+ case MRC_MEM_INIT:
+ /*
+ * Only 1 write pass through memory is needed
+ * to initialize ECC
+ */
+ test_num = 1;
+ break;
+ case MRC_MEM_TEST:
+ /* Write/read then write/read with inverted pattern */
+ test_num = 4;
+ break;
+ default:
+ DPF(D_INFO, "Unknown parameter for flag: %d\n", flag);
+ return 0xFFFFFFFF;
+ }
+
+ DPF(D_INFO, "hte_mem_init");
+
+ for (i = 0; i < test_num; i++) {
+ DPF(D_INFO, ".");
+
+ if (i == 0) {
+ msg_port_write(HTE, 0x00020061, 0x00000000);
+ msg_port_write(HTE, 0x00020020, 0x00110010);
+ } else if (i == 1) {
+ msg_port_write(HTE, 0x00020061, 0x00000000);
+ msg_port_write(HTE, 0x00020020, 0x00010010);
+ } else if (i == 2) {
+ msg_port_write(HTE, 0x00020061, 0x00010100);
+ msg_port_write(HTE, 0x00020020, 0x00110010);
+ } else {
+ msg_port_write(HTE, 0x00020061, 0x00010100);
+ msg_port_write(HTE, 0x00020020, 0x00010010);
+ }
+
+ msg_port_write(HTE, 0x00020011, 0x00111000);
+ msg_port_write(HTE, 0x00020011, 0x00111100);
+
+ hte_wait_for_complete();
+
+ /* If this is a READ pass, check for errors at the end */
+ if ((i % 2) == 1) {
+ /* Return immediately if error */
+ if (hte_check_errors())
+ break;
+ }
+ }
+
+ DPF(D_INFO, "done\n");
+
+ return hte_check_errors();
+}
+
+/**
+ * Execute a basic single-cache-line memory write/read/verify test using simple
+ * constant pattern, different for READ_TRAIN and WRITE_TRAIN modes.
+ *
+ * @mrc_params: host structure for all MRC global data
+ * @addr: memory adress being tested (must hit specific channel/rank)
+ * @first_run: if set then the HTE registers are configured, otherwise it is
+ * assumed configuration is done and we just re-run the test
+ * @mode: READ_TRAIN or WRITE_TRAIN (the difference is in the pattern)
+ *
+ * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
+ */
+u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr,
+ u8 first_run, u8 mode)
+{
+ u16 errors;
+
+ ENTERFN();
+
+ /* Enable all error reporting in preparation for HTE test */
+ hte_enable_all_errors();
+ hte_clear_error_regs();
+
+ errors = hte_basic_data_cmp(mrc_params, addr, first_run, mode);
+
+ LEAVEFN();
+
+ return errors;
+}
+
+/**
+ * Examine a single-cache-line memory with write/read/verify test using multiple
+ * data patterns (victim-aggressor algorithm).
+ *
+ * @mrc_params: host structure for all MRC global data
+ * @addr: memory adress being tested (must hit specific channel/rank)
+ * @first_run: if set then the HTE registers are configured, otherwise it is
+ * assumed configuration is done and we just re-run the test
+ *
+ * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
+ */
+u16 hte_write_stress_bit_lanes(struct mrc_params *mrc_params,
+ u32 addr, u8 first_run)
+{
+ u16 errors;
+ u8 victim_bit = 0;
+
+ ENTERFN();
+
+ /* Enable all error reporting in preparation for HTE test */
+ hte_enable_all_errors();
+ hte_clear_error_regs();
+
+ /*
+ * Loop through each bit in the bytelane.
+ *
+ * Each pass creates a victim bit while keeping all other bits the same
+ * as aggressors. AVN HTE adds an auto-rotate feature which allows us
+ * to program the entire victim/aggressor sequence in 1 step.
+ *
+ * The victim bit rotates on each pass so no need to have software
+ * implement a victim bit loop like on VLV.
+ */
+ errors = hte_rw_data_cmp(mrc_params, addr, HTE_LOOP_CNT,
+ HTE_LFSR_VICTIM_SEED, HTE_LFSR_AGRESSOR_SEED,
+ victim_bit, first_run);
+
+ LEAVEFN();
+
+ return errors;
+}
+
+/**
+ * Execute a basic single-cache-line memory write or read.
+ * This is just for receive enable / fine write-levelling purpose.
+ *
+ * @addr: memory adress being tested (must hit specific channel/rank)
+ * @first_run: if set then the HTE registers are configured, otherwise it is
+ * assumed configuration is done and we just re-run the test
+ * @is_write: when non-zero memory write operation executed, otherwise read
+ */
+void hte_mem_op(u32 addr, u8 first_run, u8 is_write)
+{
+ u32 offset;
+ u32 tmp;
+
+ hte_enable_all_errors();
+ hte_clear_error_regs();
+
+ if (first_run) {
+ tmp = is_write ? 0x01110021 : 0x01010021;
+ msg_port_write(HTE, 0x00020020, tmp);
+
+ msg_port_write(HTE, 0x00020021, 0x06000000);
+ msg_port_write(HTE, 0x00020022, addr >> 6);
+ msg_port_write(HTE, 0x00020062, 0x00800015);
+ msg_port_write(HTE, 0x00020063, 0xAAAAAAAA);
+ msg_port_write(HTE, 0x00020064, 0xCCCCCCCC);
+ msg_port_write(HTE, 0x00020065, 0xF0F0F0F0);
+ msg_port_write(HTE, 0x00020061, 0x00030008);
+
+ for (offset = 0x80; offset <= 0x8F; offset++)
+ msg_port_write(HTE, offset, 0xC33C0000);
+ }
+
+ msg_port_write(HTE, 0x000200A1, 0xFFFF1000);
+ msg_port_write(HTE, 0x00020011, 0x00011000);
+ msg_port_write(HTE, 0x00020011, 0x00011100);
+
+ hte_wait_for_complete();
+}
diff --git a/arch/x86/cpu/quark/hte.h b/arch/x86/cpu/quark/hte.h
new file mode 100644
index 0000000..6577796
--- /dev/null
+++ b/arch/x86/cpu/quark/hte.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Ported from Intel released Quark UEFI BIOS
+ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef _HTE_H_
+#define _HTE_H_
+
+enum {
+ MRC_MEM_INIT,
+ MRC_MEM_TEST
+};
+
+enum {
+ READ_TRAIN,
+ WRITE_TRAIN
+};
+
+/*
+ * EXP_LOOP_CNT field of HTE_CMD_CTL
+ *
+ * This CANNOT be less than 4!
+ */
+#define HTE_LOOP_CNT 5
+
+/* random seed for victim */
+#define HTE_LFSR_VICTIM_SEED 0xF294BA21
+
+/* random seed for aggressor */
+#define HTE_LFSR_AGRESSOR_SEED 0xEBA7492D
+
+u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag);
+u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr,
+ u8 first_run, u8 mode);
+u16 hte_write_stress_bit_lanes(struct mrc_params *mrc_params,
+ u32 addr, u8 first_run);
+void hte_mem_op(u32 addr, u8 first_run, u8 is_write);
+
+#endif /* _HTE_H_ */
diff --git a/arch/x86/cpu/quark/mrc.c b/arch/x86/cpu/quark/mrc.c
new file mode 100644
index 0000000..7eb34c5
--- /dev/null
+++ b/arch/x86/cpu/quark/mrc.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Ported from Intel released Quark UEFI BIOS
+ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+/*
+ * This is the main Quark Memory Reference Code (MRC)
+ *
+ * These functions are generic and should work for any Quark-based board.
+ *
+ * MRC requires two data structures to be passed in which are initialized by
+ * mrc_adjust_params().
+ *
+ * The basic flow is as follows:
+ * 01) Check for supported DDR speed configuration
+ * 02) Set up Memory Manager buffer as pass-through (POR)
+ * 03) Set Channel Interleaving Mode and Channel Stride to the most aggressive
+ * setting possible
+ * 04) Set up the Memory Controller logic
+ * 05) Set up the DDR_PHY logic
+ * 06) Initialise the DRAMs (JEDEC)
+ * 07) Perform the Receive Enable Calibration algorithm
+ * 08) Perform the Write Leveling algorithm
+ * 09) Perform the Read Training algorithm (includes internal Vref)
+ * 10) Perform the Write Training algorithm
+ * 11) Set Channel Interleaving Mode and Channel Stride to the desired settings
+ *
+ * DRAM unit configuration based on Valleyview MRC.
+ */
+
+#include <common.h>
+#include <asm/arch/mrc.h>
+#include <asm/arch/msg_port.h>
+#include "mrc_util.h"
+#include "smc.h"
+
+static const struct mem_init init[] = {
+ { 0x0101, BM_COLD | BM_FAST | BM_WARM | BM_S3, clear_self_refresh },
+ { 0x0200, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_ddr_timing_control },
+ { 0x0103, BM_COLD | BM_FAST , prog_decode_before_jedec },
+ { 0x0104, BM_COLD | BM_FAST , perform_ddr_reset },
+ { 0x0300, BM_COLD | BM_FAST | BM_S3, ddrphy_init },
+ { 0x0400, BM_COLD | BM_FAST , perform_jedec_init },
+ { 0x0105, BM_COLD | BM_FAST , set_ddr_init_complete },
+ { 0x0106, BM_FAST | BM_WARM | BM_S3, restore_timings },
+ { 0x0106, BM_COLD , default_timings },
+ { 0x0500, BM_COLD , rcvn_cal },
+ { 0x0600, BM_COLD , wr_level },
+ { 0x0120, BM_COLD , prog_page_ctrl },
+ { 0x0700, BM_COLD , rd_train },
+ { 0x0800, BM_COLD , wr_train },
+ { 0x010b, BM_COLD , store_timings },
+ { 0x010c, BM_COLD | BM_FAST | BM_WARM | BM_S3, enable_scrambling },
+ { 0x010d, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_ddr_control },
+ { 0x010e, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_dra_drb },
+ { 0x010f, BM_WARM | BM_S3, perform_wake },
+ { 0x0110, BM_COLD | BM_FAST | BM_WARM | BM_S3, change_refresh_period },
+ { 0x0111, BM_COLD | BM_FAST | BM_WARM | BM_S3, set_auto_refresh },
+ { 0x0112, BM_COLD | BM_FAST | BM_WARM | BM_S3, ecc_enable },
+ { 0x0113, BM_COLD | BM_FAST , memory_test },
+ { 0x0114, BM_COLD | BM_FAST | BM_WARM | BM_S3, lock_registers }
+};
+
+/* Adjust configuration parameters before initialization sequence */
+static void mrc_adjust_params(struct mrc_params *mrc_params)
+{
+ const struct dram_params *dram_params;
+ uint8_t dram_width;
+ uint32_t rank_enables;
+ uint32_t channel_width;
+
+ ENTERFN();
+
+ /* initially expect success */
+ mrc_params->status = MRC_SUCCESS;
+
+ dram_width = mrc_params->dram_width;
+ rank_enables = mrc_params->rank_enables;
+ channel_width = mrc_params->channel_width;
+
+ /*
+ * Setup board layout (must be reviewed as is selecting static timings)
+ * 0 == R0 (DDR3 x16), 1 == R1 (DDR3 x16),
+ * 2 == DV (DDR3 x8), 3 == SV (DDR3 x8).
+ */
+ if (dram_width == X8)
+ mrc_params->board_id = 2; /* select x8 layout */
+ else
+ mrc_params->board_id = 0; /* select x16 layout */
+
+ /* initially no memory */
+ mrc_params->mem_size = 0;
+
+ /* begin of channel settings */
+ dram_params = &mrc_params->params;
+
+ /*
+ * Determine column bits:
+ *
+ * Column: 11 for 8Gbx8, else 10
+ */
+ mrc_params->column_bits[0] =
+ ((dram_params[0].density == 4) &&
+ (dram_width == X8)) ? (11) : (10);
+
+ /*
+ * Determine row bits:
+ *
+ * 512Mbx16=12 512Mbx8=13
+ * 1Gbx16=13 1Gbx8=14
+ * 2Gbx16=14 2Gbx8=15
+ * 4Gbx16=15 4Gbx8=16
+ * 8Gbx16=16 8Gbx8=16
+ */
+ mrc_params->row_bits[0] = 12 + (dram_params[0].density) +
+ (((dram_params[0].density < 4) &&
+ (dram_width == X8)) ? (1) : (0));
+
+ /*
+ * Determine per-channel memory size:
+ *
+ * (For 2 RANKs, multiply by 2)
+ * (For 16 bit data bus, divide by 2)
+ *
+ * DENSITY WIDTH MEM_AVAILABLE
+ * 512Mb x16 0x008000000 ( 128MB)
+ * 512Mb x8 0x010000000 ( 256MB)
+ * 1Gb x16 0x010000000 ( 256MB)
+ * 1Gb x8 0x020000000 ( 512MB)
+ * 2Gb x16 0x020000000 ( 512MB)
+ * 2Gb x8 0x040000000 (1024MB)
+ * 4Gb x16 0x040000000 (1024MB)
+ * 4Gb x8 0x080000000 (2048MB)
+ */
+ mrc_params->channel_size[0] = (1 << dram_params[0].density);
+ mrc_params->channel_size[0] *= (dram_width == X8) ? 2 : 1;
+ mrc_params->channel_size[0] *= (rank_enables == 0x3) ? 2 : 1;
+ mrc_params->channel_size[0] *= (channel_width == X16) ? 1 : 2;
+
+ /* Determine memory size (convert number of 64MB/512Mb units) */
+ mrc_params->mem_size += mrc_params->channel_size[0] << 26;
+
+ LEAVEFN();
+}
+
+static void mrc_mem_init(struct mrc_params *mrc_params)
+{
+ int i;
+
+ ENTERFN();
+
+ /* MRC started */
+ mrc_post_code(0x01, 0x00);
+
+ if (mrc_params->boot_mode != BM_COLD) {
+ if (mrc_params->ddr_speed != mrc_params->timings.ddr_speed) {
+ /* full training required as frequency changed */
+ mrc_params->boot_mode = BM_COLD;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(init); i++) {
+ uint64_t my_tsc;
+
+ if (mrc_params->boot_mode & init[i].boot_path) {
+ uint8_t major = init[i].post_code >> 8 & 0xff;
+ uint8_t minor = init[i].post_code >> 0 & 0xff;
+ mrc_post_code(major, minor);
+
+ my_tsc = rdtsc();
+ init[i].init_fn(mrc_params);
+ DPF(D_TIME, "Execution time %llx", rdtsc() - my_tsc);
+ }
+ }
+
+ /* display the timings */
+ print_timings(mrc_params);
+
+ /* MRC complete */
+ mrc_post_code(0x01, 0xff);
+
+ LEAVEFN();
+}
+
+void mrc_init(struct mrc_params *mrc_params)
+{
+ ENTERFN();
+
+ DPF(D_INFO, "MRC Version %04x %s %s\n", MRC_VERSION,
+ __DATE__, __TIME__);
+
+ /* Set up the data structures used by mrc_mem_init() */
+ mrc_adjust_params(mrc_params);
+
+ /* Initialize system memory */
+ mrc_mem_init(mrc_params);
+
+ LEAVEFN();
+}
diff --git a/arch/x86/cpu/quark/mrc_util.c b/arch/x86/cpu/quark/mrc_util.c
new file mode 100644
index 0000000..3a79ae5
--- /dev/null
+++ b/arch/x86/cpu/quark/mrc_util.c
@@ -0,0 +1,1475 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Ported from Intel released Quark UEFI BIOS
+ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#include <common.h>
+#include <asm/arch/device.h>
+#include <asm/arch/mrc.h>
+#include <asm/arch/msg_port.h>
+#include "mrc_util.h"
+#include "hte.h"
+#include "smc.h"
+
+static const uint8_t vref_codes[64] = {
+ /* lowest to highest */
+ 0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39, 0x38,
+ 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30,
+ 0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29, 0x28,
+ 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20,
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F
+};
+
+void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask)
+{
+ msg_port_write(unit, addr,
+ (msg_port_read(unit, addr) & ~(mask)) |
+ ((data) & (mask)));
+}
+
+void mrc_alt_write_mask(u32 unit, u32 addr, u32 data, u32 mask)
+{
+ msg_port_alt_write(unit, addr,
+ (msg_port_alt_read(unit, addr) & ~(mask)) |
+ ((data) & (mask)));
+}
+
+void mrc_post_code(uint8_t major, uint8_t minor)
+{
+ /* send message to UART */
+ DPF(D_INFO, "POST: 0x%01x%02x\n", major, minor);
+
+ /* error check */
+ if (major == 0xee)
+ hang();
+}
+
+/* Delay number of nanoseconds */
+void delay_n(uint32_t ns)
+{
+ /* 1000 MHz clock has 1ns period --> no conversion required */
+ uint64_t final_tsc = rdtsc();
+
+ final_tsc += ((get_tbclk_mhz() * ns) / 1000);
+
+ while (rdtsc() < final_tsc)
+ ;
+}
+
+/* Delay number of microseconds */
+void delay_u(uint32_t ms)
+{
+ /* 64-bit math is not an option, just use loops */
+ while (ms--)
+ delay_n(1000);
+}
+
+/* Select Memory Manager as the source for PRI interface */
+void select_mem_mgr(void)
+{
+ u32 dco;
+
+ ENTERFN();
+
+ dco = msg_port_read(MEM_CTLR, DCO);
+ dco &= ~BIT28;
+ msg_port_write(MEM_CTLR, DCO, dco);
+
+ LEAVEFN();
+}
+
+/* Select HTE as the source for PRI interface */
+void select_hte(void)
+{
+ u32 dco;
+
+ ENTERFN();
+
+ dco = msg_port_read(MEM_CTLR, DCO);
+ dco |= BIT28;
+ msg_port_write(MEM_CTLR, DCO, dco);
+
+ LEAVEFN();
+}
+
+/*
+ * Send DRAM command
+ * data should be formated using DCMD_Xxxx macro or emrsXCommand structure
+ */
+void dram_init_command(uint32_t data)
+{
+ pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, data);
+ pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, 0);
+ msg_port_setup(MSG_OP_DRAM_INIT, MEM_CTLR, 0);
+
+ DPF(D_REGWR, "WR32 %03X %08X %08X\n", MEM_CTLR, 0, data);
+}
+
+/* Send DRAM wake command using special MCU side-band WAKE opcode */
+void dram_wake_command(void)
+{
+ ENTERFN();
+
+ msg_port_setup(MSG_OP_DRAM_WAKE, MEM_CTLR, 0);
+
+ LEAVEFN();
+}
+
+void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane)
+{
+ /* send message to UART */
+ DPF(D_INFO, "CH%01X RK%01X BL%01X\n", channel, rank, byte_lane);
+}
+
+/*
+ * This function will program the RCVEN delays
+ *
+ * (currently doesn't comprehend rank)
+ */
+void set_rcvn(uint8_t channel, uint8_t rank,
+ uint8_t byte_lane, uint32_t pi_count)
+{
+ uint32_t reg;
+ uint32_t msk;
+ uint32_t temp;
+
+ ENTERFN();
+
+ DPF(D_TRN, "Rcvn ch%d rnk%d ln%d : pi=%03X\n",
+ channel, rank, byte_lane, pi_count);
+
+ /*
+ * RDPTR (1/2 MCLK, 64 PIs)
+ * BL0 -> B01PTRCTL0[11:08] (0x0-0xF)
+ * BL1 -> B01PTRCTL0[23:20] (0x0-0xF)
+ */
+ reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET);
+ msk = (byte_lane & BIT0) ? (BIT23 | BIT22 | BIT21 | BIT20) :
+ (BIT11 | BIT10 | BIT9 | BIT8);
+ temp = (byte_lane & BIT0) ? ((pi_count / HALF_CLK) << 20) :
+ ((pi_count / HALF_CLK) << 8);
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /* Adjust PI_COUNT */
+ pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
+
+ /*
+ * PI (1/64 MCLK, 1 PIs)
+ * BL0 -> B0DLLPICODER0[29:24] (0x00-0x3F)
+ * BL1 -> B1DLLPICODER0[29:24] (0x00-0x3F)
+ */
+ reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
+ reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET));
+ msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24);
+ temp = pi_count << 24;
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /*
+ * DEADBAND
+ * BL0/1 -> B01DBCTL1[08/11] (+1 select)
+ * BL0/1 -> B01DBCTL1[02/05] (enable)
+ */
+ reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET);
+ msk = 0x00;
+ temp = 0x00;
+
+ /* enable */
+ msk |= (byte_lane & BIT0) ? BIT5 : BIT2;
+ if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
+ temp |= msk;
+
+ /* select */
+ msk |= (byte_lane & BIT0) ? BIT11 : BIT8;
+ if (pi_count < EARLY_DB)
+ temp |= msk;
+
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /* error check */
+ if (pi_count > 0x3F) {
+ training_message(channel, rank, byte_lane);
+ mrc_post_code(0xee, 0xe0);
+ }
+
+ LEAVEFN();
+}
+
+/*
+ * This function will return the current RCVEN delay on the given
+ * channel, rank, byte_lane as an absolute PI count.
+ *
+ * (currently doesn't comprehend rank)
+ */
+uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane)
+{
+ uint32_t reg;
+ uint32_t temp;
+ uint32_t pi_count;
+
+ ENTERFN();
+
+ /*
+ * RDPTR (1/2 MCLK, 64 PIs)
+ * BL0 -> B01PTRCTL0[11:08] (0x0-0xF)
+ * BL1 -> B01PTRCTL0[23:20] (0x0-0xF)
+ */
+ reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET);
+ temp = msg_port_alt_read(DDRPHY, reg);
+ temp >>= (byte_lane & BIT0) ? 20 : 8;
+ temp &= 0xF;
+
+ /* Adjust PI_COUNT */
+ pi_count = temp * HALF_CLK;
+
+ /*
+ * PI (1/64 MCLK, 1 PIs)
+ * BL0 -> B0DLLPICODER0[29:24] (0x00-0x3F)
+ * BL1 -> B1DLLPICODER0[29:24] (0x00-0x3F)
+ */
+ reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
+ reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET));
+ temp = msg_port_alt_read(DDRPHY, reg);
+ temp >>= 24;
+ temp &= 0x3F;
+
+ /* Adjust PI_COUNT */
+ pi_count += temp;
+
+ LEAVEFN();
+
+ return pi_count;
+}
+
+/*
+ * This function will program the RDQS delays based on an absolute
+ * amount of PIs.
+ *
+ * (currently doesn't comprehend rank)
+ */
+void set_rdqs(uint8_t channel, uint8_t rank,
+ uint8_t byte_lane, uint32_t pi_count)
+{
+ uint32_t reg;
+ uint32_t msk;
+ uint32_t temp;
+
+ ENTERFN();
+ DPF(D_TRN, "Rdqs ch%d rnk%d ln%d : pi=%03X\n",
+ channel, rank, byte_lane, pi_count);
+
+ /*
+ * PI (1/128 MCLK)
+ * BL0 -> B0RXDQSPICODE[06:00] (0x00-0x47)
+ * BL1 -> B1RXDQSPICODE[06:00] (0x00-0x47)
+ */
+ reg = (byte_lane & BIT0) ? B1RXDQSPICODE : B0RXDQSPICODE;
+ reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET));
+ msk = (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
+ temp = pi_count << 0;
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /* error check (shouldn't go above 0x3F) */
+ if (pi_count > 0x47) {
+ training_message(channel, rank, byte_lane);
+ mrc_post_code(0xee, 0xe1);
+ }
+
+ LEAVEFN();
+}
+
+/*
+ * This function will return the current RDQS delay on the given
+ * channel, rank, byte_lane as an absolute PI count.
+ *
+ * (currently doesn't comprehend rank)
+ */
+uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane)
+{
+ uint32_t reg;
+ uint32_t temp;
+ uint32_t pi_count;
+
+ ENTERFN();
+
+ /*
+ * PI (1/128 MCLK)
+ * BL0 -> B0RXDQSPICODE[06:00] (0x00-0x47)
+ * BL1 -> B1RXDQSPICODE[06:00] (0x00-0x47)
+ */
+ reg = (byte_lane & BIT0) ? B1RXDQSPICODE : B0RXDQSPICODE;
+ reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET));
+ temp = msg_port_alt_read(DDRPHY, reg);
+
+ /* Adjust PI_COUNT */
+ pi_count = temp & 0x7F;
+
+ LEAVEFN();
+
+ return pi_count;
+}
+
+/*
+ * This function will program the WDQS delays based on an absolute
+ * amount of PIs.
+ *
+ * (currently doesn't comprehend rank)
+ */
+void set_wdqs(uint8_t channel, uint8_t rank,
+ uint8_t byte_lane, uint32_t pi_count)
+{
+ uint32_t reg;
+ uint32_t msk;
+ uint32_t temp;
+
+ ENTERFN();
+
+ DPF(D_TRN, "Wdqs ch%d rnk%d ln%d : pi=%03X\n",
+ channel, rank, byte_lane, pi_count);
+
+ /*
+ * RDPTR (1/2 MCLK, 64 PIs)
+ * BL0 -> B01PTRCTL0[07:04] (0x0-0xF)
+ * BL1 -> B01PTRCTL0[19:16] (0x0-0xF)
+ */
+ reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET);
+ msk = (byte_lane & BIT0) ? (BIT19 | BIT18 | BIT17 | BIT16) :
+ (BIT7 | BIT6 | BIT5 | BIT4);
+ temp = pi_count / HALF_CLK;
+ temp <<= (byte_lane & BIT0) ? 16 : 4;
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /* Adjust PI_COUNT */
+ pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
+
+ /*
+ * PI (1/64 MCLK, 1 PIs)
+ * BL0 -> B0DLLPICODER0[21:16] (0x00-0x3F)
+ * BL1 -> B1DLLPICODER0[21:16] (0x00-0x3F)
+ */
+ reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
+ reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET));
+ msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16);
+ temp = pi_count << 16;
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /*
+ * DEADBAND
+ * BL0/1 -> B01DBCTL1[07/10] (+1 select)
+ * BL0/1 -> B01DBCTL1[01/04] (enable)
+ */
+ reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET);
+ msk = 0x00;
+ temp = 0x00;
+
+ /* enable */
+ msk |= (byte_lane & BIT0) ? BIT4 : BIT1;
+ if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
+ temp |= msk;
+
+ /* select */
+ msk |= (byte_lane & BIT0) ? BIT10 : BIT7;
+ if (pi_count < EARLY_DB)
+ temp |= msk;
+
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /* error check */
+ if (pi_count > 0x3F) {
+ training_message(channel, rank, byte_lane);
+ mrc_post_code(0xee, 0xe2);
+ }
+
+ LEAVEFN();
+}
+
+/*
+ * This function will return the amount of WDQS delay on the given
+ * channel, rank, byte_lane as an absolute PI count.
+ *
+ * (currently doesn't comprehend rank)
+ */
+uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane)
+{
+ uint32_t reg;
+ uint32_t temp;
+ uint32_t pi_count;
+
+ ENTERFN();
+
+ /*
+ * RDPTR (1/2 MCLK, 64 PIs)
+ * BL0 -> B01PTRCTL0[07:04] (0x0-0xF)
+ * BL1 -> B01PTRCTL0[19:16] (0x0-0xF)
+ */
+ reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET);
+ temp = msg_port_alt_read(DDRPHY, reg);
+ temp >>= (byte_lane & BIT0) ? 16 : 4;
+ temp &= 0xF;
+
+ /* Adjust PI_COUNT */
+ pi_count = (temp * HALF_CLK);
+
+ /*
+ * PI (1/64 MCLK, 1 PIs)
+ * BL0 -> B0DLLPICODER0[21:16] (0x00-0x3F)
+ * BL1 -> B1DLLPICODER0[21:16] (0x00-0x3F)
+ */
+ reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
+ reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET));
+ temp = msg_port_alt_read(DDRPHY, reg);
+ temp >>= 16;
+ temp &= 0x3F;
+
+ /* Adjust PI_COUNT */
+ pi_count += temp;
+
+ LEAVEFN();
+
+ return pi_count;
+}
+
+/*
+ * This function will program the WDQ delays based on an absolute
+ * number of PIs.
+ *
+ * (currently doesn't comprehend rank)
+ */
+void set_wdq(uint8_t channel, uint8_t rank,
+ uint8_t byte_lane, uint32_t pi_count)
+{
+ uint32_t reg;
+ uint32_t msk;
+ uint32_t temp;
+
+ ENTERFN();
+
+ DPF(D_TRN, "Wdq ch%d rnk%d ln%d : pi=%03X\n",
+ channel, rank, byte_lane, pi_count);
+
+ /*
+ * RDPTR (1/2 MCLK, 64 PIs)
+ * BL0 -> B01PTRCTL0[03:00] (0x0-0xF)
+ * BL1 -> B01PTRCTL0[15:12] (0x0-0xF)
+ */
+ reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET);
+ msk = (byte_lane & BIT0) ? (BIT15 | BIT14 | BIT13 | BIT12) :
+ (BIT3 | BIT2 | BIT1 | BIT0);
+ temp = pi_count / HALF_CLK;
+ temp <<= (byte_lane & BIT0) ? 12 : 0;
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /* Adjust PI_COUNT */
+ pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
+
+ /*
+ * PI (1/64 MCLK, 1 PIs)
+ * BL0 -> B0DLLPICODER0[13:08] (0x00-0x3F)
+ * BL1 -> B1DLLPICODER0[13:08] (0x00-0x3F)
+ */
+ reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
+ reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET));
+ msk = (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8);
+ temp = pi_count << 8;
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /*
+ * DEADBAND
+ * BL0/1 -> B01DBCTL1[06/09] (+1 select)
+ * BL0/1 -> B01DBCTL1[00/03] (enable)
+ */
+ reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET);
+ msk = 0x00;
+ temp = 0x00;
+
+ /* enable */
+ msk |= (byte_lane & BIT0) ? BIT3 : BIT0;
+ if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
+ temp |= msk;
+
+ /* select */
+ msk |= (byte_lane & BIT0) ? BIT9 : BIT6;
+ if (pi_count < EARLY_DB)
+ temp |= msk;
+
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /* error check */
+ if (pi_count > 0x3F) {
+ training_message(channel, rank, byte_lane);
+ mrc_post_code(0xee, 0xe3);
+ }
+
+ LEAVEFN();
+}
+
+/*
+ * This function will return the amount of WDQ delay on the given
+ * channel, rank, byte_lane as an absolute PI count.
+ *
+ * (currently doesn't comprehend rank)
+ */
+uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane)
+{
+ uint32_t reg;
+ uint32_t temp;
+ uint32_t pi_count;
+
+ ENTERFN();
+
+ /*
+ * RDPTR (1/2 MCLK, 64 PIs)
+ * BL0 -> B01PTRCTL0[03:00] (0x0-0xF)
+ * BL1 -> B01PTRCTL0[15:12] (0x0-0xF)
+ */
+ reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET);
+ temp = msg_port_alt_read(DDRPHY, reg);
+ temp >>= (byte_lane & BIT0) ? (12) : (0);
+ temp &= 0xF;
+
+ /* Adjust PI_COUNT */
+ pi_count = temp * HALF_CLK;
+
+ /*
+ * PI (1/64 MCLK, 1 PIs)
+ * BL0 -> B0DLLPICODER0[13:08] (0x00-0x3F)
+ * BL1 -> B1DLLPICODER0[13:08] (0x00-0x3F)
+ */
+ reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
+ reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET));
+ temp = msg_port_alt_read(DDRPHY, reg);
+ temp >>= 8;
+ temp &= 0x3F;
+
+ /* Adjust PI_COUNT */
+ pi_count += temp;
+
+ LEAVEFN();
+
+ return pi_count;
+}
+
+/*
+ * This function will program the WCMD delays based on an absolute
+ * number of PIs.
+ */
+void set_wcmd(uint8_t channel, uint32_t pi_count)
+{
+ uint32_t reg;
+ uint32_t msk;
+ uint32_t temp;
+
+ ENTERFN();
+
+ /*
+ * RDPTR (1/2 MCLK, 64 PIs)
+ * CMDPTRREG[11:08] (0x0-0xF)
+ */
+ reg = CMDPTRREG + (channel * DDRIOCCC_CH_OFFSET);
+ msk = (BIT11 | BIT10 | BIT9 | BIT8);
+ temp = pi_count / HALF_CLK;
+ temp <<= 8;
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /* Adjust PI_COUNT */
+ pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
+
+ /*
+ * PI (1/64 MCLK, 1 PIs)
+ * CMDDLLPICODER0[29:24] -> CMDSLICE R3 (unused)
+ * CMDDLLPICODER0[21:16] -> CMDSLICE L3 (unused)
+ * CMDDLLPICODER0[13:08] -> CMDSLICE R2 (unused)
+ * CMDDLLPICODER0[05:00] -> CMDSLICE L2 (unused)
+ * CMDDLLPICODER1[29:24] -> CMDSLICE R1 (unused)
+ * CMDDLLPICODER1[21:16] -> CMDSLICE L1 (0x00-0x3F)
+ * CMDDLLPICODER1[13:08] -> CMDSLICE R0 (unused)
+ * CMDDLLPICODER1[05:00] -> CMDSLICE L0 (unused)
+ */
+ reg = CMDDLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET);
+
+ msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24 |
+ BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 |
+ BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 |
+ BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
+
+ temp = (pi_count << 24) | (pi_count << 16) |
+ (pi_count << 8) | (pi_count << 0);
+
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+ reg = CMDDLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET); /* PO */
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /*
+ * DEADBAND
+ * CMDCFGREG0[17] (+1 select)
+ * CMDCFGREG0[16] (enable)
+ */
+ reg = CMDCFGREG0 + (channel * DDRIOCCC_CH_OFFSET);
+ msk = 0x00;
+ temp = 0x00;
+
+ /* enable */
+ msk |= BIT16;
+ if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
+ temp |= msk;
+
+ /* select */
+ msk |= BIT17;
+ if (pi_count < EARLY_DB)
+ temp |= msk;
+
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /* error check */
+ if (pi_count > 0x3F)
+ mrc_post_code(0xee, 0xe4);
+
+ LEAVEFN();
+}
+
+/*
+ * This function will return the amount of WCMD delay on the given
+ * channel as an absolute PI count.
+ */
+uint32_t get_wcmd(uint8_t channel)
+{
+ uint32_t reg;
+ uint32_t temp;
+ uint32_t pi_count;
+
+ ENTERFN();
+
+ /*
+ * RDPTR (1/2 MCLK, 64 PIs)
+ * CMDPTRREG[11:08] (0x0-0xF)
+ */
+ reg = CMDPTRREG + (channel * DDRIOCCC_CH_OFFSET);
+ temp = msg_port_alt_read(DDRPHY, reg);
+ temp >>= 8;
+ temp &= 0xF;
+
+ /* Adjust PI_COUNT */
+ pi_count = temp * HALF_CLK;
+
+ /*
+ * PI (1/64 MCLK, 1 PIs)
+ * CMDDLLPICODER0[29:24] -> CMDSLICE R3 (unused)
+ * CMDDLLPICODER0[21:16] -> CMDSLICE L3 (unused)
+ * CMDDLLPICODER0[13:08] -> CMDSLICE R2 (unused)
+ * CMDDLLPICODER0[05:00] -> CMDSLICE L2 (unused)
+ * CMDDLLPICODER1[29:24] -> CMDSLICE R1 (unused)
+ * CMDDLLPICODER1[21:16] -> CMDSLICE L1 (0x00-0x3F)
+ * CMDDLLPICODER1[13:08] -> CMDSLICE R0 (unused)
+ * CMDDLLPICODER1[05:00] -> CMDSLICE L0 (unused)
+ */
+ reg = CMDDLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET);
+ temp = msg_port_alt_read(DDRPHY, reg);
+ temp >>= 16;
+ temp &= 0x3F;
+
+ /* Adjust PI_COUNT */
+ pi_count += temp;
+
+ LEAVEFN();
+
+ return pi_count;
+}
+
+/*
+ * This function will program the WCLK delays based on an absolute
+ * number of PIs.
+ */
+void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count)
+{
+ uint32_t reg;
+ uint32_t msk;
+ uint32_t temp;
+
+ ENTERFN();
+
+ /*
+ * RDPTR (1/2 MCLK, 64 PIs)
+ * CCPTRREG[15:12] -> CLK1 (0x0-0xF)
+ * CCPTRREG[11:08] -> CLK0 (0x0-0xF)
+ */
+ reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET);
+ msk = (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8);
+ temp = ((pi_count / HALF_CLK) << 12) | ((pi_count / HALF_CLK) << 8);
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /* Adjust PI_COUNT */
+ pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
+
+ /*
+ * PI (1/64 MCLK, 1 PIs)
+ * ECCB1DLLPICODER0[13:08] -> CLK0 (0x00-0x3F)
+ * ECCB1DLLPICODER0[21:16] -> CLK1 (0x00-0x3F)
+ */
+ reg = rank ? ECCB1DLLPICODER0 : ECCB1DLLPICODER0;
+ reg += (channel * DDRIOCCC_CH_OFFSET);
+ msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 |
+ BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8);
+ temp = (pi_count << 16) | (pi_count << 8);
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+ reg = rank ? ECCB1DLLPICODER1 : ECCB1DLLPICODER1;
+ reg += (channel * DDRIOCCC_CH_OFFSET);
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+ reg = rank ? ECCB1DLLPICODER2 : ECCB1DLLPICODER2;
+ reg += (channel * DDRIOCCC_CH_OFFSET);
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+ reg = rank ? ECCB1DLLPICODER3 : ECCB1DLLPICODER3;
+ reg += (channel * DDRIOCCC_CH_OFFSET);
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /*
+ * DEADBAND
+ * CCCFGREG1[11:08] (+1 select)
+ * CCCFGREG1[03:00] (enable)
+ */
+ reg = CCCFGREG1 + (channel * DDRIOCCC_CH_OFFSET);
+ msk = 0x00;
+ temp = 0x00;
+
+ /* enable */
+ msk |= (BIT3 | BIT2 | BIT1 | BIT0);
+ if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
+ temp |= msk;
+
+ /* select */
+ msk |= (BIT11 | BIT10 | BIT9 | BIT8);
+ if (pi_count < EARLY_DB)
+ temp |= msk;
+
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /* error check */
+ if (pi_count > 0x3F)
+ mrc_post_code(0xee, 0xe5);
+
+ LEAVEFN();
+}
+
+/*
+ * This function will return the amout of WCLK delay on the given
+ * channel, rank as an absolute PI count.
+ */
+uint32_t get_wclk(uint8_t channel, uint8_t rank)
+{
+ uint32_t reg;
+ uint32_t temp;
+ uint32_t pi_count;
+
+ ENTERFN();
+
+ /*
+ * RDPTR (1/2 MCLK, 64 PIs)
+ * CCPTRREG[15:12] -> CLK1 (0x0-0xF)
+ * CCPTRREG[11:08] -> CLK0 (0x0-0xF)
+ */
+ reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET);
+ temp = msg_port_alt_read(DDRPHY, reg);
+ temp >>= rank ? 12 : 8;
+ temp &= 0xF;
+
+ /* Adjust PI_COUNT */
+ pi_count = temp * HALF_CLK;
+
+ /*
+ * PI (1/64 MCLK, 1 PIs)
+ * ECCB1DLLPICODER0[13:08] -> CLK0 (0x00-0x3F)
+ * ECCB1DLLPICODER0[21:16] -> CLK1 (0x00-0x3F)
+ */
+ reg = rank ? ECCB1DLLPICODER0 : ECCB1DLLPICODER0;
+ reg += (channel * DDRIOCCC_CH_OFFSET);
+ temp = msg_port_alt_read(DDRPHY, reg);
+ temp >>= rank ? 16 : 8;
+ temp &= 0x3F;
+
+ pi_count += temp;
+
+ LEAVEFN();
+
+ return pi_count;
+}
+
+/*
+ * This function will program the WCTL delays based on an absolute
+ * number of PIs.
+ *
+ * (currently doesn't comprehend rank)
+ */
+void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count)
+{
+ uint32_t reg;
+ uint32_t msk;
+ uint32_t temp;
+
+ ENTERFN();
+
+ /*
+ * RDPTR (1/2 MCLK, 64 PIs)
+ * CCPTRREG[31:28] (0x0-0xF)
+ * CCPTRREG[27:24] (0x0-0xF)
+ */
+ reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET);
+ msk = (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24);
+ temp = ((pi_count / HALF_CLK) << 28) | ((pi_count / HALF_CLK) << 24);
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /* Adjust PI_COUNT */
+ pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
+
+ /*
+ * PI (1/64 MCLK, 1 PIs)
+ * ECCB1DLLPICODER?[29:24] (0x00-0x3F)
+ * ECCB1DLLPICODER?[29:24] (0x00-0x3F)
+ */
+ reg = ECCB1DLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET);
+ msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24);
+ temp = (pi_count << 24);
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+ reg = ECCB1DLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET);
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+ reg = ECCB1DLLPICODER2 + (channel * DDRIOCCC_CH_OFFSET);
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+ reg = ECCB1DLLPICODER3 + (channel * DDRIOCCC_CH_OFFSET);
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /*
+ * DEADBAND
+ * CCCFGREG1[13:12] (+1 select)
+ * CCCFGREG1[05:04] (enable)
+ */
+ reg = CCCFGREG1 + (channel * DDRIOCCC_CH_OFFSET);
+ msk = 0x00;
+ temp = 0x00;
+
+ /* enable */
+ msk |= (BIT5 | BIT4);
+ if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
+ temp |= msk;
+
+ /* select */
+ msk |= (BIT13 | BIT12);
+ if (pi_count < EARLY_DB)
+ temp |= msk;
+
+ mrc_alt_write_mask(DDRPHY, reg, temp, msk);
+
+ /* error check */
+ if (pi_count > 0x3F)
+ mrc_post_code(0xee, 0xe6);
+
+ LEAVEFN();
+}
+
+/*
+ * This function will return the amount of WCTL delay on the given
+ * channel, rank as an absolute PI count.
+ *
+ * (currently doesn't comprehend rank)
+ */
+uint32_t get_wctl(uint8_t channel, uint8_t rank)
+{
+ uint32_t reg;
+ uint32_t temp;
+ uint32_t pi_count;
+
+ ENTERFN();
+
+ /*
+ * RDPTR (1/2 MCLK, 64 PIs)
+ * CCPTRREG[31:28] (0x0-0xF)
+ * CCPTRREG[27:24] (0x0-0xF)
+ */
+ reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET);
+ temp = msg_port_alt_read(DDRPHY, reg);
+ temp >>= 24;
+ temp &= 0xF;
+
+ /* Adjust PI_COUNT */
+ pi_count = temp * HALF_CLK;
+
+ /*
+ * PI (1/64 MCLK, 1 PIs)
+ * ECCB1DLLPICODER?[29:24] (0x00-0x3F)
+ * ECCB1DLLPICODER?[29:24] (0x00-0x3F)
+ */
+ reg = ECCB1DLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET);
+ temp = msg_port_alt_read(DDRPHY, reg);
+ temp >>= 24;
+ temp &= 0x3F;
+
+ /* Adjust PI_COUNT */
+ pi_count += temp;
+
+ LEAVEFN();
+
+ return pi_count;
+}
+
+/*
+ * This function will program the internal Vref setting in a given
+ * byte lane in a given channel.
+ */
+void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting)
+{
+ uint32_t reg = (byte_lane & 0x1) ? (B1VREFCTL) : (B0VREFCTL);
+
+ ENTERFN();
+
+ DPF(D_TRN, "Vref ch%d ln%d : val=%03X\n",
+ channel, byte_lane, setting);
+
+ mrc_alt_write_mask(DDRPHY, (reg + (channel * DDRIODQ_CH_OFFSET) +
+ ((byte_lane >> 1) * DDRIODQ_BL_OFFSET)),
+ (vref_codes[setting] << 2),
+ (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2));
+
+ /*
+ * need to wait ~300ns for Vref to settle
+ * (check that this is necessary)
+ */
+ delay_n(300);
+
+ /* ??? may need to clear pointers ??? */
+
+ LEAVEFN();
+}
+
+/*
+ * This function will return the internal Vref setting for the given
+ * channel, byte_lane.
+ */
+uint32_t get_vref(uint8_t channel, uint8_t byte_lane)
+{
+ uint8_t j;
+ uint32_t ret_val = sizeof(vref_codes) / 2;
+ uint32_t reg = (byte_lane & 0x1) ? (B1VREFCTL) : (B0VREFCTL);
+ uint32_t temp;
+
+ ENTERFN();
+
+ temp = msg_port_alt_read(DDRPHY, (reg + (channel * DDRIODQ_CH_OFFSET) +
+ ((byte_lane >> 1) * DDRIODQ_BL_OFFSET)));
+ temp >>= 2;
+ temp &= 0x3F;
+
+ for (j = 0; j < sizeof(vref_codes); j++) {
+ if (vref_codes[j] == temp) {
+ ret_val = j;
+ break;
+ }
+ }
+
+ LEAVEFN();
+
+ return ret_val;
+}
+
+/*
+ * This function will return a 32-bit address in the desired
+ * channel and rank.
+ */
+uint32_t get_addr(uint8_t channel, uint8_t rank)
+{
+ uint32_t offset = 0x02000000; /* 32MB */
+
+ /* Begin product specific code */
+ if (channel > 0) {
+ DPF(D_ERROR, "ILLEGAL CHANNEL\n");
+ DEAD_LOOP();
+ }
+
+ if (rank > 1) {
+ DPF(D_ERROR, "ILLEGAL RANK\n");
+ DEAD_LOOP();
+ }
+
+ /* use 256MB lowest density as per DRP == 0x0003 */
+ offset += rank * (256 * 1024 * 1024);
+
+ return offset;
+}
+
+/*
+ * This function will sample the DQTRAINSTS registers in the given
+ * channel/rank SAMPLE_SIZE times looking for a valid '0' or '1'.
+ *
+ * It will return an encoded 32-bit date in which each bit corresponds to
+ * the sampled value on the byte lane.
+ */
+uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel,
+ uint8_t rank, bool rcvn)
+{
+ uint8_t j; /* just a counter */
+ uint8_t bl; /* which BL in the module (always 2 per module) */
+ uint8_t bl_grp; /* which BL module */
+ /* byte lane divisor */
+ uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1;
+ uint32_t msk[2]; /* BLx in module */
+ /* DQTRAINSTS register contents for each sample */
+ uint32_t sampled_val[SAMPLE_SIZE];
+ uint32_t num_0s; /* tracks the number of '0' samples */
+ uint32_t num_1s; /* tracks the number of '1' samples */
+ uint32_t ret_val = 0x00; /* assume all '0' samples */
+ uint32_t address = get_addr(channel, rank);
+
+ /* initialise msk[] */
+ msk[0] = rcvn ? BIT1 : BIT9; /* BL0 */
+ msk[1] = rcvn ? BIT0 : BIT8; /* BL1 */
+
+ /* cycle through each byte lane group */
+ for (bl_grp = 0; bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) {
+ /* take SAMPLE_SIZE samples */
+ for (j = 0; j < SAMPLE_SIZE; j++) {
+ hte_mem_op(address, mrc_params->first_run,
+ rcvn ? 0 : 1);
+ mrc_params->first_run = 0;
+
+ /*
+ * record the contents of the proper
+ * DQTRAINSTS register
+ */
+ sampled_val[j] = msg_port_alt_read(DDRPHY,
+ (DQTRAINSTS +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET)));
+ }
+
+ /*
+ * look for a majority value (SAMPLE_SIZE / 2) + 1
+ * on the byte lane and set that value in the corresponding
+ * ret_val bit
+ */
+ for (bl = 0; bl < 2; bl++) {
+ num_0s = 0x00; /* reset '0' tracker for byte lane */
+ num_1s = 0x00; /* reset '1' tracker for byte lane */
+ for (j = 0; j < SAMPLE_SIZE; j++) {
+ if (sampled_val[j] & msk[bl])
+ num_1s++;
+ else
+ num_0s++;
+ }
+ if (num_1s > num_0s)
+ ret_val |= (1 << (bl + (bl_grp * 2)));
+ }
+ }
+
+ /*
+ * "ret_val.0" contains the status of BL0
+ * "ret_val.1" contains the status of BL1
+ * "ret_val.2" contains the status of BL2
+ * etc.
+ */
+ return ret_val;
+}
+
+/* This function will find the rising edge transition on RCVN or WDQS */
+void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[],
+ uint8_t channel, uint8_t rank, bool rcvn)
+{
+ bool all_edges_found; /* determines stop condition */
+ bool direction[NUM_BYTE_LANES]; /* direction indicator */
+ uint8_t sample; /* sample counter */
+ uint8_t bl; /* byte lane counter */
+ /* byte lane divisor */
+ uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1;
+ uint32_t sample_result[SAMPLE_CNT]; /* results of sample_dqs() */
+ uint32_t temp;
+ uint32_t transition_pattern;
+
+ ENTERFN();
+
+ /* select hte and request initial configuration */
+ select_hte();
+ mrc_params->first_run = 1;
+
+ /* Take 3 sample points (T1,T2,T3) to obtain a transition pattern */
+ for (sample = 0; sample < SAMPLE_CNT; sample++) {
+ /* program the desired delays for sample */
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ /* increase sample delay by 26 PI (0.2 CLK) */
+ if (rcvn) {
+ set_rcvn(channel, rank, bl,
+ delay[bl] + (sample * SAMPLE_DLY));
+ } else {
+ set_wdqs(channel, rank, bl,
+ delay[bl] + (sample * SAMPLE_DLY));
+ }
+ }
+
+ /* take samples (Tsample_i) */
+ sample_result[sample] = sample_dqs(mrc_params,
+ channel, rank, rcvn);
+
+ DPF(D_TRN,
+ "Find rising edge %s ch%d rnk%d: #%d dly=%d dqs=%02X\n",
+ (rcvn ? "RCVN" : "WDQS"), channel, rank, sample,
+ sample * SAMPLE_DLY, sample_result[sample]);
+ }
+
+ /*
+ * This pattern will help determine where we landed and ultimately
+ * how to place RCVEN/WDQS.
+ */
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ /* build transition_pattern (MSB is 1st sample) */
+ transition_pattern = 0;
+ for (sample = 0; sample < SAMPLE_CNT; sample++) {
+ transition_pattern |=
+ ((sample_result[sample] & (1 << bl)) >> bl) <<
+ (SAMPLE_CNT - 1 - sample);
+ }
+
+ DPF(D_TRN, "=== transition pattern %d\n", transition_pattern);
+
+ /*
+ * set up to look for rising edge based on
+ * transition_pattern
+ */
+ switch (transition_pattern) {
+ case 0: /* sampled 0->0->0 */
+ /* move forward from T3 looking for 0->1 */
+ delay[bl] += 2 * SAMPLE_DLY;
+ direction[bl] = FORWARD;
+ break;
+ case 1: /* sampled 0->0->1 */
+ case 5: /* sampled 1->0->1 (bad duty cycle) *HSD#237503* */
+ /* move forward from T2 looking for 0->1 */
+ delay[bl] += 1 * SAMPLE_DLY;
+ direction[bl] = FORWARD;
+ break;
+ case 2: /* sampled 0->1->0 (bad duty cycle) *HSD#237503* */
+ case 3: /* sampled 0->1->1 */
+ /* move forward from T1 looking for 0->1 */
+ delay[bl] += 0 * SAMPLE_DLY;
+ direction[bl] = FORWARD;
+ break;
+ case 4: /* sampled 1->0->0 (assumes BL8, HSD#234975) */
+ /* move forward from T3 looking for 0->1 */
+ delay[bl] += 2 * SAMPLE_DLY;
+ direction[bl] = FORWARD;
+ break;
+ case 6: /* sampled 1->1->0 */
+ case 7: /* sampled 1->1->1 */
+ /* move backward from T1 looking for 1->0 */
+ delay[bl] += 0 * SAMPLE_DLY;
+ direction[bl] = BACKWARD;
+ break;
+ default:
+ mrc_post_code(0xee, 0xee);
+ break;
+ }
+
+ /* program delays */
+ if (rcvn)
+ set_rcvn(channel, rank, bl, delay[bl]);
+ else
+ set_wdqs(channel, rank, bl, delay[bl]);
+ }
+
+ /*
+ * Based on the observed transition pattern on the byte lane,
+ * begin looking for a rising edge with single PI granularity.
+ */
+ do {
+ all_edges_found = true; /* assume all byte lanes passed */
+ /* take a sample */
+ temp = sample_dqs(mrc_params, channel, rank, rcvn);
+ /* check all each byte lane for proper edge */
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ if (temp & (1 << bl)) {
+ /* sampled "1" */
+ if (direction[bl] == BACKWARD) {
+ /*
+ * keep looking for edge
+ * on this byte lane
+ */
+ all_edges_found = false;
+ delay[bl] -= 1;
+ if (rcvn) {
+ set_rcvn(channel, rank,
+ bl, delay[bl]);
+ } else {
+ set_wdqs(channel, rank,
+ bl, delay[bl]);
+ }
+ }
+ } else {
+ /* sampled "0" */
+ if (direction[bl] == FORWARD) {
+ /*
+ * keep looking for edge
+ * on this byte lane
+ */
+ all_edges_found = false;
+ delay[bl] += 1;
+ if (rcvn) {
+ set_rcvn(channel, rank,
+ bl, delay[bl]);
+ } else {
+ set_wdqs(channel, rank,
+ bl, delay[bl]);
+ }
+ }
+ }
+ }
+ } while (!all_edges_found);
+
+ /* restore DDR idle state */
+ dram_init_command(DCMD_PREA(rank));
+
+ DPF(D_TRN, "Delay %03X %03X %03X %03X\n",
+ delay[0], delay[1], delay[2], delay[3]);
+
+ LEAVEFN();
+}
+
+/*
+ * This function will return a 32 bit mask that will be used to
+ * check for byte lane failures.
+ */
+uint32_t byte_lane_mask(struct mrc_params *mrc_params)
+{
+ uint32_t j;
+ uint32_t ret_val = 0x00;
+
+ /*
+ * set ret_val based on NUM_BYTE_LANES such that you will check
+ * only BL0 in result
+ *
+ * (each bit in result represents a byte lane)
+ */
+ for (j = 0; j < MAX_BYTE_LANES; j += NUM_BYTE_LANES)
+ ret_val |= (1 << ((j / NUM_BYTE_LANES) * NUM_BYTE_LANES));
+
+ /*
+ * HSD#235037
+ * need to adjust the mask for 16-bit mode
+ */
+ if (mrc_params->channel_width == X16)
+ ret_val |= (ret_val << 2);
+
+ return ret_val;
+}
+
+/*
+ * Check memory executing simple write/read/verify at the specified address.
+ *
+ * Bits in the result indicate failure on specific byte lane.
+ */
+uint32_t check_rw_coarse(struct mrc_params *mrc_params, uint32_t address)
+{
+ uint32_t result = 0;
+ uint8_t first_run = 0;
+
+ if (mrc_params->hte_setup) {
+ mrc_params->hte_setup = 0;
+ first_run = 1;
+ select_hte();
+ }
+
+ result = hte_basic_write_read(mrc_params, address, first_run,
+ WRITE_TRAIN);
+
+ DPF(D_TRN, "check_rw_coarse result is %x\n", result);
+
+ return result;
+}
+
+/*
+ * Check memory executing write/read/verify of many data patterns
+ * at the specified address. Bits in the result indicate failure
+ * on specific byte lane.
+ */
+uint32_t check_bls_ex(struct mrc_params *mrc_params, uint32_t address)
+{
+ uint32_t result;
+ uint8_t first_run = 0;
+
+ if (mrc_params->hte_setup) {
+ mrc_params->hte_setup = 0;
+ first_run = 1;
+ select_hte();
+ }
+
+ result = hte_write_stress_bit_lanes(mrc_params, address, first_run);
+
+ DPF(D_TRN, "check_bls_ex result is %x\n", result);
+
+ return result;
+}
+
+/*
+ * 32-bit LFSR with characteristic polynomial: X^32 + X^22 +X^2 + X^1
+ *
+ * The function takes pointer to previous 32 bit value and
+ * modifies it to next value.
+ */
+void lfsr32(uint32_t *lfsr_ptr)
+{
+ uint32_t bit;
+ uint32_t lfsr;
+ int i;
+
+ lfsr = *lfsr_ptr;
+
+ for (i = 0; i < 32; i++) {
+ bit = 1 ^ (lfsr & BIT0);
+ bit = bit ^ ((lfsr & BIT1) >> 1);
+ bit = bit ^ ((lfsr & BIT2) >> 2);
+ bit = bit ^ ((lfsr & BIT22) >> 22);
+
+ lfsr = ((lfsr >> 1) | (bit << 31));
+ }
+
+ *lfsr_ptr = lfsr;
+}
+
+/* Clear the pointers in a given byte lane in a given channel */
+void clear_pointers(void)
+{
+ uint8_t channel;
+ uint8_t bl;
+
+ ENTERFN();
+
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ for (bl = 0; bl < NUM_BYTE_LANES; bl++) {
+ mrc_alt_write_mask(DDRPHY,
+ (B01PTRCTL1 +
+ (channel * DDRIODQ_CH_OFFSET) +
+ ((bl >> 1) * DDRIODQ_BL_OFFSET)),
+ ~BIT8, BIT8);
+
+ mrc_alt_write_mask(DDRPHY,
+ (B01PTRCTL1 +
+ (channel * DDRIODQ_CH_OFFSET) +
+ ((bl >> 1) * DDRIODQ_BL_OFFSET)),
+ BIT8, BIT8);
+ }
+ }
+
+ LEAVEFN();
+}
+
+static void print_timings_internal(uint8_t algo, uint8_t channel, uint8_t rank,
+ uint8_t bl_divisor)
+{
+ uint8_t bl;
+
+ switch (algo) {
+ case RCVN:
+ DPF(D_INFO, "\nRCVN[%02d:%02d]", channel, rank);
+ break;
+ case WDQS:
+ DPF(D_INFO, "\nWDQS[%02d:%02d]", channel, rank);
+ break;
+ case WDQX:
+ DPF(D_INFO, "\nWDQx[%02d:%02d]", channel, rank);
+ break;
+ case RDQS:
+ DPF(D_INFO, "\nRDQS[%02d:%02d]", channel, rank);
+ break;
+ case VREF:
+ DPF(D_INFO, "\nVREF[%02d:%02d]", channel, rank);
+ break;
+ case WCMD:
+ DPF(D_INFO, "\nWCMD[%02d:%02d]", channel, rank);
+ break;
+ case WCTL:
+ DPF(D_INFO, "\nWCTL[%02d:%02d]", channel, rank);
+ break;
+ case WCLK:
+ DPF(D_INFO, "\nWCLK[%02d:%02d]", channel, rank);
+ break;
+ default:
+ break;
+ }
+
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ switch (algo) {
+ case RCVN:
+ DPF(D_INFO, " %03d", get_rcvn(channel, rank, bl));
+ break;
+ case WDQS:
+ DPF(D_INFO, " %03d", get_wdqs(channel, rank, bl));
+ break;
+ case WDQX:
+ DPF(D_INFO, " %03d", get_wdq(channel, rank, bl));
+ break;
+ case RDQS:
+ DPF(D_INFO, " %03d", get_rdqs(channel, rank, bl));
+ break;
+ case VREF:
+ DPF(D_INFO, " %03d", get_vref(channel, bl));
+ break;
+ case WCMD:
+ DPF(D_INFO, " %03d", get_wcmd(channel));
+ break;
+ case WCTL:
+ DPF(D_INFO, " %03d", get_wctl(channel, rank));
+ break;
+ case WCLK:
+ DPF(D_INFO, " %03d", get_wclk(channel, rank));
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+void print_timings(struct mrc_params *mrc_params)
+{
+ uint8_t algo;
+ uint8_t channel;
+ uint8_t rank;
+ uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1;
+
+ DPF(D_INFO, "\n---------------------------");
+ DPF(D_INFO, "\nALGO[CH:RK] BL0 BL1 BL2 BL3");
+ DPF(D_INFO, "\n===========================");
+
+ for (algo = 0; algo < MAX_ALGOS; algo++) {
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (mrc_params->channel_enables & (1 << channel)) {
+ for (rank = 0; rank < NUM_RANKS; rank++) {
+ if (mrc_params->rank_enables &
+ (1 << rank)) {
+ print_timings_internal(algo,
+ channel, rank,
+ bl_divisor);
+ }
+ }
+ }
+ }
+ }
+
+ DPF(D_INFO, "\n---------------------------");
+ DPF(D_INFO, "\n");
+}
diff --git a/arch/x86/cpu/quark/mrc_util.h b/arch/x86/cpu/quark/mrc_util.h
new file mode 100644
index 0000000..f0ddbce
--- /dev/null
+++ b/arch/x86/cpu/quark/mrc_util.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Ported from Intel released Quark UEFI BIOS
+ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef _MRC_UTIL_H_
+#define _MRC_UTIL_H_
+
+/* Turn on this macro to enable MRC debugging output */
+#undef MRC_DEBUG
+
+/* MRC Debug Support */
+#define DPF debug_cond
+
+/* debug print type */
+
+#ifdef MRC_DEBUG
+#define D_ERROR 0x0001
+#define D_INFO 0x0002
+#define D_REGRD 0x0004
+#define D_REGWR 0x0008
+#define D_FCALL 0x0010
+#define D_TRN 0x0020
+#define D_TIME 0x0040
+#else
+#define D_ERROR 0
+#define D_INFO 0
+#define D_REGRD 0
+#define D_REGWR 0
+#define D_FCALL 0
+#define D_TRN 0
+#define D_TIME 0
+#endif
+
+#define ENTERFN(...) debug_cond(D_FCALL, "<%s>\n", __func__)
+#define LEAVEFN(...) debug_cond(D_FCALL, "</%s>\n", __func__)
+#define REPORTFN(...) debug_cond(D_FCALL, "<%s/>\n", __func__)
+
+/* Generic Register Bits */
+#define BIT0 0x00000001
+#define BIT1 0x00000002
+#define BIT2 0x00000004
+#define BIT3 0x00000008
+#define BIT4 0x00000010
+#define BIT5 0x00000020
+#define BIT6 0x00000040
+#define BIT7 0x00000080
+#define BIT8 0x00000100
+#define BIT9 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+
+/* Message Bus Port */
+#define MEM_CTLR 0x01
+#define HOST_BRIDGE 0x03
+#define MEM_MGR 0x05
+#define HTE 0x11
+#define DDRPHY 0x12
+
+/* number of sample points */
+#define SAMPLE_CNT 3
+/* number of PIs to increment per sample */
+#define SAMPLE_DLY 26
+
+enum {
+ /* indicates to decrease delays when looking for edge */
+ BACKWARD,
+ /* indicates to increase delays when looking for edge */
+ FORWARD
+};
+
+enum {
+ RCVN,
+ WDQS,
+ WDQX,
+ RDQS,
+ VREF,
+ WCMD,
+ WCTL,
+ WCLK,
+ MAX_ALGOS,
+};
+
+void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask);
+void mrc_alt_write_mask(u32 unit, u32 addr, u32 data, u32 mask);
+void mrc_post_code(uint8_t major, uint8_t minor);
+void delay_n(uint32_t ns);
+void delay_u(uint32_t ms);
+void select_mem_mgr(void);
+void select_hte(void);
+void dram_init_command(uint32_t data);
+void dram_wake_command(void);
+void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane);
+
+void set_rcvn(uint8_t channel, uint8_t rank,
+ uint8_t byte_lane, uint32_t pi_count);
+uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane);
+void set_rdqs(uint8_t channel, uint8_t rank,
+ uint8_t byte_lane, uint32_t pi_count);
+uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
+void set_wdqs(uint8_t channel, uint8_t rank,
+ uint8_t byte_lane, uint32_t pi_count);
+uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
+void set_wdq(uint8_t channel, uint8_t rank,
+ uint8_t byte_lane, uint32_t pi_count);
+uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane);
+void set_wcmd(uint8_t channel, uint32_t pi_count);
+uint32_t get_wcmd(uint8_t channel);
+void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count);
+uint32_t get_wclk(uint8_t channel, uint8_t rank);
+void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count);
+uint32_t get_wctl(uint8_t channel, uint8_t rank);
+void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting);
+uint32_t get_vref(uint8_t channel, uint8_t byte_lane);
+
+uint32_t get_addr(uint8_t channel, uint8_t rank);
+uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel,
+ uint8_t rank, bool rcvn);
+void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[],
+ uint8_t channel, uint8_t rank, bool rcvn);
+uint32_t byte_lane_mask(struct mrc_params *mrc_params);
+uint32_t check_rw_coarse(struct mrc_params *mrc_params, uint32_t address);
+uint32_t check_bls_ex(struct mrc_params *mrc_params, uint32_t address);
+void lfsr32(uint32_t *lfsr_ptr);
+void clear_pointers(void);
+void print_timings(struct mrc_params *mrc_params);
+
+#endif /* _MRC_UTIL_H_ */
diff --git a/arch/x86/cpu/quark/msg_port.c b/arch/x86/cpu/quark/msg_port.c
new file mode 100644
index 0000000..31713e3
--- /dev/null
+++ b/arch/x86/cpu/quark/msg_port.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/arch/device.h>
+#include <asm/arch/msg_port.h>
+
+void msg_port_setup(int op, int port, int reg)
+{
+ pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
+ (((op) << 24) | ((port) << 16) |
+ (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE));
+}
+
+u32 msg_port_read(u8 port, u32 reg)
+{
+ u32 value;
+
+ pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+ reg & 0xffffff00);
+ msg_port_setup(MSG_OP_READ, port, reg);
+ pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
+
+ return value;
+}
+
+void msg_port_write(u8 port, u32 reg, u32 value)
+{
+ pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
+ pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+ reg & 0xffffff00);
+ msg_port_setup(MSG_OP_WRITE, port, reg);
+}
+
+u32 msg_port_alt_read(u8 port, u32 reg)
+{
+ u32 value;
+
+ pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+ reg & 0xffffff00);
+ msg_port_setup(MSG_OP_ALT_READ, port, reg);
+ pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
+
+ return value;
+}
+
+void msg_port_alt_write(u8 port, u32 reg, u32 value)
+{
+ pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
+ pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+ reg & 0xffffff00);
+ msg_port_setup(MSG_OP_ALT_WRITE, port, reg);
+}
+
+u32 msg_port_io_read(u8 port, u32 reg)
+{
+ u32 value;
+
+ pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+ reg & 0xffffff00);
+ msg_port_setup(MSG_OP_IO_READ, port, reg);
+ pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
+
+ return value;
+}
+
+void msg_port_io_write(u8 port, u32 reg, u32 value)
+{
+ pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
+ pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+ reg & 0xffffff00);
+ msg_port_setup(MSG_OP_IO_WRITE, port, reg);
+}
diff --git a/arch/x86/cpu/quark/pci.c b/arch/x86/cpu/quark/pci.c
new file mode 100644
index 0000000..354e15a
--- /dev/null
+++ b/arch/x86/cpu/quark/pci.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/arch/device.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_pci_setup_hose(struct pci_controller *hose)
+{
+ hose->first_busno = 0;
+ hose->last_busno = 0;
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 0,
+ CONFIG_PCI_MEM_BUS,
+ CONFIG_PCI_MEM_PHYS,
+ CONFIG_PCI_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 1,
+ CONFIG_PCI_IO_BUS,
+ CONFIG_PCI_IO_PHYS,
+ CONFIG_PCI_IO_SIZE,
+ PCI_REGION_IO);
+
+ pci_set_region(hose->regions + 2,
+ CONFIG_PCI_PREF_BUS,
+ CONFIG_PCI_PREF_PHYS,
+ CONFIG_PCI_PREF_SIZE,
+ PCI_REGION_PREFETCH);
+
+ pci_set_region(hose->regions + 3,
+ 0,
+ 0,
+ gd->ram_size,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+ hose->region_count = 4;
+}
+
+int board_pci_post_scan(struct pci_controller *hose)
+{
+ return 0;
+}
+
+int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
+{
+ /*
+ * TODO:
+ *
+ * For some unknown reason, the PCI enumeration process hangs
+ * when it scans to the PCIe root port 0 (D23:F0) & 1 (D23:F1).
+ *
+ * For now we just skip these two devices, and this needs to
+ * be revisited later.
+ */
+ if (dev == QUARK_HOST_BRIDGE ||
+ dev == QUARK_PCIE0 || dev == QUARK_PCIE1) {
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
new file mode 100644
index 0000000..dccf7ac
--- /dev/null
+++ b/arch/x86/cpu/quark/quark.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/post.h>
+#include <asm/processor.h>
+#include <asm/arch/device.h>
+#include <asm/arch/msg_port.h>
+#include <asm/arch/quark.h>
+
+static struct pci_device_id mmc_supported[] = {
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
+};
+
+/*
+ * TODO:
+ *
+ * This whole routine should be removed until we fully convert the ICH SPI
+ * driver to DM and make use of DT to pass the bios control register offset
+ */
+static void unprotect_spi_flash(void)
+{
+ u32 bc;
+
+ bc = pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8);
+ bc |= 0x1; /* unprotect the flash */
+ pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc);
+}
+
+static void quark_setup_bars(void)
+{
+ /* GPIO - D31:F0:R44h */
+ pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
+ CONFIG_GPIO_BASE | IO_BAR_EN);
+
+ /* ACPI PM1 Block - D31:F0:R48h */
+ pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
+ CONFIG_ACPI_PM1_BASE | IO_BAR_EN);
+
+ /* GPE0 - D31:F0:R4Ch */
+ pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
+ CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);
+
+ /* WDT - D31:F0:R84h */
+ pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
+ CONFIG_WDT_BASE | IO_BAR_EN);
+
+ /* RCBA - D31:F0:RF0h */
+ pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
+ CONFIG_RCBA_BASE | MEM_BAR_EN);
+
+ /* ACPI P Block - Msg Port 04:R70h */
+ msg_port_write(MSG_PORT_RMU, PBLK_BA,
+ CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);
+
+ /* SPI DMA - Msg Port 04:R7Ah */
+ msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
+ CONFIG_SPI_DMA_BASE | IO_BAR_EN);
+
+ /* PCIe ECAM */
+ msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
+ CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
+ msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
+ CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
+}
+
+int arch_cpu_init(void)
+{
+ struct pci_controller *hose;
+ int ret;
+
+ post_code(POST_CPU_INIT);
+#ifdef CONFIG_SYS_X86_TSC_TIMER
+ timer_set_base(rdtsc());
+#endif
+
+ ret = x86_cpu_init_f();
+ if (ret)
+ return ret;
+
+ ret = pci_early_init_hose(&hose);
+ if (ret)
+ return ret;
+
+ /*
+ * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
+ * which need be initialized with suggested values
+ */
+ quark_setup_bars();
+
+ unprotect_spi_flash();
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ post_code(POST_CPU_INFO);
+ return default_print_cpuinfo();
+}
+
+void reset_cpu(ulong addr)
+{
+ /* cold reset */
+ outb(0x08, PORT_RESET);
+}
+
+int cpu_mmc_init(bd_t *bis)
+{
+ return pci_mmc_init("Quark SDHCI", mmc_supported,
+ ARRAY_SIZE(mmc_supported));
+}
diff --git a/arch/x86/cpu/quark/smc.c b/arch/x86/cpu/quark/smc.c
new file mode 100644
index 0000000..e34bec4
--- /dev/null
+++ b/arch/x86/cpu/quark/smc.c
@@ -0,0 +1,2764 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Ported from Intel released Quark UEFI BIOS
+ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/arch/device.h>
+#include <asm/arch/mrc.h>
+#include <asm/arch/msg_port.h>
+#include "mrc_util.h"
+#include "hte.h"
+#include "smc.h"
+
+/* t_rfc values (in picoseconds) per density */
+static const uint32_t t_rfc[5] = {
+ 90000, /* 512Mb */
+ 110000, /* 1Gb */
+ 160000, /* 2Gb */
+ 300000, /* 4Gb */
+ 350000, /* 8Gb */
+};
+
+/* t_ck clock period in picoseconds per speed index 800, 1066, 1333 */
+static const uint32_t t_ck[3] = {
+ 2500,
+ 1875,
+ 1500
+};
+
+/* Global variables */
+static const uint16_t ddr_wclk[] = {193, 158};
+static const uint16_t ddr_wctl[] = {1, 217};
+static const uint16_t ddr_wcmd[] = {1, 220};
+
+#ifdef BACKUP_RCVN
+static const uint16_t ddr_rcvn[] = {129, 498};
+#endif
+
+#ifdef BACKUP_WDQS
+static const uint16_t ddr_wdqs[] = {65, 289};
+#endif
+
+#ifdef BACKUP_RDQS
+static const uint8_t ddr_rdqs[] = {32, 24};
+#endif
+
+#ifdef BACKUP_WDQ
+static const uint16_t ddr_wdq[] = {32, 257};
+#endif
+
+/* Stop self refresh driven by MCU */
+void clear_self_refresh(struct mrc_params *mrc_params)
+{
+ ENTERFN();
+
+ /* clear the PMSTS Channel Self Refresh bits */
+ mrc_write_mask(MEM_CTLR, PMSTS, BIT0, BIT0);
+
+ LEAVEFN();
+}
+
+/* It will initialize timing registers in the MCU (DTR0..DTR4) */
+void prog_ddr_timing_control(struct mrc_params *mrc_params)
+{
+ uint8_t tcl, wl;
+ uint8_t trp, trcd, tras, twr, twtr, trrd, trtp, tfaw;
+ uint32_t tck;
+ u32 dtr0, dtr1, dtr2, dtr3, dtr4;
+ u32 tmp1, tmp2;
+
+ ENTERFN();
+
+ /* mcu_init starts */
+ mrc_post_code(0x02, 0x00);
+
+ dtr0 = msg_port_read(MEM_CTLR, DTR0);
+ dtr1 = msg_port_read(MEM_CTLR, DTR1);
+ dtr2 = msg_port_read(MEM_CTLR, DTR2);
+ dtr3 = msg_port_read(MEM_CTLR, DTR3);
+ dtr4 = msg_port_read(MEM_CTLR, DTR4);
+
+ tck = t_ck[mrc_params->ddr_speed]; /* Clock in picoseconds */
+ tcl = mrc_params->params.cl; /* CAS latency in clocks */
+ trp = tcl; /* Per CAT MRC */
+ trcd = tcl; /* Per CAT MRC */
+ tras = MCEIL(mrc_params->params.ras, tck);
+
+ /* Per JEDEC: tWR=15000ps DDR2/3 from 800-1600 */
+ twr = MCEIL(15000, tck);
+
+ twtr = MCEIL(mrc_params->params.wtr, tck);
+ trrd = MCEIL(mrc_params->params.rrd, tck);
+ trtp = 4; /* Valid for 800 and 1066, use 5 for 1333 */
+ tfaw = MCEIL(mrc_params->params.faw, tck);
+
+ wl = 5 + mrc_params->ddr_speed;
+
+ dtr0 &= ~(BIT0 | BIT1);
+ dtr0 |= mrc_params->ddr_speed;
+ dtr0 &= ~(BIT12 | BIT13 | BIT14);
+ tmp1 = tcl - 5;
+ dtr0 |= ((tcl - 5) << 12);
+ dtr0 &= ~(BIT4 | BIT5 | BIT6 | BIT7);
+ dtr0 |= ((trp - 5) << 4); /* 5 bit DRAM Clock */
+ dtr0 &= ~(BIT8 | BIT9 | BIT10 | BIT11);
+ dtr0 |= ((trcd - 5) << 8); /* 5 bit DRAM Clock */
+
+ dtr1 &= ~(BIT0 | BIT1 | BIT2);
+ tmp2 = wl - 3;
+ dtr1 |= (wl - 3);
+ dtr1 &= ~(BIT8 | BIT9 | BIT10 | BIT11);
+ dtr1 |= ((wl + 4 + twr - 14) << 8); /* Change to tWTP */
+ dtr1 &= ~(BIT28 | BIT29 | BIT30);
+ dtr1 |= ((MMAX(trtp, 4) - 3) << 28); /* 4 bit DRAM Clock */
+ dtr1 &= ~(BIT24 | BIT25);
+ dtr1 |= ((trrd - 4) << 24); /* 4 bit DRAM Clock */
+ dtr1 &= ~(BIT4 | BIT5);
+ dtr1 |= (1 << 4);
+ dtr1 &= ~(BIT20 | BIT21 | BIT22 | BIT23);
+ dtr1 |= ((tras - 14) << 20); /* 6 bit DRAM Clock */
+ dtr1 &= ~(BIT16 | BIT17 | BIT18 | BIT19);
+ dtr1 |= ((((tfaw + 1) >> 1) - 5) << 16);/* 4 bit DRAM Clock */
+ /* Set 4 Clock CAS to CAS delay (multi-burst) */
+ dtr1 &= ~(BIT12 | BIT13);
+
+ dtr2 &= ~(BIT0 | BIT1 | BIT2);
+ dtr2 |= 1;
+ dtr2 &= ~(BIT8 | BIT9 | BIT10);
+ dtr2 |= (2 << 8);
+ dtr2 &= ~(BIT16 | BIT17 | BIT18 | BIT19);
+ dtr2 |= (2 << 16);
+
+ dtr3 &= ~(BIT0 | BIT1 | BIT2);
+ dtr3 |= 2;
+ dtr3 &= ~(BIT4 | BIT5 | BIT6);
+ dtr3 |= (2 << 4);
+
+ dtr3 &= ~(BIT8 | BIT9 | BIT10 | BIT11);
+ if (mrc_params->ddr_speed == DDRFREQ_800) {
+ /* Extended RW delay (+1) */
+ dtr3 |= ((tcl - 5 + 1) << 8);
+ } else if (mrc_params->ddr_speed == DDRFREQ_1066) {
+ /* Extended RW delay (+1) */
+ dtr3 |= ((tcl - 5 + 1) << 8);
+ }
+
+ dtr3 &= ~(BIT13 | BIT14 | BIT15 | BIT16);
+ dtr3 |= ((4 + wl + twtr - 11) << 13);
+
+ dtr3 &= ~(BIT22 | BIT23);
+ if (mrc_params->ddr_speed == DDRFREQ_800)
+ dtr3 |= ((MMAX(0, 1 - 1)) << 22);
+ else
+ dtr3 |= ((MMAX(0, 2 - 1)) << 22);
+
+ dtr4 &= ~(BIT0 | BIT1);
+ dtr4 |= 1;
+ dtr4 &= ~(BIT4 | BIT5 | BIT6);
+ dtr4 |= (1 << 4);
+ dtr4 &= ~(BIT8 | BIT9 | BIT10);
+ dtr4 |= ((1 + tmp1 - tmp2 + 2) << 8);
+ dtr4 &= ~(BIT12 | BIT13 | BIT14);
+ dtr4 |= ((1 + tmp1 - tmp2 + 2) << 12);
+ dtr4 &= ~(BIT15 | BIT16);
+
+ msg_port_write(MEM_CTLR, DTR0, dtr0);
+ msg_port_write(MEM_CTLR, DTR1, dtr1);
+ msg_port_write(MEM_CTLR, DTR2, dtr2);
+ msg_port_write(MEM_CTLR, DTR3, dtr3);
+ msg_port_write(MEM_CTLR, DTR4, dtr4);
+
+ LEAVEFN();
+}
+
+/* Configure MCU before jedec init sequence */
+void prog_decode_before_jedec(struct mrc_params *mrc_params)
+{
+ u32 drp;
+ u32 drfc;
+ u32 dcal;
+ u32 dsch;
+ u32 dpmc0;
+
+ ENTERFN();
+
+ /* Disable power saving features */
+ dpmc0 = msg_port_read(MEM_CTLR, DPMC0);
+ dpmc0 |= (BIT24 | BIT25);
+ dpmc0 &= ~(BIT16 | BIT17 | BIT18);
+ dpmc0 &= ~BIT23;
+ msg_port_write(MEM_CTLR, DPMC0, dpmc0);
+
+ /* Disable out of order transactions */
+ dsch = msg_port_read(MEM_CTLR, DSCH);
+ dsch |= (BIT8 | BIT12);
+ msg_port_write(MEM_CTLR, DSCH, dsch);
+
+ /* Disable issuing the REF command */
+ drfc = msg_port_read(MEM_CTLR, DRFC);
+ drfc &= ~(BIT12 | BIT13 | BIT14);
+ msg_port_write(MEM_CTLR, DRFC, drfc);
+
+ /* Disable ZQ calibration short */
+ dcal = msg_port_read(MEM_CTLR, DCAL);
+ dcal &= ~(BIT8 | BIT9 | BIT10);
+ dcal &= ~(BIT12 | BIT13);
+ msg_port_write(MEM_CTLR, DCAL, dcal);
+
+ /*
+ * Training performed in address mode 0, rank population has limited
+ * impact, however simulator complains if enabled non-existing rank.
+ */
+ drp = 0;
+ if (mrc_params->rank_enables & 1)
+ drp |= BIT0;
+ if (mrc_params->rank_enables & 2)
+ drp |= BIT1;
+ msg_port_write(MEM_CTLR, DRP, drp);
+
+ LEAVEFN();
+}
+
+/*
+ * After Cold Reset, BIOS should set COLDWAKE bit to 1 before
+ * sending the WAKE message to the Dunit.
+ *
+ * For Standby Exit, or any other mode in which the DRAM is in
+ * SR, this bit must be set to 0.
+ */
+void perform_ddr_reset(struct mrc_params *mrc_params)
+{
+ ENTERFN();
+
+ /* Set COLDWAKE bit before sending the WAKE message */
+ mrc_write_mask(MEM_CTLR, DRMC, BIT16, BIT16);
+
+ /* Send wake command to DUNIT (MUST be done before JEDEC) */
+ dram_wake_command();
+
+ /* Set default value */
+ msg_port_write(MEM_CTLR, DRMC,
+ (mrc_params->rd_odt_value == 0 ? BIT12 : 0));
+
+ LEAVEFN();
+}
+
+
+/*
+ * This function performs some initialization on the DDRIO unit.
+ * This function is dependent on BOARD_ID, DDR_SPEED, and CHANNEL_ENABLES.
+ */
+void ddrphy_init(struct mrc_params *mrc_params)
+{
+ uint32_t temp;
+ uint8_t ch; /* channel counter */
+ uint8_t rk; /* rank counter */
+ uint8_t bl_grp; /* byte lane group counter (2 BLs per module) */
+ uint8_t bl_divisor = 1; /* byte lane divisor */
+ /* For DDR3 --> 0 == 800, 1 == 1066, 2 == 1333 */
+ uint8_t speed = mrc_params->ddr_speed & (BIT1 | BIT0);
+ uint8_t cas;
+ uint8_t cwl;
+
+ ENTERFN();
+
+ cas = mrc_params->params.cl;
+ cwl = 5 + mrc_params->ddr_speed;
+
+ /* ddrphy_init starts */
+ mrc_post_code(0x03, 0x00);
+
+ /*
+ * HSD#231531
+ * Make sure IOBUFACT is deasserted before initializing the DDR PHY
+ *
+ * HSD#234845
+ * Make sure WRPTRENABLE is deasserted before initializing the DDR PHY
+ */
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ /* Deassert DDRPHY Initialization Complete */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)),
+ ~BIT20, BIT20); /* SPID_INIT_COMPLETE=0 */
+ /* Deassert IOBUFACT */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)),
+ ~BIT2, BIT2); /* IOBUFACTRST_N=0 */
+ /* Disable WRPTR */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDPTRREG + (ch * DDRIOCCC_CH_OFFSET)),
+ ~BIT0, BIT0); /* WRPTRENABLE=0 */
+ }
+ }
+
+ /* Put PHY in reset */
+ mrc_alt_write_mask(DDRPHY, MASTERRSTN, 0, BIT0);
+
+ /* Initialize DQ01, DQ23, CMD, CLK-CTL, COMP modules */
+
+ /* STEP0 */
+ mrc_post_code(0x03, 0x10);
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ /* DQ01-DQ23 */
+ for (bl_grp = 0;
+ bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2);
+ bl_grp++) {
+ /* Analog MUX select - IO2xCLKSEL */
+ mrc_alt_write_mask(DDRPHY,
+ (DQOBSCKEBBCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ ((bl_grp) ? (0x00) : (BIT22)), (BIT22));
+
+ /* ODT Strength */
+ switch (mrc_params->rd_odt_value) {
+ case 1:
+ temp = 0x3;
+ break; /* 60 ohm */
+ case 2:
+ temp = 0x3;
+ break; /* 120 ohm */
+ case 3:
+ temp = 0x3;
+ break; /* 180 ohm */
+ default:
+ temp = 0x3;
+ break; /* 120 ohm */
+ }
+
+ /* ODT strength */
+ mrc_alt_write_mask(DDRPHY,
+ (B0RXIOBUFCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ (temp << 5), (BIT6 | BIT5));
+ /* ODT strength */
+ mrc_alt_write_mask(DDRPHY,
+ (B1RXIOBUFCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ (temp << 5), (BIT6 | BIT5));
+
+ /* Dynamic ODT/DIFFAMP */
+ temp = (((cas) << 24) | ((cas) << 16) |
+ ((cas) << 8) | ((cas) << 0));
+ switch (speed) {
+ case 0:
+ temp -= 0x01010101;
+ break; /* 800 */
+ case 1:
+ temp -= 0x02020202;
+ break; /* 1066 */
+ case 2:
+ temp -= 0x03030303;
+ break; /* 1333 */
+ case 3:
+ temp -= 0x04040404;
+ break; /* 1600 */
+ }
+
+ /* Launch Time: ODT, DIFFAMP, ODT, DIFFAMP */
+ mrc_alt_write_mask(DDRPHY,
+ (B01LATCTL1 +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ temp,
+ (BIT28 | BIT27 | BIT26 | BIT25 | BIT24 |
+ BIT20 | BIT19 | BIT18 | BIT17 | BIT16 |
+ BIT12 | BIT11 | BIT10 | BIT9 | BIT8 |
+ BIT4 | BIT3 | BIT2 | BIT1 | BIT0));
+ switch (speed) {
+ /* HSD#234715 */
+ case 0:
+ temp = ((0x06 << 16) | (0x07 << 8));
+ break; /* 800 */
+ case 1:
+ temp = ((0x07 << 16) | (0x08 << 8));
+ break; /* 1066 */
+ case 2:
+ temp = ((0x09 << 16) | (0x0A << 8));
+ break; /* 1333 */
+ case 3:
+ temp = ((0x0A << 16) | (0x0B << 8));
+ break; /* 1600 */
+ }
+
+ /* On Duration: ODT, DIFFAMP */
+ mrc_alt_write_mask(DDRPHY,
+ (B0ONDURCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ temp,
+ (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 |
+ BIT16 | BIT13 | BIT12 | BIT11 | BIT10 |
+ BIT9 | BIT8));
+ /* On Duration: ODT, DIFFAMP */
+ mrc_alt_write_mask(DDRPHY,
+ (B1ONDURCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ temp,
+ (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 |
+ BIT16 | BIT13 | BIT12 | BIT11 | BIT10 |
+ BIT9 | BIT8));
+
+ switch (mrc_params->rd_odt_value) {
+ case 0:
+ /* override DIFFAMP=on, ODT=off */
+ temp = ((0x3F << 16) | (0x3f << 10));
+ break;
+ default:
+ /* override DIFFAMP=on, ODT=on */
+ temp = ((0x3F << 16) | (0x2A << 10));
+ break;
+ }
+
+ /* Override: DIFFAMP, ODT */
+ mrc_alt_write_mask(DDRPHY,
+ (B0OVRCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ temp,
+ (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 |
+ BIT16 | BIT15 | BIT14 | BIT13 | BIT12 |
+ BIT11 | BIT10));
+ /* Override: DIFFAMP, ODT */
+ mrc_alt_write_mask(DDRPHY,
+ (B1OVRCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ temp,
+ (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 |
+ BIT16 | BIT15 | BIT14 | BIT13 | BIT12 |
+ BIT11 | BIT10));
+
+ /* DLL Setup */
+
+ /* 1xCLK Domain Timings: tEDP,RCVEN,WDQS (PO) */
+ mrc_alt_write_mask(DDRPHY,
+ (B0LATCTL0 +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ (((cas + 7) << 16) | ((cas - 4) << 8) |
+ ((cwl - 2) << 0)),
+ (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 |
+ BIT16 | BIT12 | BIT11 | BIT10 | BIT9 |
+ BIT8 | BIT4 | BIT3 | BIT2 | BIT1 |
+ BIT0));
+ mrc_alt_write_mask(DDRPHY,
+ (B1LATCTL0 +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ (((cas + 7) << 16) | ((cas - 4) << 8) |
+ ((cwl - 2) << 0)),
+ (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 |
+ BIT16 | BIT12 | BIT11 | BIT10 | BIT9 |
+ BIT8 | BIT4 | BIT3 | BIT2 | BIT1 |
+ BIT0));
+
+ /* RCVEN Bypass (PO) */
+ mrc_alt_write_mask(DDRPHY,
+ (B0RXIOBUFCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ ((0x0 << 7) | (0x0 << 0)),
+ (BIT7 | BIT0));
+ mrc_alt_write_mask(DDRPHY,
+ (B1RXIOBUFCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ ((0x0 << 7) | (0x0 << 0)),
+ (BIT7 | BIT0));
+
+ /* TX */
+ mrc_alt_write_mask(DDRPHY,
+ (DQCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ (BIT16), (BIT16));
+ mrc_alt_write_mask(DDRPHY,
+ (B01PTRCTL1 +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ (BIT8), (BIT8));
+
+ /* RX (PO) */
+ /* Internal Vref Code, Enable#, Ext_or_Int (1=Ext) */
+ mrc_alt_write_mask(DDRPHY,
+ (B0VREFCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ ((0x03 << 2) | (0x0 << 1) | (0x0 << 0)),
+ (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 |
+ BIT2 | BIT1 | BIT0));
+ /* Internal Vref Code, Enable#, Ext_or_Int (1=Ext) */
+ mrc_alt_write_mask(DDRPHY,
+ (B1VREFCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ ((0x03 << 2) | (0x0 << 1) | (0x0 << 0)),
+ (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 |
+ BIT2 | BIT1 | BIT0));
+ /* Per-Bit De-Skew Enable */
+ mrc_alt_write_mask(DDRPHY,
+ (B0RXIOBUFCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ (0), (BIT4));
+ /* Per-Bit De-Skew Enable */
+ mrc_alt_write_mask(DDRPHY,
+ (B1RXIOBUFCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ (0), (BIT4));
+ }
+
+ /* CLKEBB */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDOBSCKEBBCTL + (ch * DDRIOCCC_CH_OFFSET)),
+ 0, (BIT23));
+
+ /* Enable tristate control of cmd/address bus */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)),
+ 0, (BIT1 | BIT0));
+
+ /* ODT RCOMP */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDRCOMPODT + (ch * DDRIOCCC_CH_OFFSET)),
+ ((0x03 << 5) | (0x03 << 0)),
+ (BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 |
+ BIT3 | BIT2 | BIT1 | BIT0));
+
+ /* CMDPM* registers must be programmed in this order */
+
+ /* Turn On Delays: SFR (regulator), MPLL */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDPMDLYREG4 + (ch * DDRIOCCC_CH_OFFSET)),
+ ((0xFFFFU << 16) | (0xFFFF << 0)),
+ 0xFFFFFFFF);
+ /*
+ * Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3,
+ * VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT
+ * for_PM_MSG_gt0, MDLL Turn On
+ */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDPMDLYREG3 + (ch * DDRIOCCC_CH_OFFSET)),
+ ((0xFU << 28) | (0xFFF << 16) | (0xF << 12) |
+ (0x616 << 0)), 0xFFFFFFFF);
+ /* MPLL Divider Reset Delays */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDPMDLYREG2 + (ch * DDRIOCCC_CH_OFFSET)),
+ ((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) |
+ (0xFF << 0)), 0xFFFFFFFF);
+ /* Turn Off Delays: VREG, Staggered MDLL, MDLL, PI */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDPMDLYREG1 + (ch * DDRIOCCC_CH_OFFSET)),
+ ((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) |
+ (0xFF << 0)), 0xFFFFFFFF);
+ /* Turn On Delays: MPLL, Staggered MDLL, PI, IOBUFACT */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDPMDLYREG0 + (ch * DDRIOCCC_CH_OFFSET)),
+ ((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) |
+ (0xFF << 0)), 0xFFFFFFFF);
+ /* Allow PUnit signals */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)),
+ ((0x6 << 8) | BIT6 | (0x4 << 0)),
+ (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 |
+ BIT25 | BIT24 | BIT23 | BIT22 | BIT21 | BIT11 |
+ BIT10 | BIT9 | BIT8 | BIT6 | BIT3 | BIT2 |
+ BIT1 | BIT0));
+ /* DLL_VREG Bias Trim, VREF Tuning for DLL_VREG */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)),
+ ((0x3 << 4) | (0x7 << 0)),
+ (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 |
+ BIT0));
+
+ /* CLK-CTL */
+ mrc_alt_write_mask(DDRPHY,
+ (CCOBSCKEBBCTL + (ch * DDRIOCCC_CH_OFFSET)),
+ 0, BIT24); /* CLKEBB */
+ /* Buffer Enable: CS,CKE,ODT,CLK */
+ mrc_alt_write_mask(DDRPHY,
+ (CCCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)),
+ ((0x0 << 16) | (0x0 << 12) | (0x0 << 8) |
+ (0xF << 4) | BIT0),
+ (BIT19 | BIT18 | BIT17 | BIT16 | BIT15 | BIT14 |
+ BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 |
+ BIT7 | BIT6 | BIT5 | BIT4 | BIT0));
+ /* ODT RCOMP */
+ mrc_alt_write_mask(DDRPHY,
+ (CCRCOMPODT + (ch * DDRIOCCC_CH_OFFSET)),
+ ((0x03 << 8) | (0x03 << 0)),
+ (BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | BIT4 |
+ BIT3 | BIT2 | BIT1 | BIT0));
+ /* DLL_VREG Bias Trim, VREF Tuning for DLL_VREG */
+ mrc_alt_write_mask(DDRPHY,
+ (CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)),
+ ((0x3 << 4) | (0x7 << 0)),
+ (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 |
+ BIT0));
+
+ /*
+ * COMP (RON channel specific)
+ * - DQ/DQS/DM RON: 32 Ohm
+ * - CTRL/CMD RON: 27 Ohm
+ * - CLK RON: 26 Ohm
+ */
+ /* RCOMP Vref PU/PD */
+ mrc_alt_write_mask(DDRPHY,
+ (DQVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ ((0x08 << 24) | (0x03 << 16)),
+ (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 |
+ BIT24 | BIT21 | BIT20 | BIT19 | BIT18 |
+ BIT17 | BIT16));
+ /* RCOMP Vref PU/PD */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ ((0x0C << 24) | (0x03 << 16)),
+ (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 |
+ BIT24 | BIT21 | BIT20 | BIT19 | BIT18 |
+ BIT17 | BIT16));
+ /* RCOMP Vref PU/PD */
+ mrc_alt_write_mask(DDRPHY,
+ (CLKVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ ((0x0F << 24) | (0x03 << 16)),
+ (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 |
+ BIT24 | BIT21 | BIT20 | BIT19 | BIT18 |
+ BIT17 | BIT16));
+ /* RCOMP Vref PU/PD */
+ mrc_alt_write_mask(DDRPHY,
+ (DQSVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ ((0x08 << 24) | (0x03 << 16)),
+ (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 |
+ BIT24 | BIT21 | BIT20 | BIT19 | BIT18 |
+ BIT17 | BIT16));
+ /* RCOMP Vref PU/PD */
+ mrc_alt_write_mask(DDRPHY,
+ (CTLVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ ((0x0C << 24) | (0x03 << 16)),
+ (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 |
+ BIT24 | BIT21 | BIT20 | BIT19 | BIT18 |
+ BIT17 | BIT16));
+
+ /* DQS Swapped Input Enable */
+ mrc_alt_write_mask(DDRPHY,
+ (COMPEN1CH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT19 | BIT17),
+ (BIT31 | BIT30 | BIT19 | BIT17 |
+ BIT15 | BIT14));
+
+ /* ODT VREF = 1.5 x 274/360+274 = 0.65V (code of ~50) */
+ /* ODT Vref PU/PD */
+ mrc_alt_write_mask(DDRPHY,
+ (DQVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ ((0x32 << 8) | (0x03 << 0)),
+ (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 |
+ BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0));
+ /* ODT Vref PU/PD */
+ mrc_alt_write_mask(DDRPHY,
+ (DQSVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ ((0x32 << 8) | (0x03 << 0)),
+ (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 |
+ BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0));
+ /* ODT Vref PU/PD */
+ mrc_alt_write_mask(DDRPHY,
+ (CLKVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ ((0x0E << 8) | (0x05 << 0)),
+ (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 |
+ BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0));
+
+ /*
+ * Slew rate settings are frequency specific,
+ * numbers below are for 800Mhz (speed == 0)
+ * - DQ/DQS/DM/CLK SR: 4V/ns,
+ * - CTRL/CMD SR: 1.5V/ns
+ */
+ temp = (0x0E << 16) | (0x0E << 12) | (0x08 << 8) |
+ (0x0B << 4) | (0x0B << 0);
+ /* DCOMP Delay Select: CTL,CMD,CLK,DQS,DQ */
+ mrc_alt_write_mask(DDRPHY,
+ (DLYSELCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ temp,
+ (BIT19 | BIT18 | BIT17 | BIT16 | BIT15 |
+ BIT14 | BIT13 | BIT12 | BIT11 | BIT10 |
+ BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 |
+ BIT3 | BIT2 | BIT1 | BIT0));
+ /* TCO Vref CLK,DQS,DQ */
+ mrc_alt_write_mask(DDRPHY,
+ (TCOVREFCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ ((0x05 << 16) | (0x05 << 8) | (0x05 << 0)),
+ (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 |
+ BIT16 | BIT13 | BIT12 | BIT11 | BIT10 |
+ BIT9 | BIT8 | BIT5 | BIT4 | BIT3 | BIT2 |
+ BIT1 | BIT0));
+ /* ODTCOMP CMD/CTL PU/PD */
+ mrc_alt_write_mask(DDRPHY,
+ (CCBUFODTCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ ((0x03 << 8) | (0x03 << 0)),
+ (BIT12 | BIT11 | BIT10 | BIT9 | BIT8 |
+ BIT4 | BIT3 | BIT2 | BIT1 | BIT0));
+ /* COMP */
+ mrc_alt_write_mask(DDRPHY,
+ (COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)),
+ 0, (BIT31 | BIT30 | BIT8));
+
+#ifdef BACKUP_COMPS
+ /* DQ COMP Overrides */
+ /* RCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (DQDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0A << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* RCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (DQDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0A << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* DCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (DQDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x10 << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* DCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (DQDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x10 << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* ODTCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (DQODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0B << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* ODTCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (DQODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0B << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* TCOCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (DQTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31), (BIT31));
+ /* TCOCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (DQTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31), (BIT31));
+
+ /* DQS COMP Overrides */
+ /* RCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (DQSDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0A << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* RCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (DQSDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0A << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* DCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (DQSDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x10 << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* DCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (DQSDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x10 << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* ODTCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (DQSODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0B << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* ODTCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (DQSODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0B << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* TCOCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (DQSTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31), (BIT31));
+ /* TCOCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (DQSTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31), (BIT31));
+
+ /* CLK COMP Overrides */
+ /* RCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (CLKDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0C << 16)),
+ (BIT31 | (0x0B << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* RCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (CLKDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0C << 16)),
+ (BIT31 | (0x0B << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* DCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (CLKDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x07 << 16)),
+ (BIT31 | (0x0B << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* DCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (CLKDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x07 << 16)),
+ (BIT31 | (0x0B << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* ODTCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (CLKODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0B << 16)),
+ (BIT31 | (0x0B << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* ODTCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (CLKODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0B << 16)),
+ (BIT31 | (0x0B << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* TCOCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (CLKTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31), (BIT31));
+ /* TCOCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (CLKTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31), (BIT31));
+
+ /* CMD COMP Overrides */
+ /* RCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0D << 16)),
+ (BIT31 | BIT21 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* RCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0D << 16)),
+ (BIT31 | BIT21 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* DCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0A << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* DCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0A << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+
+ /* CTL COMP Overrides */
+ /* RCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (CTLDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0D << 16)),
+ (BIT31 | BIT21 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* RCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (CTLDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0D << 16)),
+ (BIT31 | BIT21 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* DCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (CTLDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0A << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* DCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (CTLDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x0A << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+#else
+ /* DQ TCOCOMP Overrides */
+ /* TCOCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (DQTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x1F << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* TCOCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (DQTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x1F << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+
+ /* DQS TCOCOMP Overrides */
+ /* TCOCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (DQSTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x1F << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* TCOCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (DQSTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x1F << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+
+ /* CLK TCOCOMP Overrides */
+ /* TCOCOMP PU */
+ mrc_alt_write_mask(DDRPHY,
+ (CLKTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x1F << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+ /* TCOCOMP PD */
+ mrc_alt_write_mask(DDRPHY,
+ (CLKTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)),
+ (BIT31 | (0x1F << 16)),
+ (BIT31 | BIT20 | BIT19 |
+ BIT18 | BIT17 | BIT16));
+#endif
+
+ /* program STATIC delays */
+#ifdef BACKUP_WCMD
+ set_wcmd(ch, ddr_wcmd[PLATFORM_ID]);
+#else
+ set_wcmd(ch, ddr_wclk[PLATFORM_ID] + HALF_CLK);
+#endif
+
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ if (mrc_params->rank_enables & (1<<rk)) {
+ set_wclk(ch, rk, ddr_wclk[PLATFORM_ID]);
+#ifdef BACKUP_WCTL
+ set_wctl(ch, rk, ddr_wctl[PLATFORM_ID]);
+#else
+ set_wctl(ch, rk, ddr_wclk[PLATFORM_ID] + HALF_CLK);
+#endif
+ }
+ }
+ }
+ }
+
+ /* COMP (non channel specific) */
+ /* RCOMP: Dither PU Enable */
+ mrc_alt_write_mask(DDRPHY, (DQANADRVPUCTL), (BIT30), (BIT30));
+ /* RCOMP: Dither PD Enable */
+ mrc_alt_write_mask(DDRPHY, (DQANADRVPDCTL), (BIT30), (BIT30));
+ /* RCOMP: Dither PU Enable */
+ mrc_alt_write_mask(DDRPHY, (CMDANADRVPUCTL), (BIT30), (BIT30));
+ /* RCOMP: Dither PD Enable */
+ mrc_alt_write_mask(DDRPHY, (CMDANADRVPDCTL), (BIT30), (BIT30));
+ /* RCOMP: Dither PU Enable */
+ mrc_alt_write_mask(DDRPHY, (CLKANADRVPUCTL), (BIT30), (BIT30));
+ /* RCOMP: Dither PD Enable */
+ mrc_alt_write_mask(DDRPHY, (CLKANADRVPDCTL), (BIT30), (BIT30));
+ /* RCOMP: Dither PU Enable */
+ mrc_alt_write_mask(DDRPHY, (DQSANADRVPUCTL), (BIT30), (BIT30));
+ /* RCOMP: Dither PD Enable */
+ mrc_alt_write_mask(DDRPHY, (DQSANADRVPDCTL), (BIT30), (BIT30));
+ /* RCOMP: Dither PU Enable */
+ mrc_alt_write_mask(DDRPHY, (CTLANADRVPUCTL), (BIT30), (BIT30));
+ /* RCOMP: Dither PD Enable */
+ mrc_alt_write_mask(DDRPHY, (CTLANADRVPDCTL), (BIT30), (BIT30));
+ /* ODT: Dither PU Enable */
+ mrc_alt_write_mask(DDRPHY, (DQANAODTPUCTL), (BIT30), (BIT30));
+ /* ODT: Dither PD Enable */
+ mrc_alt_write_mask(DDRPHY, (DQANAODTPDCTL), (BIT30), (BIT30));
+ /* ODT: Dither PU Enable */
+ mrc_alt_write_mask(DDRPHY, (CLKANAODTPUCTL), (BIT30), (BIT30));
+ /* ODT: Dither PD Enable */
+ mrc_alt_write_mask(DDRPHY, (CLKANAODTPDCTL), (BIT30), (BIT30));
+ /* ODT: Dither PU Enable */
+ mrc_alt_write_mask(DDRPHY, (DQSANAODTPUCTL), (BIT30), (BIT30));
+ /* ODT: Dither PD Enable */
+ mrc_alt_write_mask(DDRPHY, (DQSANAODTPDCTL), (BIT30), (BIT30));
+ /* DCOMP: Dither PU Enable */
+ mrc_alt_write_mask(DDRPHY, (DQANADLYPUCTL), (BIT30), (BIT30));
+ /* DCOMP: Dither PD Enable */
+ mrc_alt_write_mask(DDRPHY, (DQANADLYPDCTL), (BIT30), (BIT30));
+ /* DCOMP: Dither PU Enable */
+ mrc_alt_write_mask(DDRPHY, (CMDANADLYPUCTL), (BIT30), (BIT30));
+ /* DCOMP: Dither PD Enable */
+ mrc_alt_write_mask(DDRPHY, (CMDANADLYPDCTL), (BIT30), (BIT30));
+ /* DCOMP: Dither PU Enable */
+ mrc_alt_write_mask(DDRPHY, (CLKANADLYPUCTL), (BIT30), (BIT30));
+ /* DCOMP: Dither PD Enable */
+ mrc_alt_write_mask(DDRPHY, (CLKANADLYPDCTL), (BIT30), (BIT30));
+ /* DCOMP: Dither PU Enable */
+ mrc_alt_write_mask(DDRPHY, (DQSANADLYPUCTL), (BIT30), (BIT30));
+ /* DCOMP: Dither PD Enable */
+ mrc_alt_write_mask(DDRPHY, (DQSANADLYPDCTL), (BIT30), (BIT30));
+ /* DCOMP: Dither PU Enable */
+ mrc_alt_write_mask(DDRPHY, (CTLANADLYPUCTL), (BIT30), (BIT30));
+ /* DCOMP: Dither PD Enable */
+ mrc_alt_write_mask(DDRPHY, (CTLANADLYPDCTL), (BIT30), (BIT30));
+ /* TCO: Dither PU Enable */
+ mrc_alt_write_mask(DDRPHY, (DQANATCOPUCTL), (BIT30), (BIT30));
+ /* TCO: Dither PD Enable */
+ mrc_alt_write_mask(DDRPHY, (DQANATCOPDCTL), (BIT30), (BIT30));
+ /* TCO: Dither PU Enable */
+ mrc_alt_write_mask(DDRPHY, (CLKANATCOPUCTL), (BIT30), (BIT30));
+ /* TCO: Dither PD Enable */
+ mrc_alt_write_mask(DDRPHY, (CLKANATCOPDCTL), (BIT30), (BIT30));
+ /* TCO: Dither PU Enable */
+ mrc_alt_write_mask(DDRPHY, (DQSANATCOPUCTL), (BIT30), (BIT30));
+ /* TCO: Dither PD Enable */
+ mrc_alt_write_mask(DDRPHY, (DQSANATCOPDCTL), (BIT30), (BIT30));
+ /* TCOCOMP: Pulse Count */
+ mrc_alt_write_mask(DDRPHY, (TCOCNTCTRL), (0x1 << 0), (BIT1 | BIT0));
+ /* ODT: CMD/CTL PD/PU */
+ mrc_alt_write_mask(DDRPHY,
+ (CHNLBUFSTATIC), ((0x03 << 24) | (0x03 << 16)),
+ (BIT28 | BIT27 | BIT26 | BIT25 | BIT24 |
+ BIT20 | BIT19 | BIT18 | BIT17 | BIT16));
+ /* Set 1us counter */
+ mrc_alt_write_mask(DDRPHY,
+ (MSCNTR), (0x64 << 0),
+ (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0));
+ mrc_alt_write_mask(DDRPHY,
+ (LATCH1CTL), (0x1 << 28),
+ (BIT30 | BIT29 | BIT28));
+
+ /* Release PHY from reset */
+ mrc_alt_write_mask(DDRPHY, MASTERRSTN, BIT0, BIT0);
+
+ /* STEP1 */
+ mrc_post_code(0x03, 0x11);
+
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ /* DQ01-DQ23 */
+ for (bl_grp = 0;
+ bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2);
+ bl_grp++) {
+ mrc_alt_write_mask(DDRPHY,
+ (DQMDLLCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ (BIT13),
+ (BIT13)); /* Enable VREG */
+ delay_n(3);
+ }
+
+ /* ECC */
+ mrc_alt_write_mask(DDRPHY, (ECCMDLLCTL),
+ (BIT13), (BIT13)); /* Enable VREG */
+ delay_n(3);
+ /* CMD */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)),
+ (BIT13), (BIT13)); /* Enable VREG */
+ delay_n(3);
+ /* CLK-CTL */
+ mrc_alt_write_mask(DDRPHY,
+ (CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)),
+ (BIT13), (BIT13)); /* Enable VREG */
+ delay_n(3);
+ }
+ }
+
+ /* STEP2 */
+ mrc_post_code(0x03, 0x12);
+ delay_n(200);
+
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ /* DQ01-DQ23 */
+ for (bl_grp = 0;
+ bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2);
+ bl_grp++) {
+ mrc_alt_write_mask(DDRPHY,
+ (DQMDLLCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ (BIT17),
+ (BIT17)); /* Enable MCDLL */
+ delay_n(50);
+ }
+
+ /* ECC */
+ mrc_alt_write_mask(DDRPHY, (ECCMDLLCTL),
+ (BIT17), (BIT17)); /* Enable MCDLL */
+ delay_n(50);
+ /* CMD */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)),
+ (BIT18), (BIT18)); /* Enable MCDLL */
+ delay_n(50);
+ /* CLK-CTL */
+ mrc_alt_write_mask(DDRPHY,
+ (CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)),
+ (BIT18), (BIT18)); /* Enable MCDLL */
+ delay_n(50);
+ }
+ }
+
+ /* STEP3: */
+ mrc_post_code(0x03, 0x13);
+ delay_n(100);
+
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ /* DQ01-DQ23 */
+ for (bl_grp = 0;
+ bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2);
+ bl_grp++) {
+#ifdef FORCE_16BIT_DDRIO
+ temp = ((bl_grp) &&
+ (mrc_params->channel_width == X16)) ?
+ ((0x1 << 12) | (0x1 << 8) |
+ (0xF << 4) | (0xF << 0)) :
+ ((0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0));
+#else
+ temp = ((0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0));
+#endif
+ /* Enable TXDLL */
+ mrc_alt_write_mask(DDRPHY,
+ (DQDLLTXCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ temp, 0xFFFF);
+ delay_n(3);
+ /* Enable RXDLL */
+ mrc_alt_write_mask(DDRPHY,
+ (DQDLLRXCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ (BIT3 | BIT2 | BIT1 | BIT0),
+ (BIT3 | BIT2 | BIT1 | BIT0));
+ delay_n(3);
+ /* Enable RXDLL Overrides BL0 */
+ mrc_alt_write_mask(DDRPHY,
+ (B0OVRCTL +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ (BIT3 | BIT2 | BIT1 | BIT0),
+ (BIT3 | BIT2 | BIT1 | BIT0));
+ }
+
+ /* ECC */
+ temp = ((0xF << 12) | (0xF << 8) |
+ (0xF << 4) | (0xF << 0));
+ mrc_alt_write_mask(DDRPHY, (ECCDLLTXCTL),
+ temp, 0xFFFF);
+ delay_n(3);
+
+ /* CMD (PO) */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDDLLTXCTL + (ch * DDRIOCCC_CH_OFFSET)),
+ temp, 0xFFFF);
+ delay_n(3);
+ }
+ }
+
+ /* STEP4 */
+ mrc_post_code(0x03, 0x14);
+
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ /* Host To Memory Clock Alignment (HMC) for 800/1066 */
+ for (bl_grp = 0;
+ bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2);
+ bl_grp++) {
+ /* CLK_ALIGN_MOD_ID */
+ mrc_alt_write_mask(DDRPHY,
+ (DQCLKALIGNREG2 +
+ (bl_grp * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ (bl_grp) ? (0x3) : (0x1),
+ (BIT3 | BIT2 | BIT1 | BIT0));
+ }
+
+ mrc_alt_write_mask(DDRPHY,
+ (ECCCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)),
+ 0x2,
+ (BIT3 | BIT2 | BIT1 | BIT0));
+ mrc_alt_write_mask(DDRPHY,
+ (CMDCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)),
+ 0x0,
+ (BIT3 | BIT2 | BIT1 | BIT0));
+ mrc_alt_write_mask(DDRPHY,
+ (CCCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)),
+ 0x2,
+ (BIT3 | BIT2 | BIT1 | BIT0));
+ mrc_alt_write_mask(DDRPHY,
+ (CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET)),
+ (0x2 << 4), (BIT5 | BIT4));
+ /*
+ * NUM_SAMPLES, MAX_SAMPLES,
+ * MACRO_PI_STEP, MICRO_PI_STEP
+ */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDCLKALIGNREG1 + (ch * DDRIOCCC_CH_OFFSET)),
+ ((0x18 << 16) | (0x10 << 8) |
+ (0x8 << 2) | (0x1 << 0)),
+ (BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 |
+ BIT16 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 |
+ BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 |
+ BIT2 | BIT1 | BIT0));
+ /* TOTAL_NUM_MODULES, FIRST_U_PARTITION */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDCLKALIGNREG2 + (ch * DDRIOCCC_CH_OFFSET)),
+ ((0x10 << 16) | (0x4 << 8) | (0x2 << 4)),
+ (BIT20 | BIT19 | BIT18 | BIT17 | BIT16 |
+ BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 |
+ BIT5 | BIT4));
+#ifdef HMC_TEST
+ /* START_CLK_ALIGN=1 */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET)),
+ BIT24, BIT24);
+ while (msg_port_alt_read(DDRPHY,
+ (CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET))) &
+ BIT24)
+ ; /* wait for START_CLK_ALIGN=0 */
+#endif
+
+ /* Set RD/WR Pointer Seperation & COUNTEN & FIFOPTREN */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDPTRREG + (ch * DDRIOCCC_CH_OFFSET)),
+ BIT0, BIT0); /* WRPTRENABLE=1 */
+
+ /* COMP initial */
+ /* enable bypass for CLK buffer (PO) */
+ mrc_alt_write_mask(DDRPHY,
+ (COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)),
+ BIT5, BIT5);
+ /* Initial COMP Enable */
+ mrc_alt_write_mask(DDRPHY, (CMPCTRL),
+ (BIT0), (BIT0));
+ /* wait for Initial COMP Enable = 0 */
+ while (msg_port_alt_read(DDRPHY, (CMPCTRL)) & BIT0)
+ ;
+ /* disable bypass for CLK buffer (PO) */
+ mrc_alt_write_mask(DDRPHY,
+ (COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)),
+ ~BIT5, BIT5);
+
+ /* IOBUFACT */
+
+ /* STEP4a */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)),
+ BIT2, BIT2); /* IOBUFACTRST_N=1 */
+
+ /* DDRPHY initialization complete */
+ mrc_alt_write_mask(DDRPHY,
+ (CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)),
+ BIT20, BIT20); /* SPID_INIT_COMPLETE=1 */
+ }
+ }
+
+ LEAVEFN();
+}
+
+/* This function performs JEDEC initialization on all enabled channels */
+void perform_jedec_init(struct mrc_params *mrc_params)
+{
+ uint8_t twr, wl, rank;
+ uint32_t tck;
+ u32 dtr0;
+ u32 drp;
+ u32 drmc;
+ u32 mrs0_cmd = 0;
+ u32 emrs1_cmd = 0;
+ u32 emrs2_cmd = 0;
+ u32 emrs3_cmd = 0;
+
+ ENTERFN();
+
+ /* jedec_init starts */
+ mrc_post_code(0x04, 0x00);
+
+ /* DDR3_RESET_SET=0, DDR3_RESET_RESET=1 */
+ mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, BIT1, (BIT8 | BIT1));
+
+ /* Assert RESET# for 200us */
+ delay_u(200);
+
+ /* DDR3_RESET_SET=1, DDR3_RESET_RESET=0 */
+ mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, BIT8, (BIT8 | BIT1));
+
+ dtr0 = msg_port_read(MEM_CTLR, DTR0);
+
+ /*
+ * Set CKEVAL for populated ranks
+ * then send NOP to each rank (#4550197)
+ */
+
+ drp = msg_port_read(MEM_CTLR, DRP);
+ drp &= 0x3;
+
+ drmc = msg_port_read(MEM_CTLR, DRMC);
+ drmc &= 0xFFFFFFFC;
+ drmc |= (BIT4 | drp);
+
+ msg_port_write(MEM_CTLR, DRMC, drmc);
+
+ for (rank = 0; rank < NUM_RANKS; rank++) {
+ /* Skip to next populated rank */
+ if ((mrc_params->rank_enables & (1 << rank)) == 0)
+ continue;
+
+ dram_init_command(DCMD_NOP(rank));
+ }
+
+ msg_port_write(MEM_CTLR, DRMC,
+ (mrc_params->rd_odt_value == 0 ? BIT12 : 0));
+
+ /*
+ * setup for emrs 2
+ * BIT[15:11] --> Always "0"
+ * BIT[10:09] --> Rtt_WR: want "Dynamic ODT Off" (0)
+ * BIT[08] --> Always "0"
+ * BIT[07] --> SRT: use sr_temp_range
+ * BIT[06] --> ASR: want "Manual SR Reference" (0)
+ * BIT[05:03] --> CWL: use oem_tCWL
+ * BIT[02:00] --> PASR: want "Full Array" (0)
+ */
+ emrs2_cmd |= (2 << 3);
+ wl = 5 + mrc_params->ddr_speed;
+ emrs2_cmd |= ((wl - 5) << 9);
+ emrs2_cmd |= (mrc_params->sr_temp_range << 13);
+
+ /*
+ * setup for emrs 3
+ * BIT[15:03] --> Always "0"
+ * BIT[02] --> MPR: want "Normal Operation" (0)
+ * BIT[01:00] --> MPR_Loc: want "Predefined Pattern" (0)
+ */
+ emrs3_cmd |= (3 << 3);
+
+ /*
+ * setup for emrs 1
+ * BIT[15:13] --> Always "0"
+ * BIT[12:12] --> Qoff: want "Output Buffer Enabled" (0)
+ * BIT[11:11] --> TDQS: want "Disabled" (0)
+ * BIT[10:10] --> Always "0"
+ * BIT[09,06,02] --> Rtt_nom: use rtt_nom_value
+ * BIT[08] --> Always "0"
+ * BIT[07] --> WR_LVL: want "Disabled" (0)
+ * BIT[05,01] --> DIC: use ron_value
+ * BIT[04:03] --> AL: additive latency want "0" (0)
+ * BIT[00] --> DLL: want "Enable" (0)
+ *
+ * (BIT5|BIT1) set Ron value
+ * 00 --> RZQ/6 (40ohm)
+ * 01 --> RZQ/7 (34ohm)
+ * 1* --> RESERVED
+ *
+ * (BIT9|BIT6|BIT2) set Rtt_nom value
+ * 000 --> Disabled
+ * 001 --> RZQ/4 ( 60ohm)
+ * 010 --> RZQ/2 (120ohm)
+ * 011 --> RZQ/6 ( 40ohm)
+ * 1** --> RESERVED
+ */
+ emrs1_cmd |= (1 << 3);
+ emrs1_cmd &= ~BIT6;
+
+ if (mrc_params->ron_value == 0)
+ emrs1_cmd |= BIT7;
+ else
+ emrs1_cmd &= ~BIT7;
+
+ if (mrc_params->rtt_nom_value == 0)
+ emrs1_cmd |= (DDR3_EMRS1_RTTNOM_40 << 6);
+ else if (mrc_params->rtt_nom_value == 1)
+ emrs1_cmd |= (DDR3_EMRS1_RTTNOM_60 << 6);
+ else if (mrc_params->rtt_nom_value == 2)
+ emrs1_cmd |= (DDR3_EMRS1_RTTNOM_120 << 6);
+
+ /* save MRS1 value (excluding control fields) */
+ mrc_params->mrs1 = emrs1_cmd >> 6;
+
+ /*
+ * setup for mrs 0
+ * BIT[15:13] --> Always "0"
+ * BIT[12] --> PPD: for Quark (1)
+ * BIT[11:09] --> WR: use oem_tWR
+ * BIT[08] --> DLL: want "Reset" (1, self clearing)
+ * BIT[07] --> MODE: want "Normal" (0)
+ * BIT[06:04,02] --> CL: use oem_tCAS
+ * BIT[03] --> RD_BURST_TYPE: want "Interleave" (1)
+ * BIT[01:00] --> BL: want "8 Fixed" (0)
+ * WR:
+ * 0 --> 16
+ * 1 --> 5
+ * 2 --> 6
+ * 3 --> 7
+ * 4 --> 8
+ * 5 --> 10
+ * 6 --> 12
+ * 7 --> 14
+ * CL:
+ * BIT[02:02] "0" if oem_tCAS <= 11 (1866?)
+ * BIT[06:04] use oem_tCAS-4
+ */
+ mrs0_cmd |= BIT14;
+ mrs0_cmd |= BIT18;
+ mrs0_cmd |= ((((dtr0 >> 12) & 7) + 1) << 10);
+
+ tck = t_ck[mrc_params->ddr_speed];
+ /* Per JEDEC: tWR=15000ps DDR2/3 from 800-1600 */
+ twr = MCEIL(15000, tck);
+ mrs0_cmd |= ((twr - 4) << 15);
+
+ for (rank = 0; rank < NUM_RANKS; rank++) {
+ /* Skip to next populated rank */
+ if ((mrc_params->rank_enables & (1 << rank)) == 0)
+ continue;
+
+ emrs2_cmd |= (rank << 22);
+ dram_init_command(emrs2_cmd);
+
+ emrs3_cmd |= (rank << 22);
+ dram_init_command(emrs3_cmd);
+
+ emrs1_cmd |= (rank << 22);
+ dram_init_command(emrs1_cmd);
+
+ mrs0_cmd |= (rank << 22);
+ dram_init_command(mrs0_cmd);
+
+ dram_init_command(DCMD_ZQCL(rank));
+ }
+
+ LEAVEFN();
+}
+
+/*
+ * Dunit Initialization Complete
+ *
+ * Indicates that initialization of the Dunit has completed.
+ *
+ * Memory accesses are permitted and maintenance operation begins.
+ * Until this bit is set to a 1, the memory controller will not accept
+ * DRAM requests from the MEMORY_MANAGER or HTE.
+ */
+void set_ddr_init_complete(struct mrc_params *mrc_params)
+{
+ u32 dco;
+
+ ENTERFN();
+
+ dco = msg_port_read(MEM_CTLR, DCO);
+ dco &= ~BIT28;
+ dco |= BIT31;
+ msg_port_write(MEM_CTLR, DCO, dco);
+
+ LEAVEFN();
+}
+
+/*
+ * This function will retrieve relevant timing data
+ *
+ * This data will be used on subsequent boots to speed up boot times
+ * and is required for Suspend To RAM capabilities.
+ */
+void restore_timings(struct mrc_params *mrc_params)
+{
+ uint8_t ch, rk, bl;
+ const struct mrc_timings *mt = &mrc_params->timings;
+
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ for (bl = 0; bl < NUM_BYTE_LANES; bl++) {
+ set_rcvn(ch, rk, bl, mt->rcvn[ch][rk][bl]);
+ set_rdqs(ch, rk, bl, mt->rdqs[ch][rk][bl]);
+ set_wdqs(ch, rk, bl, mt->wdqs[ch][rk][bl]);
+ set_wdq(ch, rk, bl, mt->wdq[ch][rk][bl]);
+ if (rk == 0) {
+ /* VREF (RANK0 only) */
+ set_vref(ch, bl, mt->vref[ch][bl]);
+ }
+ }
+ set_wctl(ch, rk, mt->wctl[ch][rk]);
+ }
+ set_wcmd(ch, mt->wcmd[ch]);
+ }
+}
+
+/*
+ * Configure default settings normally set as part of read training
+ *
+ * Some defaults have to be set earlier as they may affect earlier
+ * training steps.
+ */
+void default_timings(struct mrc_params *mrc_params)
+{
+ uint8_t ch, rk, bl;
+
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ for (bl = 0; bl < NUM_BYTE_LANES; bl++) {
+ set_rdqs(ch, rk, bl, 24);
+ if (rk == 0) {
+ /* VREF (RANK0 only) */
+ set_vref(ch, bl, 32);
+ }
+ }
+ }
+ }
+}
+
+/*
+ * This function will perform our RCVEN Calibration Algorithm.
+ * We will only use the 2xCLK domain timings to perform RCVEN Calibration.
+ * All byte lanes will be calibrated "simultaneously" per channel per rank.
+ */
+void rcvn_cal(struct mrc_params *mrc_params)
+{
+ uint8_t ch; /* channel counter */
+ uint8_t rk; /* rank counter */
+ uint8_t bl; /* byte lane counter */
+ uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1;
+
+#ifdef R2R_SHARING
+ /* used to find placement for rank2rank sharing configs */
+ uint32_t final_delay[NUM_CHANNELS][NUM_BYTE_LANES];
+#ifndef BACKUP_RCVN
+ /* used to find placement for rank2rank sharing configs */
+ uint32_t num_ranks_enabled = 0;
+#endif
+#endif
+
+#ifdef BACKUP_RCVN
+#else
+ uint32_t temp;
+ /* absolute PI value to be programmed on the byte lane */
+ uint32_t delay[NUM_BYTE_LANES];
+ u32 dtr1, dtr1_save;
+#endif
+
+ ENTERFN();
+
+ /* rcvn_cal starts */
+ mrc_post_code(0x05, 0x00);
+
+#ifndef BACKUP_RCVN
+ /* need separate burst to sample DQS preamble */
+ dtr1 = msg_port_read(MEM_CTLR, DTR1);
+ dtr1_save = dtr1;
+ dtr1 |= BIT12;
+ msg_port_write(MEM_CTLR, DTR1, dtr1);
+#endif
+
+#ifdef R2R_SHARING
+ /* need to set "final_delay[][]" elements to "0" */
+ memset((void *)(final_delay), 0x00, (size_t)sizeof(final_delay));
+#endif
+
+ /* loop through each enabled channel */
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ /* perform RCVEN Calibration on a per rank basis */
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ if (mrc_params->rank_enables & (1 << rk)) {
+ /*
+ * POST_CODE here indicates the current
+ * channel and rank being calibrated
+ */
+ mrc_post_code(0x05, (0x10 + ((ch << 4) | rk)));
+
+#ifdef BACKUP_RCVN
+ /* et hard-coded timing values */
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++)
+ set_rcvn(ch, rk, bl, ddr_rcvn[PLATFORM_ID]);
+#else
+ /* enable FIFORST */
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl += 2) {
+ mrc_alt_write_mask(DDRPHY,
+ (B01PTRCTL1 +
+ ((bl >> 1) * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ 0, BIT8);
+ }
+ /* initialize the starting delay to 128 PI (cas +1 CLK) */
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ /* 1x CLK domain timing is cas-4 */
+ delay[bl] = (4 + 1) * FULL_CLK;
+
+ set_rcvn(ch, rk, bl, delay[bl]);
+ }
+
+ /* now find the rising edge */
+ find_rising_edge(mrc_params, delay, ch, rk, true);
+
+ /* Now increase delay by 32 PI (1/4 CLK) to place in center of high pulse */
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ delay[bl] += QRTR_CLK;
+ set_rcvn(ch, rk, bl, delay[bl]);
+ }
+ /* Now decrement delay by 128 PI (1 CLK) until we sample a "0" */
+ do {
+ temp = sample_dqs(mrc_params, ch, rk, true);
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ if (temp & (1 << bl)) {
+ if (delay[bl] >= FULL_CLK) {
+ delay[bl] -= FULL_CLK;
+ set_rcvn(ch, rk, bl, delay[bl]);
+ } else {
+ /* not enough delay */
+ training_message(ch, rk, bl);
+ mrc_post_code(0xEE, 0x50);
+ }
+ }
+ }
+ } while (temp & 0xFF);
+
+#ifdef R2R_SHARING
+ /* increment "num_ranks_enabled" */
+ num_ranks_enabled++;
+ /* Finally increment delay by 32 PI (1/4 CLK) to place in center of preamble */
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ delay[bl] += QRTR_CLK;
+ /* add "delay[]" values to "final_delay[][]" for rolling average */
+ final_delay[ch][bl] += delay[bl];
+ /* set timing based on rolling average values */
+ set_rcvn(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled));
+ }
+#else
+ /* Finally increment delay by 32 PI (1/4 CLK) to place in center of preamble */
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ delay[bl] += QRTR_CLK;
+ set_rcvn(ch, rk, bl, delay[bl]);
+ }
+#endif
+
+ /* disable FIFORST */
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl += 2) {
+ mrc_alt_write_mask(DDRPHY,
+ (B01PTRCTL1 +
+ ((bl >> 1) * DDRIODQ_BL_OFFSET) +
+ (ch * DDRIODQ_CH_OFFSET)),
+ BIT8, BIT8);
+ }
+#endif
+ }
+ }
+ }
+ }
+
+#ifndef BACKUP_RCVN
+ /* restore original */
+ msg_port_write(MEM_CTLR, DTR1, dtr1_save);
+#endif
+
+ LEAVEFN();
+}
+
+/*
+ * This function will perform the Write Levelling algorithm
+ * (align WCLK and WDQS).
+ *
+ * This algorithm will act on each rank in each channel separately.
+ */
+void wr_level(struct mrc_params *mrc_params)
+{
+ uint8_t ch; /* channel counter */
+ uint8_t rk; /* rank counter */
+ uint8_t bl; /* byte lane counter */
+ uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1;
+
+#ifdef R2R_SHARING
+ /* used to find placement for rank2rank sharing configs */
+ uint32_t final_delay[NUM_CHANNELS][NUM_BYTE_LANES];
+#ifndef BACKUP_WDQS
+ /* used to find placement for rank2rank sharing configs */
+ uint32_t num_ranks_enabled = 0;
+#endif
+#endif
+
+#ifdef BACKUP_WDQS
+#else
+ /* determines stop condition for CRS_WR_LVL */
+ bool all_edges_found;
+ /* absolute PI value to be programmed on the byte lane */
+ uint32_t delay[NUM_BYTE_LANES];
+ /*
+ * static makes it so the data is loaded in the heap once by shadow(),
+ * where non-static copies the data onto the stack every time this
+ * function is called
+ */
+ uint32_t address; /* address to be checked during COARSE_WR_LVL */
+ u32 dtr4, dtr4_save;
+#endif
+
+ ENTERFN();
+
+ /* wr_level starts */
+ mrc_post_code(0x06, 0x00);
+
+#ifdef R2R_SHARING
+ /* need to set "final_delay[][]" elements to "0" */
+ memset((void *)(final_delay), 0x00, (size_t)sizeof(final_delay));
+#endif
+
+ /* loop through each enabled channel */
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ /* perform WRITE LEVELING algorithm on a per rank basis */
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ if (mrc_params->rank_enables & (1 << rk)) {
+ /*
+ * POST_CODE here indicates the current
+ * rank and channel being calibrated
+ */
+ mrc_post_code(0x06, (0x10 + ((ch << 4) | rk)));
+
+#ifdef BACKUP_WDQS
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ set_wdqs(ch, rk, bl, ddr_wdqs[PLATFORM_ID]);
+ set_wdq(ch, rk, bl, (ddr_wdqs[PLATFORM_ID] - QRTR_CLK));
+ }
+#else
+ /*
+ * perform a single PRECHARGE_ALL command to
+ * make DRAM state machine go to IDLE state
+ */
+ dram_init_command(DCMD_PREA(rk));
+
+ /*
+ * enable Write Levelling Mode
+ * (EMRS1 w/ Write Levelling Mode Enable)
+ */
+ dram_init_command(DCMD_MRS1(rk, 0x0082));
+
+ /*
+ * set ODT DRAM Full Time Termination
+ * disable in MCU
+ */
+
+ dtr4 = msg_port_read(MEM_CTLR, DTR4);
+ dtr4_save = dtr4;
+ dtr4 |= BIT15;
+ msg_port_write(MEM_CTLR, DTR4, dtr4);
+
+ for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) {
+ /*
+ * Enable Sandy Bridge Mode (WDQ Tri-State) &
+ * Ensure 5 WDQS pulses during Write Leveling
+ */
+ mrc_alt_write_mask(DDRPHY,
+ DQCTL + (DDRIODQ_BL_OFFSET * bl) + (DDRIODQ_CH_OFFSET * ch),
+ (BIT28 | BIT8 | BIT6 | BIT4 | BIT2),
+ (BIT28 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2));
+ }
+
+ /* Write Leveling Mode enabled in IO */
+ mrc_alt_write_mask(DDRPHY,
+ CCDDR3RESETCTL + (DDRIOCCC_CH_OFFSET * ch),
+ BIT16, BIT16);
+
+ /* Initialize the starting delay to WCLK */
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ /*
+ * CLK0 --> RK0
+ * CLK1 --> RK1
+ */
+ delay[bl] = get_wclk(ch, rk);
+
+ set_wdqs(ch, rk, bl, delay[bl]);
+ }
+
+ /* now find the rising edge */
+ find_rising_edge(mrc_params, delay, ch, rk, false);
+
+ /* disable Write Levelling Mode */
+ mrc_alt_write_mask(DDRPHY,
+ CCDDR3RESETCTL + (DDRIOCCC_CH_OFFSET * ch),
+ 0, BIT16);
+
+ for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) {
+ /* Disable Sandy Bridge Mode & Ensure 4 WDQS pulses during normal operation */
+ mrc_alt_write_mask(DDRPHY,
+ DQCTL + (DDRIODQ_BL_OFFSET * bl) + (DDRIODQ_CH_OFFSET * ch),
+ (BIT8 | BIT6 | BIT4 | BIT2),
+ (BIT28 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2));
+ }
+
+ /* restore original DTR4 */
+ msg_port_write(MEM_CTLR, DTR4, dtr4_save);
+
+ /*
+ * restore original value
+ * (Write Levelling Mode Disable)
+ */
+ dram_init_command(DCMD_MRS1(rk, mrc_params->mrs1));
+
+ /*
+ * perform a single PRECHARGE_ALL command to
+ * make DRAM state machine go to IDLE state
+ */
+ dram_init_command(DCMD_PREA(rk));
+
+ mrc_post_code(0x06, (0x30 + ((ch << 4) | rk)));
+
+ /*
+ * COARSE WRITE LEVEL:
+ * check that we're on the correct clock edge
+ */
+
+ /* hte reconfiguration request */
+ mrc_params->hte_setup = 1;
+
+ /* start CRS_WR_LVL with WDQS = WDQS + 128 PI */
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ delay[bl] = get_wdqs(ch, rk, bl) + FULL_CLK;
+ set_wdqs(ch, rk, bl, delay[bl]);
+ /*
+ * program WDQ timings based on WDQS
+ * (WDQ = WDQS - 32 PI)
+ */
+ set_wdq(ch, rk, bl, (delay[bl] - QRTR_CLK));
+ }
+
+ /* get an address in the targeted channel/rank */
+ address = get_addr(ch, rk);
+ do {
+ uint32_t coarse_result = 0x00;
+ uint32_t coarse_result_mask = byte_lane_mask(mrc_params);
+ /* assume pass */
+ all_edges_found = true;
+
+ mrc_params->hte_setup = 1;
+ coarse_result = check_rw_coarse(mrc_params, address);
+
+ /* check for failures and margin the byte lane back 128 PI (1 CLK) */
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ if (coarse_result & (coarse_result_mask << bl)) {
+ all_edges_found = false;
+ delay[bl] -= FULL_CLK;
+ set_wdqs(ch, rk, bl, delay[bl]);
+ /* program WDQ timings based on WDQS (WDQ = WDQS - 32 PI) */
+ set_wdq(ch, rk, bl, (delay[bl] - QRTR_CLK));
+ }
+ }
+ } while (!all_edges_found);
+
+#ifdef R2R_SHARING
+ /* increment "num_ranks_enabled" */
+ num_ranks_enabled++;
+ /* accumulate "final_delay[][]" values from "delay[]" values for rolling average */
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ final_delay[ch][bl] += delay[bl];
+ set_wdqs(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled));
+ /* program WDQ timings based on WDQS (WDQ = WDQS - 32 PI) */
+ set_wdq(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled) - QRTR_CLK);
+ }
+#endif
+#endif
+ }
+ }
+ }
+ }
+
+ LEAVEFN();
+}
+
+void prog_page_ctrl(struct mrc_params *mrc_params)
+{
+ u32 dpmc0;
+
+ ENTERFN();
+
+ dpmc0 = msg_port_read(MEM_CTLR, DPMC0);
+ dpmc0 &= ~(BIT16 | BIT17 | BIT18);
+ dpmc0 |= (4 << 16);
+ dpmc0 |= BIT21;
+ msg_port_write(MEM_CTLR, DPMC0, dpmc0);
+}
+
+/*
+ * This function will perform the READ TRAINING Algorithm on all
+ * channels/ranks/byte_lanes simultaneously to minimize execution time.
+ *
+ * The idea here is to train the VREF and RDQS (and eventually RDQ) values
+ * to achieve maximum READ margins. The algorithm will first determine the
+ * X coordinate (RDQS setting). This is done by collapsing the VREF eye
+ * until we find a minimum required RDQS eye for VREF_MIN and VREF_MAX.
+ * Then we take the averages of the RDQS eye at VREF_MIN and VREF_MAX,
+ * then average those; this will be the final X coordinate. The algorithm
+ * will then determine the Y coordinate (VREF setting). This is done by
+ * collapsing the RDQS eye until we find a minimum required VREF eye for
+ * RDQS_MIN and RDQS_MAX. Then we take the averages of the VREF eye at
+ * RDQS_MIN and RDQS_MAX, then average those; this will be the final Y
+ * coordinate.
+ *
+ * NOTE: this algorithm assumes the eye curves have a one-to-one relationship,
+ * meaning for each X the curve has only one Y and vice-a-versa.
+ */
+void rd_train(struct mrc_params *mrc_params)
+{
+ uint8_t ch; /* channel counter */
+ uint8_t rk; /* rank counter */
+ uint8_t bl; /* byte lane counter */
+ uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1;
+#ifdef BACKUP_RDQS
+#else
+ uint8_t side_x; /* tracks LEFT/RIGHT approach vectors */
+ uint8_t side_y; /* tracks BOTTOM/TOP approach vectors */
+ /* X coordinate data (passing RDQS values) for approach vectors */
+ uint8_t x_coordinate[2][2][NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
+ /* Y coordinate data (passing VREF values) for approach vectors */
+ uint8_t y_coordinate[2][2][NUM_CHANNELS][NUM_BYTE_LANES];
+ /* centered X (RDQS) */
+ uint8_t x_center[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
+ /* centered Y (VREF) */
+ uint8_t y_center[NUM_CHANNELS][NUM_BYTE_LANES];
+ uint32_t address; /* target address for check_bls_ex() */
+ uint32_t result; /* result of check_bls_ex() */
+ uint32_t bl_mask; /* byte lane mask for result checking */
+#ifdef R2R_SHARING
+ /* used to find placement for rank2rank sharing configs */
+ uint32_t final_delay[NUM_CHANNELS][NUM_BYTE_LANES];
+ /* used to find placement for rank2rank sharing configs */
+ uint32_t num_ranks_enabled = 0;
+#endif
+#endif
+
+ /* rd_train starts */
+ mrc_post_code(0x07, 0x00);
+
+ ENTERFN();
+
+#ifdef BACKUP_RDQS
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ if (mrc_params->rank_enables & (1 << rk)) {
+ for (bl = 0;
+ bl < (NUM_BYTE_LANES / bl_divisor);
+ bl++) {
+ set_rdqs(ch, rk, bl, ddr_rdqs[PLATFORM_ID]);
+ }
+ }
+ }
+ }
+ }
+#else
+ /* initialize x/y_coordinate arrays */
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ if (mrc_params->rank_enables & (1 << rk)) {
+ for (bl = 0;
+ bl < (NUM_BYTE_LANES / bl_divisor);
+ bl++) {
+ /* x_coordinate */
+ x_coordinate[L][B][ch][rk][bl] = RDQS_MIN;
+ x_coordinate[R][B][ch][rk][bl] = RDQS_MAX;
+ x_coordinate[L][T][ch][rk][bl] = RDQS_MIN;
+ x_coordinate[R][T][ch][rk][bl] = RDQS_MAX;
+ /* y_coordinate */
+ y_coordinate[L][B][ch][bl] = VREF_MIN;
+ y_coordinate[R][B][ch][bl] = VREF_MIN;
+ y_coordinate[L][T][ch][bl] = VREF_MAX;
+ y_coordinate[R][T][ch][bl] = VREF_MAX;
+ }
+ }
+ }
+ }
+ }
+
+ /* initialize other variables */
+ bl_mask = byte_lane_mask(mrc_params);
+ address = get_addr(0, 0);
+
+#ifdef R2R_SHARING
+ /* need to set "final_delay[][]" elements to "0" */
+ memset((void *)(final_delay), 0x00, (size_t)sizeof(final_delay));
+#endif
+
+ /* look for passing coordinates */
+ for (side_y = B; side_y <= T; side_y++) {
+ for (side_x = L; side_x <= R; side_x++) {
+ mrc_post_code(0x07, (0x10 + (side_y * 2) + (side_x)));
+
+ /* find passing values */
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (0x1 << ch)) {
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ if (mrc_params->rank_enables &
+ (0x1 << rk)) {
+ /* set x/y_coordinate search starting settings */
+ for (bl = 0;
+ bl < (NUM_BYTE_LANES / bl_divisor);
+ bl++) {
+ set_rdqs(ch, rk, bl,
+ x_coordinate[side_x][side_y][ch][rk][bl]);
+ set_vref(ch, bl,
+ y_coordinate[side_x][side_y][ch][bl]);
+ }
+
+ /* get an address in the target channel/rank */
+ address = get_addr(ch, rk);
+
+ /* request HTE reconfiguration */
+ mrc_params->hte_setup = 1;
+
+ /* test the settings */
+ do {
+ /* result[07:00] == failing byte lane (MAX 8) */
+ result = check_bls_ex(mrc_params, address);
+
+ /* check for failures */
+ if (result & 0xFF) {
+ /* at least 1 byte lane failed */
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ if (result &
+ (bl_mask << bl)) {
+ /* adjust the RDQS values accordingly */
+ if (side_x == L)
+ x_coordinate[L][side_y][ch][rk][bl] += RDQS_STEP;
+ else
+ x_coordinate[R][side_y][ch][rk][bl] -= RDQS_STEP;
+
+ /* check that we haven't closed the RDQS_EYE too much */
+ if ((x_coordinate[L][side_y][ch][rk][bl] > (RDQS_MAX - MIN_RDQS_EYE)) ||
+ (x_coordinate[R][side_y][ch][rk][bl] < (RDQS_MIN + MIN_RDQS_EYE)) ||
+ (x_coordinate[L][side_y][ch][rk][bl] ==
+ x_coordinate[R][side_y][ch][rk][bl])) {
+ /*
+ * not enough RDQS margin available at this VREF
+ * update VREF values accordingly
+ */
+ if (side_y == B)
+ y_coordinate[side_x][B][ch][bl] += VREF_STEP;
+ else
+ y_coordinate[side_x][T][ch][bl] -= VREF_STEP;
+
+ /* check that we haven't closed the VREF_EYE too much */
+ if ((y_coordinate[side_x][B][ch][bl] > (VREF_MAX - MIN_VREF_EYE)) ||
+ (y_coordinate[side_x][T][ch][bl] < (VREF_MIN + MIN_VREF_EYE)) ||
+ (y_coordinate[side_x][B][ch][bl] == y_coordinate[side_x][T][ch][bl])) {
+ /* VREF_EYE collapsed below MIN_VREF_EYE */
+ training_message(ch, rk, bl);
+ mrc_post_code(0xEE, (0x70 + (side_y * 2) + (side_x)));
+ } else {
+ /* update the VREF setting */
+ set_vref(ch, bl, y_coordinate[side_x][side_y][ch][bl]);
+ /* reset the X coordinate to begin the search at the new VREF */
+ x_coordinate[side_x][side_y][ch][rk][bl] =
+ (side_x == L) ? (RDQS_MIN) : (RDQS_MAX);
+ }
+ }
+
+ /* update the RDQS setting */
+ set_rdqs(ch, rk, bl, x_coordinate[side_x][side_y][ch][rk][bl]);
+ }
+ }
+ }
+ } while (result & 0xFF);
+ }
+ }
+ }
+ }
+ }
+ }
+
+ mrc_post_code(0x07, 0x20);
+
+ /* find final RDQS (X coordinate) & final VREF (Y coordinate) */
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ if (mrc_params->rank_enables & (1 << rk)) {
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ uint32_t temp1;
+ uint32_t temp2;
+
+ /* x_coordinate */
+ DPF(D_INFO,
+ "RDQS T/B eye rank%d lane%d : %d-%d %d-%d\n",
+ rk, bl,
+ x_coordinate[L][T][ch][rk][bl],
+ x_coordinate[R][T][ch][rk][bl],
+ x_coordinate[L][B][ch][rk][bl],
+ x_coordinate[R][B][ch][rk][bl]);
+
+ /* average the TOP side LEFT & RIGHT values */
+ temp1 = (x_coordinate[R][T][ch][rk][bl] + x_coordinate[L][T][ch][rk][bl]) / 2;
+ /* average the BOTTOM side LEFT & RIGHT values */
+ temp2 = (x_coordinate[R][B][ch][rk][bl] + x_coordinate[L][B][ch][rk][bl]) / 2;
+ /* average the above averages */
+ x_center[ch][rk][bl] = (uint8_t) ((temp1 + temp2) / 2);
+
+ /* y_coordinate */
+ DPF(D_INFO,
+ "VREF R/L eye lane%d : %d-%d %d-%d\n",
+ bl,
+ y_coordinate[R][B][ch][bl],
+ y_coordinate[R][T][ch][bl],
+ y_coordinate[L][B][ch][bl],
+ y_coordinate[L][T][ch][bl]);
+
+ /* average the RIGHT side TOP & BOTTOM values */
+ temp1 = (y_coordinate[R][T][ch][bl] + y_coordinate[R][B][ch][bl]) / 2;
+ /* average the LEFT side TOP & BOTTOM values */
+ temp2 = (y_coordinate[L][T][ch][bl] + y_coordinate[L][B][ch][bl]) / 2;
+ /* average the above averages */
+ y_center[ch][bl] = (uint8_t) ((temp1 + temp2) / 2);
+ }
+ }
+ }
+ }
+ }
+
+#ifdef RX_EYE_CHECK
+ /* perform an eye check */
+ for (side_y = B; side_y <= T; side_y++) {
+ for (side_x = L; side_x <= R; side_x++) {
+ mrc_post_code(0x07, (0x30 + (side_y * 2) + (side_x)));
+
+ /* update the settings for the eye check */
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ if (mrc_params->rank_enables & (1 << rk)) {
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ if (side_x == L)
+ set_rdqs(ch, rk, bl, (x_center[ch][rk][bl] - (MIN_RDQS_EYE / 2)));
+ else
+ set_rdqs(ch, rk, bl, (x_center[ch][rk][bl] + (MIN_RDQS_EYE / 2)));
+
+ if (side_y == B)
+ set_vref(ch, bl, (y_center[ch][bl] - (MIN_VREF_EYE / 2)));
+ else
+ set_vref(ch, bl, (y_center[ch][bl] + (MIN_VREF_EYE / 2)));
+ }
+ }
+ }
+ }
+ }
+
+ /* request HTE reconfiguration */
+ mrc_params->hte_setup = 1;
+
+ /* check the eye */
+ if (check_bls_ex(mrc_params, address) & 0xFF) {
+ /* one or more byte lanes failed */
+ mrc_post_code(0xEE, (0x74 + (side_x * 2) + (side_y)));
+ }
+ }
+ }
+#endif
+
+ mrc_post_code(0x07, 0x40);
+
+ /* set final placements */
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ if (mrc_params->rank_enables & (1 << rk)) {
+#ifdef R2R_SHARING
+ /* increment "num_ranks_enabled" */
+ num_ranks_enabled++;
+#endif
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ /* x_coordinate */
+#ifdef R2R_SHARING
+ final_delay[ch][bl] += x_center[ch][rk][bl];
+ set_rdqs(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled));
+#else
+ set_rdqs(ch, rk, bl, x_center[ch][rk][bl]);
+#endif
+ /* y_coordinate */
+ set_vref(ch, bl, y_center[ch][bl]);
+ }
+ }
+ }
+ }
+ }
+#endif
+
+ LEAVEFN();
+}
+
+/*
+ * This function will perform the WRITE TRAINING Algorithm on all
+ * channels/ranks/byte_lanes simultaneously to minimize execution time.
+ *
+ * The idea here is to train the WDQ timings to achieve maximum WRITE margins.
+ * The algorithm will start with WDQ at the current WDQ setting (tracks WDQS
+ * in WR_LVL) +/- 32 PIs (+/- 1/4 CLK) and collapse the eye until all data
+ * patterns pass. This is because WDQS will be aligned to WCLK by the
+ * Write Leveling algorithm and WDQ will only ever have a 1/2 CLK window
+ * of validity.
+ */
+void wr_train(struct mrc_params *mrc_params)
+{
+ uint8_t ch; /* channel counter */
+ uint8_t rk; /* rank counter */
+ uint8_t bl; /* byte lane counter */
+ uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1;
+#ifdef BACKUP_WDQ
+#else
+ uint8_t side; /* LEFT/RIGHT side indicator (0=L, 1=R) */
+ uint32_t temp; /* temporary DWORD */
+ /* 2 arrays, for L & R side passing delays */
+ uint32_t delay[2][NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
+ uint32_t address; /* target address for check_bls_ex() */
+ uint32_t result; /* result of check_bls_ex() */
+ uint32_t bl_mask; /* byte lane mask for result checking */
+#ifdef R2R_SHARING
+ /* used to find placement for rank2rank sharing configs */
+ uint32_t final_delay[NUM_CHANNELS][NUM_BYTE_LANES];
+ /* used to find placement for rank2rank sharing configs */
+ uint32_t num_ranks_enabled = 0;
+#endif
+#endif
+
+ /* wr_train starts */
+ mrc_post_code(0x08, 0x00);
+
+ ENTERFN();
+
+#ifdef BACKUP_WDQ
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ if (mrc_params->rank_enables & (1 << rk)) {
+ for (bl = 0;
+ bl < (NUM_BYTE_LANES / bl_divisor);
+ bl++) {
+ set_wdq(ch, rk, bl, ddr_wdq[PLATFORM_ID]);
+ }
+ }
+ }
+ }
+ }
+#else
+ /* initialize "delay" */
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ if (mrc_params->rank_enables & (1 << rk)) {
+ for (bl = 0;
+ bl < (NUM_BYTE_LANES / bl_divisor);
+ bl++) {
+ /*
+ * want to start with
+ * WDQ = (WDQS - QRTR_CLK)
+ * +/- QRTR_CLK
+ */
+ temp = get_wdqs(ch, rk, bl) - QRTR_CLK;
+ delay[L][ch][rk][bl] = temp - QRTR_CLK;
+ delay[R][ch][rk][bl] = temp + QRTR_CLK;
+ }
+ }
+ }
+ }
+ }
+
+ /* initialize other variables */
+ bl_mask = byte_lane_mask(mrc_params);
+ address = get_addr(0, 0);
+
+#ifdef R2R_SHARING
+ /* need to set "final_delay[][]" elements to "0" */
+ memset((void *)(final_delay), 0x00, (size_t)sizeof(final_delay));
+#endif
+
+ /*
+ * start algorithm on the LEFT side and train each channel/bl
+ * until no failures are observed, then repeat for the RIGHT side.
+ */
+ for (side = L; side <= R; side++) {
+ mrc_post_code(0x08, (0x10 + (side)));
+
+ /* set starting values */
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ if (mrc_params->rank_enables &
+ (1 << rk)) {
+ for (bl = 0;
+ bl < (NUM_BYTE_LANES / bl_divisor);
+ bl++) {
+ set_wdq(ch, rk, bl, delay[side][ch][rk][bl]);
+ }
+ }
+ }
+ }
+ }
+
+ /* find passing values */
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ if (mrc_params->rank_enables &
+ (1 << rk)) {
+ /* get an address in the target channel/rank */
+ address = get_addr(ch, rk);
+
+ /* request HTE reconfiguration */
+ mrc_params->hte_setup = 1;
+
+ /* check the settings */
+ do {
+ /* result[07:00] == failing byte lane (MAX 8) */
+ result = check_bls_ex(mrc_params, address);
+ /* check for failures */
+ if (result & 0xFF) {
+ /* at least 1 byte lane failed */
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ if (result &
+ (bl_mask << bl)) {
+ if (side == L)
+ delay[L][ch][rk][bl] += WDQ_STEP;
+ else
+ delay[R][ch][rk][bl] -= WDQ_STEP;
+
+ /* check for algorithm failure */
+ if (delay[L][ch][rk][bl] != delay[R][ch][rk][bl]) {
+ /*
+ * margin available
+ * update delay setting
+ */
+ set_wdq(ch, rk, bl,
+ delay[side][ch][rk][bl]);
+ } else {
+ /*
+ * no margin available
+ * notify the user and halt
+ */
+ training_message(ch, rk, bl);
+ mrc_post_code(0xEE, (0x80 + side));
+ }
+ }
+ }
+ }
+ /* stop when all byte lanes pass */
+ } while (result & 0xFF);
+ }
+ }
+ }
+ }
+ }
+
+ /* program WDQ to the middle of passing window */
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ if (mrc_params->channel_enables & (1 << ch)) {
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ if (mrc_params->rank_enables & (1 << rk)) {
+#ifdef R2R_SHARING
+ /* increment "num_ranks_enabled" */
+ num_ranks_enabled++;
+#endif
+ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
+ DPF(D_INFO,
+ "WDQ eye rank%d lane%d : %d-%d\n",
+ rk, bl,
+ delay[L][ch][rk][bl],
+ delay[R][ch][rk][bl]);
+
+ temp = (delay[R][ch][rk][bl] + delay[L][ch][rk][bl]) / 2;
+
+#ifdef R2R_SHARING
+ final_delay[ch][bl] += temp;
+ set_wdq(ch, rk, bl,
+ ((final_delay[ch][bl]) / num_ranks_enabled));
+#else
+ set_wdq(ch, rk, bl, temp);
+#endif
+ }
+ }
+ }
+ }
+ }
+#endif
+
+ LEAVEFN();
+}
+
+/*
+ * This function will store relevant timing data
+ *
+ * This data will be used on subsequent boots to speed up boot times
+ * and is required for Suspend To RAM capabilities.
+ */
+void store_timings(struct mrc_params *mrc_params)
+{
+ uint8_t ch, rk, bl;
+ struct mrc_timings *mt = &mrc_params->timings;
+
+ for (ch = 0; ch < NUM_CHANNELS; ch++) {
+ for (rk = 0; rk < NUM_RANKS; rk++) {
+ for (bl = 0; bl < NUM_BYTE_LANES; bl++) {
+ mt->rcvn[ch][rk][bl] = get_rcvn(ch, rk, bl);
+ mt->rdqs[ch][rk][bl] = get_rdqs(ch, rk, bl);
+ mt->wdqs[ch][rk][bl] = get_wdqs(ch, rk, bl);
+ mt->wdq[ch][rk][bl] = get_wdq(ch, rk, bl);
+
+ if (rk == 0)
+ mt->vref[ch][bl] = get_vref(ch, bl);
+ }
+
+ mt->wctl[ch][rk] = get_wctl(ch, rk);
+ }
+
+ mt->wcmd[ch] = get_wcmd(ch);
+ }
+
+ /* need to save for a case of changing frequency after warm reset */
+ mt->ddr_speed = mrc_params->ddr_speed;
+}
+
+/*
+ * The purpose of this function is to ensure the SEC comes out of reset
+ * and IA initiates the SEC enabling Memory Scrambling.
+ */
+void enable_scrambling(struct mrc_params *mrc_params)
+{
+ uint32_t lfsr = 0;
+ uint8_t i;
+
+ if (mrc_params->scrambling_enables == 0)
+ return;
+
+ ENTERFN();
+
+ /* 32 bit seed is always stored in BIOS NVM */
+ lfsr = mrc_params->timings.scrambler_seed;
+
+ if (mrc_params->boot_mode == BM_COLD) {
+ /*
+ * factory value is 0 and in first boot,
+ * a clock based seed is loaded.
+ */
+ if (lfsr == 0) {
+ /*
+ * get seed from system clock
+ * and make sure it is not all 1's
+ */
+ lfsr = rdtsc() & 0x0FFFFFFF;
+ } else {
+ /*
+ * Need to replace scrambler
+ *
+ * get next 32bit LFSR 16 times which is the last
+ * part of the previous scrambler vector
+ */
+ for (i = 0; i < 16; i++)
+ lfsr32(&lfsr);
+ }
+
+ /* save new seed */
+ mrc_params->timings.scrambler_seed = lfsr;
+ }
+
+ /*
+ * In warm boot or S3 exit, we have the previous seed.
+ * In cold boot, we have the last 32bit LFSR which is the new seed.
+ */
+ lfsr32(&lfsr); /* shift to next value */
+ msg_port_write(MEM_CTLR, SCRMSEED, (lfsr & 0x0003FFFF));
+
+ for (i = 0; i < 2; i++)
+ msg_port_write(MEM_CTLR, SCRMLO + i, (lfsr & 0xAAAAAAAA));
+
+ LEAVEFN();
+}
+
+/*
+ * Configure MCU Power Management Control Register
+ * and Scheduler Control Register
+ */
+void prog_ddr_control(struct mrc_params *mrc_params)
+{
+ u32 dsch;
+ u32 dpmc0;
+
+ ENTERFN();
+
+ dsch = msg_port_read(MEM_CTLR, DSCH);
+ dsch &= ~(BIT8 | BIT9 | BIT12);
+ msg_port_write(MEM_CTLR, DSCH, dsch);
+
+ dpmc0 = msg_port_read(MEM_CTLR, DPMC0);
+ dpmc0 &= ~BIT25;
+ dpmc0 |= (mrc_params->power_down_disable << 25);
+ dpmc0 &= ~BIT24;
+ dpmc0 &= ~(BIT16 | BIT17 | BIT18);
+ dpmc0 |= (4 << 16);
+ dpmc0 |= BIT21;
+ msg_port_write(MEM_CTLR, DPMC0, dpmc0);
+
+ /* CMDTRIST = 2h - CMD/ADDR are tristated when no valid command */
+ mrc_write_mask(MEM_CTLR, DPMC1, 2 << 4, BIT4 | BIT5);
+
+ LEAVEFN();
+}
+
+/*
+ * After training complete configure MCU Rank Population Register
+ * specifying: ranks enabled, device width, density, address mode
+ */
+void prog_dra_drb(struct mrc_params *mrc_params)
+{
+ u32 drp;
+ u32 dco;
+ u8 density = mrc_params->params.density;
+
+ ENTERFN();
+
+ dco = msg_port_read(MEM_CTLR, DCO);
+ dco &= ~BIT31;
+ msg_port_write(MEM_CTLR, DCO, dco);
+
+ drp = 0;
+ if (mrc_params->rank_enables & 1)
+ drp |= BIT0;
+ if (mrc_params->rank_enables & 2)
+ drp |= BIT1;
+ if (mrc_params->dram_width == X16) {
+ drp |= (1 << 4);
+ drp |= (1 << 9);
+ }
+
+ /*
+ * Density encoding in struct dram_params: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb
+ * has to be mapped RANKDENSx encoding (0=1Gb)
+ */
+ if (density == 0)
+ density = 4;
+
+ drp |= ((density - 1) << 6);
+ drp |= ((density - 1) << 11);
+
+ /* Address mode can be overwritten if ECC enabled */
+ drp |= (mrc_params->address_mode << 14);
+
+ msg_port_write(MEM_CTLR, DRP, drp);
+
+ dco &= ~BIT28;
+ dco |= BIT31;
+ msg_port_write(MEM_CTLR, DCO, dco);
+
+ LEAVEFN();
+}
+
+/* Send DRAM wake command */
+void perform_wake(struct mrc_params *mrc_params)
+{
+ ENTERFN();
+
+ dram_wake_command();
+
+ LEAVEFN();
+}
+
+/*
+ * Configure refresh rate and short ZQ calibration interval
+ * Activate dynamic self refresh
+ */
+void change_refresh_period(struct mrc_params *mrc_params)
+{
+ u32 drfc;
+ u32 dcal;
+ u32 dpmc0;
+
+ ENTERFN();
+
+ drfc = msg_port_read(MEM_CTLR, DRFC);
+ drfc &= ~(BIT12 | BIT13 | BIT14);
+ drfc |= (mrc_params->refresh_rate << 12);
+ drfc |= BIT21;
+ msg_port_write(MEM_CTLR, DRFC, drfc);
+
+ dcal = msg_port_read(MEM_CTLR, DCAL);
+ dcal &= ~(BIT8 | BIT9 | BIT10);
+ dcal |= (3 << 8); /* 63ms */
+ msg_port_write(MEM_CTLR, DCAL, dcal);
+
+ dpmc0 = msg_port_read(MEM_CTLR, DPMC0);
+ dpmc0 |= (BIT23 | BIT29);
+ msg_port_write(MEM_CTLR, DPMC0, dpmc0);
+
+ LEAVEFN();
+}
+
+/*
+ * Configure DDRPHY for Auto-Refresh, Periodic Compensations,
+ * Dynamic Diff-Amp, ZQSPERIOD, Auto-Precharge, CKE Power-Down
+ */
+void set_auto_refresh(struct mrc_params *mrc_params)
+{
+ uint32_t channel;
+ uint32_t rank;
+ uint32_t bl;
+ uint32_t bl_divisor = 1;
+ uint32_t temp;
+
+ ENTERFN();
+
+ /*
+ * Enable Auto-Refresh, Periodic Compensations, Dynamic Diff-Amp,
+ * ZQSPERIOD, Auto-Precharge, CKE Power-Down
+ */
+ for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (mrc_params->channel_enables & (1 << channel)) {
+ /* Enable Periodic RCOMPS */
+ mrc_alt_write_mask(DDRPHY, CMPCTRL, BIT1, BIT1);
+
+ /* Enable Dynamic DiffAmp & Set Read ODT Value */
+ switch (mrc_params->rd_odt_value) {
+ case 0:
+ temp = 0x3F; /* OFF */
+ break;
+ default:
+ temp = 0x00; /* Auto */
+ break;
+ }
+
+ for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) {
+ /* Override: DIFFAMP, ODT */
+ mrc_alt_write_mask(DDRPHY,
+ (B0OVRCTL + (bl * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET)),
+ (0x00 << 16) | (temp << 10),
+ (BIT21 | BIT20 | BIT19 | BIT18 |
+ BIT17 | BIT16 | BIT15 | BIT14 |
+ BIT13 | BIT12 | BIT11 | BIT10));
+
+ /* Override: DIFFAMP, ODT */
+ mrc_alt_write_mask(DDRPHY,
+ (B1OVRCTL + (bl * DDRIODQ_BL_OFFSET) +
+ (channel * DDRIODQ_CH_OFFSET)),
+ (0x00 << 16) | (temp << 10),
+ (BIT21 | BIT20 | BIT19 | BIT18 |
+ BIT17 | BIT16 | BIT15 | BIT14 |
+ BIT13 | BIT12 | BIT11 | BIT10));
+ }
+
+ /* Issue ZQCS command */
+ for (rank = 0; rank < NUM_RANKS; rank++) {
+ if (mrc_params->rank_enables & (1 << rank))
+ dram_init_command(DCMD_ZQCS(rank));
+ }
+ }
+ }
+
+ clear_pointers();
+
+ LEAVEFN();
+}
+
+/*
+ * Depending on configuration enables ECC support
+ *
+ * Available memory size is decreased, and updated with 0s
+ * in order to clear error status. Address mode 2 forced.
+ */
+void ecc_enable(struct mrc_params *mrc_params)
+{
+ u32 drp;
+ u32 dsch;
+ u32 ecc_ctrl;
+
+ if (mrc_params->ecc_enables == 0)
+ return;
+
+ ENTERFN();
+
+ /* Configuration required in ECC mode */
+ drp = msg_port_read(MEM_CTLR, DRP);
+ drp &= ~(BIT14 | BIT15);
+ drp |= BIT15;
+ drp |= BIT13;
+ msg_port_write(MEM_CTLR, DRP, drp);
+
+ /* Disable new request bypass */
+ dsch = msg_port_read(MEM_CTLR, DSCH);
+ dsch |= BIT12;
+ msg_port_write(MEM_CTLR, DSCH, dsch);
+
+ /* Enable ECC */
+ ecc_ctrl = (BIT0 | BIT1 | BIT17);
+ msg_port_write(MEM_CTLR, DECCCTRL, ecc_ctrl);
+
+ /* Assume 8 bank memory, one bank is gone for ECC */
+ mrc_params->mem_size -= mrc_params->mem_size / 8;
+
+ /* For S3 resume memory content has to be preserved */
+ if (mrc_params->boot_mode != BM_S3) {
+ select_hte();
+ hte_mem_init(mrc_params, MRC_MEM_INIT);
+ select_mem_mgr();
+ }
+
+ LEAVEFN();
+}
+
+/*
+ * Execute memory test
+ * if error detected it is indicated in mrc_params->status
+ */
+void memory_test(struct mrc_params *mrc_params)
+{
+ uint32_t result = 0;
+
+ ENTERFN();
+
+ select_hte();
+ result = hte_mem_init(mrc_params, MRC_MEM_TEST);
+ select_mem_mgr();
+
+ DPF(D_INFO, "Memory test result %x\n", result);
+ mrc_params->status = ((result == 0) ? MRC_SUCCESS : MRC_E_MEMTEST);
+ LEAVEFN();
+}
+
+/* Lock MCU registers at the end of initialization sequence */
+void lock_registers(struct mrc_params *mrc_params)
+{
+ u32 dco;
+
+ ENTERFN();
+
+ dco = msg_port_read(MEM_CTLR, DCO);
+ dco &= ~(BIT28 | BIT29);
+ dco |= (BIT0 | BIT8);
+ msg_port_write(MEM_CTLR, DCO, dco);
+
+ LEAVEFN();
+}
diff --git a/arch/x86/cpu/quark/smc.h b/arch/x86/cpu/quark/smc.h
new file mode 100644
index 0000000..46017a1
--- /dev/null
+++ b/arch/x86/cpu/quark/smc.h
@@ -0,0 +1,446 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Ported from Intel released Quark UEFI BIOS
+ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef _SMC_H_
+#define _SMC_H_
+
+/* System Memory Controller Register Defines */
+
+/* Memory Controller Message Bus Registers Offsets */
+#define DRP 0x00
+#define DTR0 0x01
+#define DTR1 0x02
+#define DTR2 0x03
+#define DTR3 0x04
+#define DTR4 0x05
+#define DPMC0 0x06
+#define DPMC1 0x07
+#define DRFC 0x08
+#define DSCH 0x09
+#define DCAL 0x0A
+#define DRMC 0x0B
+#define PMSTS 0x0C
+#define DCO 0x0F
+#define DSTAT 0x20
+#define SSKPD0 0x4A
+#define SSKPD1 0x4B
+#define DECCCTRL 0x60
+#define DECCSTAT 0x61
+#define DECCSBECNT 0x62
+#define DECCSBECA 0x68
+#define DECCSBECS 0x69
+#define DECCDBECA 0x6A
+#define DECCDBECS 0x6B
+#define DFUSESTAT 0x70
+#define SCRMSEED 0x80
+#define SCRMLO 0x81
+#define SCRMHI 0x82
+
+/* DRAM init command */
+#define DCMD_MRS1(rnk, dat) (0 | ((rnk) << 22) | (1 << 3) | ((dat) << 6))
+#define DCMD_REF(rnk) (1 | ((rnk) << 22))
+#define DCMD_PRE(rnk) (2 | ((rnk) << 22))
+#define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (BIT10 << 6))
+#define DCMD_ACT(rnk, row) (3 | ((rnk) << 22) | ((row) << 6))
+#define DCMD_WR(rnk, col) (4 | ((rnk) << 22) | ((col) << 6))
+#define DCMD_RD(rnk, col) (5 | ((rnk) << 22) | ((col) << 6))
+#define DCMD_ZQCS(rnk) (6 | ((rnk) << 22))
+#define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (BIT10 << 6))
+#define DCMD_NOP(rnk) (7 | ((rnk) << 22))
+
+#define DDR3_EMRS1_DIC_40 (0)
+#define DDR3_EMRS1_DIC_34 (1)
+
+#define DDR3_EMRS1_RTTNOM_0 (0)
+#define DDR3_EMRS1_RTTNOM_60 (0x04)
+#define DDR3_EMRS1_RTTNOM_120 (0x40)
+#define DDR3_EMRS1_RTTNOM_40 (0x44)
+#define DDR3_EMRS1_RTTNOM_20 (0x200)
+#define DDR3_EMRS1_RTTNOM_30 (0x204)
+
+#define DDR3_EMRS2_RTTWR_60 (1 << 9)
+#define DDR3_EMRS2_RTTWR_120 (1 << 10)
+
+/* BEGIN DDRIO Registers */
+
+/* DDR IOs & COMPs */
+#define DDRIODQ_BL_OFFSET 0x0800
+#define DDRIODQ_CH_OFFSET ((NUM_BYTE_LANES / 2) * DDRIODQ_BL_OFFSET)
+#define DDRIOCCC_CH_OFFSET 0x0800
+#define DDRCOMP_CH_OFFSET 0x0100
+
+/* CH0-BL01-DQ */
+#define DQOBSCKEBBCTL 0x0000
+#define DQDLLTXCTL 0x0004
+#define DQDLLRXCTL 0x0008
+#define DQMDLLCTL 0x000C
+#define B0RXIOBUFCTL 0x0010
+#define B0VREFCTL 0x0014
+#define B0RXOFFSET1 0x0018
+#define B0RXOFFSET0 0x001C
+#define B1RXIOBUFCTL 0x0020
+#define B1VREFCTL 0x0024
+#define B1RXOFFSET1 0x0028
+#define B1RXOFFSET0 0x002C
+#define DQDFTCTL 0x0030
+#define DQTRAINSTS 0x0034
+#define B1DLLPICODER0 0x0038
+#define B0DLLPICODER0 0x003C
+#define B1DLLPICODER1 0x0040
+#define B0DLLPICODER1 0x0044
+#define B1DLLPICODER2 0x0048
+#define B0DLLPICODER2 0x004C
+#define B1DLLPICODER3 0x0050
+#define B0DLLPICODER3 0x0054
+#define B1RXDQSPICODE 0x0058
+#define B0RXDQSPICODE 0x005C
+#define B1RXDQPICODER32 0x0060
+#define B1RXDQPICODER10 0x0064
+#define B0RXDQPICODER32 0x0068
+#define B0RXDQPICODER10 0x006C
+#define B01PTRCTL0 0x0070
+#define B01PTRCTL1 0x0074
+#define B01DBCTL0 0x0078
+#define B01DBCTL1 0x007C
+#define B0LATCTL0 0x0080
+#define B1LATCTL0 0x0084
+#define B01LATCTL1 0x0088
+#define B0ONDURCTL 0x008C
+#define B1ONDURCTL 0x0090
+#define B0OVRCTL 0x0094
+#define B1OVRCTL 0x0098
+#define DQCTL 0x009C
+#define B0RK2RKCHGPTRCTRL 0x00A0
+#define B1RK2RKCHGPTRCTRL 0x00A4
+#define DQRK2RKCTL 0x00A8
+#define DQRK2RKPTRCTL 0x00AC
+#define B0RK2RKLAT 0x00B0
+#define B1RK2RKLAT 0x00B4
+#define DQCLKALIGNREG0 0x00B8
+#define DQCLKALIGNREG1 0x00BC
+#define DQCLKALIGNREG2 0x00C0
+#define DQCLKALIGNSTS0 0x00C4
+#define DQCLKALIGNSTS1 0x00C8
+#define DQCLKGATE 0x00CC
+#define B0COMPSLV1 0x00D0
+#define B1COMPSLV1 0x00D4
+#define B0COMPSLV2 0x00D8
+#define B1COMPSLV2 0x00DC
+#define B0COMPSLV3 0x00E0
+#define B1COMPSLV3 0x00E4
+#define DQVISALANECR0TOP 0x00E8
+#define DQVISALANECR1TOP 0x00EC
+#define DQVISACONTROLCRTOP 0x00F0
+#define DQVISALANECR0BL 0x00F4
+#define DQVISALANECR1BL 0x00F8
+#define DQVISACONTROLCRBL 0x00FC
+#define DQTIMINGCTRL 0x010C
+
+/* CH0-ECC */
+#define ECCDLLTXCTL 0x2004
+#define ECCDLLRXCTL 0x2008
+#define ECCMDLLCTL 0x200C
+#define ECCB1DLLPICODER0 0x2038
+#define ECCB1DLLPICODER1 0x2040
+#define ECCB1DLLPICODER2 0x2048
+#define ECCB1DLLPICODER3 0x2050
+#define ECCB01DBCTL0 0x2078
+#define ECCB01DBCTL1 0x207C
+#define ECCCLKALIGNREG0 0x20B8
+#define ECCCLKALIGNREG1 0x20BC
+#define ECCCLKALIGNREG2 0x20C0
+
+/* CH0-CMD */
+#define CMDOBSCKEBBCTL 0x4800
+#define CMDDLLTXCTL 0x4808
+#define CMDDLLRXCTL 0x480C
+#define CMDMDLLCTL 0x4810
+#define CMDRCOMPODT 0x4814
+#define CMDDLLPICODER0 0x4820
+#define CMDDLLPICODER1 0x4824
+#define CMDCFGREG0 0x4840
+#define CMDPTRREG 0x4844
+#define CMDCLKALIGNREG0 0x4850
+#define CMDCLKALIGNREG1 0x4854
+#define CMDCLKALIGNREG2 0x4858
+#define CMDPMCONFIG0 0x485C
+#define CMDPMDLYREG0 0x4860
+#define CMDPMDLYREG1 0x4864
+#define CMDPMDLYREG2 0x4868
+#define CMDPMDLYREG3 0x486C
+#define CMDPMDLYREG4 0x4870
+#define CMDCLKALIGNSTS0 0x4874
+#define CMDCLKALIGNSTS1 0x4878
+#define CMDPMSTS0 0x487C
+#define CMDPMSTS1 0x4880
+#define CMDCOMPSLV 0x4884
+#define CMDBONUS0 0x488C
+#define CMDBONUS1 0x4890
+#define CMDVISALANECR0 0x4894
+#define CMDVISALANECR1 0x4898
+#define CMDVISACONTROLCR 0x489C
+#define CMDCLKGATE 0x48A0
+#define CMDTIMINGCTRL 0x48A4
+
+/* CH0-CLK-CTL */
+#define CCOBSCKEBBCTL 0x5800
+#define CCRCOMPIO 0x5804
+#define CCDLLTXCTL 0x5808
+#define CCDLLRXCTL 0x580C
+#define CCMDLLCTL 0x5810
+#define CCRCOMPODT 0x5814
+#define CCDLLPICODER0 0x5820
+#define CCDLLPICODER1 0x5824
+#define CCDDR3RESETCTL 0x5830
+#define CCCFGREG0 0x5838
+#define CCCFGREG1 0x5840
+#define CCPTRREG 0x5844
+#define CCCLKALIGNREG0 0x5850
+#define CCCLKALIGNREG1 0x5854
+#define CCCLKALIGNREG2 0x5858
+#define CCPMCONFIG0 0x585C
+#define CCPMDLYREG0 0x5860
+#define CCPMDLYREG1 0x5864
+#define CCPMDLYREG2 0x5868
+#define CCPMDLYREG3 0x586C
+#define CCPMDLYREG4 0x5870
+#define CCCLKALIGNSTS0 0x5874
+#define CCCLKALIGNSTS1 0x5878
+#define CCPMSTS0 0x587C
+#define CCPMSTS1 0x5880
+#define CCCOMPSLV1 0x5884
+#define CCCOMPSLV2 0x5888
+#define CCCOMPSLV3 0x588C
+#define CCBONUS0 0x5894
+#define CCBONUS1 0x5898
+#define CCVISALANECR0 0x589C
+#define CCVISALANECR1 0x58A0
+#define CCVISACONTROLCR 0x58A4
+#define CCCLKGATE 0x58A8
+#define CCTIMINGCTL 0x58AC
+
+/* COMP */
+#define CMPCTRL 0x6800
+#define SOFTRSTCNTL 0x6804
+#define MSCNTR 0x6808
+#define NMSCNTRL 0x680C
+#define LATCH1CTL 0x6814
+#define COMPVISALANECR0 0x681C
+#define COMPVISALANECR1 0x6820
+#define COMPVISACONTROLCR 0x6824
+#define COMPBONUS0 0x6830
+#define TCOCNTCTRL 0x683C
+#define DQANAODTPUCTL 0x6840
+#define DQANAODTPDCTL 0x6844
+#define DQANADRVPUCTL 0x6848
+#define DQANADRVPDCTL 0x684C
+#define DQANADLYPUCTL 0x6850
+#define DQANADLYPDCTL 0x6854
+#define DQANATCOPUCTL 0x6858
+#define DQANATCOPDCTL 0x685C
+#define CMDANADRVPUCTL 0x6868
+#define CMDANADRVPDCTL 0x686C
+#define CMDANADLYPUCTL 0x6870
+#define CMDANADLYPDCTL 0x6874
+#define CLKANAODTPUCTL 0x6880
+#define CLKANAODTPDCTL 0x6884
+#define CLKANADRVPUCTL 0x6888
+#define CLKANADRVPDCTL 0x688C
+#define CLKANADLYPUCTL 0x6890
+#define CLKANADLYPDCTL 0x6894
+#define CLKANATCOPUCTL 0x6898
+#define CLKANATCOPDCTL 0x689C
+#define DQSANAODTPUCTL 0x68A0
+#define DQSANAODTPDCTL 0x68A4
+#define DQSANADRVPUCTL 0x68A8
+#define DQSANADRVPDCTL 0x68AC
+#define DQSANADLYPUCTL 0x68B0
+#define DQSANADLYPDCTL 0x68B4
+#define DQSANATCOPUCTL 0x68B8
+#define DQSANATCOPDCTL 0x68BC
+#define CTLANADRVPUCTL 0x68C8
+#define CTLANADRVPDCTL 0x68CC
+#define CTLANADLYPUCTL 0x68D0
+#define CTLANADLYPDCTL 0x68D4
+#define CHNLBUFSTATIC 0x68F0
+#define COMPOBSCNTRL 0x68F4
+#define COMPBUFFDBG0 0x68F8
+#define COMPBUFFDBG1 0x68FC
+#define CFGMISCCH0 0x6900
+#define COMPEN0CH0 0x6904
+#define COMPEN1CH0 0x6908
+#define COMPEN2CH0 0x690C
+#define STATLEGEN0CH0 0x6910
+#define STATLEGEN1CH0 0x6914
+#define DQVREFCH0 0x6918
+#define CMDVREFCH0 0x691C
+#define CLKVREFCH0 0x6920
+#define DQSVREFCH0 0x6924
+#define CTLVREFCH0 0x6928
+#define TCOVREFCH0 0x692C
+#define DLYSELCH0 0x6930
+#define TCODRAMBUFODTCH0 0x6934
+#define CCBUFODTCH0 0x6938
+#define RXOFFSETCH0 0x693C
+#define DQODTPUCTLCH0 0x6940
+#define DQODTPDCTLCH0 0x6944
+#define DQDRVPUCTLCH0 0x6948
+#define DQDRVPDCTLCH0 0x694C
+#define DQDLYPUCTLCH0 0x6950
+#define DQDLYPDCTLCH0 0x6954
+#define DQTCOPUCTLCH0 0x6958
+#define DQTCOPDCTLCH0 0x695C
+#define CMDDRVPUCTLCH0 0x6968
+#define CMDDRVPDCTLCH0 0x696C
+#define CMDDLYPUCTLCH0 0x6970
+#define CMDDLYPDCTLCH0 0x6974
+#define CLKODTPUCTLCH0 0x6980
+#define CLKODTPDCTLCH0 0x6984
+#define CLKDRVPUCTLCH0 0x6988
+#define CLKDRVPDCTLCH0 0x698C
+#define CLKDLYPUCTLCH0 0x6990
+#define CLKDLYPDCTLCH0 0x6994
+#define CLKTCOPUCTLCH0 0x6998
+#define CLKTCOPDCTLCH0 0x699C
+#define DQSODTPUCTLCH0 0x69A0
+#define DQSODTPDCTLCH0 0x69A4
+#define DQSDRVPUCTLCH0 0x69A8
+#define DQSDRVPDCTLCH0 0x69AC
+#define DQSDLYPUCTLCH0 0x69B0
+#define DQSDLYPDCTLCH0 0x69B4
+#define DQSTCOPUCTLCH0 0x69B8
+#define DQSTCOPDCTLCH0 0x69BC
+#define CTLDRVPUCTLCH0 0x69C8
+#define CTLDRVPDCTLCH0 0x69CC
+#define CTLDLYPUCTLCH0 0x69D0
+#define CTLDLYPDCTLCH0 0x69D4
+#define FNLUPDTCTLCH0 0x69F0
+
+/* PLL */
+#define MPLLCTRL0 0x7800
+#define MPLLCTRL1 0x7808
+#define MPLLCSR0 0x7810
+#define MPLLCSR1 0x7814
+#define MPLLCSR2 0x7820
+#define MPLLDFT 0x7828
+#define MPLLMON0CTL 0x7830
+#define MPLLMON1CTL 0x7838
+#define MPLLMON2CTL 0x783C
+#define SFRTRIM 0x7850
+#define MPLLDFTOUT0 0x7858
+#define MPLLDFTOUT1 0x785C
+#define MASTERRSTN 0x7880
+#define PLLLOCKDEL 0x7884
+#define SFRDEL 0x7888
+#define CRUVISALANECR0 0x78F0
+#define CRUVISALANECR1 0x78F4
+#define CRUVISACONTROLCR 0x78F8
+#define IOSFVISALANECR0 0x78FC
+#define IOSFVISALANECR1 0x7900
+#define IOSFVISACONTROLCR 0x7904
+
+/* END DDRIO Registers */
+
+/* DRAM Specific Message Bus OpCodes */
+#define MSG_OP_DRAM_INIT 0x68
+#define MSG_OP_DRAM_WAKE 0xCA
+
+#define SAMPLE_SIZE 6
+
+/* must be less than this number to enable early deadband */
+#define EARLY_DB 0x12
+/* must be greater than this number to enable late deadband */
+#define LATE_DB 0x34
+
+#define CHX_REGS (11 * 4)
+#define FULL_CLK 128
+#define HALF_CLK 64
+#define QRTR_CLK 32
+
+#define MCEIL(num, den) ((uint8_t)((num + den - 1) / den))
+#define MMAX(a, b) ((a) > (b) ? (a) : (b))
+#define DEAD_LOOP() for (;;);
+
+#define MIN_RDQS_EYE 10 /* in PI Codes */
+#define MIN_VREF_EYE 10 /* in VREF Codes */
+/* how many RDQS codes to jump while margining */
+#define RDQS_STEP 1
+/* how many VREF codes to jump while margining */
+#define VREF_STEP 1
+/* offset into "vref_codes[]" for minimum allowed VREF setting */
+#define VREF_MIN 0x00
+/* offset into "vref_codes[]" for maximum allowed VREF setting */
+#define VREF_MAX 0x3F
+#define RDQS_MIN 0x00 /* minimum RDQS delay value */
+#define RDQS_MAX 0x3F /* maximum RDQS delay value */
+
+/* how many WDQ codes to jump while margining */
+#define WDQ_STEP 1
+
+enum {
+ B, /* BOTTOM VREF */
+ T /* TOP VREF */
+};
+
+enum {
+ L, /* LEFT RDQS */
+ R /* RIGHT RDQS */
+};
+
+/* Memory Options */
+
+/* enable STATIC timing settings for RCVN (BACKUP_MODE) */
+#undef BACKUP_RCVN
+/* enable STATIC timing settings for WDQS (BACKUP_MODE) */
+#undef BACKUP_WDQS
+/* enable STATIC timing settings for RDQS (BACKUP_MODE) */
+#undef BACKUP_RDQS
+/* enable STATIC timing settings for WDQ (BACKUP_MODE) */
+#undef BACKUP_WDQ
+/* enable *COMP overrides (BACKUP_MODE) */
+#undef BACKUP_COMPS
+/* enable the RD_TRAIN eye check */
+#undef RX_EYE_CHECK
+
+/* enable Host to Memory Clock Alignment */
+#define HMC_TEST
+/* enable multi-rank support via rank2rank sharing */
+#define R2R_SHARING
+/* disable signals not used in 16bit mode of DDRIO */
+#define FORCE_16BIT_DDRIO
+
+#define PLATFORM_ID 1
+
+void clear_self_refresh(struct mrc_params *mrc_params);
+void prog_ddr_timing_control(struct mrc_params *mrc_params);
+void prog_decode_before_jedec(struct mrc_params *mrc_params);
+void perform_ddr_reset(struct mrc_params *mrc_params);
+void ddrphy_init(struct mrc_params *mrc_params);
+void perform_jedec_init(struct mrc_params *mrc_params);
+void set_ddr_init_complete(struct mrc_params *mrc_params);
+void restore_timings(struct mrc_params *mrc_params);
+void default_timings(struct mrc_params *mrc_params);
+void rcvn_cal(struct mrc_params *mrc_params);
+void wr_level(struct mrc_params *mrc_params);
+void prog_page_ctrl(struct mrc_params *mrc_params);
+void rd_train(struct mrc_params *mrc_params);
+void wr_train(struct mrc_params *mrc_params);
+void store_timings(struct mrc_params *mrc_params);
+void enable_scrambling(struct mrc_params *mrc_params);
+void prog_ddr_control(struct mrc_params *mrc_params);
+void prog_dra_drb(struct mrc_params *mrc_params);
+void perform_wake(struct mrc_params *mrc_params);
+void change_refresh_period(struct mrc_params *mrc_params);
+void set_auto_refresh(struct mrc_params *mrc_params);
+void ecc_enable(struct mrc_params *mrc_params);
+void memory_test(struct mrc_params *mrc_params);
+void lock_registers(struct mrc_params *mrc_params);
+
+#endif /* _SMC_H_ */
diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
index f6b5201..397e599 100644
--- a/arch/x86/cpu/queensbay/Kconfig
+++ b/arch/x86/cpu/queensbay/Kconfig
@@ -11,44 +11,6 @@ config INTEL_QUEENSBAY
if INTEL_QUEENSBAY
-config HAVE_FSP
- bool "Add an Firmware Support Package binary"
- help
- Select this option to add an Firmware Support Package binary to
- the resulting U-Boot image. It is a binary blob which U-Boot uses
- to set up SDRAM and other chipset specific initialization.
-
- Note: Without this binary U-Boot will not be able to set up its
- SDRAM so will not boot.
-
-config FSP_FILE
- string "Firmware Support Package binary filename"
- depends on HAVE_FSP
- default "fsp.bin"
- help
- The filename of the file to use as Firmware Support Package binary
- in the board directory.
-
-config FSP_ADDR
- hex "Firmware Support Package binary location"
- depends on HAVE_FSP
- default 0xfffc0000
- help
- FSP is not Position Independent Code (PIC) and the whole FSP has to
- be rebased if it is placed at a location which is different from the
- perferred base address specified during the FSP build. Use Intel's
- Binary Configuration Tool (BCT) to do the rebase.
-
- The default base address of 0xfffc0000 indicates that the binary must
- be located at offset 0xc0000 from the beginning of a 1MB flash device.
-
-config FSP_TEMP_RAM_ADDR
- hex
- default 0x2000000
- help
- Stack top address which is used in FspInit after DRAM is ready and
- CAR is disabled.
-
config HAVE_CMC
bool "Add a Chipset Micro Code state machine binary"
help
diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
index 2c2ec01..d8761fd 100644
--- a/arch/x86/cpu/queensbay/Makefile
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -4,6 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o
-obj-y += fsp_configs.o fsp_support.o
+obj-y += fsp_configs.o
+obj-y += tnc.o topcliff.o
obj-$(CONFIG_PCI) += tnc_pci.o
diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c
index af28e45..78bc966 100644
--- a/arch/x86/cpu/queensbay/fsp_configs.c
+++ b/arch/x86/cpu/queensbay/fsp_configs.c
@@ -6,7 +6,7 @@
*/
#include <common.h>
-#include <asm/arch/fsp/fsp_support.h>
+#include <asm/fsp/fsp_support.h>
void update_fsp_upd(struct upd_region *fsp_upd)
{
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 8637cdc..30ab725 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -9,7 +9,7 @@
#include <asm/pci.h>
#include <asm/post.h>
#include <asm/arch/tnc.h>
-#include <asm/arch/fsp/fsp_support.h>
+#include <asm/fsp/fsp_support.h>
#include <asm/processor.h>
static void unprotect_spi_flash(void)
@@ -43,30 +43,3 @@ int arch_cpu_init(void)
return 0;
}
-
-int print_cpuinfo(void)
-{
- post_code(POST_CPU_INFO);
- return default_print_cpuinfo();
-}
-
-void reset_cpu(ulong addr)
-{
- /* cold reset */
- outb(0x06, PORT_RESET);
-}
-
-void board_final_cleanup(void)
-{
- u32 status;
-
- /* call into FspNotify */
- debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
- status = fsp_notify(NULL, INIT_PHASE_BOOT);
- if (status != FSP_SUCCESS)
- debug("fail, error code %x\n", status);
- else
- debug("OK\n");
-
- return;
-}
diff --git a/arch/x86/cpu/queensbay/tnc_pci.c b/arch/x86/cpu/queensbay/tnc_pci.c
index 39bff49..6c291f9 100644
--- a/arch/x86/cpu/queensbay/tnc_pci.c
+++ b/arch/x86/cpu/queensbay/tnc_pci.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <pci.h>
#include <asm/pci.h>
-#include <asm/arch/fsp/fsp_support.h>
+#include <asm/fsp/fsp_support.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -44,18 +44,3 @@ void board_pci_setup_hose(struct pci_controller *hose)
hose->region_count = 4;
}
-
-int board_pci_post_scan(struct pci_controller *hose)
-{
- u32 status;
-
- /* call into FspNotify */
- debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
- status = fsp_notify(NULL, INIT_PHASE_PCI);
- if (status != FSP_SUCCESS)
- debug("fail, error code %x\n", status);
- else
- debug("OK\n");
-
- return 0;
-}
diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c
index b01422a..9faf1b9 100644
--- a/arch/x86/cpu/queensbay/topcliff.c
+++ b/arch/x86/cpu/queensbay/topcliff.c
@@ -5,43 +5,16 @@
*/
#include <common.h>
-#include <errno.h>
-#include <malloc.h>
-#include <pci.h>
+#include <mmc.h>
#include <pci_ids.h>
-#include <sdhci.h>
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
- { }
};
int cpu_mmc_init(bd_t *bis)
{
- struct sdhci_host *mmc_host;
- pci_dev_t devbusfn;
- u32 iobase;
- int ret;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) {
- devbusfn = pci_find_devices(mmc_supported, i);
- if (devbusfn == -1)
- return -ENODEV;
-
- mmc_host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
- if (!mmc_host)
- return -ENOMEM;
-
- mmc_host->name = "Topcliff SDHCI";
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
- mmc_host->ioaddr = (void *)iobase;
- mmc_host->quirks = 0;
- ret = add_sdhci(mmc_host, 0, 0);
- if (ret)
- return ret;
- }
-
- return 0;
+ return pci_mmc_init("Topcliff SDHCI", mmc_supported,
+ ARRAY_SIZE(mmc_supported));
}
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 97ed884..7a66133 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -1,5 +1,7 @@
dtb-y += chromebook_link.dtb \
- crownbay.dtb
+ crownbay.dtb \
+ galileo.dtb \
+ minnowmax.dtb
targets += $(dtb-y)
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
new file mode 100644
index 0000000..66af64a
--- /dev/null
+++ b/arch/x86/dts/galileo.dts
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/mrc/quark.h>
+
+/include/ "skeleton.dtsi"
+
+/ {
+ model = "Intel Galileo";
+ compatible = "intel,galileo", "intel,quark";
+
+ config {
+ silent_console = <0>;
+ };
+
+ chosen {
+ stdout-path = &pciuart0;
+ };
+
+ mrc {
+ compatible = "intel,quark-mrc";
+ flags = <MRC_FLAG_SCRAMBLE_EN>;
+ dram-width = <DRAM_WIDTH_X8>;
+ dram-speed = <DRAM_FREQ_800>;
+ dram-type = <DRAM_TYPE_DDR3>;
+ rank-mask = <DRAM_RANK(0)>;
+ chan-mask = <DRAM_CHANNEL(0)>;
+ chan-width = <DRAM_CHANNEL_WIDTH_X16>;
+ addr-mode = <DRAM_ADDR_MODE0>;
+ refresh-rate = <DRAM_REFRESH_RATE_785US>;
+ sr-temp-range = <DRAM_SRT_RANGE_NORMAL>;
+ ron-value = <DRAM_RON_34OHM>;
+ rtt-nom-value = <DRAM_RTT_NOM_120OHM>;
+ rd-odt-value = <DRAM_RD_ODT_OFF>;
+ dram-density = <DRAM_DENSITY_1G>;
+ dram-cl = <6>;
+ dram-ras = <0x0000927c>;
+ dram-wtr = <0x00002710>;
+ dram-rrd = <0x00002710>;
+ dram-faw = <0x00009c40>;
+ };
+
+ pci {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ compatible = "intel,pci";
+ device_type = "pci";
+
+ pciuart0: uart@14,5 {
+ compatible = "pci8086,0936.00",
+ "pci8086,0936",
+ "pciclass,070002",
+ "pciclass,0700",
+ "x86-uart";
+ reg = <0x0000a500 0x0 0x0 0x0 0x0
+ 0x0200a510 0x0 0x0 0x0 0x0>;
+ reg-shift = <2>;
+ clock-frequency = <44236800>;
+ current-speed = <115200>;
+ };
+ };
+
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0 0x20>;
+ bank-name = "A";
+ };
+
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x20 0x20>;
+ bank-name = "B";
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich-spi";
+ spi-flash@0 {
+ #size-cells = <1>;
+ #address-cells = <1>;
+ reg = <0>;
+ compatible = "winbond,w25q64", "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ };
+ };
+
+};
diff --git a/arch/x86/dts/microcode/m0130673322.dtsi b/arch/x86/dts/microcode/m0130673322.dtsi
new file mode 100644
index 0000000..90bf2fb
--- /dev/null
+++ b/arch/x86/dts/microcode/m0130673322.dtsi
@@ -0,0 +1,3284 @@
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x322>;
+intel,date-code = <0x4012014>;
+intel,processor-signature = <0x30673>;
+intel,checksum = <0x17b0d914>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x22030000 0x14200104 0x73060300
+ 0x14d9b017 0x01000000 0x01000000 0xd0cb0000
+ 0x00cc0000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x22030000
+ 0x00000000 0x00000000 0x31031420 0x11320000
+ 0x01000000 0x73060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xf4320000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x0ae10178 0x7c98f9d1 0x41962d85 0x19391270
+ 0xcf3c0336 0xc1f13d6f 0xe46abaf6 0x3b65ca6b
+ 0xdb666815 0x5a17bfc4 0x4fca009d 0x099ae8b3
+ 0x198e2c7d 0x7c665bbf 0xc07a1a7a 0x7dbcee26
+ 0x867296b2 0xc885b6ce 0xe602baff 0x68544b14
+ 0xc928c400 0x3add156d 0x531946f9 0x92a03216
+ 0xda352322 0xd967ee1f 0x3c5170a7 0xf6de834e
+ 0x5a2ed8b3 0x9fb8f050 0x450de17f 0xfd5ef070
+ 0x4954575f 0xa3a071ab 0xb56e2afb 0xe2b48302
+ 0x6655a958 0x57c9a438 0x1b2f688a 0x09309bc4
+ 0x0be95612 0x529c1633 0xc48515d9 0x29eb78df
+ 0x9933409f 0xda58dea9 0x58c805fd 0xbc110f5a
+ 0x40780ec0 0x6ad59bb3 0xc7387fb8 0x591c1490
+ 0xf9335932 0x32130e0b 0xef4b3c96 0xacd903f2
+ 0x5b362539 0xe7f85529 0xcb17c41f 0xe7e440d8
+ 0xfaf7e925 0x969b76fb 0x5edab8c7 0xf00012e8
+ 0x121c2971 0xe5b18959 0xadfd07c0 0x1f09c9d7
+ 0x9781006a 0x39550073 0x6c438b6d 0x436f60bc
+ 0x11000000 0x8514b971 0x40df7b4a 0x6a6b7285
+ 0x7978ef59 0x319bddf5 0x04c68e5a 0xe1c28b10
+ 0x172f63dc 0x306fb95d 0x31d881e8 0x69f8e08d
+ 0x617a99e1 0x1ab6b574 0x2951fa5b 0xcc7e3e94
+ 0xff379d19 0x5c035dec 0xe28ed726 0x22b8a5ac
+ 0xd08b3ac5 0x45c03b9e 0xcea4083c 0xc26758aa
+ 0xbe7cf81e 0x43d898f3 0x5c45a635 0xc9cac095
+ 0xb89aea20 0x2c02b40e 0xe3a8b48d 0xeabfb60e
+ 0x776ed2a9 0x080ae6d5 0x7f64b1df 0x00e40ee6
+ 0x0f1c10f4 0x792e5423 0x787f5459 0x63a8b02c
+ 0x3fd6a255 0x049cae26 0x0949f5ff 0x9aebb236
+ 0xecc01775 0x91b57b84 0xe0e45ea3 0x5a8bf79e
+ 0x356a843a 0x2406795f 0x8aaae5d8 0x6a8c877c
+ 0xa8b2b8f4 0x04cf8f49 0x422d9e2c 0xf09f9896
+ 0xe9b92215 0x9c98fb44 0x88556b7f 0x519d6f4c
+ 0x9e8a016b 0xcb18d16c 0x419b4ee7 0x080b49c8
+ 0xc51b875e 0x46aabc9c 0x262d27eb 0x93ea189d
+ 0xdd0da69d 0x3e5b17e8 0xcc78509a 0x00b07e6e
+ 0x363d5a70 0x64572070 0x8a84abc4 0x1cb03838
+ 0x965fd76a 0x540aafc9 0x83a91654 0x1a722e67
+ 0x4bf98ce1 0x2b3c2ff9 0x972cebd4 0xf3a68395
+ 0x2613e422 0xf8d031d7 0xb1c79a0f 0xfd44f65b
+ 0xa7012a9b 0xd9a15a60 0xc311fc0c 0x6f52f878
+ 0x3d68381d 0xd2a035d7 0xb790c50e 0x9f1e5010
+ 0x41877064 0xa9d1e4ae 0xfe9abbd5 0x60c2c748
+ 0x8167e5ad 0x022dbfb3 0x75abe483 0x51c37170
+ 0x09b8590d 0xc1bb323d 0x2c7336b1 0xd4d0d49b
+ 0xc7f6152b 0x7919d596 0x1e1ff62e 0xc49604a0
+ 0x33857369 0xeaa3f382 0x98b8cd86 0x176e1bf3
+ 0x1a68867b 0x6af0a11c 0x69a82b25 0x48c72525
+ 0xa00aae2d 0xb09f67f4 0x1a99f83d 0x7266cca3
+ 0x8d03a7da 0x2e1d7c49 0x01ac68ae 0x93188770
+ 0x0609e769 0x982ed28d 0xe40999e0 0x8932ebab
+ 0x5637ad5a 0x2725e8ad 0x56d7caaf 0xc351faa2
+ 0x09dbd737 0x0d2f3bf0 0x0623330d 0xdd547489
+ 0xcca7e722 0xa9096d13 0x95b17818 0xc092cb81
+ 0x72c6eefc 0x1811c37e 0x78161497 0x8be0c4c6
+ 0xd63aeb19 0x91ab68df 0x8f2e5e4d 0xf4c74566
+ 0x7677a553 0x19698ac3 0xedca0620 0x77f32470
+ 0x031e011b 0x751f6696 0xb277d06e 0x3eae2742
+ 0x133e621a 0x38fa3172 0x9398cc1c 0xf42a507b
+ 0x4547d933 0x63a91eb0 0xf5bcf6a4 0x926ba056
+ 0x0adf5bce 0x140f53e4 0x7ff6bb5c 0x87dd79ba
+ 0xbba240ac 0x694f743d 0x709cdb20 0x5b4d4401
+ 0xc9693610 0x55f9f268 0x1142bc3f 0xf8fe3689
+ 0x04a93c4c 0x33dedc46 0xdc73c725 0x2f5ba264
+ 0x5b7a6a69 0x024b64f5 0x6e8bfa12 0x62bf2aa7
+ 0x520f5a07 0x3c7c4292 0xb7ad2613 0x1f78fc87
+ 0xd5284e4e 0x2c730f33 0x8861e947 0x8bacef7d
+ 0xbafa2608 0x14ed0b5b 0x3b9bfb02 0x24ced271
+ 0x002b2941 0x22d4431c 0x855f4248 0x5ec46e29
+ 0x6f1f42fb 0x5dd24fe0 0x290961f6 0xf392dbaf
+ 0xa1a8d9c2 0x61e18f4e 0xfda59a70 0x5498daa5
+ 0x5ae7ea6f 0xf058c635 0x6817ebee 0x8e30dc8b
+ 0x7c8d79be 0x5fb15b9b 0xeed64741 0xe2642a94
+ 0x680d7e6e 0x3cbad7aa 0x808c415f 0xe9323aa2
+ 0xaadf5b25 0xf60abf13 0xd5c47967 0xc248d0b3
+ 0x0f232cbd 0x84092449 0x5744384b 0x5e153ded
+ 0x8bb19817 0x34430271 0x917d2315 0x1fc790c7
+ 0xc21b5db6 0xec578b1f 0x903a286e 0xca0c59bc
+ 0x03e95c7a 0x8c659e99 0x7b09da0a 0xd61e7517
+ 0x90b1c519 0x8deac92c 0xf99c7bec 0xb6257d92
+ 0x3d61c16e 0xebd58be0 0xb470e655 0xa44bbf4f
+ 0xfebe5313 0x4662110a 0x5d42ccd9 0x140845ec
+ 0xc80329a9 0x915ca966 0x71e33828 0xe46c870a
+ 0x7da9a490 0x255544da 0xa20fb8df 0xf94062b3
+ 0xb2df5870 0xebf31e88 0x6e723e2f 0xe6ba9cf1
+ 0x7e7084c2 0x1782ac71 0x0a0b0127 0xe9234e38
+ 0x881356d6 0xb27a54b6 0x5594730e 0x9a14bd8f
+ 0x6dba7da9 0x1069e285 0x02a52798 0x61ea7d86
+ 0x665b2572 0x29d41eb5 0x1d211169 0x1218b345
+ 0xbfbd264c 0x5b8b0625 0xbbfdcf39 0x6768dfce
+ 0x0b5f10cb 0xe159414c 0x74356ed6 0x70077f49
+ 0x672107e8 0x11616856 0x824e6f2f 0x99614958
+ 0x5857305d 0x416a193f 0x010d266c 0xe5194f03
+ 0x152d6516 0xeb83872e 0x4923cc1f 0x1191d1ca
+ 0x23feb738 0x6817c1d7 0xe49129ed 0x4a53132a
+ 0xdb46b95b 0x3f970366 0x93f1a518 0xae8d72ae
+ 0xb689d915 0x0bdfda17 0x2ac7238d 0x1c4291e7
+ 0xc5b11085 0x3c51c1ba 0x9fd63edd 0xe464d740
+ 0xc17f2789 0x0adef6b9 0xf9aaf83e 0xfb2a9798
+ 0x7f16268b 0x4c8ca6c5 0x2b17be52 0x00c91157
+ 0xb69eb5db 0xe55ed94a 0xdf13b5a5 0xbb52d1e3
+ 0x651bb017 0xc7795724 0x0dfd4711 0x02d2d6e0
+ 0xc835e771 0x8ab5dd50 0x7caca109 0xd5c18d6e
+ 0xbef0e727 0xaff2dd07 0xf1062a32 0x26d14796
+ 0x97f6e36c 0xf845278e 0x185eb5b3 0xcde4e201
+ 0x13166ab7 0xcdcebcdc 0x143ef0c7 0x2349893f
+ 0x9dfcb70e 0x7ef72725 0x141c5b71 0x7da0f5d3
+ 0x76bebb67 0x28bc0a83 0xb67ecf0f 0xd60a1303
+ 0x9391b279 0x6ad41154 0x317896b0 0x1237efa6
+ 0x7b2a2e6c 0x3ad9a110 0xb44357d4 0xb32e39fe
+ 0x2358d28e 0x76e847d9 0x3e85db01 0x6c74e466
+ 0x9e4e6b32 0x13072a53 0x5972132e 0xd97cb04d
+ 0x55ee6a0b 0xc1434b92 0x772f6a1d 0x0f81f7a6
+ 0x072aa8f7 0x179da0e0 0x976bd78c 0x2e43c16b
+ 0x4f4a6b51 0x92d9c61b 0xa9c15fe4 0x3f8a527a
+ 0x3a232408 0x543d7957 0x21cbd682 0x896de3b0
+ 0xba6b3df6 0x2ec86e51 0x2be889e3 0xae764ff0
+ 0x3a2f0003 0x7a5f7949 0x577fb5ce 0xb5cbd1a6
+ 0xc910ffe2 0x7fd76712 0xfc1e93ff 0xbee7b15c
+ 0x5db2356d 0x9721a3fd 0x0d408aed 0x4df4c922
+ 0x45d5be91 0x6c79b1fc 0xf0bf73bd 0x3f6a73b6
+ 0xdcc1b51e 0x2049fe2d 0xf2b2ad4b 0xd0484d3a
+ 0x1f097d3f 0xced1bf3d 0x10f4416b 0x73cb307c
+ 0x4b4d94b4 0x2918ece0 0x0cfe69f3 0xb7e86cfb
+ 0xa6c373b4 0x0d862b62 0x1735cd72 0xef23c127
+ 0x09809c16 0x86cfb70b 0xe67c6903 0x743223a7
+ 0x13c7d27f 0xb70a58cc 0x82c57566 0x2ead3c65
+ 0xf9409863 0xf2b578ef 0x1622a34d 0x5ae8e861
+ 0xf4384016 0x443ff5f4 0x088b8510 0xd738d1c5
+ 0x577d624b 0x5adf3973 0x5f79add3 0xed7e7145
+ 0x29008fc0 0xd5b278cf 0x5b4c08c2 0xb063af5c
+ 0x67d41bd9 0x2d11424a 0x727924de 0x8903a86f
+ 0xb122d314 0xd9675c8b 0xc2eb1382 0x4c4185da
+ 0x257a0fe1 0xc3fd536b 0xadbfc223 0xc940dab4
+ 0x2e83d4b0 0xf1135ad4 0xfeb1cc1a 0x9178ae04
+ 0x996d72ba 0x07f6bf0f 0x6588f833 0x44f95205
+ 0xee4e6897 0xa9006735 0xa5f5502c 0xeb61aca6
+ 0xf2ceddb5 0x40ef9001 0xf862c3d7 0x73deaad3
+ 0x7b1d8b1d 0x467bcbcf 0x7f76f969 0x6c8e7f8c
+ 0xfb8e27c3 0x5075ce65 0x1c8628a8 0x7b6e3e32
+ 0x4885fc9f 0xa9fa768c 0x15426120 0x1df9d006
+ 0x31c52df4 0x1457f5c6 0xde5f2daa 0xfa250108
+ 0xbcf7e460 0x565d4679 0x82c94142 0xae76342a
+ 0x85aca7c7 0x8bc49e03 0x73f03da3 0x1e500b4c
+ 0x250288a2 0x25a39951 0x66087700 0x6317754b
+ 0x6ff62bdc 0xa519ad4f 0xa537b8ac 0xea6292ab
+ 0xb5d66b68 0x15997d1f 0x0fdbf04a 0xaa2b1a25
+ 0x74b72321 0xf8b1753a 0x33658d1e 0xb1cc5d96
+ 0x5b0da6af 0x48f24997 0xb031146e 0xfe98e8d1
+ 0x9bd75bf0 0x0ae088fe 0xb8fce721 0x964bc398
+ 0xe82daef6 0x393884b5 0xa814f792 0xb3667bde
+ 0x1d1cf32d 0xce862720 0x7b69e921 0xabd26f33
+ 0x61fad35f 0xd7144eeb 0x74016bce 0x1d56277b
+ 0x7f934eed 0xb1a3396a 0xd5090c7a 0x4ea94d12
+ 0x1455ac10 0x7c37294c 0x06c60a9a 0xa735ab29
+ 0xbffb880f 0x59e2cb48 0x54cca9d7 0xb569da05
+ 0x595e72ec 0x7c82f204 0x7690420d 0xe02fbb37
+ 0x4dbf4e68 0x221eda99 0x31868046 0xda435487
+ 0xb4c0dcc4 0x37610096 0x35569b02 0xefcd4ecf
+ 0x7b6917bf 0x45946a25 0x5d42a84a 0x8c3801b7
+ 0x5ac838fa 0x7a7f252d 0xbccf3cb5 0x99a54c4c
+ 0x39145831 0xfd5c1af3 0xcabb180c 0x8f0fe9dd
+ 0xabd42357 0x3b6d9aa9 0x0e87ede1 0x65ea46ae
+ 0xd89b618e 0x1e5cc772 0xfb43c9b4 0xdad3fdb2
+ 0x96be6600 0x4887696e 0x82a4e73a 0xb2ca2cf0
+ 0xc6840738 0x397d27a9 0xce971271 0x067e4de6
+ 0xb593f079 0x6a77de2f 0xf9a92497 0xdc3e94aa
+ 0x03239a80 0x7f38430a 0xf7f87908 0x682a8425
+ 0x2d491962 0xb5737b4b 0xa26434e5 0x238ced20
+ 0x1ed9fcbe 0x283a8f7b 0x18f33cf6 0x29f27cd5
+ 0xd95018aa 0x883dbd25 0xfb216723 0xe939d42c
+ 0xf4b1207d 0x54f5e102 0xbe2e46eb 0xb2ca8219
+ 0xab181ad4 0x3a7dc3e6 0xf3713256 0x53f081ab
+ 0xd630a7a3 0x07c40bc3 0x7a1fde0c 0xb368bab8
+ 0xc0baaad3 0xf070baac 0xe4ab7a4f 0x82a8cf5e
+ 0x9c3d7bb5 0xfe5f74a3 0x02548e86 0x2710ff5d
+ 0x1b42a8c4 0x34d4f5d8 0x8dfde8f2 0xf2949298
+ 0xe9d711bf 0x44d91e17 0x51ba8b32 0xbc3f60cc
+ 0xa0d6c440 0xf71959b4 0x3b5f0603 0x02465794
+ 0xff5d9b8a 0xd4a4abcf 0x8123626c 0x883ed4e4
+ 0x9eaeaa09 0x91c38865 0xa0aaeebf 0xc48983ab
+ 0x1df7a001 0x7519a65e 0x5ef3cd1d 0x8348225d
+ 0x0f318b0b 0xbab1d51b 0x15ba9b84 0xef8c57bf
+ 0x15d0a8c1 0x0b542fb4 0x1d51ccc8 0x6c297041
+ 0xf3bee946 0x6a8c3d64 0x6e16361d 0xed50ca69
+ 0x8c1f66ba 0xff7220e0 0x84a87cba 0x15d75922
+ 0x77546d82 0x7bd456e3 0x10166195 0x55604f1f
+ 0x894280d2 0x0ed406c4 0xc1b4058e 0x645252e5
+ 0x670ea74e 0xd5b07337 0x9944e2cf 0xf2ac2579
+ 0xd00c3ae8 0x2df3146d 0x4ee1c72a 0x3a3621cf
+ 0x8c099145 0xf5f530e6 0x210da136 0x7908cec6
+ 0xc6e47e22 0xe9bcbe4e 0x94cbcb12 0xb81f0792
+ 0x1111f81e 0x4df4ac93 0x335c69be 0x9e3546b9
+ 0x06c046b4 0x6f29a99c 0xbcd48ee7 0xeb011efe
+ 0x41e80474 0xcee30bf4 0xad4e2ae0 0x6929a359
+ 0xbdaa88e3 0x9e68a38e 0x16bbdac7 0x020d8d61
+ 0x7bab6738 0x559cddbd 0xa6ae3d0c 0xe032c355
+ 0xcb45a045 0x9f7680b2 0xc1cb73da 0x466052f7
+ 0x488cb929 0xd93f0307 0xb2c9d81c 0xe25fdcd9
+ 0xfe8b08c4 0xae6230bd 0x5238b335 0x3474b2a5
+ 0x480ce0b7 0xd9a2942f 0xe830fa5b 0x3efa774f
+ 0x84e53e93 0xf49e7d79 0x59897b26 0x75b1080f
+ 0xc2212b0f 0xe5fe56bd 0x4556e908 0x1bd0bb17
+ 0x2f159d20 0x866477e5 0x4e95a374 0xbdc9fd65
+ 0x2ff87073 0x5d7dceea 0x69ada0c7 0x89f16ad0
+ 0x97da55d8 0xe4457728 0x5ab7613e 0xf6bbe6ec
+ 0x56b83617 0x9119b521 0x4fabf948 0x2e1ab994
+ 0xd16363f0 0xaee14b3f 0x5461ea55 0x55d95d02
+ 0xf72c902c 0x1ede6c56 0x697006d9 0x4d15007f
+ 0x0c1cb5e5 0x55d3d5d5 0x1f18d76f 0x55c9f017
+ 0x3e1d3b5b 0x8f775636 0x97e6bf8f 0x360a9fb5
+ 0x1e080721 0xf9825356 0x30e900f3 0x55453bfe
+ 0xbd8f1df0 0x35b43ba8 0x45db013f 0x20484d34
+ 0x944ca654 0x79c2c151 0xd4e9b39b 0x1b2e79b6
+ 0x554314d6 0xce4ee44d 0xd0394232 0x9da4db20
+ 0xa70beed6 0x4ae4ed10 0x4c244770 0x4b91208c
+ 0x39a01e0b 0x5eea0a55 0x4b36ffbe 0x6fd18df2
+ 0x43fd13e3 0xa99302bc 0x63762b5d 0xd014d6b4
+ 0xbf0e53d2 0x0f5b5aa5 0x3c23f5b7 0x16335036
+ 0xe011bd10 0x66e596a3 0xf463e3ad 0x9670c0a3
+ 0x4004e177 0xbd2b3260 0x01967017 0x1159a682
+ 0x62931eb8 0xc581df9e 0x6710932f 0xfb2bb0b2
+ 0xb8a0339c 0xc66f0fff 0x333f5ee3 0xc06f8586
+ 0x7b9f47f1 0x9aaedaa3 0x6044562a 0x26c73565
+ 0x82c6e5b2 0x39d4eed0 0x83b7432e 0x0c4f0e4a
+ 0x4d9df788 0x989e7f41 0x61cacc3b 0xdc34efeb
+ 0x240b22a8 0x70a508b0 0x7554f517 0x7269f02b
+ 0xd27ffcf6 0x96a5879f 0x0650f7e4 0xdc1fc1ac
+ 0x80781334 0x04ab3381 0x8bad17c1 0x18311833
+ 0x65f06ee9 0xfaac30e1 0xe39b8b54 0x20b988ce
+ 0xa6a818f3 0x75ac753b 0x66f815a4 0x224d7121
+ 0x63dc6031 0xcfeed2c7 0x3ccd07d7 0x9df44157
+ 0xb9dcca97 0xcf5178f1 0x10e8fb28 0xa1faa527
+ 0x8851846e 0x01f56075 0x2dd4fff2 0x40786960
+ 0x41aa9e6c 0xf7c85573 0x64a36432 0x4449e726
+ 0x7aa7bb0d 0x08f596cc 0x248e1eb3 0x5c5567cb
+ 0x62ffd012 0x2d79ce59 0xf9ed4239 0xe98e107a
+ 0x4da25561 0xc6f83333 0x1ca0482d 0xcc3f3b69
+ 0xa9f48711 0x99139510 0xc5777d2b 0x9c80814d
+ 0xab47fbe4 0xf302d145 0x20aecccc 0x3be9e431
+ 0x7dc34793 0x4d38171c 0xaa34e505 0xc32e492b
+ 0x4f31bd0b 0xb7549889 0xdb3da9cf 0x084d0791
+ 0xa4c63c9f 0x62e770e9 0x862fdb93 0x52c45b9e
+ 0xf21019a5 0xdde6aa07 0xcb46386e 0x830693a8
+ 0x651510c8 0xf3af66a4 0x78775e07 0xc9f22414
+ 0x5769f089 0xac2ae873 0x044357d8 0x9fdc76f8
+ 0xea16ade5 0x144e9211 0x181ade72 0xba50ce80
+ 0x4573571a 0x5437c668 0x39c3b81d 0x013d766d
+ 0xc1754b48 0xa611fa3b 0x725eae72 0x04b02ca9
+ 0x186a2541 0xa2784e47 0x8b7601bb 0x7f9132e3
+ 0x3295d5b5 0x4b470dee 0xaf5ec559 0xc4c442d6
+ 0x5b07293d 0x9a68b079 0xc1408c0c 0xc2371025
+ 0x4af99e8c 0x332c416a 0xec04321b 0xb8493ffb
+ 0x51eab7de 0x26d7e9db 0x7880126e 0x439be5e3
+ 0x7e8910f0 0xa8ba727b 0x88cb04df 0x70750495
+ 0xc13413f6 0x684312db 0x0579d5b1 0x05fe44f7
+ 0x627e04f3 0xe85b47da 0xbf646f0b 0x2ddf4932
+ 0x1bcb6fc0 0x611de27d 0xb3ee1bed 0x247dad06
+ 0xa7107d34 0xba434b88 0x6eb90466 0x45a65871
+ 0xa9a67088 0x6af3b796 0xf5b73689 0xcab03ca4
+ 0xca1f25e6 0xd4b7c32b 0x5908c88d 0xac6c1fa3
+ 0x653184a5 0x062bc0bf 0x383de594 0x17064fc6
+ 0x0650dbad 0xaec15153 0xab0572ff 0xab8c6f3c
+ 0x37a93f91 0xbe51b8c5 0xabcd8573 0x05b3ad78
+ 0xad6c9ecc 0xf302c7ab 0x4b3b88f7 0x805a0107
+ 0xa5821ddd 0xc36f10ad 0x374b1056 0x79e69f8c
+ 0x8368b6cf 0xf69458a7 0x9fad691d 0xb937724e
+ 0xc542bfb1 0x37c0178d 0xc4707414 0xd6c7fa86
+ 0xb3933710 0x227800f4 0x6dca3e39 0xd88bdb91
+ 0x03755bda 0xa7f2d11d 0x4ab40803 0xf353e7ed
+ 0xf2464ee4 0x8e58cea4 0xd05807fd 0xd8d8da5f
+ 0x1a461333 0x5e84830d 0xb94ea4bc 0x5bf3506f
+ 0x76461ba7 0xabe88c54 0x124c2e39 0xc3b01867
+ 0xc6b0d4d1 0x9cc3c7be 0x8039ce38 0xfceb0e88
+ 0xa965c5ce 0x9ff3811a 0x1af1c60e 0xae9c5f9b
+ 0xee28bd50 0x202cbd2e 0x340a1312 0xa8f7115e
+ 0xb000cf3a 0x21ff4052 0xa555f08f 0x1bead4d7
+ 0xac14e135 0x449e208c 0x05ef8d94 0xb555a613
+ 0x9d65a902 0x3ad8cc2a 0x55170533 0x75782927
+ 0xefd4b5e5 0x6127ef1e 0x23fb5114 0x7ca3e1bc
+ 0xc08957ba 0x44c4e2cd 0xc0b97ef9 0xea99db5a
+ 0x53fdeb31 0x61721ee2 0xe41ef3c1 0x5f4788f5
+ 0xa8543eca 0x3f36d642 0xda6eccef 0x0341c756
+ 0xbfe7d2b9 0x66bb5cef 0xbfb43507 0xbd9c878e
+ 0x94f307bc 0x7cd56198 0xf98596ba 0x21e9c50b
+ 0xb9c9d725 0xf16211c2 0xe594b398 0x7e01aefc
+ 0x745e5ddb 0x00bae556 0xc317ed35 0x4269b4c6
+ 0x02f6b67d 0xccb4aa57 0x8a3fa0fa 0xcc660149
+ 0x57cf5e87 0x4ed03819 0x77286134 0x631cc0a5
+ 0x877fe8e0 0xa48856dc 0xe1c57e93 0xef04482a
+ 0x40cd9ac8 0xc7f43528 0x473306c8 0x01eb339e
+ 0x52612a88 0x65c3212f 0x7cc5f5e6 0xd3efbc2a
+ 0xf2537dbc 0xa9428ffd 0x76ff40f9 0x0ad4a8e6
+ 0x2020fbab 0xf8c5bbe4 0xb409e5a0 0x358d7b37
+ 0x08220bd3 0xd3707d96 0x5e2f5edc 0x638feed5
+ 0x045afa36 0x4f1604b4 0xd4dc85c7 0x37f97cef
+ 0xe1c8f5a6 0xd16fdbbc 0x986137fd 0x25b3e84c
+ 0x7f73be76 0xe25dbdcb 0x1f13d28a 0x7a31215b
+ 0x241967d2 0x2c5b4063 0xe8339988 0x13689262
+ 0x0b6d2b79 0x58773464 0xe822e560 0x77d6ba8e
+ 0x6ae6c07f 0x105e1e88 0x0045bc6d 0x88ad198e
+ 0xa350b9de 0xd5d0b3e6 0xc4e1cd14 0x47ca431a
+ 0x2ee94476 0xa2aae1f9 0xfa2042a7 0x37b0cf82
+ 0xb1aca28e 0x9a019883 0xbfb11afb 0x754ffff9
+ 0xf065a9b5 0x916e14f2 0x93fba80f 0x1dd82da0
+ 0xe41c950a 0x12b374bb 0x0f4d533f 0xbef539e2
+ 0x1eb5c86a 0x577dd484 0x98900e2f 0xcaec8695
+ 0x6a6ab336 0x135e9e68 0xc9b62a35 0xb8982b6c
+ 0x5bcdb533 0x389b1517 0xbb106e40 0xd402a301
+ 0x7446687b 0x35eda3ec 0xd44ceb2a 0xcfa4e441
+ 0x29664690 0x598a273e 0xf2a144b1 0x68f81403
+ 0xca53e666 0x064e69a4 0x87bb8ca8 0x58193c68
+ 0x9b34b17a 0xde2bffc7 0xf72594dc 0x388d3f3f
+ 0x638a1273 0x5ccf3567 0xcf1017a9 0xe616a6fd
+ 0x64cab73c 0xd209b022 0x6f08cd26 0xc30f57b1
+ 0xac2295b2 0x0c05b1c8 0xf7915ad8 0x9bcf836f
+ 0x56d8b57a 0xc8b65a2c 0x11868dd3 0xea4764f8
+ 0xa7bd30e8 0x8c895321 0xd276a894 0x86042daa
+ 0xaf6cd261 0x18cc4ea4 0x2c2185f6 0x2bf3ae70
+ 0xf3023c31 0x49f4b0e2 0x1e00afc3 0x2053b3c6
+ 0xb188c9cc 0x7437a27a 0x1b29925e 0xbc488906
+ 0x81cd9003 0x332fcf9b 0xeb20987a 0x831f912a
+ 0x857387da 0xaf1edccb 0xfe01d809 0x05351b4a
+ 0x31ec96ac 0x4f064e52 0x10ec8119 0x96c2d29f
+ 0xc6e1f3fe 0x15b0d45f 0xdca23bc6 0x7b672563
+ 0xa94fdc1b 0x7dd22f4f 0xd4d2260f 0xc9e055ff
+ 0x89e066cc 0x98200d25 0xcba82cf7 0xffb8475b
+ 0x26550a20 0xf5b4f84a 0x506cb84b 0x00d92997
+ 0x7a5c5535 0xe11194eb 0x1ff21f4b 0x725d2be5
+ 0xbe89242f 0x0b18afa7 0x6f5b1433 0x829bdaf9
+ 0x42db07b9 0x479493cb 0xabd2ead3 0xea6afa58
+ 0xf994c740 0x4cb77f7e 0xb946cbdc 0xfe558e82
+ 0xa2ed5c20 0x7012b99c 0x72a41e08 0x2058815b
+ 0x0528d06d 0xe6dbd7e1 0x3d1f6f9e 0xca78b63c
+ 0x91fa57a2 0xb6d524a7 0x1a61863d 0x89c25c5f
+ 0x16960596 0x6ebed63e 0xfcd617d1 0x0a927121
+ 0x887fdc75 0xec27c8de 0x8c91a821 0xd6bb116d
+ 0x51fe2c18 0x4af774d9 0x7aa13fdb 0xfc6ff59d
+ 0x27dd287b 0xe7e3151c 0x835552ea 0xe628aa1c
+ 0xe0edda2a 0x1957ade4 0x52336fae 0x9cecef28
+ 0x2be84cbf 0xa5959450 0x65299682 0x8151d4f8
+ 0x716a5209 0x0a8ca663 0x2187bc46 0x000767f5
+ 0xe7295b8d 0xa8bc7a6c 0x2b4d2f10 0xf251372f
+ 0x92ff27ff 0x9bfd83e8 0x8e2b593e 0x8915fd15
+ 0x1e44eed0 0x4a3a4679 0xce135f45 0xf996ec1b
+ 0xfd86c8ac 0x25b008fa 0x8973cf58 0x481512ae
+ 0xf2bc46f1 0x8b3a92bf 0xbf2a7b24 0xb19e88be
+ 0x1823f658 0xa8486c11 0x237771c0 0x6f5f0da2
+ 0xb05a42e3 0xb562583c 0xa13d37f7 0xe8eede16
+ 0xc5154af2 0xfdf7f9b9 0x0b907685 0x1f567e56
+ 0x19987b40 0xc82974ab 0xf02ae429 0x9c356634
+ 0xb85ba9e9 0xda2141b7 0xd44e331f 0x1dd722d3
+ 0x68fd2f4e 0x4e7f88a2 0xab7314b3 0x3dd05c4e
+ 0x1bb4093f 0xff73db9b 0xf917c6e0 0xae822501
+ 0x05cab9fe 0x67c91c76 0x1ebd2575 0x1ae193fd
+ 0x6f154ae6 0x13780ac7 0x6ff5bf0c 0x6b664594
+ 0x494a71d1 0x9bc35a0f 0xb34f175b 0x0069468c
+ 0x9b125042 0x7df22e49 0xf39cf8ed 0xbe020df1
+ 0xe206848b 0x8c428e75 0xc76c05d4 0x0089e2c4
+ 0x5bf9a75a 0x30677869 0x544797ed 0x68456dbd
+ 0x45b8f0aa 0xac5c82d1 0x05aefb75 0x6d5c28bf
+ 0x009ddb3b 0x551ff144 0xd19127ea 0xfc860071
+ 0x30c93457 0xa4c4b56a 0x6928a07c 0x9f63e6a7
+ 0x9fa2b174 0x7c1b2fa4 0x4a5a1f25 0x24acb022
+ 0x0c3c11f4 0xc7d4cec8 0x4484a031 0x6d3cc1c7
+ 0x2eb86733 0x8cd4f77d 0x7b551519 0x124b6805
+ 0x57385eef 0x3efd3da9 0xea300d5d 0xe64fc82d
+ 0x7d33386b 0x3933c4d3 0xe3cb61f8 0xc6fe8846
+ 0xbe0df669 0x8646e4cf 0x194a444a 0x404c81af
+ 0x9448791e 0x586f2132 0x3def508a 0xa3edebe5
+ 0x2f3b0b5c 0xc974f91f 0x400ec25b 0xf1513ffb
+ 0xc13b8859 0x32ac4d39 0xf8f334b2 0xab53ba5d
+ 0x9e196996 0xf14d8046 0x22fcb441 0xf27ac4c8
+ 0xbbdf5623 0x255df428 0xd95a2352 0x8d26f0dd
+ 0x60a301d1 0x4a2e3e49 0x4654b081 0xf775e35f
+ 0x592b5eba 0x6a3f9583 0x6ec3d395 0xc8ab02e8
+ 0xf343f806 0x62745498 0xb499dbf3 0xd427334a
+ 0xdf0b61e7 0xda67999e 0x14f9be12 0xf164898a
+ 0xd6347aa7 0x079a537e 0x294542e1 0x687b7b6b
+ 0x8478cffc 0xf335963f 0x6c1b9ac2 0x68ff2779
+ 0xe3d3f8a8 0x5453c548 0xd968189b 0x13ad95b4
+ 0xd71bee24 0x3939f36e 0xb19b3595 0x001961aa
+ 0x5f2f001a 0x77137eea 0x477698a0 0x1c07c440
+ 0x9606b6d3 0x6ce95229 0x25445629 0x5a935f13
+ 0x3e2154aa 0x6876442c 0xd9175c78 0xc94d2535
+ 0xf2070dd4 0xd4d1f50b 0xa04d18e5 0x3456cfa4
+ 0xc7610f62 0xb705a1a8 0xb8766e3e 0x225642de
+ 0x4be5b1b5 0x44d32453 0x80b8a9d4 0x7297d633
+ 0x09e8aa04 0x540929ec 0xbcc58c41 0x6dcf7b61
+ 0x6992928c 0xcd40ff22 0x13e4a724 0xd331d5f3
+ 0xa512aeb5 0x1c1c4ae8 0x5f0fe5d2 0x3d539538
+ 0x383c214c 0xd0a983e9 0x977e8682 0xf38a571d
+ 0xdb92de78 0x04ba543f 0xb531e880 0xfea55473
+ 0xd6d17b05 0xbdd676ed 0xfc7d4f68 0x8b5170ed
+ 0xa738734f 0x8a25fff2 0xb1b0239f 0x60545acb
+ 0xcfb00725 0x35f58585 0xcce4ed42 0x05da1c3f
+ 0x29428b1b 0x099680c9 0xb4608916 0xa9f177b7
+ 0x3b393c9d 0x92d19426 0x472dfe73 0x7b12de81
+ 0x557ec0f2 0x166fa28f 0xfb6855da 0x592d3e69
+ 0x373a1dba 0x9c76abae 0x13c7f717 0xbc53e796
+ 0xb2d39602 0xf1efa3b2 0x00046c93 0x1faf82fa
+ 0x55dec395 0x22a034c8 0x576bd5f2 0x97c36a45
+ 0x08a1a923 0x9ac2f22c 0xb029e4bf 0x6c4ca958
+ 0xed7276cb 0xa0924918 0x1894c9d8 0xdb993c42
+ 0xc31c6e18 0xbadc738b 0x57f95d64 0x4d766a25
+ 0xea41493b 0x60c19727 0xe7c63d8a 0xcbc52763
+ 0x7882b244 0xe2da61e5 0xd19111df 0x526d01d2
+ 0x4e7021db 0xa13fb9fb 0x23e082cd 0xb426b603
+ 0x9cac0cdc 0x44a94870 0xd0adbbe2 0x9b77a80b
+ 0xe1845f75 0xa1704da3 0x2d1c6207 0xba3ee883
+ 0x0c3089d8 0x0cba7fdb 0xcb069fb0 0x38738df4
+ 0x89971c2a 0xfbaeb7e6 0x459e1365 0x45fba877
+ 0x02046ea3 0xd9d0bdb7 0x83c74383 0xc248e9d5
+ 0xaae85a56 0x33092ec7 0x6bece02b 0x3b7af1d3
+ 0xc92b6e83 0xba032588 0x70e61198 0xa5eb1239
+ 0x4d9a6456 0x7d3fe964 0xdb3eb780 0x7e188648
+ 0x511a6402 0x48c4ade9 0xba7e9153 0x09490df7
+ 0x11b5ea7c 0x4e63145f 0x07ca7947 0xc337360a
+ 0x2b399632 0x5d1fef78 0x9b1e439e 0x8daa70b7
+ 0xf55a59bb 0xc3a8c84c 0x4d18eb22 0x74568737
+ 0xf0419b6a 0xbab459a5 0x0cb07a0a 0xeeb8e086
+ 0x0a9241a7 0x419c5ce5 0xec841275 0x3ec13615
+ 0x49e42b6f 0x2dae6c7d 0x3fc35088 0x1b92ff9e
+ 0x573b1cda 0x54381503 0x29a5b7b6 0x82994130
+ 0xffb93c4c 0xc0a66aa1 0x68889181 0x0826e555
+ 0xe81cdf31 0x740109a6 0xb8835558 0xaa5d9aac
+ 0x0d97ea3b 0x89f744c6 0x2b702162 0x992fe0ea
+ 0xab3a585a 0x3e7554db 0x9d97ebdc 0x9939bce8
+ 0x486a5f50 0x804ccd06 0xff2e15cc 0x67bf77cb
+ 0xf9beadd4 0x2da33477 0x18adbaf0 0xdb00dae4
+ 0xe727033c 0xd10ce1ac 0x4f8c4a29 0x281bf150
+ 0x764e1387 0x8c65a901 0x841521e3 0x31d9dfd7
+ 0x1e7ba122 0xe8fd6d3b 0x4bfe880b 0xd2c1c20f
+ 0x9a07169f 0xedbb94b8 0xe9cbcd9e 0x33cac378
+ 0xa42fef1e 0xf0e5ff32 0xa86b9038 0x7dbec0cd
+ 0x7ad1abe8 0x5e3e4e8f 0xc4dfe8cd 0x86630ba1
+ 0x02003c6f 0xbcb50d9c 0x65d874b1 0x01a09ddd
+ 0xc97d3d65 0x2d02bedf 0x6fc63309 0x214b421b
+ 0x72e0a28d 0xd9c8a577 0x1c8665a1 0xd33b4583
+ 0xfa004d9b 0x5c2470b7 0xc671fed3 0xe033617a
+ 0x5a86c333 0x13388e4e 0x3bccdcda 0xc62fd60b
+ 0xcae17379 0xf6d84d27 0xaaa52422 0x5771e380
+ 0xeb1feaf3 0x3c28e7fe 0xa0fded4c 0x5f63a3c7
+ 0x3b42ed09 0x1748d617 0xbc2d4fd6 0x3416fabc
+ 0xc1e60e41 0x48ffe41d 0x4ea5532b 0xba7dba76
+ 0x21378ac1 0x7425d0f3 0x426b3153 0xdc57d14a
+ 0x54997f9a 0xeda2a56a 0xfcec5ef5 0x6fd7acb3
+ 0xf2691009 0xc1a219e3 0x09a82589 0xc6e1792c
+ 0xb4674578 0x0aaf55d2 0x23c7e9dc 0x7607d612
+ 0x580fc695 0xd24b2629 0x0a8726a1 0x3544e0a2
+ 0xc1de7011 0x30982b80 0x9cf4f328 0x02b22d26
+ 0x78e33c10 0x2ce6bb5a 0x92280ed7 0x2ce5b007
+ 0x64552836 0xda4a7b51 0xa6122870 0x00b28bb1
+ 0xb98cda46 0x84cbe910 0xeccb62a8 0xe13c3645
+ 0x2f4494e4 0xed0da7b1 0xb8aa8a1a 0x1adcbc0a
+ 0xdab03e90 0x904d9041 0xaa8fe377 0x087cf59e
+ 0xa123b5aa 0x633c29c0 0x36d915d6 0x8f5cacbb
+ 0x8834d1b5 0xa2c12731 0xfab5176b 0xe1888d76
+ 0x4875b9d7 0x5747b32c 0x73fc6d36 0x202ffb90
+ 0x62900e06 0xa5f2a41f 0x497589c6 0x7ec701fd
+ 0x45801f09 0x1833e8fd 0x734acfc5 0x2f65bdb8
+ 0xe6add84d 0x4ad6dfaa 0xf59dd63b 0xb2150e00
+ 0xed32ddd6 0x370ce8d7 0x5fec9315 0xb8e6ba73
+ 0xccb15a6b 0x302a0084 0x9e49e2ce 0x7af3bc8b
+ 0x488e6ee3 0xcdbf0b31 0x762ce0d4 0xc50a111c
+ 0xd07d6e3e 0x18c391a2 0x1a7a559d 0x10b4b3bd
+ 0xd0703a3d 0x4e431eb9 0xf78edbe3 0x896604ba
+ 0xc0e8d4c9 0xd42f2292 0x5414ea6f 0x0ce7d429
+ 0xbb659e0d 0x46fa830f 0xdad39c12 0x0f65fa5b
+ 0xa002e598 0x5408cfcf 0xc1c3a5e0 0x28ca35fc
+ 0x52b2b588 0xb76e1f54 0xb6c355c7 0x08e3ba79
+ 0xfd89c1f8 0x6ebf03a9 0x51ebb756 0x729e1c5c
+ 0x1ed0cce2 0x29733f1c 0x42b76fcc 0xd94022b4
+ 0x3efc8ac9 0x3f23eae1 0xa0ccf230 0x9da59cf1
+ 0x5f6db360 0x922686e1 0xc9138d5d 0xda43fd20
+ 0xe0757988 0xa315c62f 0xe3642291 0xc45d9701
+ 0x2c394ee3 0xab92e7bf 0xf6037b8e 0x1f523243
+ 0xe91791d1 0x19961c4d 0x35d3b069 0x1596143c
+ 0x203bca40 0xd26d72c1 0x94c059c2 0xae0df468
+ 0x3b0909a4 0x34aa916f 0xe0c254e6 0xd0969c55
+ 0xa9b0b923 0x80a9dd5c 0xe79b8d8a 0x3599f269
+ 0x623c20dd 0x41e11b9c 0x40fcee5d 0x65dfa8f5
+ 0xbffa7357 0xa5b8f59e 0x2bb8191f 0x226a1b43
+ 0x910b6d4f 0x73837092 0xd666f5da 0x14fd4426
+ 0xd41a8547 0x6f4e928d 0x8096c2f2 0x525ba180
+ 0xc6a28d43 0x960b7cb0 0xb76dacbc 0x024de046
+ 0xc8e3c937 0x0217493b 0x1516dc22 0xe19e70d0
+ 0x655321c8 0xa46a9105 0x61ec2a61 0x1400405b
+ 0xcd0a758d 0xdc792982 0xbd994932 0x6565c8b2
+ 0x187be349 0x0afa44ad 0x714870fc 0xede1b8dc
+ 0x2c4ac6b5 0x7d9793ea 0xe0bc3c0d 0xaa56f23a
+ 0x7fd4e2ec 0x2131ad26 0x2cd34428 0x45e9dec0
+ 0xc15b692a 0xae73e713 0x37c5c3d4 0x70ff213c
+ 0x4d6322fe 0xa29a9b4a 0xca7d3c65 0x1024df74
+ 0x308f4a3f 0x4f48c7d9 0x0c71a17b 0x540441ed
+ 0xbc2f36a8 0x2592d7d4 0xbb643dd3 0xb8fb607b
+ 0x6b2b339b 0x9a40ecc7 0x59226bdc 0x42a5c04c
+ 0x6a1dc320 0x14e3c7c4 0x39cb912c 0xcf5eb477
+ 0xa3a43975 0x79f92cc3 0xe9d4cdfd 0x02dc8fb3
+ 0x240b6842 0xe9ff7bed 0x8f5269b3 0xc4f44baa
+ 0x1f1c74b8 0xb5c39051 0x291cce82 0xfc129a8b
+ 0x0fae02cf 0x31b4d4cc 0x1dfe9722 0x093cd430
+ 0x96c2a838 0x19b3a068 0xa7ead8c3 0xa2b3b92c
+ 0x2e1dc49f 0xe2f84217 0x670e73d3 0xd7c3710e
+ 0x94e4a7c9 0x33e063ab 0x35176206 0x910504bf
+ 0xb04b61d3 0xbed9c702 0x5d6c4cc3 0x63276a86
+ 0x0bfe5143 0x7ed925a1 0xc455934b 0x402a8b04
+ 0x01c03292 0x5de0933c 0xd932d260 0xb5b3b5ce
+ 0xde53664e 0xeaec4fc0 0x506030ac 0x6fbd8304
+ 0x0b0e4881 0x99c16b3a 0x6fc976ad 0xeae57df9
+ 0xc53a953c 0xca681bc7 0x905e49e1 0x405d42c5
+ 0xef39b878 0x57ded0df 0x56b98e32 0x392ce7d0
+ 0xaa7fbfb5 0x6ff550e8 0xf346ae82 0x2b25a8dc
+ 0x3ff980eb 0x302aff14 0x1a43c7ae 0x23f8ec16
+ 0xf774024b 0x1c4e163d 0x6b6f9408 0x0646b4e5
+ 0x2e55bfcb 0x14e3f7bf 0x86fec07a 0xda898470
+ 0xd99a274a 0x8630e98f 0x8c843f0e 0xa840c028
+ 0x950d7fb1 0xeca930fd 0xd281c9e3 0x29b3aed6
+ 0xc419314d 0xa6147b28 0xb504311a 0x91c07531
+ 0xe19ac720 0xfa8cfb5c 0xf8158bcd 0x42202a1d
+ 0xfff43b87 0xdc6fa0d9 0x8a599eeb 0xac3a8df2
+ 0x83ffa50f 0x346a8ff1 0x0947d1ca 0x318a8949
+ 0xe409dd30 0xf73ac9cd 0x9504c972 0xa2392b4c
+ 0x5594ac9f 0x7a45c3e8 0x181d42db 0x085e24a9
+ 0x6cb3e60b 0x3568d771 0xfa96b628 0x945817e8
+ 0xca9d28da 0xcd3a174b 0x7f84ca3d 0x90381d0e
+ 0x09a6f9d7 0x11396376 0x4d158586 0xcc451745
+ 0x9844225c 0xa45b8a9c 0x0c64efde 0x7429ee29
+ 0x308c39b5 0xa3454fb6 0xf949f709 0x09391206
+ 0x0168257e 0x94e10cb6 0x48e49996 0x92928443
+ 0x4a826036 0x9a777b3f 0xf77adfdf 0xc111b354
+ 0xa7ece533 0x050706ac 0x91ed3fd2 0xca15baf6
+ 0xd1714105 0xb564c842 0x886800cc 0xd57309e1
+ 0x38e4fa43 0xb74fe550 0x26f300bc 0x6349cbe6
+ 0x4bc132ae 0x310c1d40 0x3353100c 0x0a308892
+ 0xea6ab62d 0x0a438e7c 0xb000cf51 0xa21aadb3
+ 0xd3628343 0xee7f1a6f 0x3ee28d91 0xa846f25a
+ 0xc898e7c0 0x1198f67e 0x2401caf3 0x78d7acfc
+ 0xbc592220 0x1efd847f 0x1e3e935d 0xdb9025f6
+ 0x41ab6bb6 0x08a10f85 0x160dc5b4 0x4f0ed74e
+ 0x8c3db59d 0x34034397 0xe26017c3 0x03fe3b41
+ 0xc4480582 0x7c0c85de 0x4957c26d 0x9eb32143
+ 0x28676ce2 0xe3627f34 0x71e3afb1 0x7e978fbe
+ 0x3b3ee0f9 0xb5ae1bcf 0x474dc4cc 0x470e2114
+ 0x2490e60c 0xbb534e7c 0x7a8ad252 0x7cc08810
+ 0x9ea23718 0x04ecf4e1 0x732a9f10 0x62c69e22
+ 0x5a94fb4e 0xc1da497b 0x3ab3f2b9 0x09ff7310
+ 0xd7749df9 0x170471dd 0xaa551e91 0x2d605856
+ 0x66a13f75 0x0be4b8a2 0xe64a0c3f 0x288e5671
+ 0x5ee690c8 0x9e1c4b10 0x9f055568 0x8c6ff177
+ 0xa7229231 0x19e678db 0xd90be83f 0x0cf70d67
+ 0x47462463 0x327fdd91 0x51986170 0x3ad883b2
+ 0xa32fa5f2 0x82167691 0x74b6c59e 0x3eae0a3a
+ 0x569386dc 0x6d67fc33 0xa0943958 0x40b2939f
+ 0x334acedf 0x91b6a866 0x5debd880 0xa6f3712d
+ 0xbe8ca5c8 0x4b43fa68 0x72b677d7 0xa42b4d60
+ 0xc719163c 0xa469fbb9 0xb484def6 0x508ddfd1
+ 0x23bf14bd 0x857a13ad 0xf7a47090 0xe6816794
+ 0xbf6d3db3 0xd19fe091 0xb9421e39 0x35b184c2
+ 0xa5c94a6c 0x13b2b25c 0x5c7b45cf 0x648fdd47
+ 0x8832d949 0x0e2380c2 0x2f8e4f88 0xc01022aa
+ 0x4dec89bb 0x0a2c5bff 0xa97e58f8 0x304dddd1
+ 0x468828ac 0x603da881 0x646ddc90 0x1afa151b
+ 0x985bf8ad 0x6e3635d5 0x181268c6 0x420e1647
+ 0x913af569 0x14075a17 0x803aba15 0x2a2562b7
+ 0x2f0627db 0x52785b48 0x36ce7fc3 0x6057349e
+ 0x4affb11c 0x84e82be9 0xa0f60f66 0x1d176256
+ 0x9f1dba85 0x2852129f 0x4592540a 0xae083e7e
+ 0x744edf82 0x75a1e1b7 0x518fbebc 0xf1828d15
+ 0xfa1e31b7 0x88ebf51e 0x0a648385 0x956c002d
+ 0xc8b660cd 0xa82eeb58 0x0754bcf9 0xc4873df1
+ 0xf06c843b 0x7e5ac181 0x59661ea5 0xef2ae542
+ 0x0fea9691 0x9493a352 0xb401f705 0x85573914
+ 0x4e1eefc9 0x45e51c5f 0xd713688c 0x97efca3f
+ 0x292d0e73 0x8db44fd8 0x9f4479e0 0xc049ff9a
+ 0xfac5ddbb 0x4d610fdf 0xa9e01cdf 0x93b4dafd
+ 0x925004b9 0xb0796ea4 0x7e166ac1 0xd030c4ea
+ 0xa9f34c73 0x276cbadb 0xf3b9c282 0xa5bd6a69
+ 0x53df3f11 0xded46173 0x70bff329 0x0ddd0e77
+ 0x52e4a782 0xf01b024c 0xda90618a 0x34a2dd05
+ 0xc144d1fe 0xbaca12a5 0xbbd28cf1 0xc54d84f5
+ 0x0e7cb67b 0xe009e900 0x23657441 0x2214b4fe
+ 0x37693ee7 0x62e093d0 0xf79ca670 0xf1bc6cec
+ 0x1b91f787 0xc9d234c4 0x2a193a4c 0x8c2bfaf4
+ 0x75f4514b 0x03501d9a 0x5554de35 0x5ff35a26
+ 0x670ad976 0xbc8151eb 0x725fb971 0x5768e86f
+ 0x7fdcf5ad 0xe814f3ce 0xe8b9510a 0x55bf074a
+ 0x415fc288 0xa1a360c5 0xf5fef671 0x2d6253fd
+ 0x7fa09b81 0x2bb2e018 0x7159e648 0x10d5d59d
+ 0x462047cd 0x77583e64 0x47f1074c 0xc3c0e0d3
+ 0x023a55b5 0x4ad55057 0xe6d4b9d2 0x9cdd844f
+ 0x87eff8f4 0xd95c1e55 0x7499004e 0x2a43a598
+ 0x0c1472b4 0x33c90a5c 0xc4703c62 0xf293e2d9
+ 0xc3153c7e 0x6eeffef9 0x115e14ec 0x4ad27157
+ 0x888d87c3 0x33edc70f 0x7c38ce66 0x61c10a52
+ 0x5db41c48 0x8e309060 0x7b847b63 0x6b619cd1
+ 0x12855e03 0x52c3281e 0x704f969e 0xf9ab7862
+ 0xb143fc54 0x1ac23fd5 0x89dcd807 0x40a7ffc7
+ 0xc84245b8 0x0248d94d 0x29aca158 0x92d7b241
+ 0x751588ff 0xe8203587 0xc5bd7cdc 0x9de82608
+ 0xb075493c 0x5d43c228 0xff6a5345 0xa64cae5c
+ 0x4a1a9a26 0x08c60b16 0x9399ba46 0x3f535d1c
+ 0x3b9a6ab1 0xa446115c 0xa77bd99c 0x2431dc72
+ 0x729a637f 0x13f960d4 0x230d4e9f 0x0c608153
+ 0x9b9670fc 0x72494838 0x14832ade 0x65aba892
+ 0xd6434455 0x17697982 0x68b9bb34 0x1d700b3f
+ 0x6d0dda39 0x30e0d15e 0x87de41fa 0x9fc55b16
+ 0x0f5730d3 0xc3ea8127 0xeee64f5f 0xa02c5baf
+ 0x64e18d74 0x31de5660 0x5cf8d724 0x6c07ceca
+ 0x409e862a 0xd4ee7999 0x90c22c99 0x59cd395f
+ 0x09c36563 0x1993b09f 0xb0c4e064 0x8d6870a5
+ 0xe2e8e337 0xe8bef0cd 0x708d869e 0xdf808519
+ 0x6fa61e32 0x27161ea8 0x063c783c 0x2aa55c1a
+ 0xa6fcc8a3 0x918b284d 0xbb7870b9 0x788102c3
+ 0x3e49edfa 0x6c5eae4e 0x1c9fc361 0x554ca60b
+ 0xa08364d3 0xa7bd4442 0x204822a5 0x000b71a2
+ 0xd4dff005 0x43265901 0xbdb99200 0xc438e254
+ 0xa4982e58 0x02812101 0xfacbff1d 0xeec56aaa
+ 0xa5525774 0x21ada574 0xffe2f703 0x15d30ea7
+ 0x600696f9 0xc7ff3f59 0xdb57c175 0xa16f78df
+ 0x54a15622 0xe3742dcf 0x06d32994 0xd48463a2
+ 0x44c7c25a 0x41d6ded1 0x3b314de0 0x09992482
+ 0xbeb183c5 0xa0a65c27 0x842075b7 0x9b97e3c6
+ 0xd9545fc7 0x16d00629 0xd85640df 0xe79e694a
+ 0xe818d277 0x1c3d4623 0x23a9a926 0x83ac1b3d
+ 0x39e890c8 0xb3738b84 0x54b772ef 0x74518f0c
+ 0x7190098e 0xe26aff75 0xf6237011 0xbd3400fe
+ 0xda1b8fa6 0xdbf5566b 0x5155cef3 0xddbf1973
+ 0x34e2cb2e 0x535fd6b8 0xbfd337aa 0x6dd1fb0e
+ 0x52b04fbb 0xab5eca05 0xdb740dc1 0x104e6131
+ 0xbf4dcb75 0xaeff3524 0x4257c6b9 0xbf1c8cbb
+ 0x0a69ed82 0x90d991c7 0xea075cba 0x5e3c8330
+ 0x823116f8 0xba8f8a2d 0xcb98a1e9 0x8b2655c6
+ 0xd2f11133 0x3422f3ba 0x3e3a5742 0xdb9714fd
+ 0x91701f60 0xeba19983 0x8bf9f157 0xec87cd03
+ 0xb63260fa 0x207c345c 0x0c838d5a 0x736415ba
+ 0x9638ab07 0xb32c72bc 0x304d191b 0x7775adc8
+ 0x57ece662 0x0467bb66 0xb7cf80e8 0x4c635024
+ 0x176946c3 0x29cba0ae 0xf214b3f2 0x6e727126
+ 0x87b3747c 0x4c19b86b 0xfcc66fce 0x86681713
+ 0x636387f1 0x589e78f3 0x2e8abf1c 0x22c828f7
+ 0x99653c62 0x8e3bd31c 0x79187a73 0xc6d0e5e2
+ 0x8005a045 0x78a38c60 0xe1e8ff4b 0x1102d320
+ 0xaaf4ba7a 0x7223d041 0x45f73e81 0xaf7168af
+ 0x218ab3ae 0x8b1956a7 0x4db00173 0x482c3bc2
+ 0xd982b945 0x4bd7757d 0x0c5ef18e 0x74e66de3
+ 0xcf421ae1 0xf2ddc098 0xcec27e0c 0xe79e711c
+ 0x6f76e136 0xa8d72245 0x196390a6 0xbf56633d
+ 0xd1156298 0x5712cd8b 0xaed801ae 0xa345fab5
+ 0xfde1ba97 0x437a0b29 0xfc5628a4 0x93acf698
+ 0x83ce0bff 0x212f15c3 0x723ef016 0xe793bd50
+ 0x8bc51b39 0x42f17ad2 0x1df73878 0x19af3c24
+ 0xf55b6f93 0x506138d0 0x164c542a 0x8d4e1a26
+ 0x6c606f83 0x6fbebdf5 0x0e4ad76e 0xabd88e6b
+ 0x0e0d74e6 0xd139e08d 0x8b6cf03b 0x04a527b1
+ 0xe619c7a8 0xbf0d57f6 0xb38a5f5f 0x3f328013
+ 0x374c0a9d 0xff36910c 0xe950a494 0xfc477720
+ 0x37bd9390 0x4667497e 0x724eb66b 0x86bda8f7
+ 0x52efc959 0x32d5c2bd 0xddbb49ca 0x9c1eef2c
+ 0x508d8b81 0xc33d7001 0x360ae3c7 0x1197f6c2
+ 0x25efc933 0x4ad234a5 0x9e9c8658 0xc16d4aff
+ 0xbc428573 0x30e8b4c0 0x728c2c48 0xf34e1e70
+ 0xd62187c5 0xca869f89 0x34685a33 0x85d9b877
+ 0x9f77605f 0x93724d34 0x5fc8e8d1 0x70dd81a6
+ 0x643e543b 0xe4ad6c73 0xd6b4e5cd 0x387519c3
+ 0x719d8c6a 0xb2e0565f 0x02235c90 0x230c9b5e
+ 0xe76841a3 0xc2833be0 0x4dab4a72 0x0ae6c0a9
+ 0x0b5e12e2 0x4cda3610 0x954b6ff8 0x6d89a683
+ 0x3583e633 0xdc540da7 0xe2955deb 0x0f290d9d
+ 0xb01e57c4 0x977f4588 0x24b95f0c 0x45529128
+ 0x4528b5ee 0x27511439 0xd088d9bc 0x7c471853
+ 0xf03b8455 0xbda4a828 0xf49736df 0x50eb17c3
+ 0x2affe0e6 0x6727858c 0x6500b8f0 0x0483aa89
+ 0x0e1f6a41 0x72666733 0x85617ce8 0xa0c86838
+ 0xbccd2eed 0x06e8462d 0xc947bf5c 0x4d2d0a53
+ 0x02e70008 0x5039a596 0xb0118cc1 0x690ba325
+ 0x057ca95e 0x032cc1ba 0x3dae2c88 0x4eaa740e
+ 0xf07b09b5 0x6b2c2135 0xeca746b7 0x76019533
+ 0x4cf477b7 0x31848299 0x6b5c7df9 0xc0db5ff1
+ 0x7cd3e08d 0xe25fa562 0x260d66a4 0xda30cf2c
+ 0x14ab6c70 0x029a8dd5 0x7cd5fe2d 0x98ea5852
+ 0x555cf635 0x6c72ccbd 0x64120bef 0xd9e19613
+ 0xf26ac6e8 0xafea03a4 0xc14a11d7 0xb2f8420e
+ 0xe319634a 0x8a8fedd9 0x6ce0da89 0x74269f31
+ 0xd7e0d776 0x86ae9513 0x48bdea80 0xb2e4c581
+ 0xab25566e 0x9ccb71a5 0x7cedb09f 0xd2bdade6
+ 0x39c96ad5 0xe8ebbeec 0xac8a2e2a 0x915be930
+ 0x95e7c98b 0xd00e1d3b 0xdacd08ac 0xd9f515fd
+ 0x45cd3946 0x828a2cc3 0xfbe1bd9a 0xc5e1ebcd
+ 0xac69128c 0xcd6423ba 0xd8653b60 0x48f0614f
+ 0x0c1ebbbe 0x7ab89792 0x9a4b0097 0x2bda854d
+ 0xf17ab2c9 0xcde54eb9 0x4b53a030 0xe2399c4c
+ 0x19454a2f 0x473fe390 0x3a42c16c 0xc4c106a9
+ 0xf5d96e73 0x2ab4078c 0x5d20e7ba 0x47880aab
+ 0xff5e0d78 0xa374bdc2 0xc17109ea 0x39fce648
+ 0x00821cbe 0xc54a60ee 0xd753386e 0x7b28fc16
+ 0xb6309bbe 0xaefd0548 0x41168500 0xee5989a3
+ 0xe0177f09 0xc9fc9eb6 0x09a6e188 0x45776a0d
+ 0xf19a4830 0xc6774893 0x814b2e43 0xf8be5e3c
+ 0x22fa8237 0x75c98f46 0xb1c52edc 0x443d54f8
+ 0x6a1a886e 0xc7f33598 0xaa794644 0x685e5ca2
+ 0x97a735ba 0x3c1a391c 0x13f6f89a 0x660d7041
+ 0x333c3eef 0x40541bb9 0x5c3724d5 0xc348023e
+ 0x89791dd9 0xe72fba89 0x5af98b2c 0xb534fd29
+ 0x64d0e6b1 0xa578e77f 0xf311215e 0x634cc8cb
+ 0xbc534e51 0xdfce3ac7 0x90f88f51 0xb3f7dd48
+ 0x20b3e0ae 0xf4456e85 0xacb3925b 0x2eb3ce78
+ 0x37e61d82 0x724b9cbc 0x1462d9c1 0xd3f49dc4
+ 0xc1ffcc00 0x7c3e3f86 0x6f283bf8 0xf43671ab
+ 0x90cbfb35 0x55390829 0xc8fd0d31 0xc687c45d
+ 0x724ee656 0xfc1eab3c 0x3c8c2f04 0x3caa3af4
+ 0xbe220358 0x4d5b49a2 0x12cf4893 0x867173fb
+ 0xccd4b513 0x7c94a1bb 0x86c42c18 0x2b2070f3
+ 0xd2a70638 0x9d7c07e3 0xd02ed59e 0xd349488f
+ 0x1e85754d 0x333db889 0x0d0defdf 0xef282e45
+ 0xac3f6c29 0xd65a68d1 0x5d0914e4 0x395ec78a
+ 0xb056aa6b 0x4d98d059 0x7ae08f88 0x25c923d2
+ 0x79670f38 0xa881d62f 0x89cd5015 0xfb01da43
+ 0x5861244c 0x05e201eb 0x41d71eda 0xb2babb53
+ 0xc3845fb3 0x1f3b5c56 0xde6c10ac 0x73adb998
+ 0x714aac3f 0x4ad9fc65 0x3acdd014 0xeb319d58
+ 0x48842806 0x47ec1040 0xbfdf0052 0x3c478ec6
+ 0x83b43a0f 0x9e727e69 0x9f4d5925 0x9f45c13e
+ 0x30b8572b 0x26edf8cb 0x577e8b9d 0x9b98d7b3
+ 0xa44a9bbb 0x903e39eb 0x51226dbc 0x933a52b7
+ 0x14c6dc86 0xbc24db59 0x21054454 0x98fc5fa6
+ 0x2c9d8606 0x19178173 0xeda24205 0x90dfaca4
+ 0x21d562ad 0x7e3ad05e 0x2b3a40a4 0x46513f35
+ 0x0d13a598 0x8bf71ca2 0x6a36c430 0xe66f5587
+ 0xc9f13bd6 0xb6534a8b 0x8a3fbfd6 0x38cdfe6c
+ 0x1a1c89f8 0x6d782709 0x7919c451 0x6ccc96fa
+ 0x334029b2 0xa638356e 0x001e709f 0xb2132b06
+ 0x483f1933 0x189ab8f9 0x4ba0ec13 0x490aee0a
+ 0xda63f1fc 0x5679d38a 0xcf1e92f3 0xe7257fbe
+ 0xfeb733d7 0x0704860a 0x34ce2032 0x663b948f
+ 0x544cc928 0x8c23d5aa 0x67986469 0x93f9ac08
+ 0x4fa9a13f 0x9eb311d4 0x41a64161 0x29d1050a
+ 0xa5285c24 0xb53d03a6 0xc5de26f3 0x7876d1c5
+ 0xbdcdcb4b 0x79d1196c 0xe9890732 0x3e58a8c0
+ 0x874f03c7 0xfdfc9cac 0x5d57fa57 0xa3ef01df
+ 0x47bcff48 0x8beb1aae 0xf4bb4f9b 0xa5c83b64
+ 0xd69ab0ce 0x40f6691d 0x2eb8fb7d 0x22640f8d
+ 0xac1ba157 0x3687d705 0x7fac8727 0x4ad75cd8
+ 0x7016d2e9 0x25c36c08 0x7e4248ea 0x292bda19
+ 0x2acf589d 0x0ef7726d 0x835f9e62 0x3f9a1973
+ 0xbb6d2588 0x078ff6b4 0xaec22b5d 0xc740501e
+ 0xa2ab115a 0xea993e64 0xa0cc3ed1 0x934e4e0e
+ 0xd732b66d 0x5fd28c47 0xe4ccb898 0xc6a101c0
+ 0x78274bae 0x625df6a1 0xaf774052 0x3b7c08d2
+ 0x6180ac39 0x3e5aa769 0x6ec74578 0x6b5d27b9
+ 0x98e58a17 0x119dd7d4 0x39429c5a 0xe3d5b391
+ 0xbb8fddb8 0x5929801c 0x68cef71c 0xc36fa301
+ 0xeace4850 0x29f4f97d 0xa58bad79 0x2823998f
+ 0x0fe1352b 0x5960ded0 0x69308816 0x0d7e33c8
+ 0x2fb13bfa 0xff6a326f 0x69cb631a 0x839ea2a1
+ 0x528a8065 0x34cbebfa 0xd4432cc4 0xe13b550b
+ 0xe046569f 0x87b41fb1 0x7751107c 0x0ef6e60b
+ 0x856ffc50 0x11995683 0x77c2ebf1 0x4dec97f9
+ 0x3a28ebc0 0xb7bfa04a 0x40cdceb0 0xd559dd06
+ 0x61c2cd6a 0x8a906fa2 0xd55f43d6 0x7fb3ac35
+ 0x8cea4e81 0x1d359c2e 0xec447c57 0x3414f7f1
+ 0x18243b84 0xdf76849f 0xd753044a 0x7af2d51e
+ 0xaee26ecc 0xae6946b2 0x7478c675 0x88b22f49
+ 0x4de13fc9 0xd35c5956 0xeebb60b6 0xa15b1736
+ 0xa6e78d78 0xfd5e30b3 0xb4fade2d 0x964eb418
+ 0xe9035f51 0x22ab8242 0xfaa64053 0xdfe03834
+ 0x47beb588 0xb82a0887 0x11182e85 0x2f2f9a67
+ 0x4b612f11 0xae04077e 0x7f783c25 0x883a34e1
+ 0x32d43beb 0x6f0536f7 0x85c1537e 0xfb26199a
+ 0x45417e88 0x4af2c8cf 0x0a334486 0x2a3e6838
+ 0x31b8725b 0x63d64541 0x7e516a0e 0x7e42e766
+ 0x4cf30198 0x68abecff 0x7fb49c43 0x8f5b558b
+ 0x32b99abe 0x67337248 0x224c3411 0x4e7c41b7
+ 0xd3aee3a2 0xca19e704 0x2a430b7d 0xe9aee453
+ 0xf4ce492d 0x48fab2a9 0x42ec2076 0x0182cea5
+ 0x8a6373c7 0x18f41b5d 0xdd062fd5 0xb1db44a7
+ 0x285ad917 0xeaaabbd1 0x359b1b23 0xcc123c8e
+ 0x38b70cb9 0xb01ae722 0xa6e72010 0xb647530e
+ 0xf9651d41 0x366d6d0f 0x4b656a6d 0xd36637f0
+ 0x4b5ab8bf 0xc22fdb1e 0xc57c8250 0x799f4e60
+ 0xb55bd50b 0xe8a3432b 0xe752e4e0 0xd0c86482
+ 0x122991f1 0x5bec598e 0xbcb89abd 0x739f61d0
+ 0xd230ae2a 0xd0b99c05 0x2a998a6d 0xab715831
+ 0xb7dd1939 0x57db0ea7 0xed1f4952 0x49274caa
+ 0x35e319b0 0xed2c9cb3 0x601caa20 0xfe782688
+ 0x64b6d30b 0xcd5c325c 0x2c836157 0xa3552f79
+ 0x188094db 0xa42dd7e8 0xc09c2dda 0x02d98d8d
+ 0xed270d28 0xb0f38ada 0x5d7b4261 0xb41df8d8
+ 0x7341b6ae 0x024ce90a 0x0727ae4c 0xa8dd3a0d
+ 0x390f84d5 0x43f5bd12 0xd11fb61f 0x6fc330e1
+ 0x7f2d7fa6 0xf758a4e0 0xceb1f3c3 0x2f341836
+ 0x98fb470f 0x5bf68e58 0x1917a5b2 0x75f33be6
+ 0x16e22316 0x8aa810a0 0x1fc6c9b2 0x22179249
+ 0x3de701e9 0xec48d8b6 0xe85248c1 0x314ce9c1
+ 0xddeb2f47 0x0187909e 0xaa755f62 0xb2019460
+ 0xb2016a9c 0x91f789be 0xe5925997 0xe4864300
+ 0x1fd13759 0x0ad97c1d 0x7cf08c01 0x7eac2dd6
+ 0xcf61a7f3 0xaf9e108f 0x939a2fd9 0x0cb48e78
+ 0xe6ea1a8b 0x0b968273 0xef1c9310 0xf60e82b7
+ 0xe76e9bed 0xb8fa9668 0xf889765b 0x0e51eed6
+ 0x6b6566ea 0xa8f7e2c5 0x9d8c283a 0x879afdcf
+ 0x944873c5 0x58afcfa2 0x2e60600e 0x59666667
+ 0xc812b833 0x5842d0be 0xdbdc0829 0x786bcff9
+ 0x5857ba06 0x6968c729 0xf5447949 0xdb1ceeb0
+ 0xaf04d1f5 0x30614f7f 0x3e80fdc9 0x8a6e1ce0
+ 0xa267d7d5 0x8896143e 0x24e59072 0x68122e1d
+ 0x3ce24add 0xda677bdc 0x8c3f74ef 0xfa60e825
+ 0xf5c136cc 0x2cc5f249 0xa1c6b642 0x47a2305f
+ 0x52cadbc8 0x4d0c32f6 0x07f4d344 0x1f496d59
+ 0x5699b970 0xb8cbe564 0x707f7a2e 0x818bfd45
+ 0x800a8be0 0xd3de4f1f 0x62de0a3a 0x6b342869
+ 0x054daa7c 0xc72b945f 0x1612f126 0xdb4ad492
+ 0xa28c467b 0x78542799 0x61607353 0x39f1c142
+ 0xebf30ad6 0xabe076d0 0x5125cce4 0x5584149c
+ 0x65fa33f4 0x878a918f 0x8c7e5c37 0x334c4284
+ 0xbfd816e1 0x0f0f3460 0xd54519fd 0x03701ca9
+ 0x64885229 0x00e841d0 0x756a9472 0x0c16c5f6
+ 0x65560e81 0x129b6995 0x91c9dd1e 0xe9730dae
+ 0xce47f2a2 0xead8a0ee 0xcd58078f 0x7ca2df31
+ 0x0ebbf13d 0x3c74e061 0xb7f3980a 0x0d354b88
+ 0xfd8db90c 0xec6726d0 0x6bfce0f5 0xea98b7a0
+ 0xac5ddde2 0xb372a14c 0x47b09ed5 0x531bd5c3
+ 0xcfaf5a0a 0x51d6394f 0xe9efdfa8 0x37c79445
+ 0xb13ebf62 0x46715efb 0x31e6a0d7 0xfa48ab48
+ 0xc6552f2c 0x3067b978 0x0afa4ab7 0xc2c17055
+ 0x68dd427d 0xeac01e43 0xe90f12d8 0x6d97c3b1
+ 0xe0d339b0 0x2f3c84cd 0xca3eb3b1 0xbc0d86e1
+ 0x3566f657 0x083374b0 0x199c677f 0xa4a8a4d3
+ 0x224dd5a8 0x8f304abf 0xe1019878 0x9b290d4c
+ 0x5cef7341 0x59ff7e48 0xc91663ac 0xb0b1bede
+ 0xe9d8a9a5 0x8f34cb70 0x588d00d6 0xb7fe69b6
+ 0x29036caa 0xd21d7998 0x4edc3ee9 0xdbd94f37
+ 0x99c63455 0xac94efda 0x545635dc 0xb787b5e1
+ 0x8228666b 0xc7cd8170 0x4f1924a5 0x437884c1
+ 0xfa9236fb 0x1f0f949c 0xd1dc0597 0x56082a24
+ 0x04e51919 0x05dd926f 0x06d264ac 0xaa672d38
+ 0x5a3e396b 0xab48a57c 0x53489bd1 0xb36b3ba2
+ 0x55164db6 0x5b52c5f9 0x68aa8b7f 0x922ce829
+ 0x09e6e5bd 0xbc488a86 0xc0fb6dab 0x98e7754b
+ 0x4c9ad717 0xe3ae7045 0x0b498742 0x80a4384b
+ 0x0dfe0b99 0x70eab3b9 0xbee30b9f 0x4237ca85
+ 0xe67662b1 0xdae3dce5 0x47c84a45 0xf72febf2
+ 0xa58dfdc8 0x77ae88d4 0x038c76b7 0xae699990
+ 0xf5f10de7 0x65d4c59a 0x004a8b4b 0x67c788ec
+ 0x71c918d7 0x0ec70171 0x7041de53 0x43591e1c
+ 0x807242f8 0xa27fe146 0x0055fc7e 0x2f08467e
+ 0x5e04a068 0x54dab094 0x4f6e8c7a 0x20ac2825
+ 0x47949a42 0x9181486c 0x038e3132 0x7c1c51be
+ 0x97544f38 0xe2d27588 0x64889c21 0xdad9a1a9
+ 0xf1d328a4 0x7d47991f 0x2faa1b85 0x2430cab0
+ 0x0e849f91 0x213686c1 0xa2635f37 0xee7983ae
+ 0x87871273 0x6867d60f 0x04cb29ae 0x4e0ee4ee
+ 0xfbd2666a 0xfd7fe017 0x870b26ee 0xc42e104b
+ 0x78919117 0x19590e66 0x9e1a5039 0x9609471b
+ 0x4057fde6 0xc1f27544 0x30af8a8b 0x2ea267a6
+ 0xcfd886b6 0xe632b1f3 0x3f10bc50 0xf38a1bd8
+ 0x7ae1e284 0xe3876d7a 0xb4ce64f8 0xf74b4100
+ 0xa97686da 0x17ebacde 0x2ab068e8 0xcebd1076
+ 0xee8f81d8 0x0d394301 0x6f32c277 0xa926dc1c
+ 0xd5d2ea55 0xdc016b6b 0x6a96022f 0x0143e314
+ 0x23836eed 0xa3e18369 0xd2a155bd 0x8022cef6
+ 0x080b32a8 0x74ba38f0 0xd1ca2089 0x7c80219e
+ 0xf536af16 0xd7a337e3 0xa33600a6 0x39c7754d
+ 0x7d215312 0x1dd65026 0x8cb496c7 0x89dfd508
+ 0x9f945a1c 0x45caec32 0x020a1edc 0x5917baa3
+ 0x296b4b1a 0xcfaa2023 0x63e7a0e5 0xc48b19ae
+ 0x78d98b1e 0xc5d6be01 0xfe4ef13d 0xea6c9915
+ 0xb8190f09 0xf1793822 0x9acf1593 0xc7710fa0
+ 0x6b9a9f3d 0x0220ee2a 0x5d63043d 0x7292a0d5
+ 0xba9a1682 0x6f1e7c19 0xed7cc52e 0x6bb89645
+ 0x4370269c 0x9cb2c1a1 0xa7135973 0xfd1f3bbb
+ 0x50e6eb67 0xf2b9bd22 0xd891f6a7 0x4e0a7449
+ 0xc3dc0005 0x878e3333 0x3b4b8686 0xb215c65c
+ 0x5d8d24c0 0x8d203496 0xff20d243 0x0a6c1253
+ 0x2385c79f 0x52e8d6dc 0xda4bb8b7 0xfab66d97
+ 0x05a4a795 0x6876e856 0x9dabedc2 0x53550c20
+ 0xb3bba16e 0x853bf1cf 0xb85b906d 0x3f374468
+ 0x62e07c2c 0x6903a495 0xdb119586 0x07e91546
+ 0xa8388945 0x5a4e1dda 0xf054cdad 0x4b052880
+ 0xe9bbc9ec 0xe3555e11 0xd4d6479a 0xcad6a986
+ 0x31d9c4ae 0x510ff951 0xcb2f3164 0xbe283401
+ 0x0c390b9e 0x0c9cb487 0xe64e8ffe 0x611a63c0
+ 0xa1d700a5 0x3f864335 0xd1fdf32d 0x7a3aeb09
+ 0xabbc8c4d 0x4d703604 0x6532c8e7 0xccebc529
+ 0xf3c0f514 0x1567f19d 0x591abf6c 0x6c7fc459
+ 0x0858b061 0x092b2489 0x33c1a9cd 0xd6cc8e2e
+ 0x7c1ffeb3 0x3f45cf40 0x1fbcbd39 0xc6f0e628
+ 0xb88bab4d 0xc699de42 0xb62d850c 0xf71a6768
+ 0x2866b891 0x13093fcc 0xc730c502 0x2deaeff4
+ 0xb1bc8535 0x4303997b 0xb31ebd2f 0x82debe94
+ 0x843fa02d 0xba29f80d 0x03cb58c1 0xef1d2017
+ 0x0b5aadf0 0x6c5c3286 0xf084faeb 0x8b96a39b
+ 0x67cb38f8 0xf686ee62 0xbfdc22a1 0xee3f779c
+ 0x8ec73c8c 0xb448536d 0x67bb5d68 0x4369ea8d
+ 0x4b5367cd 0x2dbbc0be 0x8f5986e7 0x798c8392
+ 0xd3aac078 0x0081c0bd 0x94d9d70b 0x40bdeae8
+ 0x6b528e89 0xb0713745 0x063e535f 0x7d696463
+ 0x64f0666b 0x68a82e8c 0xc749dd19 0x875883cc
+ 0x3d35728d 0x4c0e5d8d 0x135f11b3 0xb649b37f
+ 0x8aead5cb 0xdfbd573e 0x563bf917 0xcdb75f08
+ 0x024b93fb 0xc6477eea 0xd88ce51d 0x95f7d77f
+ 0x0b561446 0x2fb6992c 0x4b48c8b1 0x940da60f
+ 0xf1be60b9 0x66d8641b 0x17a0ce15 0x49d22f40
+ 0xb8c494da 0x91930bb1 0xcd317991 0x4c5b4c23
+ 0xafda60eb 0x212c9f04 0xe4732f4e 0xf731ae57
+ 0x19165943 0x2d9288c3 0xc9c45dd3 0x2e05b148
+ 0x225a256a 0xc0249ea2 0xe96733d1 0x56a6803f
+ 0x20458549 0x28210fd6 0x13da740e 0xf0f0be41
+ 0x029c1fa9 0xb1daf3f7 0x1bf0c9aa 0x6f0d5221
+ 0x998b3616 0xa02212a3 0xe76b39b1 0xba0823e6
+ 0x146da6a4 0x858a3e0e 0x58e75b32 0x732f75ed
+ 0x8d88385e 0xe0e7ed55 0xc08ca86d 0x97e2ef67
+ 0xbb048208 0xd384c40b 0x8595bc69 0x65581977
+ 0x7b091c4c 0x60bfbbb5 0x23bcf38f 0x32e4621a
+ 0x7f790d95 0x72c3267c 0x34dd0c12 0x27438915
+ 0x5619893a 0x09d55159 0xdba7eef9 0x7413634f
+ 0xf4883417 0x59a2f28e 0x491f5779 0x0c138f9c
+ 0xc52a03de 0xcb1f92d0 0xb6cfcd21 0xbba95c83
+ 0x5302f12d 0xfc4c030f 0x18722dde 0x131cd3b1
+ 0xa19a1cdb 0x103d9216 0x403e45db 0x5cab72f3
+ 0x17e18f5c 0xbad9d0d9 0xd0d2e010 0x798106fc
+ 0x3abace6c 0x2c3131c6 0xf9529b61 0x27cfa158
+ 0x8890951f 0x87ccf0f3 0xa112b1e8 0x3e0eb033
+ 0xd7469e14 0xb6ccd2ca 0x3d238069 0xb32f057e
+ 0x8d2c939b 0x18d8aa3d 0xdb3cdb2b 0x861ba258
+ 0x46e7b170 0x4830d004 0xeea1b8b2 0x44e29b51
+ 0x0cdd8591 0xf93ad973 0x9383c44d 0x24e323be
+ 0xaaac87a1 0x84eb09d7 0x1f66b641 0x303f92b4
+ 0x81a63a86 0x516321e4 0xe33dfe2e 0x371a4624
+ 0x8f936425 0x596976ca 0x7b1947ef 0x83a9db29
+ 0xc5f337b0 0xe4d51b73 0xb35b56ce 0xb9cac5ba
+ 0x51705ecf 0x93e7d63f 0x5ee7d916 0x479f25b9
+ 0xe90bb406 0xfcd6e78d 0xbd8ed9b7 0xbca7c8b7
+ 0xdf95f4cb 0xc28baeba 0xb4534bbb 0x98b4f840
+ 0xf2218357 0x726e4f81 0x7591ebc4 0xc0523d15
+ 0x6bc82550 0xedfbcfa0 0x57280f50 0xbe7e420c
+ 0xd1152012 0xbf3ee0a2 0x11825710 0x18e728d1
+ 0xb8af00b5 0x2d1e940d 0x1c9ade8f 0x923ed269
+ 0xfd8c2580 0xf6477ff7 0x476a486e 0xd09c18dd
+ 0xaede7959 0x55fb68fc 0xe5692f7f 0x0bf4bd18
+ 0xf5fede2b 0x07bb05e7 0x1bb8ec54 0xa46bba84
+ 0x15051826 0x762ce6ae 0xa0246225 0x35c38cab
+ 0xbbd00a24 0x8205d3f4 0x4cb33ba4 0x293013fd
+ 0xd4f67965 0xe9c1951b 0xff108efa 0xb8e68197
+ 0x36d51e4c 0x2959f7f9 0xf2e4206f 0xc9973e09
+ 0xb61ce3fa 0x9543be90 0x63642668 0xcaaf02be
+ 0x7346a8eb 0x4111f5b5 0xa453cc2b 0xdb524b49
+ 0x4d528cfa 0x71e5fc4d 0x62cbbab2 0x8423f40b
+ 0x1a4db908 0x560c41c2 0x03982d88 0xa49c553a
+ 0x529f6acc 0x82dae294 0x6c5dbaa4 0xfb4ae1f2
+ 0x36e31345 0xb5cba88e 0x3704c623 0xe35245ea
+ 0xa412107c 0x35faf59c 0x08ceb649 0xbd67a6b9
+ 0xe37ddfdf 0x21303abc 0xb7de5e8e 0x88d9366f
+ 0x49bdd73c 0xeca0cd02 0xfe1e01eb 0x30a56c2d
+ 0x0cae1f5b 0xe77521c7 0x5ca59eaf 0x1288aa13
+ 0xc60bc96f 0xf7292504 0x2b037e4d 0xf34757b4
+ 0xedcdc492 0x39044092 0x5d710fbb 0xb8658511
+ 0xe23e4d57 0x595d4d3f 0xc0f80105 0xfe952879
+ 0xe81e2cb6 0x4f5a8fed 0x3bd0d700 0x211887d3
+ 0x6ea6e78a 0xe066640c 0x0d29c725 0xdabbeedd
+ 0xd2aca4d4 0x65c4a06a 0x6645b62f 0xb1de0cd7
+ 0x022e07ea 0xe9f9248b 0x0a2251da 0xdf34159c
+ 0x7894bab3 0x72e465eb 0x37448fca 0xbfbc1911
+ 0xa79e4938 0x48b83ec3 0xb9c6833f 0x19d24abb
+ 0xa434e777 0x77947277 0x2309612e 0x546a6ebb
+ 0x4c96447e 0xab918dce 0x5075ba1d 0x0aa55a7c
+ 0xadcce25b 0x837819d4 0x90d62a9d 0xf116ede5
+ 0xb056cc7f 0xb036353e 0xb7c1af8d 0x014c2cd1
+ 0x356f1593 0x008c2634 0xf7cd0cb0 0x02b0576c
+ 0x5364c954 0x5b40800b 0x60054bd7 0xef31bb60
+ 0x1a85370a 0x458c4348 0x435b8da2 0xd8df0e06
+ 0xde0cf1b8 0xd3c6171c 0x0bc14938 0xdc874128
+ 0x694f96cc 0x7b6687e0 0x9ca59f25 0x617aea60
+ 0x63ebcc8d 0x4bb44d00 0xce46d01c 0x4ab07a75
+ 0x64757638 0xe5903811 0x3562895b 0x760627ce
+ 0x8939cc7f 0x225db9b1 0x730062d9 0x7a5a7a15
+ 0x49678fc3 0x8620cb95 0x9439dee1 0x501f2cae
+ 0x3d08a33c 0x352de5c1 0xe7b24442 0x6ec76b79
+ 0xc575a1e8 0xb7024b20 0xc9dbb9f0 0xfe2303c0
+ 0xba3716ae 0x0cf37bdc 0x1c68a4a7 0x7ba0d609
+ 0x43003a93 0x17dd96c3 0xb884aa37 0x15b2d65f
+ 0xf6016133 0xd1fd7e04 0xc0a22822 0xf8c26247
+ 0x818c35fa 0x4e2b3605 0x83923c44 0x4ddd4397
+ 0x6faf6a11 0x50438703 0x67796dac 0x3443b780
+ 0x484f5bb9 0x8ead98ea 0x472ae543 0x94b0b17b
+ 0x1307833e 0xcb0e8286 0xb02e1ab1 0x36a89f9a
+ 0x372e82f0 0x84741303 0x111ad8ae 0xb1eeacb7
+ 0xd7d8ccd6 0x5f779f32 0x0d65184c 0x0a398467
+ 0xc07c099f 0x0704ffdc 0xa10b2f17 0x4c926dc9
+ 0xd80829ee 0x0821015a 0x512e6d0e 0x57b514dd
+ 0x509cdfd6 0x7e08ef24 0xf536c381 0x65483797
+ 0x439311fd 0xabed0f15 0x51a372c2 0xdd24c506
+ 0x839cdd63 0x0c21c8dd 0x513d9eb4 0x43c6a95e
+ 0x5d543848 0x64843a49 0x687bbf41 0x93d3bce3
+ 0xcf85eea3 0x5f3a6fc4 0xe7b45979 0x4c5848ce
+ 0x924188e3 0xbcbded12 0x0cc18c86 0xf3fd5723
+ 0x148dddb6 0x77cb388f 0x30afd47c 0xa306c453
+ 0x1da0b234 0x0f206f46 0xf25975bb 0x9c75d28f
+ 0xc60ad2fe 0x0067c5b0 0x497a1617 0x81d330e6
+ 0x2c5362ef 0x86a54b1e 0x80ad976e 0x0a86ed37
+ 0x1183b84e 0x2e2ce6e5 0x10b02598 0xd56fb0b7
+ 0xe3e0bca5 0x755d2333 0xe0be1b85 0x6c976f4a
+ 0x555a1465 0x8ab38399 0x51d4a5c8 0xec3d86e1
+ 0x2a85d0dd 0x0d31c16f 0x603f2d48 0x274d5d68
+ 0x292e7df9 0xe444f292 0x329946f1 0x132c3230
+ 0xb2c3ec05 0x88362f92 0x763dc2fa 0x7ee6f3ab
+ 0x7ca649e8 0xafee8a8b 0xeef65517 0x4789c1e3
+ 0x85bd4cb3 0xc87762d3 0xfa528ba7 0xa8e20dde
+ 0xd369c227 0x97e7f300 0x8256f4ce 0xdd5d2901
+ 0x1e37c55e 0xbb6e22fa 0xd9424392 0x8798d9a5
+ 0xc118ddb2 0xc3c91c40 0xe68ead77 0x8cf3655b
+ 0x4381e8fc 0xc94f312a 0x0b372483 0x70b620df
+ 0x53820813 0xb50d6f0c 0x64a53e9e 0x6f7f19f3
+ 0x6315f718 0x9aafff2e 0xf3b5a338 0xf1f3293c
+ 0x750ac26c 0xefe3ddf9 0xdc7369eb 0x024dafe0
+ 0xf56354fe 0xf0afaf86 0x7da1df00 0x7447ffa2
+ 0x4afd091f 0x24f39c82 0x3b3c8aa3 0xd90fc65d
+ 0x10d90b8a 0xf05d49fd 0x281320fe 0x75f62523
+ 0x0537b558 0xf52ae61c 0x77961852 0xbd0db386
+ 0xcb650cb6 0x7387ec69 0x320764c4 0xf5013b3f
+ 0x4f4239c8 0x4983a307 0xf510f405 0x7e355790
+ 0x4f8480d2 0x50dd84ca 0x66947bed 0x56efdfe0
+ 0xa593407d 0xdac216de 0x642a5f74 0x92bb9c2f
+ 0xf37abdd9 0xa24b1b64 0xca1f722c 0xaa5de969
+ 0xb6cb128a 0x697f787b 0x5bd74fb3 0x6de74e39
+ 0x2bc9a4aa 0x634455ab 0xa82aecc4 0x69647f0d
+ 0x4be06592 0x0c220c92 0xb08adf1f 0xd4571d2a
+ 0x0fadece6 0x297c124f 0x2830a499 0x3cc8363f
+ 0x44e34d3a 0x27b4d820 0x98be7f08 0x43417964
+ 0x8a3af8ac 0x89c42336 0xe55d19dd 0x00ee1f6e
+ 0x47d48658 0x55986f58 0x11ccb046 0xf3b97a07
+ 0x7ed364a3 0x106cfcd0 0xc1533857 0x3add2c15
+ 0x143852c7 0x55b38512 0x49a85ce8 0xd61a285d
+ 0x513bd0b9 0x21bde48e 0x4f231482 0x93aa6dde
+ 0x88035659 0xa83e3d2b 0x542513f8 0xe6e74a1c
+ 0x06092343 0xd37c8770 0x41553ead 0x09980a79
+ 0xb0e45895 0x80db4662 0xa6ce0960 0x965cfa7e
+ 0xfea96644 0x2a79157e 0xf020e115 0x61823e96
+ 0xf14f63d7 0xd753d1bd 0xd24a060d 0xfd2691b9
+ 0x18da9d0e 0x9f3c93c4 0x2730e0f2 0xb47e2afa
+ 0x920fda38 0xb5d89646 0xfb4728e5 0x7e78c2cb
+ 0xe46f812c 0xe51cc5c0 0x9d2957fc 0x548798a1
+ 0x240c2103 0xd650ff70 0x15c49ff6 0x99587c0a
+ 0x1bb4a5ca 0xd6db66e7 0xec2d3ac5 0x54164690
+ 0xe61bd6f8 0xc7a45cf8 0xee25f4f4 0xd1eb3ae7
+ 0x90085a1b 0x46a7a74b 0x829717f2 0x7f0769cd
+ 0x3ef72792 0x0c8617a7 0xa86becad 0x9dfe5329
+ 0x1a33c5a6 0x47d4c75b 0x2e10b45f 0xbd11762e
+ 0x15b72a9b 0x015c7f84 0x379c6bd2 0x27525345
+ 0xff3ac5a6 0xac916082 0xf5c24317 0xcc43fc64
+ 0x7f092c8d 0x931d9a0c 0x5a07f13e 0x3e1aa46b
+ 0x717a343f 0xd51221c4 0xc9422fcd 0x63f7af00
+ 0xde81a497 0x0322d271 0x972a4065 0xd75df029
+ 0x343a94a0 0x8c225f7d 0xb4abe87e 0x3cb8ba1b
+ 0x0babab14 0xf29704e7 0xd7134233 0x391f1a35
+ 0x33aca565 0xe6ae586b 0x0470a42c 0x570efddf
+ 0xfea26a3b 0xcee8d934 0x99ece522 0xb8af1375
+ 0xfe4dea4b 0xb96a32c2 0x3469ef9c 0x029fade7
+ 0xc4e77d55 0xc0449b95 0x63336e95 0x8d46c2e0
+ 0xd86d6e23 0xd365b781 0xe73ba0fe 0x10a354c5
+ 0x2d4511a0 0x077206cf 0x1c0dbd55 0x03396771
+ 0x8bce27af 0x70355b4b 0xc2275e58 0x3cfa4df5
+ 0xc8b3b9b8 0xf3fd510f 0x6b055de5 0xb3fef295
+ 0x42b95a20 0x5b5e75e7 0x0aaaa734 0x636d50ae
+ 0x8329283e 0x446e76f3 0x6adc320d 0x69a3e9df
+ 0x1da68939 0x6f071783 0x498dfee5 0xaece51ed
+ 0x4f8a72a8 0x4f2f2f65 0xdac3ba47 0xcbab0287
+ 0xf966cb4d 0xba27861f 0x54c79a21 0x44e2359a
+ 0x6e6b0e7f 0xceae84fb 0xb1530a59 0xecb8cd96
+ 0xff60633e 0xed748fe3 0xf1ab0d95 0x59997216
+ 0x6894cf41 0x948fc7bc 0xfb162ae5 0xeb9951a1
+ 0x99d0a7a3 0x9234587f 0xcd42615b 0x6f9ad0e8
+ 0xeb936dbe 0xbe72b62c 0x44ab5e9f 0xed736b08
+ 0xffaedca9 0x103b89bb 0x7896b40e 0x13a5a924
+ 0x56786357 0x02ab80ec 0x72ef47fd 0x81bf0fd7
+ 0x6661b300 0xaefadc79 0x9968433a 0x16f3718b
+ 0xe997a663 0xbbb55a49 0xf9b9a710 0x5727271f
+ 0x20e9bf55 0x358e3986 0xd1214e1f 0x4d42c46f
+ 0xa6bf8194 0x0c14a853 0x7b51aeb0 0x2f3d4de4
+ 0x3d6ffef6 0x4e94ba19 0x71a9c861 0xcade2398
+ 0xe0b3eb18 0xc9f028b0 0x7d29d2d0 0x372ec60a
+ 0x288a5bfd 0x4fc2bab3 0xc01dd045 0x8222e147
+ 0xe06676de 0x750bbfea 0x586ffb3d 0x2addb655
+ 0x767a6528 0x78abceec 0x1646cb38 0x21e26890
+ 0xd2a7937b 0x2463457c 0x764103fb 0xd540867f
+ 0x3566875f 0x007449ba 0xf9c0c523 0x2c51c86c
+ 0x437e1196 0x69fc0059 0xe0103408 0x19f23997
+ 0x23fdf335 0x7262eef4 0xcbe09390 0x583d0099
+ 0xe862084d 0x19fffbab 0xd2958a5a 0xcb165416
+ 0x32f3a97c 0xe502303a 0x16c4eda5 0xa1bcfd1d
+ 0xc4f35053 0xfd037f66 0xdeac9fee 0xbfb167b1
+ 0x39804db6 0x0bc2011d 0xf56bcd68 0x368cb345
+ 0x52fcb352 0xc306c535 0xf6bff09c 0xa429cbf7
+ 0x7e504be4 0xd2240214 0xf09ee41f 0xcbcf1fe4
+ 0x70f96a85 0x8394bf28 0x3cc19a50 0x49581f96
+ 0x58da5ae0 0x94708c48 0x63febeaa 0x4f656940
+ 0xa7fd6879 0x65524f66 0x5f7ee0df 0x11d487f9
+ 0xb494641e 0x7eb57255 0x5aa208c0 0x5666243a
+ 0x7d5970b5 0x71ea69a1 0x67059c9d 0xd3bde5bc
+ 0xe952b3fe 0x27bbf258 0x197504f4 0x5da6649d
+ 0xecddf4de 0x2d040d3d 0xbc9d3ab6 0xd8cdfb81
+ 0xb36ab627 0x7a548111 0xaaeefa4c 0x0e55b263
+ 0x4f9da6e6 0x26a137dd 0xdea03395 0x23b87267
+ 0x5b3cc98a 0x206de858 0x8d2e5cd2 0xb60f14e6
+ 0xfc10356f 0xeecae1d5 0x39783cbe 0x1a1c9a70
+ 0xb52c6f05 0x64adf10b 0xe12d9f3b 0xb3fb7cf1
+ 0x9051fdea 0xc16ed3bc 0x697199b0 0x08f34342
+ 0x2fb2bab6 0x729ed2b8 0x7691088b 0x82bc9cc1
+ 0xafce7ac3 0xe167bbb9 0x362e5d43 0x945510ec
+ 0xf32dce5e 0x4aec9a82 0xb80520d3 0xd8fcbe40
+ 0xf4877350 0xcfdd487e 0x8c9ff8b5 0x84ce70df
+ 0xffa6abd3 0xf9d2f273 0x342dbff8 0xa72580e3
+ 0x6ffccdc3 0x0c7ccc0f 0x6b24afd4 0x82b71a25
+ 0x1ba361f2 0x6ed8a67d 0x243ce000 0xd16b2e19
+ 0x86d3c3e6 0xca209063 0xaff0b983 0xf411f71f
+ 0x0f2ca724 0xa6fb0fb6 0xfa663640 0xe40fe20e
+ 0xf8e2a5cc 0x1a0e8862 0x11de13a4 0xc811e4a7
+ 0xfe6fa8e6 0xfefce644 0x8f7fcde9 0x94477c62
+ 0xec9b942f 0xfda6b166 0x91330c4d 0xd059d679
+ 0x96b0f7a1 0x22df13ce 0x3f36c3e9 0xc814e342
+ 0x7b7dce7c 0x1000640a 0x8cbe7a56 0x622fa655
+ 0x209d82d7 0x55668514 0x1534f8af 0xc2b7dc1f
+ 0xd89da0dc 0x3ddfe751 0x0532dfe4 0xd39c360c
+ 0x090f91d6 0x48587117 0x8ee383fe 0xf5ffdee4
+ 0xd8bca448 0xd26d6d82 0xe8adcc12 0x8b14b8c1
+ 0x7f872f36 0xb8cb0e16 0x76d60c06 0xf62ddbec
+ 0x3ec7c151 0xe418a789 0x920a3bf8 0xc5b62e09
+ 0x4974ea7e 0x0d8d7962 0x5bbb246a 0x37183d1c
+ 0xf25c63dd 0xb15730a5 0x903e3400 0xdab426eb
+ 0x0323289f 0x9bc16f49 0x2dfd02a1 0x3ab916a1
+ 0xcb6f770a 0x342021b2 0xf9f5c9c0 0x9c8d53a5
+ 0x3d53f39b 0x8e693c58 0xebecc732 0xbf30c538
+ 0x96648d11 0x60f62751 0x29745559 0x8e365fb3
+ 0x7d0b1179 0xea5abbb2 0xe45c4af0 0x53056b1d
+ 0xac7b03dd 0x7015c355 0xf17f8dfd 0xe1ace271
+ 0x9abacdc0 0x5ccedc75 0x478c717d 0xc01dfdad
+ 0x26fb551f 0x73e61f00 0x8bc0b111 0xb6855743
+ 0x28690dc2 0xf13b6766 0xc098861c 0x5c0ffa55
+ 0x271e7d0c 0x66b47b80 0x9921a158 0xd9c560d0
+ 0xb29b6ee7 0x50a9bc97 0xbec4d91e 0xdb2c1fcc
+ 0xdf215786 0x1541e380 0x59cae516 0x2342b2ee
+ 0x8088cd9b 0x7312579d 0xb17be14a 0xa1638c41
+ 0x805c6b18 0xb8a56151 0x56f0a6da 0x96b114d2
+ 0x0845ea7c 0x23e8f7eb 0x4e88e7ce 0x84640f2c
+ 0xacf8eebe 0x4039725a 0x49bf9982 0xfbcfcbd9
+ 0xfbbfb1c1 0x8041659b 0x5b8ee4f3 0x1b6d7a38
+ 0xeb634fc4 0xbf818ab6 0x8076c921 0xc50be762
+ 0x24c43f4b 0x3252acca 0xa7528630 0x9885b151
+ 0x9154b37f 0xfd9d3ab1 0x4f93c117 0x578fba44
+ 0xa56851fc 0x9d8083de 0x769f6fb4 0xd89fec27
+ 0x747c8071 0xe6b2b747 0x8196e2a8 0x3ed6c699
+ 0x8716f1df 0x65325e96 0xfbc715d5 0xb06f9171
+ 0x7aa9cbdd 0x84bda56b 0xdeab06ee 0x80432d8b
+ 0xd76f0a57 0xe0ed5f9a 0x70f991a2 0xf1a9e557
+ 0xcbecbcdd 0xcf0d91fc 0x6751fd67 0x590f206a
+ 0xa26d8130 0x1df02179 0x826303ce 0x6cd58190
+ 0x1219d005 0x4bb2f3b2 0x0dbd8193 0xd8d8f582
+ 0xa5867eed 0x2d6b8ec9 0x5f85ec18 0x7983775a
+ 0x214ca0c1 0x9af3febb 0x213d6568 0x2f8e8c43
+ 0x92add018 0x6e33e00f 0x6fa6834f 0xc3c2cbbc
+ 0x1c65c8c5 0x1827f812 0x868d3a09 0xdac83ade
+ 0x57623da5 0x5ff83257 0x0992e621 0x25cc9ca9
+ 0x10580130 0xff2ae8fe 0x40a58253 0xffdc24d5
+ 0x3e4dbe68 0x291b11f7 0xb3594b9a 0x570c7b6d
+ 0x38d31bd4 0x7155ba24 0x84d56490 0xd98842d5
+ 0xe037d2f6 0xdd2ba821 0xbeb861d5 0x0fda5758
+ 0x5921c665 0x98c7676d 0x8eee487b 0xac0f2411
+ 0xb332d321 0xa0816c65 0x76edde5c 0xab868b36
+ 0x3f8da4fd 0x516af4e7 0xabf748a8 0xbe7820fc
+ 0xbf763827 0xa03a3566 0x8a63e804 0xb4f8f901
+ 0x5d262ee9 0xaf905cf5 0x896d0c94 0x5f992cab
+ 0x81c2faf9 0xda3c686a 0xb01a06dc 0x45ef0c90
+ 0xf2ca525f 0x0e74fe18 0x36ecdb11 0x494125d2
+ 0x226b4aab 0x3e92ae29 0x5bb48774 0xc2c2ef90
+ 0xa9e77d5a 0x409db546 0x7728f003 0x72229503
+ 0x2e8febab 0x8322cfbc 0x5eaf74e9 0x621837f8
+ 0xc70668d1 0xb25c1325 0xd741c010 0xf52e3166
+ 0x71ef7a87 0x74cc93a4 0x7c25ecf4 0xb8b8e20f
+ 0x3658c239 0xbc58fba7 0xf13ec858 0x9271b2a1
+ 0x37084dd5 0x6fc92e82 0x44a6abe6 0x92b9238a
+ 0x9ad3a57e 0xd75daf92 0x8ea573d6 0x69ce1fb6
+ 0xe80df5f2 0xcc1c6ae7 0x6d565a77 0x6981ae63
+ 0x18af1922 0x6e8a7af8 0x10716aa0 0xa7da9970
+ 0x1abbc7cd 0x114f814a 0x4ebb0c07 0xc8fe6a69
+ 0x93d7bc2e 0x0a16181c 0x0379c950 0x4b2e8c18
+ 0x670b83f8 0x82a75eda 0x6eb772dd 0x42cfe197
+ 0xd91ec29c 0x29fb4812 0xab693ead 0xb2f25a1c
+ 0x0b9df6cf 0xb7a1aba2 0x1d7d90bf 0x7de14655
+ 0x649965f6 0x11fbe065 0xa54ac5a3 0x418bd3df
+ 0x4223c00f 0x7bfcf9ae 0xbd979739 0x6a2ee697
+ 0x54e7d9c8 0x73803bdb 0x06654716 0x72225136
+ 0xfaef3873 0x0b4b40dd 0xd3b98b57 0xc56cbab5
+ 0x32174c47 0x4d4d8c32 0xd6f1bf93 0xeefb6950
+ 0xb84ed0da 0x590723d4 0x2d006f09 0xc4bc139c
+ 0x55434982 0x8734189f 0x0e314a50 0x94340d09
+ 0x021c24a4 0x0b0f022d 0xa61f9025 0x71eb72b6
+ 0x744ccea1 0x2030b859 0x78203d74 0x0b8a8389
+ 0xd5211777 0x2609edfc 0x6134eede 0xec74584f
+ 0x0bdb2d06 0xb1768f76 0x56221895 0xfc49bdae
+ 0xbcc6e6ed 0xfeb19c0c 0x18652996 0xaa1a0164
+ 0x3ffdcb94 0x2dc1b090 0xb68bf220 0xc33b967d
+ 0xc907a1aa 0xa3968cb1 0xb3cc65e5 0x33e2b077
+ 0x2bb22904 0xe0fe8fc2 0x4affcc46 0x6b0f0bbc
+ 0x5d1bef41 0x2de11c7f 0xb0d864ee 0x6e96d8dd
+ 0x59c1c108 0xb2544572 0xab3400af 0x604aefcd
+ 0x81be22c3 0x6741e6ca 0x3a93dc1c 0x7b10e639
+ 0x0add7a92 0x39fc1df3 0x884f150b 0xd666a96d
+ 0x87da0c1a 0xf0f73c15 0xc0c00957 0x011ba61d
+ 0xa77e9463 0x96020e4e 0x92416e99 0x881e89c4
+ 0x46981327 0x3bc624f4 0x57f226f5 0xac340cd8
+ 0x3ce239b2 0xec6b33bc 0xa9123e11 0x70640b6b
+ 0xc30f59f0 0x411576fe 0x5ab12c3b 0x3cc20b85
+ 0x924b3be2 0xd1fc7a28 0xa4b0cf7a 0x88098404
+ 0xbbd331e3 0xff2b6047 0x2a1ab042 0xdf220849
+ 0xaf774ae3 0x5a8da79d 0xf18450c8 0x8e6e235f
+ 0x1dd3c039 0x1a867ae2 0xe4ccd1f4 0x50dd3f39
+ 0x8be186ba 0xc7e30fe2 0x17552d4d 0xffac16e4
+ 0x4094bbc4 0xc18a2513 0x650e707f 0x8ecdbba2
+ 0xf53e8e7d 0x047dbce2 0x7fc2a89f 0x07628f94
+ 0x2a8bfc67 0x0d738727 0x7b5c2fd4 0x2c89d27f
+ 0x47f37a64 0xc63debc9 0x15d6c414 0x242c300a
+ 0x645d95ab 0x29e1a49d 0xaf77fab1 0x643b4cd5
+ 0x3e0f63db 0x4f7cc43a 0x33d6797b 0x497d4332
+ 0x7160786f 0xe0c5b75d 0xfb08ecb2 0x26063065
+ 0x9835bf7c 0xf5465591 0x63155d2d 0x14babba1
+ 0x384a0879 0x460db3b1 0xcd37760b 0xad675a77
+ 0xf1dceded 0x69df690a 0x44c6f456 0x87d6a7a4
+ 0x4e0d6504 0xf967f55f 0xca9bb20d 0xd5eb41f6
+ 0xa9aa9b2a 0xa907387b 0x965b6f23 0xdcd47eb5
+ 0x43b5b1a0 0xec876728 0xee7339e8 0x10c5ee16
+ 0x1bd8c0bb 0x7235ae07 0x063e3564 0x388d0bb5
+ 0x80f9a9f6 0xaf96f714 0x6895c899 0x00ad21bd
+ 0xee67961b 0x873781a9 0x22cf435a 0xee90cf3e
+ 0xc9a4fadd 0x9bc1af4c 0x35c0e803 0x211ce71a
+ 0xb9af86bb 0x97828ab5 0x9dbd002a 0x1cc981c7
+ 0xefb36876 0xea739a75 0x5d5abcc1 0xd42260f2
+ 0x95083e0a 0x31fb0b51 0xf243ab8f 0x628b1913
+ 0xe74eb210 0x620b7d9f 0xc81666d2 0xc8fd1ce1
+ 0xf054bd9e 0x78ba7618 0xe1df4e38 0x5e381b3a
+ 0xcc68da1b 0xb3ce70ac 0x7ecda229 0xf8778140
+ 0xae823fa1 0x12af1708 0xc9373879 0x1e687d29
+ 0x96062069 0xf1bfde2b 0x999ff6c0 0x8cbeddf0
+ 0xc825a2bb 0x78106bbb 0x87a964fc 0xb358ec2f
+ 0x4d959300 0x0fe9706a 0xabb1d003 0x72b65294
+ 0x43816b1f 0x6c83b958 0x5549567c 0xb474aa55
+ 0x98851640 0x751a670f 0x25900026 0x2ab174e3
+ 0x1952c3dd 0x38b47c29 0x32c0af52 0x460c8fad
+ 0x85a1004e 0x8cbddcd7 0x66578310 0x4904dcfb
+ 0x04b7a746 0x00c91fb7 0xb1ab2edb 0xd0178ae2
+ 0xc4b8b57e 0x981d4753 0xfdd8939a 0xa8a05055
+ 0x47c8c30e 0x0fab4f6b 0x6ea54079 0x23dc4151
+ 0xc23e83aa 0x2ed2ce8a 0xff95b763 0x08df1d51
+ 0xd16d104e 0x0fa3ee3b 0xdcfe8541 0xa0622490
+ 0x085e5c0f 0xd9bc007b 0x24794e89 0xce341d16
+ 0xf090a98c 0x317150a2 0xcc036257 0x3296722d
+ 0x9c8d4f58 0x7ca5f53b 0xb0e4f9d4 0x1f178bbe
+ 0xc0dcde7c 0x18551596 0x0507b8e2 0x3c40a8ca
+ 0xc632f82b 0x5d1965f9 0x92a00465 0x13a8ca32
+ 0xc0b6756f 0x669d706c 0x58056b22 0xaa25fd37
+ 0x128b731c 0xb141ed31 0x0a8d3ddf 0x48b63bd1
+ 0xd24c5c4e 0x0ccd96b8 0x4b1ff726 0x309be62b
+ 0x26002e68 0x436f2bd0 0xacb62068 0xce098f50
+ 0x330e6160 0x434da66d 0xce14054a 0x0a877e41
+ 0x705eb2fb 0x8433fc7e 0xc1bd475b 0xb550de6d
+ 0xf4faf808 0x9f9b6ebe 0x0ff98ef7 0xace2766f
+ 0x01cc9606 0xd9654327 0x3544cf5b 0xbffbcd80
+ 0xb4a5948f 0xcded4d04 0x69ef5a24 0xf5ae46de
+ 0xe2139499 0x549f82bf 0x2cdfc6b7 0x5fdd2462
+ 0x63c68a37 0x8bce0d04 0x9c66ae30 0x9fd94951
+ 0x5774366d 0xd671675a 0x5582f253 0x436c5b6b
+ 0xfc151e77 0x1974df45 0x5ea9eac2 0x30689b8a
+ 0x9806681a 0xb74d3ec8 0x4f207181 0x668b4951
+ 0xb06514b2 0xeccffed1 0x16188ff2 0x5914d385
+ 0xed4b7023 0xfb0640e8 0x179adcda 0x6e806687
+ 0xb4f0ac07 0x35813615 0x143e66b4 0x1b012a50
+ 0x384f31c5 0x1500dbca 0x06e47afe 0xa8a17374
+ 0x9d0f5c57 0x4574db82 0x91b3680e 0x794683a7
+ 0x30c25d5d 0xf8748c08 0x2e601dfc 0x553152f7
+ 0xec5d489a 0x4bd37616 0xdc04dc7b 0xf0a35ba2
+ 0xb36975db 0xbfe6f98a 0x6d744996 0x5507380b
+ 0x4191e01a 0x0092c384 0xcf3a4388 0x6b0e89c7
+ 0xded7b820 0x1fbd6bba 0x3af210b1 0xfc4a608e
+ 0xa920eb22 0x22db2d65 0x7d6f0447 0x090f3679
+ 0xc4c759cd 0x9758aac6 0xa63251a9 0x47b7a974
+ 0x65421071 0xdca8495e 0x96f879d7 0x1d22ea6f
+ 0x46dd72ba 0xe0c59ccc 0x15737309 0x6d945f11
+ 0xbcb15c8a 0xb11ef0b9 0xe2072633 0xccbd61dc
+ 0xfcb51c44 0xd2315c65 0x3087a6f8 0x5609ee34
+ 0x94c7f951 0x0a057b31 0x6e6f2733 0x179facec
+ 0x36c005b9 0x60184919 0x50b3db1f 0x7a827d7f
+ 0x88755ecc 0x3fb0d6c3 0x63b150d4 0xe2ec3004
+ 0xe0ee30f1 0x118d7040 0x2f4689e7 0xa78be0be
+ 0x3c9bb853 0x75c326cc 0x84097407 0xb0107b5e
+ 0x83a56a91 0x14e60445 0x0fa72553 0x1385e6ce
+ 0x9b8bbdcd 0xe6aa6a9b 0xc2072ccc 0xee916592
+ 0xe44082e1 0x43dbf6d8 0x09f821fc 0xdc84b023
+ 0x0e6a518b 0x945fb180 0x185d0841 0x9ece88f8
+ 0x844558c2 0xed85f422 0xeceb983c 0x6db16826
+ 0x7612b243 0xee3bf226 0xb8eebb7b 0x22e16615
+ 0xc892bb7a 0xdc475a47 0xae390e93 0xe00baa1b
+ 0x725fca23 0xbb868b3a 0x17c62a69 0xeccd3731
+ 0xbe1a4223 0x05c8fd7e 0xa8354afa 0xbbb09f8c
+ 0x31a77e83 0x01f17a68 0x5f37c847 0xa0fdd7db
+ 0x9f8da870 0x98f02167 0x1e966884 0x00e19b81
+ 0x50c91add 0x6aba2a55 0x60be9575 0x3da40b37
+ 0xde13ff4d 0x5b7a79ec 0x4700ffd9 0xfee5ea61
+ 0xaf4d1d1e 0xfccb6f04 0xcf5076d2 0x48c4c98a
+ 0xd6a8915e 0xe4a58522 0x6bf3a6a9 0x4e7c2f15
+ 0xcd7e8d2f 0x843b56b1 0xa35f1a5d 0x1ca226dc
+ 0x917fb163 0x44751f0a 0xd96fa8aa 0x5028dccc
+ 0x7792dd96 0x2a9d749d 0xe48385fb 0xde111e91
+ 0x805e6581 0x3d9b9fad 0x5b750544 0x03785b71
+ 0x9b583214 0x80022658 0xcf1f3730 0xa1be7be7
+ 0x6c1e26f2 0x26de584b 0xb4fc8e35 0x072b520b
+ 0x55db3ac9 0x81e9d490 0x4b5ea53e 0xd5628e00
+ 0x71bfcac3 0x79956bbf 0x275fab80 0x2ad497ed
+ 0x423854b2 0x686451ad 0xfd59d64e 0x9f2049d7
+ 0xcb0f8f32 0x74d7545d 0x4f9c1df8 0x6fbf0afa
+ 0x7ef06915 0xc5117549 0xf20088b4 0x731a5ccf
+ 0xe78bbe74 0xdcb4996e 0x7062a6f1 0xa624b59a
+ 0x7b2d5e41 0xc1065234 0xa7c32078 0x367e7134
+ 0x86f55f58 0x3084ee83 0x0c599d1f 0x69380e2e
+ 0xe59482b3 0x7096432e 0x81124388 0x5be8d01e
+ 0xeb25ec24 0x8b47e9ad 0x432216fd 0xdc496dea
+ 0xcb05fefe 0xe76eb9ab 0x8ed568d2 0xfa963d68
+ 0x70ed6f4e 0xb2b88d58 0x15fc42bb 0xe992ec48
+ 0x359856b3 0x4a0f7741 0x3f0b6eca 0x07c16950
+ 0xcb9dae59 0x209570c2 0xf196555d 0xbf7c0a0f
+ 0x4a814210 0xf8f206c7 0x8bbb0763 0x360fa596
+ 0x13d46195 0x901170e8 0x6dc2e376 0xbfa00989
+ 0xd12cab90 0xf4f4699d 0xbc88b362 0x4827dbd5
+ 0x7cde5cf5 0xe45dff5e 0x2d661b05 0x8902d99e
+ 0x6c9f3584 0x0db3f864 0x1132773f 0x3e944120
+ 0x27058ae1 0xef978864 0xe58eff42 0x020ae503
+ 0x77fe075b 0x9c577e08 0x210b42b9 0xcb8160c0
+ 0x09f99f36 0x6a0b6bee 0x6f18b0ef 0x5452ee3f
+ 0x6c8c4a4d 0x480cb803 0x892f3973 0x066dbb63
+ 0xf7f845c8 0x7ceeee7e 0x7c26c5ce 0xec89119a
+ 0xc64bdc20 0xf46e4324 0xff34c833 0x555b4b3c
+ 0x23ff2701 0x52360759 0xf60acad8 0x241ccb7b
+ 0x29e14901 0xcc068e2b 0xedd0ee02 0xc33a425d
+ 0x7d889b28 0x88577f8d 0xaaf614b1 0x8e8c8eb5
+ 0x81a363f8 0x29f5bcc6 0x08aeb8e9 0x6f9ee222
+ 0x1c50045b 0x792c9434 0x62bc2601 0xc9289175
+ 0x374fc38c 0xbae91a86 0x3268e89b 0x5b008f10
+ 0x0ea6b759 0x9d43ce10 0x09b30dd2 0x643e2b94
+ 0x5c19bafb 0x29515176 0x56a81f95 0x60a80534
+ 0x22fa0a73 0x1259cf8d 0x323fa5b3 0x6322f1d0
+ 0x30581c47 0x50458048 0xd711c1b6 0x4a34236e
+ 0xb60a2e40 0x58df96c9 0x947b90d7 0xd327d664
+ 0x5fe528db 0xf6d9c575 0xb0a251b9 0xed961301
+ 0x2fee3cf9 0xb687e226 0x78fc46c2 0x29e9fef4
+ 0x84bff086 0xd0482ed1 0x018996f1 0xb8b9cdf8
+ 0x20885e68 0xa6f848e2 0xfddabc3e 0x5c9a7f67
+ 0x7cbc3e40 0x5197ebe2 0x41a15775 0x8024fd2a
+ 0x7864106f 0x7cfaf482 0x27798720 0x4956355f
+ 0x30f7195e 0x6ea09dd6 0x6f2b5f3c 0xf38df38e
+ 0xcae7e8cb 0xf8a80b0b 0xbeb227ba 0xbbfa2428
+ 0xbbba3ab6 0xbf83edbc 0x2cdcaa9b 0x2b0841a7
+ 0x79d52e5e 0x40260460 0xb27709be 0x07e3bf6a
+ 0xbdccc2b9 0x369d0069 0x9d745e50 0xff251486
+ 0x1e14957f 0xf7253467 0x9a31eeb9 0x4d77108a
+ 0x44fefc47 0xd02d4082 0x232e3fc1 0xce39396b
+ 0xd7a13714 0x2bd57e7e 0x00876803 0xee73377e
+ 0x78bb6240 0x2ae63c46 0x11e009d2 0x922539cd
+ 0xf3bef05a 0xf0c664c3 0x6e132a0b 0xb0c5bddd
+ 0x40c66494 0xd7d0d02a 0xa73110d0 0x4b409d78
+ 0x6f49bf88 0xcfc9d22e 0x4836da89 0xde5a80be
+ 0xb9c8bdb3 0xe99b2e9d 0xf1b05e68 0x8ab599fc
+ 0x22675035 0x3c8480c0 0xfa3cd457 0xba617098
+ 0x422eca1c 0x0cdc0d01 0x4779b95e 0xccfa0bfa
+ 0xd22674a4 0x76462be6 0x3015ab3b 0x7891688e
+ 0x1c83bf8b 0xaa55839a 0x7a71a83f 0xad451c1b
+ 0xf8b8bf06 0xc75a91be 0xcac50366 0x87e365ae
+ 0x9013ac11 0xe9cec5a5 0xef4d88f5 0x15c27162
+ 0x3dcaf8ae 0xe023891b 0x7b6f1706 0x2f1198e4
+ 0x048e34ba 0xb647b5e8 0xa1826caa 0xed3bc134
+ 0x43b14d28 0xf0c49b54 0x1a6362d4 0xc77fa378
+ 0x3bb12e79 0xcba4cd2b 0x620f2476 0x7729add6
+ 0x9876c439 0x5f7d8795 0x858f7ac8 0x68b94589
+ 0x1321d70b 0x5353a2fc 0x912a5ea4 0x390cf0f5
+ 0x37320473 0x51b3cacf 0xe45046d2 0x9188dcc5
+ 0xb3713b54 0xc9b936e3 0xe9f24574 0x5977a68c
+ 0xc23c56bd 0xcfc39ca9 0xc891b8d0 0x3683ef22
+ 0xc1ce304a 0x3ebf1ce1 0x52cd1cc0 0x3777d973
+ 0xde614072 0xf2efe226 0xbe1f9f9b 0x92a1896b
+ 0x9ca62763 0xcf5703be 0xa6d9c56a 0x185260d6
+ 0xd9e3b86f 0x5c47180b 0x71a7a219 0xe9974375
+ 0xf22af4d3 0xfbc92962 0x968c3fe4 0xc584b60e
+ 0xb9abee26 0x7e9737d8 0x5947da83 0x2f8ccad0
+ 0x7b4ee942 0x51ad62dc 0xf517400c 0xe2bf9e37
+ 0x63057e05 0xe1bfabf8 0xbf118805 0xc038de9c
+ 0x7aa57b7b 0x05584eff 0xb15ea286 0x26c6a6c0
+ 0x8e1392e8 0x7dbf22e1 0x3546f5bd 0x0f84ed9b
+ 0x0b01da4d 0x6dc47417 0xadc6f687 0x4160c045
+ 0xdc26765f 0x63b70c6e 0x8f177107 0x6a5f13cd
+ 0xb56fce56 0x5d1f5ed1 0x62f6a18e 0xf7235691
+ 0x222fa999 0xd48b1435 0xe597d406 0x8dacf828
+ 0x694ecd8c 0xe5283c02 0x60bcdcd3 0xfb9eb384
+ 0x9895492c 0xd38172dd 0xe7b6dff6 0x0ead5894
+ 0x910e2675 0x97d9ee09 0x270b2d8a 0xd03e25e0
+ 0x9e7bbb69 0x57ab1d31 0xf2e7a13d 0x9c8e5baf
+ 0x65fa03f4 0xc66bcbfc 0xf2d8bfe1 0x23059412
+ 0xa3ae7654 0x3a4734a3 0x32c0a8d3 0x4e007b8a
+ 0x5ce30660 0xbd10c57c 0x5365f540 0xeaed3002
+ 0xc377d84d 0x87097a59 0x929edec9 0x5878368b
+ 0xbd450478 0xc3fab275 0x128fdced 0xb706fbb5
+ 0x146f1d41 0x86782651 0xa530ca29 0xa3e1b6be
+ 0x25390048 0x572b4a05 0x8c9b4c90 0xb05428cd
+ 0x33fabab5 0xd16e513e 0x1d6cc812 0x4d80a6ed
+ 0xd6a5a07e 0xc0ee4c19 0x544b75d1 0x3f887360
+ 0xb2f46d1d 0x21609cbd 0xe340211d 0xe9202fb6
+ 0x3023b005 0x3341ead9 0x76c99537 0xc9d76547
+ 0xfb736c3f 0xf6385346 0x93fe2a05 0x92de6df5
+ 0x7793acd1 0x68249b3e 0xc22cae3b 0x668988e0
+ 0xdc1ea28c 0x7ef72b95 0x974098f9 0xb214701c
+ 0xc2de7d98 0xeb1d443e 0x5975f0ec 0x21d67037
+ 0x721e8e99 0x42105562 0x74b1e821 0x20193b2c
+ 0x743a7bb3 0x24643c9c 0x240b331c 0xdf125e2e
+ 0xcb4b0205 0x19edb174 0x505eb85c 0x1830bf22
+ 0x6bf7a528 0x86a7281d 0xfee3488d 0x6c26f4ab
+ 0xbff4ce7a 0xff7cfaf1 0x5df6fd66 0x523f0802
+ 0xf8a87595 0x463b5c19 0x72c564fd 0x2e4797d6
+ 0x1f04a1af 0x0be96baf 0x44552094 0x2a158f50
+ 0x83dac587 0xad4c881d 0x3178e710 0xe938d1be
+ 0xab715a65 0xc34b451e 0x1942832e 0x91557ecb
+ 0xdaf0606d 0xa64623d9 0x84e11fbb 0xa9c9d11b
+ 0x577a15b1 0xd49a2f23 0x6f204e0b 0x0a6e6a2f
+ 0xdaf13637 0x6b4ef557 0xdcaac9a3 0xad97c404
+ 0x8471691a 0x50ca3cf5 0xde57c446 0x70aa02f1
+ 0x84baa6de 0x0232bc79 0xa06427af 0xd2ce56be
+ 0x5da13949 0x254f5f4c 0x3fc3fd02 0x00b5f8eb
+ 0x54a0d4b8 0x5e3ec3b1 0xc6718376 0x5acce6d8
+ 0x614c56e0 0x89a6b00e 0x6cb4e087 0xa9822fe9
+ 0xdea290c6 0xb294582f 0x36f9640e 0x30d0afc4
+ 0xef7d75b9 0xfd9aae2d 0xd6729573 0xac442321
+ 0x158224fc 0xfd6632df 0x10cebf98 0xc3864dd8
+ 0x31577c58 0x49e71f9c 0xb96d876c 0xd867604e
+ 0xba74c3f0 0xad69752f 0x716eb51a 0x469d9d03
+ 0xda4b2e16 0x9e80a908 0x9bcb18e8 0x2f1c595a
+ 0xe823ecfa 0xdfd5badc 0xe460e9e0 0xae418438
+ 0x457811b4 0x29df713a 0xd90b0d29 0x415ba2de
+ 0xa0af6489 0x4922a50e 0x2efa0b0b 0x9394e4cc
+ 0x0ef8f59b 0x0f851711 0xa4670f3b 0xcc6bbfc6
+ 0xae194dfe 0x78e51752 0x4c65a2d2 0x1b0741cd
+ 0xc9f401c0 0x4a678062 0x290d2bc5 0x1a4279c4
+ 0xb5f9160f 0x40ef7c77 0xa9bcfba9 0xaec75f21
+ 0x53d6258e 0x8587eb74 0x0721d492 0x2c6a6e2d
+ 0x8e6cb70e 0xa6bee309 0x6faf5706 0xf8eee239
+ 0x52c85943 0x8c198893 0x3db37858 0x557fbf2e
+ 0x92f1a0e5 0xbd279594 0x46d65132 0x90a2c32a
+ 0xd11db660 0xc73b3922 0x9d1075ff 0xdb80a1cb
+ 0x54158743 0x39694d0a 0x4a0ddc7c 0x721f9dc9
+ 0x04b1b044 0x3bb40aed 0x6be7a88a 0x429a3b09
+ 0xa6e9dfa8 0xba412f0c 0x354f08d2 0xa4569516
+ 0x928cca34 0x398b1a99 0xb7e80291 0xe67d7b71
+ 0xa6582bf0 0x556ebb23 0xdc6d9f6a 0x11b3b753
+ 0xbdf31ae5 0xd3399560 0x6148cec8 0x5188689e
+ 0xde18f46b 0x3da414ad 0x4c44ad29 0x68582541
+ 0x75c8b1e6 0x7ba572de 0xd753ed20 0x4a9c4578
+ 0xf1c9159d 0xcfd9da31 0x46799fbe 0x1aee4426
+ 0xdcdf7b57 0x327db61b 0xa160ea1c 0x84a01fc2
+ 0xbe0aa020 0x5963688b 0x24f32751 0x885b4177
+ 0x26cde88c 0x39e6df90 0x1c7fee90 0x882a5c0c
+ 0x56f1f2e0 0x10bb9f52 0x4f0502aa 0xeae6e5b9
+ 0x65e7ee25 0x8ed230ac 0x38b5e02c 0x5f5311f7
+ 0x929491c0 0xdd923e62 0x5bc6166e 0xa3c89f4e
+ 0x5844fb12 0x0c40f02f 0xdda07582 0x8ca1b803
+ 0x9398b0d0 0x4dba17f9 0xb9879c85 0x26956147
+ 0x3c26a130 0x58cdc52b 0x21fa4801 0x9d965ce6
+ 0xb9942dac 0xd83d1518 0x36e630dc 0x50bb2822
+ 0xcd472a65 0x6feee2f4 0x4853b680 0x7f54945f
+ 0xa522c561 0x28134f6a 0x89b46cb2 0x4fe0047e
+ 0xad602b28 0x4942494f 0x1536ea37 0x40ea6278
+ 0x5020bdb1 0xad3c9f7e 0x1356d0ce 0x411700c8
+ 0x1ba61954 0x65dece8c 0xb788efb9 0x26efcd5e
+ 0x9833fa21 0xea0052b8 0x119a994f 0xa71b168b
+ 0x164a96e0 0x0bd1b4e9 0xaae1e562 0xb550f48c
+ 0x3a3b55e1 0x4d921246 0xcb28af65 0xdd2388ff
+ 0xa63988c3 0x7dfa5a8b 0xc7c44102 0xc75e9f3a
+ 0x5e4305db 0xacb34d1c 0x9b50976b 0xad3f6379
+ 0x6cd20ee3 0xba806f21 0xcd0fcf4a 0x18a55973
+ 0xbafe5266 0x03ee9b8c 0xa35fbfde 0x7f2eb71b
+ 0x23d9aa11 0x0e183c35 0xefb0ae3e 0xc6093786
+ 0x5b380af5 0x64838229 0x3bd69926 0xe9758e1d
+ 0xde439e4a 0x0cbc4bdd 0xda5858e8 0xbe8afc07
+ 0x676379e1 0xccc4c628 0x763e3b38 0xb4823c67
+ 0x9f4aa538 0xd8d33f50 0x41291e48 0xaed28ade
+ 0x6c72eea8 0xa751f4e8 0x3a75dba2 0x5073e3bd
+ 0xf10b4756 0xdf46ab98 0x9ad689f1 0xc2ba74a4
+ 0xf2ce9419 0x4cf9732e 0x75cf58ca 0x249e3c52
+ 0x95d10a93 0x51120008 0x7438d467 0x0a5e7f2d
+ 0xb7a44e46 0xe31e5dee 0x26e2ed14 0x8f16a7d2
+ 0xfcda431c 0xab32ada3 0x3a863c94 0x5fe91346
+ 0x2a92c590 0xb8c17e6b 0xcaf753fe 0x50283647
+ 0x533c8f3c 0x1233e1c1 0x7a5b2eb0 0x79b4ba22
+ 0x3164670c 0x201c500d 0xafeac6bf 0x2fbb0884
+ 0x915de3b0 0xbf733b7f 0xc45d1a42 0xa3b86d4a
+ 0x333ef605 0x6348522a 0xd28d1d19 0xa2cad790
+ 0xf8ad449c 0x05aacdcf 0x64500018 0xb1d8cb18
+ 0x9e4a2ecc 0x091282c7 0xfd64bcf8 0xe1e7c24d
+ 0xfcd0f386 0x0c9faa0e 0xa82f265c 0x83cafc3e
+ 0xcad43563 0xc110837c 0x2a2da74f 0xbd98e00b
+ 0x5c24553d 0x41c75caa 0xe75cb110 0xa004b946
+ 0xd4daa77c 0x88d07273 0x0c75c7eb 0xaf05657a
+ 0xbe1f8336 0x122a7acc 0xe0e5c29d 0xd5896217
+ 0xfb2f909a 0xa74b6458 0xb33a1a38 0x815f7832
+ 0x9584b271 0x9a3bb26e 0x39aa6d36 0x2fba41db
+ 0x133797be 0x9993699e 0xdb50268d 0xccd54ff0
+ 0xb7a33011 0x71db612b 0xef9a4429 0x7217f1d0
+ 0x0ee420ba 0x1f7eb025 0x26572853 0x72712e17
+ 0x5bd7be37 0x74b2288e 0x3ffd1f1f 0xed566562
+ 0x744f4159 0xdbedb36b 0x69e25131 0x604ccb70
+ 0x50d83542 0xe4704ddb 0xdc5144aa 0x33467434
+ 0x1c7c4f2b 0xac774e8e 0xce9c4d1b 0xa0e3c7f7
+ 0xffbecc1c 0xa1c25fb2 0x0e9f6039 0xbe9ed6d0
+ 0xf958fb6a 0xaec3fba8 0x2944e767 0x77dc717e
+ 0x06e9fe1d 0xaf3a4928 0x7d4f3f29 0xead3972b
+ 0x65670bc4 0xd058cc70 0x9fb58c45 0xf5f08926
+ 0x9aed1955 0xb1a5d161 0x14b5aa11 0x66e14cee
+ 0x28d7aae3 0xae45fcec 0x92dc7dc3 0xe9eda97f
+ 0xbee84f22 0xea6f71ac 0x6347c2b8 0xe919afff
+ 0x2c409d7c 0xa9800c52 0xd8033a17 0xc3794565
+ 0xb5311fe8 0x80d8a030 0xf9cf179a 0x508ea242
+ 0x4464cd33 0x91da91a8 0x6c0806cd 0xb5473d09
+ 0x0a0b99b3 0xdaf528eb 0xca1e99e7 0x064055ef
+ 0xc2dce623 0x0b4c15ac 0x23c13327 0x3f9fc266
+ 0x335d9c40 0xaca940c2 0xc18c0797 0xd5027a07
+ 0xb0a4d322 0x2e601275 0x6cc88888 0x658eaf8d
+ 0x509e2247 0xbae254d6 0xf097f138 0xa163751e
+ 0x19558f7c 0xb66f0cd4 0x87b1d966 0x81dd2cad
+ 0xf0c25e6d 0xb8e72dd1 0x00f15f42 0x6d2c1c68
+ 0x43c7e436 0x68eedad4 0xc2686b38 0x6ff30211
+ 0x197c7734 0x905b8602 0x6ab9d204 0x0d16385c
+ 0xb1cb5e16 0x8249a5c4 0x29d1ce0e 0x779f7b63
+ 0x63042725 0x12ce98e3 0x11282058 0xca3a9eb2
+ 0xdb8294e7 0x423e41ac 0xc3ab2774 0xca658d6d
+ 0x519f8896 0xaf6010f0 0xd57a94aa 0xcc17df91
+ 0x7d25cf8b 0x041e6835 0xa056d9e0 0xf90f3964
+ 0x7f99ae59 0xd80125d7 0x9961d6e5 0x41b3da06
+ 0x65c254e4 0x787d2c61 0x16aafb02 0x157ab4a8
+ 0xdee3674a 0x1ed1b601 0x2e36dae9 0xad57ad38
+ 0xaaf25b15 0xd3c37a01 0x68ca9eba 0x2a1bc480
+ 0xba157917 0xc00017c0 0x190bd74a 0xd6c6c1cd
+ 0x4efd4f71 0x388ed702 0xc8812950 0xd0019ca4
+ 0xd44cc835 0xd838fd6a 0x1432ce88 0xce98d932
+ 0xaea21cf4 0x54a44cdf 0xdb4dc5ad 0x1d23a7ae
+ 0x5ae126ad 0x100dcb50 0xa9727413 0xcf1c61cc
+ 0x72f9d2f8 0x4d32d201 0xe27586a8 0x0a1cc932
+ 0x21858469 0xf1cda3f2 0x59703f35 0xbd81f9f4
+ 0xad6ac9cc 0x25665703 0x1212d5cc 0x98a243d3
+ 0x8f47e113 0xd98feef4 0x3c93e832 0xfd67097a
+ 0x0c73fea5 0x6132ec59 0x1dc9bdb7 0x791f79eb
+ 0x84d83574 0xbd5817e6 0x7d5a0f8d 0x18482a08
+ 0x53ac8e4f 0xadd3378f 0xd48540ac 0x4082f5d2
+ 0x3ff5badc 0x24855b3d 0x7bb948f8 0x72637822
+ 0x0687e93b 0x61290b4b 0xd9f20b3f 0xcc0e5beb
+ 0x141ca01f 0xecd1337b 0x8576ec65 0xb6f825a2
+ 0x8b84e8b6 0x5bac53f1 0xd4edd06a 0x76ae712b
+ 0xdc00a887 0x798c2ee1 0xe74a5ab5 0x1539fa68
+ 0xa30817da 0x06f7c53a 0x1930c59d 0xd4232359
+ 0x0dfb1427 0x58d7180b 0x53bf57f9 0x5f001d08
+ 0xd08128ed 0x3208b7be 0x5c2aba8c 0x0abbd0d0
+ 0x424f2041 0x7982f731 0x010ec811 0xa3489c82
+ 0x71ffdfa7 0xda0ed41f 0x8a9e806b 0xfa9bddcb
+ 0x7a9e1a41 0x53c7603f 0x9e3df28d 0xd06dd100
+ 0x2cc64f4a 0x0dfdccf2 0xb4eb9101 0xf56d506d
+ 0xdaeed218 0x45523a16 0x4d6d68ba 0xff9a8f72
+ 0x5358b2f1 0x2511a591 0x9ea2c2fb 0x08cafc7d
+ 0x7ed34bb1 0x0cf2301e 0x62b6c05d 0xc05095ec
+ 0x52128c55 0x030576af 0xef5f37a5 0xdf5ae47a
+ 0x39e55496 0xb2c2129e 0xb2d67d77 0xc5adf049
+ 0x15a1cb4f 0x981948e5 0x7d18acc0 0xec7abb43
+ 0x23f7e366 0xa919a355 0x23872683 0xb7b6d84b
+ 0x4767dab1 0xd133feb1 0x2e5536cd 0x587683d4
+ 0xa181575c 0x4329e640 0x1244ae40 0x5be82f66
+ 0x4b28dc4b 0x4106c9a9 0x517fad7e 0x9e334ca8
+ 0x3c3ba741 0xe902a475 0x91d046a8 0x31361f96
+ 0x911b83bc 0x6607fac7 0xdfbc6390 0x7213aab0
+ 0x8ca8a47a 0x4f3d1f3a 0x3ee76c84 0x22bac3f0
+ 0x475f3cab 0x05d05569 0x92b3f912 0xc632a733
+ 0xd79b7448 0x595b82fa 0x6013b96e 0x6d03b5eb
+ 0xe37045fb 0x6e4add26 0x11f116da 0x4ac8bd3b
+ 0xacb5f8a9 0x8fb943d6 0xa9ac31c7 0xf1ba9752
+ 0x43a6b29a 0xf123766f 0x536fcc32 0xcf8168ad
+ 0xd8fb1e4d 0xb9562fa5 0xfe6d8dea 0xd31ab16c
+ 0xf7dfc381 0xb70f11cb 0x371c6688 0xac3fccee
+ 0xf130a51b 0xc5b8cad7 0x0cb13762 0x64ae00f2
+ 0x45cfad12 0x753d6a4a 0xc6f69472 0x695fba60
+ 0x49d1f754 0x9db947f2 0x2364ae20 0x197492e4
+ 0xc5b9562e 0x34963cec 0xdc26402a 0xa1c88d01
+ 0x58e27195 0x9d60f5c4 0x3e200a43 0x7e9827f2
+ 0x0a4feee5 0xd401e139 0x17352152 0xd509564a
+ 0x4b3142ed 0xef7567fd 0x9a619dbf 0x56ec2cb7
+ 0xc64bb290 0x3d69fd89 0x897325a1 0x74e2cb7c
+ 0xf270fdac 0x2beb6a4f 0x5b60de30 0x49df7517
+ 0x294966cf 0x87f5f667 0x4a9e1f6a 0xabc332c3
+ 0xfaf358aa 0x5baa6cfb 0x36b99bfa 0x40259687
+ 0x584539e2 0x2710ce99 0xec1959aa 0x642c8413
+ 0xfc005d36 0x2b2e6245 0x0012d041 0x09f6b626
+ 0x70fe9e2b 0x3cf30c5c 0x69d0a3ed 0xfe621601
+ 0xb6fa9267 0xe9b507dc 0x49f35866 0x4b97647a
+ 0x9e721adb 0x89e6e8d6 0x407a2f49 0xd977cbaa
+ 0xd9359f5d 0x7b69702d 0x22d6e818 0x57eaa5a3
+ 0xdd5063b0 0x4d7d2312 0x7a865203 0xb7f0905f
+ 0xdd2c2b87 0x7215803c 0x1abe5307 0x2926f38b
+ 0xf6b0cacc 0x96f50647 0xb612feb7 0x6915bfcc
+ 0x058b5cb0 0xc39e47d5 0x7513abdd 0x9e43972a
+ 0x1e55f640 0x896db1c5 0xd9382d2c 0xa52c1f99
+ 0x8afaf5cf 0x36500aa3 0x2e65fa1a 0xbb40d668
+ 0x81188e3f 0x143fba69 0x3f61fc90 0x438d759c
+ 0x893bb96a 0x069f349f 0xffdc43c7 0x6ebfa943
+ 0x671b4751 0x629cec23 0xe717fb9c 0x53fadc0a
+ 0xddc1e212 0xb99788ba 0x78378cf8 0x2ed91106
+ 0xec1de376 0x98d86b3a 0x312a190f 0x0208a0da
+ 0x6dcb469f 0xe6407c6b 0x1c7fea86 0x83841afa
+ 0xa9caaffe 0x86e3fd0a 0x918af9b0 0x0fabdf39
+ 0xdd9fc8f7 0xf9ddd98f 0x3dd0acce 0x2064360b
+ 0x29006620 0x5d7733c2 0x682c4093 0xf038a8b4
+ 0x3a688845 0xf9d0b9d2 0x27f51a57 0xb63b063c
+ 0x533b082b 0x7f0d0dd1 0x7abdb018 0xea6f6176
+ 0x13394ac6 0x825339bb 0x1835fd8d 0xaa46df84
+ 0x0751fe4b 0xbc9fb7c7 0x233873ff 0xca200e1c
+ 0x668fd5a5 0xda059135 0x2baf8828 0x7a2efc0e
+ 0x7c63d98c 0xe71ea373 0x0f218e88 0xa031f88f
+ 0xf32bccf3 0xf15eadad 0x6df44be6 0xb2536e4b
+ 0x2903a9aa 0x42ef8689 0x444432f2 0xd27a6c4c
+ 0x0992a32e 0xaf6e65d2 0xcbefdf23 0xe602151e
+ 0x21beace6 0xd9b992b2 0xe43286cb 0xdb315c09
+ 0x0de7672d 0x9d518ff0 0x75c4e9a0 0x64b2f70a
+ 0x9deb697d 0x5bcf59b8 0x2e4b9a8a 0xd9294b49
+ 0x3fee760e 0xfba8fec6 0x1c140305 0xe400487f
+ 0xc4cd4a38 0x14e6f1c6 0xdf98e7f8 0xfa6c4992
+ 0x62908c82 0x37393196 0xc02464b8 0x4b119742
+ 0x83e5e79d 0x15ddd908 0xf75d1820 0x363025b9
+ 0xd9e1a04b 0x9e110da7 0xd8caf954 0x30f62bc6
+ 0x875fd2b7 0x8b67bc8e 0xd5c77d4c 0x1a8ce00a
+ 0x7cfb14dd 0x3a39fd65 0xaecc2b5f 0xb017dbb5
+ 0x6a57b4f3 0xa27b6509 0xcdb06076 0x000d6366
+ 0x66e4f311 0xf22e25d7 0xf91d9bc5 0x5f9d3a05
+ 0x3b37c96c 0xb0596f50 0x53c24ede 0xb620106a
+ 0x5e675314 0xd98d5b02 0x75261f6e 0x5610c20f
+ 0xedcbe43f 0xbe85b8c2 0x16f7ffb4 0x55eb91fc
+ 0x2605ab1b 0x5ad3b426 0x3658d764 0x639c0560
+ 0x987249ed 0xdc470fa2 0x0d112f6e 0xd8ab77f7
+ 0xaed9455f 0xd9f6a341 0xb9b21249 0x3ff2b69f
+ 0x37ad61d4 0xdd6a089f 0x609233f7 0x46a923f4
+ 0xe5c23e8b 0x6aff8687 0x5e8ece1e 0xc65e1e4f
+ 0xfb96cf51 0x9b697cce 0xb08e02e2 0xf874e0e9
+ 0xbc983fa6 0x870375e3 0xc88bcd2b 0xc6bb19ae
+ 0xaa0c99e3 0xb301ab7f 0x024ba529 0x4449828a
+ 0xd226454a 0x0a610f3a 0xf302a0f4 0x021a3cc2
+ 0xa9e4b6ea 0x0b690b92 0x3379c01c 0x36265ea4
+ 0x29fbc8a3 0xe6279573 0x3cdb8a1e 0x005b5332
+ 0xbab71a8e 0x9677db73 0xa8a6d6ea 0xf0afbd3d
+ 0x576fbee6 0x49a54473 0xfa7c6e95 0xcb914daf
+ 0x58266856 0xa6b53a63 0x7136515a 0x2a3da411
+ 0xb1c994e0 0xbdaecd7b 0x5b436ff8 0x6334ec5f
+ 0x0172b5d2 0x57acd652 0xca4efacd 0x87e7d313
+ 0x78ac87c8 0xaf7602aa 0x3769ff6e 0x86d39747
+ 0xd32a7aa7 0x840cb30c 0x3e7da9b1 0x3c905b44
+ 0x90290dd7 0xebc85f3e 0x32693a53 0xc7140058
+ 0x6ca5cf6c 0xdabfbc3b 0x3d559486 0xe5ce93b9
+ 0x8d3c428a 0x9d18b8ee 0x404f58d3 0x151b4a78
+ 0x2f393e9e 0x69c59344 0x7879e974 0xc32217f5
+ 0xb946562f 0x1d1b8745 0x3666cd1a 0xc6a1e2ef
+ 0xe22d2e5e 0x9e7ed504 0xe6c32118 0xb2919117
+ 0xb2bad34c 0xe7177e87 0x47b68328 0xe579fe7b
+ 0xd0d33f00 0x96923c90 0x5ff2bf45 0xff074961
+ 0x4dce1092 0xe8a89464 0xc0b1ea51 0xd65f0f12
+ 0x6b2389bb 0x48fa0960 0x82722b27 0x62625540
+ 0xd4ff4985 0x768b7c26 0xb36a4ec6 0xf6a66375
+ 0x1c89e246 0xb629fce9 0x6aa72399 0xd783733f
+ 0x6478b123 0xa374412c 0x11b5cfc8 0x73cf2286
+ 0x443f5601 0xd817fca7 0xb2ce2d63 0xf6c63479
+ 0xd16b0550 0xf2a52ac4 0x7843803c 0x1ac3b58b
+ 0x7f96b915 0x732403a1 0x64634349 0xd2ec0bf9
+ 0x10410c08 0xe95d8dfa 0xaaeb33a5 0x57893eaa
+ 0xb59afac2 0xe9fd6dd2 0x50d11a7f 0xde479c58
+ 0x9dac27dc 0xebba7d8b 0x17fa1420 0x74a1678c
+ 0x71ccdaa3 0x5e44b0bb 0x5927a75a 0x7b7580a8
+ 0x33330c9a 0x40192652 0xba6308de 0xecc81fbe
+ 0x41d48824 0x6ce4e0c7 0x145e9225 0xf8484bee
+ 0xc8675611 0x750ec207 0xfa5f5b85 0x618b9f8a
+ 0x007cdb05 0x67f98d4b 0x1035f305 0x8d700e9b
+ 0x9857a0bf 0x4b774ad8 0x8960c81e 0x344a9462
+ 0xee2680d0 0xebb5f6cf 0x7397c9f2 0xcafa01ec
+ 0xaf69f3f4 0x0a1699cb 0x90ed82f8 0xc5c8ac04
+ 0xe50bd06d 0xf75741c6 0xea52365c 0xd0c03f33
+ 0xb5e4e95c 0xebf55379 0x0aae6e4a 0x29f8b91b
+ 0xef8ad2b9 0x7bebf2ca 0xb194b728 0x7df7b083
+ 0x0ea527c4 0x6d55939f 0xb9242c58 0xb3e1f570
+ 0x4fba0507 0x82d7259b 0xb5be7b54 0x0aff6ff9
+ 0x88391023 0xfe352956 0x4a6bfb30 0xa00c9644
+ 0xc478d534 0x0cdb509d 0x9611713c 0xd7c442be
+ 0x8d16889f 0x93abfefe 0x435fa757 0x40d95d3d
+ 0x11b7bdce 0xd074874b 0xdce6add2 0x0b652a4e
+ 0x595a88e6 0x307a223d 0xb624b9bd 0x855ba51f
+ 0xad43c800 0x1fcf6afd 0x4bdd921a 0xd6777384
+ 0x8da9f15f 0x5fb03ee2 0x5e6d04e2 0xb33751cf
+ 0x55d9d38e 0x41589fad 0x6d311b4a 0x43046a7a
+ 0x8d9c7304 0xe25f9788 0x8b459e1b 0xc9a3cfe2
+ 0xe6ab721e 0x4de3c89c 0x5c2d2398 0x085d8d69
+ 0x4e27ce73 0x1cc1f44e 0x05aeaebe 0x8cedb916
+ 0x370b4d46 0x1bc29579 0x33d08b75 0x06b77cff
+ 0x155693d7 0x125d3f0b 0xd8714e15 0x3b7427ba
+ 0x13f6684d 0x834ee449 0xc5a45189 0xb2ad214c
+ 0xa61be586 0x4e4727cd 0x563d1c31 0xd4ba1cc3
+ 0xdb08cd16 0x4940a42c 0x43dfd0cc 0x9d43222c
+ 0x638a0d11 0xc33d3992 0x98bf11f0 0x1aebf6b5
+ 0x1e206582 0x5647f772 0x9255ad74 0x75915665
+ 0x0fe7dd12 0x9def740a 0x9361bdf1 0xc1409fc0
+ 0xd3bac631 0x7492ee87 0xe1e99dde 0x2fbaf552
+ 0xfc24f52c 0xc080882a 0x0a2417c8 0xcea3da70
+ 0x4fe34fad 0xb4e55427 0xd5d54d76 0xf36686ba
+ 0xd6ab1798 0x1868e364 0xa380f948 0x0eaee02a
+ 0xad5a44e8 0xb6d119f4 0x82a43444 0xafad0e68
+ 0x595c3ab7 0x385746b3 0x32df6d2a 0x0b01b2de
+ 0x51d3d6bc 0x107d8620 0x6d215143 0x29d0e901
+ 0xbc57a3ec 0xd584ba34 0x8c244547 0x23d396fa
+ 0xffb03cb4 0x8396c1a7 0x3f251905 0x8bc769b3
+ 0x68f4696c 0xfc297895 0x9ec65e40 0x22deb20b
+ 0x5d1def76 0xa7a095b1 0x3aa6a458 0x6ca11880
+ 0xcde44ece 0x62b59f4c 0x067f272d 0x9a5aae97
+ 0xc60a8d62 0xeb0f40c9 0x83ebae30 0x07dc9cb0
+ 0x05dbdc76 0x0c108eb1 0x314f9247 0x7bfd6072
+ 0xf648e1c0 0xae70bd5e 0x7c27b4d1 0xb0cff1c3
+ 0x8c2dd93c 0x580a4b19 0xfaa1ee8b 0x4173a23f
+ 0x838fa15b 0x2b0fe3c5 0x8059250d 0x659a445d
+ 0x2a1c1968 0xbf13412b 0x1a9f915e 0xaf80263d
+ 0x24508a66 0xe381d252 0x4e0f55a2 0x7ce1f4fb
+ 0xc145da4d 0xbd4b29c3 0x27540ac2 0x23ad4b42
+ 0x8e6bcda5 0x20061c20 0x1d3cb3fd 0x5c5498f3
+ 0xc468681d 0x4c28ef55 0xf0165c1d 0x2dd6d032
+ 0x7e347ccc 0xe04db59c 0x7caa883b 0x1f43df4f
+ 0xc300031c 0x85f19e9b 0x22811fa7 0x2622940e
+ 0x6299f57b 0x5c106568 0xd7da296e 0xccd36b39
+ 0xe349afc0 0xd2c2463e 0xf7f55aef 0x0e0a7e3d
+ 0x6b6fc6d1 0x8854098e 0xc87edace 0x8190c437
+ 0x333b8ec6 0xe49b3a5b 0x4aecd4e3 0x14cc5f22
+ 0xa11faf96 0x3d1cd023 0xae614c70 0x0ab662b4
+ 0x908d8082 0x76316cd0 0x3068ec32 0x829b047d
+ 0xf08d1b94 0x3b2b33f6 0x03df9ae8 0x40f632d0
+ 0x3590085b 0xa33aad24 0x39597da2 0x99415f4e
+ 0x7aed6e11 0x61a920ab 0xca851d8b 0x2606f821
+ 0xeb7c0e8b 0x8bd6edb1 0x725b39f6 0x3afa6248
+ 0x03540044 0xfb118ecf 0x8e18bd5a 0x2a85cc05
+ 0x4ecac12f 0xf53a4d25 0x8e3fc6fe 0x32233799
+ 0xc7ebb5e6 0x058fdcaa 0xe6db17ed 0x2751405c
+ 0xa195a515 0x34410c51 0x4517154e 0xbbb5674f
+ 0x28050e40 0x8fd71724 0xbe78711c 0xc1b18693
+ 0xd202b9d2 0xdf4e0b62 0x460349da 0x71463aef
+ 0xb2fb55d3 0x54a972dd 0x49379f09 0x7a7fdff3
+ 0xbd82d4f8 0xd2894393 0xa82bca57 0xe61ca9b4
+ 0x9e08e6a0 0x53dffe9d 0xe7ae1c5c 0x65bff365
+ 0x7564aef8 0xd94abd3b 0x18d1ba52 0x64a759f0
+ 0x65c5dd4f 0x6f9d433a 0x57cb5a25 0xc1862d25
+ 0xcf50223f 0x90c2724d 0xf5527605 0xb085f18a
+ 0x41e2b17d 0xfb1cabc4 0xd8ab04cc 0x761c2166
+ 0x8365afd4 0xc3276657 0x14f64be6 0x5dd779b7
+ 0x3b3f1faa 0x358d01e8 0x4c821ddd 0x7ada9f95
+ 0x2970bad5 0x3b54a4bd 0x3ca7f039 0xcb67aabc
+ 0x3b264655 0x96401a5e 0xa3990376 0x90834685
+ 0x8ba56352 0xee98c564 0x4a0534ed 0x7d70fad6
+ 0x5d73a1e7 0x23fd8de5 0x39c52296 0xefef1540
+ 0x7bc934dc 0xeed157b4 0x898d8bfa 0x5761e88f
+ 0x73af2674 0x2fb88d9e 0x28de1281 0x9aa76119
+ 0xa3ac21ea 0x28ce635c 0x7596d79a 0xd3295e0b
+ 0x7826630d 0xd815ef01 0x27cf2899 0xf3de6a01
+ 0xcbb32e58 0x6c57be3c 0x292f819f 0xaa4623d6
+ 0xb96ab772 0x90a6f778 0x44b9933b 0xa43e7543
+ 0xb9f417b7 0x7a6537a5 0xf36a6da2 0x0a9bb3fb
+ 0x177c1f28 0x0512c07f 0xdda55932 0x060dda31
+ 0x14465771 0xf3f96780 0xb459e5e3 0x49aaefbd
+ 0xb07db15d 0x2ac82807 0x8404060d 0x417d036b
+ 0x70946fb1 0xe39e68f5 0x5f9b3035 0xf0335e7f
+ 0x2ba457c6 0x2d97ba3a 0xc05156e7 0xbbc9afb2
+ 0xd25981ea 0xe70d060b 0x805c231d 0xae471b34
+ 0x31964d8d 0x3f34e35a 0x8355ee21 0x73822024
+ 0x9ce5f2d6 0xdff19812 0xae55cbaa 0x55f5ecbd
+ 0xfe558210 0x09b95751 0x41ee7cb8 0xd2b9fa15
+ 0x342c07e5 0x7ee50e8e 0xb6154e01 0xdbf4df3a
+ 0xd43e2c77 0xc3ff0498 0xd8106f33 0x9bdb25bd
+ 0x40cb843e 0x106b08a9 0x3227ce7b 0x58bb7cb6
+ 0xb84e3244 0x3f1d0e20 0x76dcbcfd 0xb750bce7
+ 0xa8c11f3f 0x161a8610 0xdc1ef5bd 0x14270b6e
+ 0x285e7898 0x68375db6 0x01d23b44 0x35a17fb0
+ 0x7c9ad882 0x7bda2e0b 0xca67bfcf 0x6e2dd9ab
+ 0x227a6aba 0x5d295397 0x5061f96e 0x47a20c68
+ 0xf5427e3d 0x3a0a3165 0x2438fd9c 0x2dc91147
+ 0xeabab62a 0xdc358e4d 0x7e1fcc9b 0xdc2a328e
+ 0x6e6bf75c 0x68c45517 0x594fe5a7 0x2feac658
+ 0x1f0a4d49 0x97575e83 0xcccbdab8 0xc13f3b64
+ 0x8bfe659f 0xa4ebf545 0x2c3cf874 0x7d78ceba
+ 0x46ac5d6e 0x09309533 0x78ffb6e3 0x7336541e
+ 0x3d270f70 0xd71e72b4 0x9772402a 0x4ed185b7
+ 0x213da698 0x78a54587 0x18054eb4 0x99179a25
+ 0xf758337b 0x94629a30 0xec6bf4e0 0x255ac299
+ 0xe56f52b1 0x1c2a6136 0xfb7cc1f6 0x87b53b53
+ 0x079ca1f7 0x3a8c340f 0xeb70ef48 0xfd1caae4
+ 0x564445e7 0xc1d5c663 0x658fb5fa 0x62d2debe
+ 0xc0907042 0xb5402269 0x16965193 0xc038c21f
+ 0x780f8b76 0x33ffeb3d 0x03ad9602 0x4a7b6432
+ 0x93c2b2f5 0x40720fcd 0xf44c164f 0xcbd43d01
+ 0xcf7098cd 0xc43242fa 0xc530a6b3 0xcc33c1f7
+ 0xde3d648c 0xf1def13d 0x2a22f5d1 0x77704fc6
+ 0x08ed5552 0x3e2295d0 0x00584764 0x6af8585e
+ 0x43f845da 0xa92e38df 0xd98c12b4 0xb4fac901
+ 0x0b05a079 0xa05f215a 0x27d635c6 0x9fc897e5
+ 0x0eb91a30 0x43bdad4c 0x705df05f 0x6b7864b7
+ 0x1b6380ba 0x4a64e8ec 0x517b7b68 0x67336d4b
+ 0xc6d51eab 0xfac40c57 0xb977cbcd 0x0674e5dc
+ 0x74ce2339 0x891cc5f5 0x3230ca78 0xa8a653a0
+ 0xa8d4b370 0x496d2f7f 0x6ca677c5 0x54260ac2
+ 0x630e1143 0xcbf6f819 0x546b2874 0x02267559
+ 0xa2e23914 0x7c9a0393 0x1704bcb3 0x6d680415
+ 0x91da300d 0xe2ce21d2 0xc38faf3e 0xcc8be7cb
+ 0x14496036 0xc98e253a 0x05ca6582 0x8c566616
+ 0xd26204dc 0x3335bd81 0xa94e5af0 0x76fbb455
+ 0x23b27f08 0xc4db6f93 0x5cb5401c 0x7cb2ed29
+ 0x7cbbad8b 0xfc1e8f5e 0x2bc79e28 0xf69228fe
+ 0xbde16357 0xc9ac3b53 0xa6afbc74 0x984bb3f4
+ 0x98a8b9d6 0xdd21c848 0x33e65c3a 0xc53c772c
+ 0x633022f8 0xa324bd5a 0xd260a77a 0x668ca5d3
+ 0x4b79a6b3 0xbfd19bbe 0xca2eb497 0x8e7eb5c9
+ 0x169b2184 0x0503d4f6 0x24f35c00 0x0ac930ab
+ 0xf694120f 0xcee12db4 0x9305757c 0x798a2db2
+ 0xed27ebec 0x2f35829b 0x4294e805 0xa7994ad7
+ 0x49fd229c 0x5d63fe52 0xb7cd7641 0x1a68af3b
+ 0x6f952e97 0x1c02f4de 0xca3a1515 0xed5bf092
+ 0x123c32ea 0x602030aa 0x7811cd1f 0x1b6c38dc
+ 0xeb7712b4 0x4aa767e1 0x6b49d384 0x7ba4ee1a
+ 0x87f02cd2 0xb8e6b0b1 0x090e9f89 0x95f8b90e
+ 0x8d76892c 0x0be06870 0x9ec963c1 0x75d67c9d
+ 0xdde23799 0xf9e3be20 0x549442fc 0x09cb0906
+ 0x95ee6c4b 0x25a2d9b7 0x98154023 0xdda91829
+ 0x0c46879b 0xfbf0e362 0xb7223786 0x7cfbc839
+ 0x3b251e5c 0x8be187a6 0xa24f9da6 0xc3192693
+ 0x7a8ac8b9 0xc493ca03 0xc736b974 0x369db725
+ 0x85a6e92f 0x26dbef75 0xa61a71e9 0x38a08fb9
+ 0x4a214ed6 0x57fc6f4b 0x9cf91617 0x322e13fe
+ 0x5ac816a3 0x748a9728 0xdc777bd6 0x69fb5335
+ 0x258439e8 0xf171a221 0xfa7a07af 0x26447b9f
+ 0xadcf3734 0x5af34b97 0xf8b4b0dd 0x08c79517
+ 0x28861618 0x64692555 0x19fe9897 0xe3bda02c
+ 0x77df51ff 0x93dedf7a 0xc7cb57c4 0x02ee5928
+ 0xd4aeb644 0x01d511e6 0x6512bd02 0x5d8f90f8
+ 0xe77ccfe0 0xe6ee3ecd 0x5403139e 0x6f7075e5
+ 0xb6484511 0x3bd42a35 0x5dcea90c 0x5bb1c6e1
+ 0xb69b5847 0xfe106914 0x74442ce9 0x10997c57
+ 0x1595af7f 0x9f04a8bb 0xa7d2870e 0x19e57681
+ 0x54b276be 0x11c3e3f9 0xc5401783 0x9c413cda
+ 0xa6aa9e8d 0x23ff8569 0xf1797ea7 0x86ce3e8e
+ 0x9ef0a776 0x56a1c30d 0xf5e18916 0xb11464d1
+ 0x7f313c1e 0x49c15cff 0xe2dcfb73 0x637819d8
+ 0x2d6ce0e2 0x2170cd43 0xb750902d 0x5eb02cd2
+ 0x6cadb7d4 0x89b96f3b 0x8d749ca2 0x8ac7abb7
+ 0x31fbdb51 0x7a6df774 0xfb9139f0 0x56f3d9c3
+ 0x0f104f2f 0xfaba3c49 0xe53aefff 0x932237d0
+ 0x8ee10e80 0xadad6e20 0x19883a1a 0xf45a543b
+ 0xd560ff0a 0x8c7b4e03 0xe35696d6 0x9e0ec159
+ 0xfc2cbae5 0x6ce2cddc 0x14a72474 0x89757fe3
+ 0x6b788e7b 0xc16fa200 0xad36bdf7 0x57bdc4d1
+ 0x55146f2b 0xa57db4c5 0x313952e1 0x2c55d0d2
+ 0x32ab0208 0x10f846bc 0xdcba1674 0x436485bb
+ 0x932704de 0xcd7e2e1c 0x59f78879 0x7ca21395
+ 0xbcc07be6 0x2b101e5b 0x38924c37 0xb90928f4
+ 0x8f824214 0x55699b67 0x54cba493 0xe71c27a3
+ 0xdde01c05 0x48d822fd 0x734ed8fe 0x29dbf298
+ 0x9ef3a499 0xfb517934 0x19c8ce8b 0x38b8bf00
+ 0x75da50eb 0x237f3b1d 0xa8940707 0xa98a4149
+ 0x35ec2d39 0xee862d31 0x36659949 0x8f3dffc2
+ 0x70afb227 0x94f443c1 0xb6f9308e 0x0e8ebd54
+ 0x92b8960f 0x56d21560 0x8453d1ca 0x74c680c0
+ 0x2d706dfc 0xd0b81c18 0xbac65445 0x40a34988
+ 0x498145a9 0xf436ae10 0x9b72fec6 0xb4100aed
+ 0xe305983c 0x349fe379 0xbf31cfa7 0xba624703
+ 0x4a491754 0xf973a686 0xa2ba725c 0xd0a23615
+ 0x31903086 0x4ae46e45 0x0f705e05 0x4ea6bbc8
+ 0xbf299e43 0x0689709c 0x9fc93571 0x07cbc14f
+ 0x542ef992 0x80ce91f1 0xf86014aa 0x17d533d1
+ 0xb55e63e2 0xe02e0e4c 0x88a5ed22 0x6302126a
+ 0x56b32e90 0x5fec4381 0xe2e98b3f 0x30693509
+ 0x862e1d75 0x2da30e3c 0xad992d90 0xc62cae4b
+ 0x379c77ba 0x467ea8f1 0x8a820048 0x74cc474e
+ 0x6bca3803 0x18aaa3f3 0x1fafd26a 0x0865f360
+ 0xe3479d10 0x6cefb2b9 0xf6612730 0x2e0f222a
+ 0x749a89e0 0x75b1fa05 0xe2ea0874 0x5d422c20
+ 0x24707d46 0x6d475835 0xed1e556e 0x6aa4543e
+ 0x28b36c16 0x22d83c4a 0x8c3e6d51 0x42a94c9f
+ 0x0c603d0e 0xa8c7f417 0x845997ff 0xdc79494e
+ 0xa130d628 0xc2df082a 0xa3a2c27e 0x3f93b00f
+ 0x1521a7e5 0xca15bae4 0x57e4e836 0xb915a471
+ 0xd9147115 0xad52f80e 0x5fd2a2be 0x15972ed7
+ 0xb69ec21c 0x502f2627 0xfb46a1ca 0xea685d34
+ 0x9226f7f2 0x4b41927d 0x7965eaa0 0xb702e76f
+ 0x79a54721 0x5b8e984a 0x37efcd59 0xfeabf30a
+ 0xd4ad7db5 0xbb2282ab 0x8a5c840b 0x2ba370c5
+ 0xdef5758d 0xa69a9aa1 0x46082250 0x6e8e8477
+ 0xf6280c61 0xf99e4a14 0xcf3c5cbd 0xcce657f0
+ 0xca635eae 0x0be182b5 0x58e8b43a 0x5c717ce5
+ 0xaa7aaff7 0xc329c6b6 0xf1cc91ef 0x8d7cc520
+ 0xda155783 0xd5e2e54c 0xf466f010 0xc5dfac4a
+ 0x606ad5de 0xf4992f1a 0x1344c9ce 0x4aea9020
+ 0xa30447c7 0x0a99ad18 0xd3caa96c 0xfe5b0b4e
+ 0x7b50bbd1 0x33e50575 0xa22d1d06 0x73a1820d
+ 0xce4c4c8c 0x2cde7764 0x511d1c26 0xad0cf826
+ 0x086dc311 0x3060ef7d 0xe6fdc617 0x3050b179
+ 0x1dbb5316 0x4145fcb7 0x2eb62505 0x2e1359e2
+ 0x79cab612 0xaa9282c9 0x7eede562 0xb016f7ed
+ 0x1445fefb 0x809b2e00 0xfafaa754 0x69ac113c
+ 0x548a6e3a 0x6d444c14 0xb3d355d8 0xbbadcd2b
+ 0x3032d634 0x7df39948 0x4c1f9098 0xa9d138ce
+ 0x42823bbe 0x2ef39e3f 0xaaf9ef1d 0x63369afb
+ 0x2bb76c9d 0xb7d38558 0x354160ce 0xc04c6378
+ 0x6c71ab10 0x7914af1a 0x1c1a4694 0x2f9fce8a
+ 0xe28f18d3 0x3acaa573 0x2503b236 0x90ca20e1
+ 0xd2c77ccc 0xc3005311 0x836d9430 0xe91d8463
+ 0xb53e4cb7 0x4e373c67 0xd06ef659 0x27e1a21c
+ 0x285c0391 0x32046fa9 0x8b1b9c92 0x49a22f4e
+ 0x81411430 0x050110e3 0x56144e6a 0x47fb824a
+ 0xdb2e9a6a 0xb5fe97a9 0xabd37259 0x93da3055
+ 0x19fb35e6 0x66661115 0xa27149a2 0xfb7d94b5
+ 0xa315f9af 0xd7d97596 0x134d7d09 0xd5cde0e9
+ 0xbc3f143a 0x1b2061ea 0xd7b15227 0xe8f506e3
+ 0x0aa17e92 0xc8565276 0xc7d90586 0x22a26c8e
+ 0x6d462029 0xe7b1ad73 0xd11fa609 0x67643f2c
+ 0x64f1ef34 0xa0e7e0b6 0x9687611d 0x09c2d32b
+ 0xb494937a 0xcc36510c 0x70555bfd 0xfa25e917
+ 0x7d88b6da 0x30f3b531 0xd19b224a 0x999d0f7a
+ 0x9fe0da18 0x45947b87 0x536dbf3b 0xa6f5182d
+ 0xdf11f95d 0xa5abcdbf 0x7528110b 0xf54fe792
+ 0x71a97619 0x680bd3ff 0x6981ea39 0x683ff854
+ 0x302fbbe4 0x12129f84 0xf63cd448 0x69fe289b
+ 0x568da933 0x2f1e1146 0xe7404e52 0xcd329394
+ 0x02e41762 0x94456d4d 0xe9416a20 0x4e5920e7
+ 0xe8db71fe 0x527a5313 0xe42c7d9e 0x58c8c1fb
+ 0x28949bc1 0x312fdf97 0x3569f41f 0x3ed5f092
+ 0x44baef39 0x5c11d5ad 0xb5d172cf 0xa9e4cfa3
+ 0xbc5ed197 0x2f290ead 0x747f53ed 0xadf1b698
+ 0x1b90440a 0x4cdfe154 0x9b24b832 0xeb97d794
+ 0xc90fe91e 0x4fef1271 0x8bf96025 0xbdb49f79
+ 0x63910640 0x26a05cce 0x3318e422 0xb2fc61de
+ 0xf14cedd1 0x4bd7687a 0x8c4c91dc 0x48a857a2
+ 0xb47aac94 0x787526e2 0x99349c7a 0x0bd6ba75
+ 0xbfbc4b0b 0x040fbec9 0xd00de44b 0xc4c7f0f5
+ 0x74a8653b 0xbd3cc036 0xa601a4f3 0xb82c0da0
+ 0x2709b674 0x73065351 0xaf4cd23f 0x3481ea0f
+ 0x6a1fa77c 0x26a9d280 0x95f4a170 0x393e7590
+ 0x015b3d73 0x36d91e55 0x61a7f3f5 0xf6d39c21
+ 0xd9ee4701 0xe57af451 0x5e141761 0xf6b6e472
+ 0xa6efc965 0x9606aa1b 0xfb8ce005 0x831ab2d1
+ 0xfe7a1af6 0x5e326881 0xa0ad32ae 0x15f86ecc
+ 0xa1a634d2 0x3a40c4a9 0x88e10130 0x2e6c4556
+ 0x8526aa32 0xa81b0d30 0x19c83936 0xdcaa556b
+ 0x6dc8064e 0x5709ad31 0x1b6fba18 0x9ebe34b1
+ 0x28abc3e6 0xd76c3908 0x4374657e 0x6f0fc085
+ 0x4f19a108 0xb774421d 0x405228d5 0x123dbbab
+ 0x18535471 0xfc6bde41 0xd4b2d82e 0x65b85772
+ 0x64731e41 0x29e886f6 0x4c2c7eda 0x91586a5f
+ 0x15b2407b 0x5fa08a72 0x56898e51 0x5424e976
+ 0x19ce4a36 0x0ada4656 0xe634446a 0x478da533
+ 0x36f1c763 0x01ec46c3 0x5e1d1040 0xf6da1918
+ 0x831f8f94 0x43ddb630 0x80b5d4e5 0xfc403ba5
+ 0x40dcdd4e 0xa19d0aa9 0x6c32fad7 0x7cdd6f3d
+ 0x8e9c123a 0x42c4edd0 0xc8247030 0xf0e6cebb
+ 0xf8d1425f 0xcfa8e403 0x67646391 0x9dee9f9b
+ 0x5683c4f6 0xd958ae1c 0xc62eedfa 0xbd67ea10
+ 0x253398d4 0x18b7f92a 0xf101a7de 0x60066732
+ 0x4ca1e3dc 0x6e1eb0a0 0x115aa9e1 0x8370aae0
+ 0xe46756d8 0xa02eb1aa 0x854dbb8a 0x6334873e
+ 0x87613a81 0xb5bd56df 0x491371d1 0x02bbace8
+ 0x2a2e45f9 0x91bdc460 0x2bcf90b6 0x81df2f07
+ 0x34aa2dd5 0x5b54a117 0xb7a5bd42 0x713e2287
+ 0x1ea184d6 0x176bdda0 0xa19c0d86 0x4180fd5c
+ 0xd018a4cc 0x60120a37 0x8f6e094b 0xfebe1b15
+ 0x42866bb7 0x4a9f772e 0x0bcf9cad 0xd936a924
+ 0xec6cf0a1 0x1f9ccf16 0x81f8229f 0xdcef1733
+ 0xb4a31fca 0xefbf0a0a 0x057e0b4b 0x59491c96
+ 0x70ce99bb 0x908ce274 0x637ae09c 0x479fdd52
+ 0x11ea6250 0x7778cdf6 0xd0ffe2ca 0x539b18dc
+ 0xbcdab649 0x3066399b 0xd685edc0 0x79d8d588
+ 0x32942aa1 0xd03531f7 0x5d024d56 0x4dc99729
+ 0xd1efff53 0xdf3ce9a1 0x31462a0e 0xe5427113
+ 0x395e2980 0xcf5c9d4e 0x91e11088 0x7e4d31e2
+ 0x5ff91ae8 0x9340e815 0xfcb89789 0xcb1b2f58
+ 0x655aa934 0x2eb022da 0x419104a9 0x6b648411
+ 0x582048e2 0xa0db392a 0x1e1d6443 0xf3c7a401
+ 0x1e737591 0x452af94c 0xfcb74331 0x2da70f75
+ 0xa8b59eb9 0x736224c8 0x5ba81657 0xfb36eac0
+ 0x4e0336b4 0x8925a32c 0xa4d60fde 0x8a95ff27
+ 0x57a7e536 0x7e6a2f58 0xd9e9751e 0x817cc66a
+ 0xca4bd134 0x627382fe 0x00e56736 0x74844fbc
+ 0xab1f8265 0xa32955e3 0x41cd361a 0xb3ae6366
+ 0x1f77ea37 0x2200c6ef 0x81854e76 0x49ed4e92
+ 0xb57a7fbd 0x7b9de6d2 0x128feedf 0x57bb65fd
+ 0x20ccd650 0xdcde5458 0xd5461b27 0x465147f4
+ 0x70719068 0x2cb48f5d 0x6edc0d43 0x83dbda97
+ 0xf077ea64 0xf61423e2 0x39a55177 0xb23ff07c
+ 0xa02e4ca4 0x9e6250d3 0x77f1df9c 0x238c632e
+ 0xce253a6a 0x096327c5 0x87f1db29 0xd75ac0de
+ 0x456704b5 0x9ee7046e 0xd693dfe0 0xf995c6b9
+ 0xa354d140 0xf16bf090 0xaf511cdd 0xdc56d21e
+ 0xd7cc4d4c 0x5398cc1e 0xe5444b3b 0xe192f473
+ 0xd09ae67d 0x8af2775e 0xc1af44a9 0x57bc4586
+ 0xa6ff5419 0xdd4ba49d 0xec4864fa 0xda9d0357
+ 0x84dfbe33 0xf41ba9c4 0x99e2bda8 0x9fba720b
+ 0xa7dd9e92 0xa0d43386 0x3e0f9ef2 0x6e388282
+ 0x8f47ea95 0xac920523 0xa98ae8a5 0xf6a6a4d4
+ 0xc3fa2e55 0x74a21b36 0x9c0b14b2 0xc6b8a79a
+ 0x367b7036 0x24b9f255 0x0b543b75 0xb630fa41
+ 0x1b260452 0x7daf6714 0xdb8a13d9 0xede8f6bc
+ 0x47a21d0c 0x01d9ca54 0x4a8e5cd4 0x257cd217
+ 0x7504cecc 0x973bbf11 0x992b731e 0xaab55b65
+ 0x77e2f058 0xf580b58e 0xb10419fe 0x679aa4df
+ 0x296c1d64 0x751380f0 0x8f70f0de 0x3f78bdb8
+ 0x1ee68ad6 0x7d5d50e4 0x823710a4 0x18b98d13
+ 0x86bdf798 0x953b8131 0xb5da3d24 0x2eccd3b1
+ 0x828a154c 0xed51b913 0x566e58ef 0xab8ff1b4
+ 0xc744d227 0xe705bbc6 0x6032eb64 0x5495e4a5
+ 0xe83add11 0x08429de8 0xa2e397dc 0x4f00c90b
+ 0xcb7672e8 0xa1d55607 0x0741ca2a 0x323d64f2
+ 0xa700ef1e 0x6ccb2967 0x07c29e41 0x018440a9
+ 0xbb1880cc 0x35502720 0x8a13a96e 0xe2bfcd29
+ 0xa76ad3aa 0xd95be915 0x6dd66033 0x41d655f3
+ 0x02009028 0xb44ec634 0x82e61d87 0x216e624a
+ 0x7fc79105 0xac0307cb 0xd22fa331 0x63746b2f
+ 0xe51ab72d 0x9b550c82 0xb28dbc01 0xd569d017
+ 0xd168d372 0x8d6bfe6b 0x5820751c 0x820a4e23
+ 0x13cfd07a 0x678c8319 0xd1e65476 0x752967ee
+ 0xafb28392 0x390d5488 0x53668098 0xa0c92673
+ 0xaf0549c2 0x644f51c3 0xd59df083 0x7cb37a42
+ 0x12261017 0x038c15b3 0xccc30b03 0x85ee24ce
+ 0x1e029b23 0xb6bb2845 0xb62a305e 0x2d0cf4e9
+ 0x182b887f 0xec423ce7 0x8c1c0b25 0xc83b4737
+ 0x71fb9023 0x63d639f6 0x16c1ce44 0x66ac8331
+ 0xd9aa0975 0xba3d445c 0x5d097729 0xb353a034
+ 0x23811786 0xb81394b5 0x5323f1b3 0x7a3e1576
+ 0x3f2867ad 0x0bc88c8e 0x74b60d63 0xd56335de
+ 0x0d40f71c 0x55ec2524 0xea3a2c78 0x19e5e0ae
+ 0x9bf3d033 0xf57bbc94 0x05b6ac55 0x4c368744
+ 0xae8c68f2 0xf23aad06 0xcf94d185 0x2360ff3d
+ 0x0e8a87f9 0xb97c8d33 0xa7122e6e 0x5ad4dc50
+ 0x6145ff8e 0x617389df 0xe8a0e09b 0x4d40ce6f
+ 0xee2b65fa 0x4104d368 0xf4bc9d85 0x0b67abbc
+ 0x7bbad9ff 0x26b293a2 0x06055372 0xbbb05665
+ 0x0560311d 0x421dc535 0x9c451ac7 0x38c83a74
+ 0xc8921ff8 0x634d52c5 0x6e66dae7 0x1c86fae3
+ 0x5a0645bd 0x6e5fddc9 0x86852d55 0x76207d9a
+ 0x6a4b7990 0x661c00eb 0xb268e55b 0x17daec24
+ 0xa2854da4 0x9b1f3f63 0xdd200bc5 0x0b50aecf
+ 0x8242f913 0xc7ab6eea 0xaa977c22 0x748d0d1b
+ 0x4490aae4 0xaa293e18 0x69aa0720 0x6115eb81
+ 0xa5b187fe 0x828bfe34 0x5fb6d155 0xe764d755
+ 0x08833186 0x8475cce3 0x718bfb48 0x063b287b
+ 0x7ea71b59 0xbedbfd29 0x3736aa07 0xe2dfd533
+ 0xf2ea49a3 0x96b0983a 0xc1f60b14 0x511bed9e
+ 0xac976686 0x9c60ce3d 0xfffd0b07 0x59d7cf79
+ 0x477942b4 0xff2f43cf 0xeb4b899b 0x37a47783
+ 0x8e6602a7 0xb6bfc410 0x7685c6e4 0xb7ec103a
+ 0xd54fdb01 0x3933d261 0x725982d1 0x86ada0a9
+ 0x83788370 0xbafb1498 0x13972979 0x2157be41
+ 0x5e976c80 0x05501107 0xb3b66da9 0xeebcb8fb
+ 0x42ac1fee 0x1dba34a9 0x3f5a7582 0x362e7ed7
+ 0xaa69be91 0x419f4d18 0xb09a9967 0x31aba127
+ 0xaa247bff 0xb31f4958 0xe79562af 0xfb73878c
+ 0x47dc697a 0x5d08fa9b 0x91dcd3c2 0x53e52d33
+ 0xc84ddc84 0xdb5f8e17 0xe51889e2 0xb1aff523
+ 0x4ffa0702 0x2c72b35a 0x9a4246fc 0x62420517
+ 0xaad11acc 0x18190bf9 0x11e140de 0xacc99086
+ 0x39347992 0x191a53d7 0xbe92c4ef 0x9a934b5d
+ 0x64cf7353 0xe30a3e8d 0x0aa6db52 0xb0a7e26d
+ 0xc8fe2f52 0x2e274a07 0x0c94b6ba 0xf80eaf3c
+ 0x1ba3e94e 0x5853ffe3 0x11652833 0xce7b0839
+ 0xd1893c23 0xd06d2078 0xa65f020e 0x281e6a7d
+ 0xdf1da5a2 0xcdf69d20 0x74fa9b92 0xd98d6000
+ 0xb732496c 0xbd12f87e 0x561dc55a 0x651d42ff
+ 0x5736b74a 0x2c48a906 0xfdcbaf15 0xf76606e1
+ 0x80dd0254 0x8105e60b 0x143200b2 0x0f02f524
+ 0x1580d2c6 0x7281c6fc 0xc971cd31 0xd4a57180
+ 0x5051e5ec 0x193c72eb 0x930332c4 0x488d7403
+ 0xa93e425c 0x93e8ca97 0xa0a55070 0xafd8f8fc
+ 0xc424f1bf 0x11050ed2 0x855d0923 0xa0fcef35
+ 0x61f9e84a 0xc2196706 0x7221d5f7 0x96d036a5
+ 0x137ca3fb 0xfd632623 0x30b10850 0xdda390eb
+ 0x270fc9af 0xe6a8d748 0xf55bc288 0x8cc912d1
+ 0xf2d9cd15 0x5ded2f07 0x2de9b076 0xf5088354
+ 0x885becf4 0x959ef88a 0x0d9ea589 0x2ceb0a27
+ 0x8925270e 0xca5ecd99 0x8ba9265c 0x209eb0b7
+ 0x2e8b51d8 0xc598e096 0x23c17aa7 0xf600bcae
+ 0x7b33f831 0x223e1501 0x361c9f12 0xe6aeea94
+ 0xa5c6948f 0xd1daf8cc 0x0b0e0b54 0xb0cea6c7
+ 0xa437fbc8 0xdb4139ab 0xcbbad47a 0x124e2117
+ 0xfb80c5dd 0xef085f4a 0xd24c5fa8 0x2548a1db
+ 0x5e6cdeb2 0x8e4f0290 0x78cd8245 0x1ebb5eb6
+ 0xd9bf1208 0xf20eaf0a 0x544df94d 0xebc9c742
+ 0xbc5b4bbe 0x33f6fcaf 0x32efb07a 0x55d91b59
+ 0x2c0ed1bf 0x39985cb7 0x4cab882f 0x530cdaca
+ 0xccc78cfd 0xdd834c48 0x7ce7898d 0xf7458891
+ 0x933c2ae8 0xa06c5762 0x2eb03e35 0x8e938b71
+ 0x3636f142 0x0026efb8 0x183d71c4 0x7e8ff92a
+ 0x63265ea6 0x0f1352b8 0x73f8a8fa 0x6594e921
+ 0x401f88db 0x64abd8e6 0x994140c7 0xb2258b0c
+ 0x9bd6e6a1 0x92bab589 0x5919a943 0x29ab4d8e
+ 0x33cbb8d4 0x57084d92 0x006c4d50 0x57c49e54
+ 0xec1ecfe6 0xeaa8109a 0x269d94a5 0x4a664f84
+ 0x2bda2944 0xdafb85c7 0x2a7b4b8c 0xd8f124d6
+ 0xbbac0e70 0xeac5a129 0x308d7e39 0x99a023a9
+ 0xf616fc22 0x76fcc40f 0x7f745409 0x83872303
+ 0x0b067846 0xdf90a414 0xb6d9b6e1 0x8d0f93d8
+ 0x6f76a627 0x02f89060 0x392cb9e0 0x6acf19a9
+ 0x7cffe4d1 0x9928b4a0 0x87a031bf 0xecff42d5
+ 0xa376e023 0x69d2e1e3 0x1fb67afd 0x5396049a
+ 0x45538549 0xec0e6f60 0xf1ab27e5 0xc679e764
+ 0xee430c38 0xa6b0c2dc 0x92824db1 0x65d5ffe7
+ 0x448b17d7 0x9c67c8e0 0x14b36e2a 0x283de0a8
+ 0xc59bb35d 0x8faf1ca7 0x4265db7f 0xb0e74749
+ 0x0924d389 0xc22bf3fa 0x017c143d 0x93b4e0d4
+ 0xf8aa8e07 0x07e0293d 0x5b40bba8 0x619c8946
+ 0xc817ee7a 0x82fd526b 0x3e5b0f9a 0x5b352d98
+ 0xc786d63a 0xcbec5c0d 0xd05e9640 0x7cab758e
+ 0xaa9bd61d 0x205ff53f 0x2f093865 0x55ef390d
+ 0x4b008d12 0x0344c52d 0x64820f87 0x8e9c5202
+ 0xdd3f2276 0xf3b46630 0x80e85ea0 0x9aea428f
+ 0xa205b11f 0xa8506b8f 0x2c89f419 0xb0b9694b
+ 0x21029e6a 0x5e05869b 0x3baf3c6f 0xde680ae1
+ 0xd65b5eb0 0x99a6937c 0x52a78fe0 0x6f577b06
+ 0x8dea8d63 0x2417d49c 0x1a0ecb5d 0x91f22002
+ 0xc540298f 0xea9f8f6d 0x01ccfdb5 0x287138c1
+ 0xef206774 0x9d5deed8 0xba844833 0xf612317d
+ 0xe0bd4bb4 0x595d0440 0x73643204 0x2c21370c
+ 0xf9d5df6e 0x05614527 0x73c4edee 0x33f45ded
+ 0xbc47170a 0x24b94b30 0xff304e54 0x4e0c3b53
+ 0x658af390 0x402418bf 0x9db7318c 0x058721ed
+ 0x896bdd56 0xa956c5cd 0x3f928400 0x94c93146
+ 0x56600758 0xf46f4f66 0xa5bf66d5 0x0e8b5870
+ 0x8ba7e755 0x4177fee6 0x32cc8824 0x90b677d8
+ 0x307e9dd3 0x853a7e3b 0xa2f064a4 0xa42dbd46
+ 0x243ed6a9 0x7164eb1f 0x9e97212a 0x9757d142
+ 0xde296a05 0x8699a74a 0xeb02fa7d 0xf80b41fa
+ 0xd9dd2198 0xd7ffbd00 0x21b15853 0x11b78093
+ 0xbb329142 0x5260fb1f 0x22fb24fe 0x7a5e7e71
+ 0x71434197 0xc5ddca32 0x930c8cb9 0x65192958
+ 0xad1a41f1 0xc77442ca 0x72b64ff7 0xa90bcde5
+ 0x184a19de 0x71df036e 0x1b69b0ed 0x023c391f
+ 0xd9847da5 0xca57d383 0x0d21255d 0x2ea68d9b
+ 0x0189eeb5 0x1ea62386 0x4c8d42f0 0xac20dd55
+ 0xacceef1d 0x972f56e3 0x0bc40455 0x3853c5a7
+ 0xcab0d1f5 0x0d2a990b 0x525be1ba 0x5cc6daf5
+ 0x4d564f06 0x834d8f94 0xc0c055e1 0xef34557b
+ 0x354537de 0x7207e6b8 0x659c9298 0xa88ac04e
+ 0x80d8014a 0x7f4f6e7b 0x1136e621 0xb1b62f79
+ 0x8d4613ec 0x673699ee 0xdd6d7741 0xdba1ffa9
+ 0xe219e1b3 0x8bf64c21 0x14aadc3b 0xc4dc4e19
+ 0x47ae1e52 0xc5409e4b 0xce8d29d8 0xe0b1cf25
+ 0xcaf06411 0xd5450dcc 0xf14f29ee 0xf3611dd5
+ 0x52bc02f3 0x886b68aa 0x3b2853ef 0x110aafb0
+ 0x6b6d765a 0x87fbaa12 0xc79f134e 0x88b910fb
+ 0xe04aa148 0x33feeccf 0x3be43d3b 0x067854eb
+ 0xf22561e5 0x56c3abc3 0xcf0ff408 0x6291d940
+ 0xe26819d9 0xcfd04da7 0x94ab2808 0x156dcd0a
+ 0xb6d1c47b 0xdca4aa76 0x877f870d 0x4e06ec17
+ 0xbb560b01 0xbe1b62e7 0xd98b51b2 0x7083e3d5
+ 0x427ab621 0xe5fce36f 0x606dc14a 0xe4b70b49
+ 0x982d2446 0xf2d2e82a 0x60836061 0x681317fe
+ 0x1667e3c8 0xf6eef490 0x1ad768d2 0xbc86ae5c
+ 0xfbb392de 0x868caaaf 0x8429b5ff 0x266b6d5b
+ 0x372e8f2e 0x6e875cce 0x3a972f08 0xabddef20
+ 0xc777c559 0xd8f924a4 0xad39137e 0x4c16a4f0
+ 0x91d51877 0xae645599 0x4d09feb1 0x0cdededf
+ 0x5749b5b8 0x513c9745 0xf4da62f7 0x6583b20d
+ 0xb599bb89 0xaf6bea53 0x7275f6b3 0xdefc5092
+ 0x01a3734f 0xd95f4c5f 0x37bce97c 0x63610b99
+ 0x30555fe4 0x20af2f26 0xf84b2652 0x67ef6d87
+ 0x2119805a 0xcc79747f 0xaa479405 0x63a02857
+ 0x1953fc39 0x4f952879 0x886bfe97 0xf0067752
+ 0xa08b5005 0xcd9a5ebb 0xb04486e6 0x560c79ae
+ 0xe8faf52c 0x64a9a961 0xae9a5f1b 0x74cb5ef7
+ 0xf8d0269d 0x2fb63c57 0xd78a9a90 0x99cc0a42
+ 0x46bb0252 0xe56b026b 0xfb5ff703 0xdc8e0588
+ 0xe5d9e280 0xa73ec2b3 0xe21bccb0 0xe22ee743
+ 0xd1bb3217 0x5d4b3f92 0x0a627d8b 0xf2fd974a
+ 0xad0a57c4 0x261ba12e 0x1670f842 0x996ab25d
+ 0xf6f8043d 0xa6cbb362 0xcac3044e 0x6fe01268
+ 0xa54ab676 0x54d7444a 0xf3be5437 0x6b2b737c
+ 0xbe10300c 0xea505599 0xd60a15f6 0xd971ecc0
+ 0x9c480c46 0x2233038d 0x66d38df9 0xcb566912
+ 0x63cffade 0x75811ca6 0x8dbfa4cc 0xee5fc07b
+ 0x23329e49 0x39ee07e5 0x5de33ff1 0x601f8348
+ 0xb60a8bc3 0x832d3660 0xd1bee11b 0x1a38d12c
+ 0xaf00744f 0x21c2639b 0x0fd34252 0xcd63a9f1
+ 0x60f34993 0xf8728afe 0x75f8bb5c 0x74a250ca
+ 0xb9f51490 0x6ac643a6 0x4011a0e5 0x77288317
+ 0x57f772b9 0x92c0715c 0xd5d0e030 0xde335025
+ 0x669f6b14 0x55c74853 0xf3ac7cd5 0x38284e8c
+ 0xb0fda481 0xf9b7f045 0x839293cc 0xdf91a0a0
+ 0x18d20454 0xf73214fc 0x09577b9d 0xb5febd00
+ 0xd9b96c88 0xb454ea2c 0x6204a932 0x736edf8a
+ 0x9724f56e 0x3092f58d 0xac17cced 0x5ae87e39
+ 0x28dd2a0d 0x3806d96f 0x5e7c8c68 0x72df4471
+ 0x0207de38 0xf026ecac 0x13258e9a 0x34a8e8ce
+ 0xdd7d7286 0x8d7553af 0x11ebac36 0xfb9965ff
+ 0x9beda82d 0x1cd898cf 0x1b791830 0xe96ca8f0
+ 0xa0d274d6 0xdd6fea3a 0x7537177f 0xdd93627c
+ 0x60b64e47 0x10f30724 0x12489cf7 0x4587e1ac
+ 0xe7835522 0x61d48d9d 0x6afd081d 0xafbbcf2c
+ 0xe31d79cd 0x49ae4218 0x7c2c4a33 0x4fdf949d
+ 0x52ccd576 0xef2c3d62 0xfd5b75db 0xe6a5c2e9
+ 0x04fc9c6e 0x47fde414 0x8a87ebfa 0x850904e4
+ 0x2f49b552 0xb5f186fd 0x772a4ba3 0x48d0be3c
+ 0x846c7d78 0xc1c2a1d7 0xb9375f9d 0x302ed828
+ 0xf79208f1 0x8fdc4f71 0xc749ed51 0x1cd0c28c
+ 0xee5a5f7e 0x7f02b7ca 0xdc3b531f 0x99c0119d
+ 0x428e5474 0x10515459 0x8d804d27 0xb7c00220
+ 0x264c2695 0x7aa6e5af 0xef807715 0xa444f446
+ 0xe51c7755 0xcd825b6c 0x39afa440 0x88638e46
+ 0x4ea4366d 0xddfc9854 0x99696f2d 0x210592ea
+ 0xf4763dcf 0x7358acdb 0xedfc8523 0xe46031c8
+ 0xc9762414 0xa71a348b 0x084b6c82 0x9162e0d7
+ 0xda6a5b8a 0x68ca14d5 0x6385741f 0xb103d4c2
+ 0x44299ef8 0x9aba89fa 0x2c87dcfd 0x476865df
+ 0x1189dbb2 0xdcd9d19c 0xac2bbd51 0xa71526f5
+ 0x745222d7 0x4813ca98 0xcfa5802c 0x5d2b3907
+ 0x8a17d1b8 0xea56f907 0x3ea58d71 0x933fa242
+ 0x021f46a7 0xab8d4e86 0xfa4eb33e 0xaecbd5c3
+ 0xb3258e74 0xaac9f193 0x415a5518 0x28b13031
+ 0xbae39e53 0x1072fd5a 0x4e0fbf55 0xb02c5d77
+ 0x5949c780 0xbecf72df 0x15e52c72 0x3ffeb165
+ 0xa8e73d50 0xa52fd918 0x2b3c4d7c 0xa1e9e021
+ 0xd8e91949 0x63bf63ed 0x8f2e150a 0x9cbceca9
+ 0x33b10a97 0x4d2c69f7 0xf26371bf 0x0b5214ec
+ 0x10eb7fca 0x1958b429 0x25f190be 0xafcfb396
+ 0x7aec0c45 0xf9a0f163 0x9c966818 0x28f83619
+ 0xe35c61d4 0x1ad8a656 0x576dba63 0x7aa44804
+ 0xf941b7b8 0xc5faf3cc 0xdf1fd628 0xc009417b
+ 0x366ea78d 0xd3cb7030 0xf3f12e97 0x5298cc89
+ 0xbb43c8ef 0xd0a8ef96 0x564bced6 0xbcbd865c
+ 0x5c80b1d7 0x131ccb04 0x7502d06e 0x465f5cb0
+ 0x93320c4c 0x9df42986 0xbdb1fe26 0x48ae8bdd
+ 0xaf44e912 0x6aa468a5 0x67ecbb05 0x30b7c0a5
+ 0x3ad75711 0xa2d5f63c 0x30150058 0x4d748121
+ 0x70804875 0xf46b6ea6 0xa3fcbb7b 0x1af6b4c4
+ 0x48496de1 0xdb1a2321 0x758eb79a 0xf35f697f
+ 0xb4ff9dfa 0x38ab5b31 0xc918f6f1 0xb3a259fb
+ 0x3610afe7 0xdfcaaa0b 0x00c747dc 0x96c40b4a
+ 0x5c815168 0x29198fee 0xc94eeea9 0x70432b55
+ 0x5de7bbd4 0x0995652d 0x4b3e846c 0x7e4c9ca1
+ 0x7c0e91e6 0x401a820e 0x3ca3429a 0xd3812f44
+ 0x9cb6a5eb 0xf03ce395 0xefca548b 0x8943bc10
+ 0x472b2108 0x82d4a386 0x1d0ef931 0x94cd70ef
+ 0x2d00d619 0x40d36f80 0x238ccc47 0xe0856568
+ 0x9f06ad8b 0x95a4052f 0x287a57fb 0x9e9f9891
+ 0x62bc3a31 0x24c3c1f8 0xbabdc3c4 0xfa40629d
+ 0xd16f1f33 0xa9f7600d 0xbcbdb2d9 0x214f24be
+ 0x623ea3b0 0x8d650418 0xe86635b7 0xb834745f
+ 0x20771340 0x3c69a0b2 0x8b7c84cc 0x740e475c
+ 0xe5a540eb 0x9e216852 0x1383201e 0xfbf1f572
+ 0x9680d736 0x3d7f8d69 0x615ea313 0x87bc1297
+ 0xe552725c 0x9bfee104 0xf2e87d90 0xde9188b4
+ 0x028d268b 0x51c75c60 0xed93377f 0xc380d9d9
+ 0xe858bf8c 0x5d0b4a40 0x05a3171f 0x76ae3ec0
+ 0xf86e3fe6 0xc3d78254 0x7cd640c5 0x6835dacb
+ 0x983bd9a8 0x05d1e564 0xc5d5e9b3 0xf81c6560
+ 0x8ecba474 0x071daa33 0xf5010276 0x5432ba59
+ 0x10f2dbc1 0xbe892680 0x7e92d3d7 0x8d2f0113
+ 0x37fa8034 0xb13058f4 0x44684553 0x2bd0e36a
+ 0x67ea83ef 0x815e7115 0x3cd123af 0xd9aec852
+ 0x67c61c95 0x861d068a 0x60c7797e 0xd9733b31
+ 0x9ed29f37 0x1ccc8e08 0x34bcfa7f 0x1c66914d
+ 0xc64dc834 0xad884c08 0x2b22b8de 0x53d6fd78
+ 0x0355dcc8 0xfd363485 0x62370358 0x0dcb046d
+ 0x22fe7d2f 0x5fdd1117 0xccd6d8d1 0xe97925a4
+ 0x309aca3d 0x56c31fb9 0xe6f81e08 0x24fc0560
+ 0xa78d459b 0x4940b35b 0x9a4a2fdb 0x203eafb8
+ 0x91e5fcab 0xfb9be08e 0x9cb903ac 0x31598d89
+ 0x4f41986c 0x77206f4e 0x61811c9d 0xff51d95b
+ 0x2d7b4c66 0x84ceb768 0xfb135597 0x58087b13
+ 0xa1681cc2 0x14009e31 0x778c3fec 0xe3faf2fb
+ 0x5092b2c9 0x8919c362 0x34e2b174 0x7bb04f44
+ 0x63c39b5e 0x8ef696ff 0x2e4c612d 0x77d390e2
+ 0x5dc958a1 0x528bb31a 0x1cb07e7a 0xe37c9c53
+ 0x002856d7 0x6a10b962 0x423a7b39 0xc6da9227
+ 0x207800e9 0xe200c119 0x0e5af6f3 0xfb580459
+ 0x71dc40a0 0x70434cd9 0x13f7f455 0xdf3fd7ca
+ 0x37cbc698 0xf5a5808d 0xa7bfdf32 0x8a0774c7
+ 0x75b67d50 0x5a6908c9 0x23611a6d 0x8b50c483
+ 0xfe1e2eba 0x7ee1c732 0x2191e47f 0x9e63eb3a
+ 0x379cd875 0x4df7258d 0x166a8aa8 0x1c94586a
+ 0x2456c4d3 0x000185fa 0x7a196b46 0x914e789c
+ 0xf562c939 0xb3bad5db 0xc2c19b89 0x8a621ffd
+ 0x0c807ce0 0x701a938f 0x69234cdd 0x36a00f09
+ 0x964c43f7 0xcf71cd85 0x5f504e16 0x446c6388
+ 0x25742397 0xf1a375c8 0x6bcf822c 0x1b175fd7
+ 0x0fe78e56 0xfe7817d6 0x66da0366 0x904e8327
+ 0x5a0749fa 0xef3ede57 0xd0fa2ac8 0x89791771
+ 0xa5cd616f 0xe9ef2860 0x9b533bc3 0x1d746f03
+ 0xf4bb82b5 0xacae0438 0x840b3e34 0x30371a0d
+ 0x8590acf3 0xeb4ff7e4 0x40437052 0xba847bf6
+ 0x24059538 0x44daca63 0x23b32e28 0x091386e0
+ 0xc480e66a 0xe4a839f5 0x34929bcc 0xb9051207
+ 0xd21252f9 0xc6524769 0x8c422851 0x36280aad
+ 0xbf00b1a1 0x4e36c85d 0x7949e8ef 0xf76be57e
+ 0x373a0ab9 0x1b7555a0 0x0c2caf56 0xc9241f75
+ 0xbe5b0ee8 0x5a486f75 0xfb2c050d 0x6aeda464
+ 0x3fa744ee 0xf6e055a1 0x0a7324ab 0xfab58776
+ 0x09baaf66 0x459ce186 0xc6eb1894 0x56a4ce4a
+ 0x58ce1069 0xf4debf5e 0x04a145b9 0x1a246583
+ 0x9b07fe23 0xd4d37068 0x7321e0bf 0x2dfe17f3
+ 0x426dd8a7 0xc561a2d5 0x7f515a47 0xe57d37fa
+ 0xa85f0aa5 0xffb78cd7 0xf30c4551 0x3572c02b
+ 0x6f4a4cbd 0x7322ecc7 0x170a7b9a 0xa1e80d28
+ 0x5a366af2 0x4f24a3a7 0xfefd29ca 0x0d7b02dc
+ 0x1adde2e1 0x5c426cc5 0xb1e53b76 0x5dba2c5c
+ 0x1458b6ca 0x73cea912 0x39626c25 0x7547e76d
+ 0xfcddbb97 0xf03d59ee 0x3cfdab3d 0x309db86e
+ 0x3de8df47 0x4a570e6d 0x09c9579a 0x19ac033e
+ 0x0a7a9a86 0x3662d261 0x048fa67f 0x4aa4009e
+ 0xc7660654 0x524d81f1 0x3157ec52 0x857d1f10
+ 0x3770162e 0x3d1ff919 0x732d2b13 0x84187da0
+ 0x95722d45 0x362cada5 0x5d67637f 0xdaae8465
+ 0x9f5c0699 0xab9aba98 0x6f97d3fa 0xf9cc4120
+ 0x0ca1872c 0x1a832c9e 0x7b74d6ae 0x98dca967
+ 0x03eb7699 0x5fd02b54 0x962c6224 0xde1ab807
+ 0x800af435 0x2458a4ca 0x717de910 0x31648afc
+ 0x871527de 0x3cb93892 0x45237e37 0x446b1315
+ 0xecd807e8 0x70f38e30 0x140dc60e 0xaef7b7c1
+ 0xadec312e 0x94d45820 0xb8960073 0xe8dd5bac
+ 0x7616ab11 0x0c3cc190 0x516003e3 0x323cdb39
+ 0xd679f9f4 0xd7c179d2 0xdfbc5e24 0xaa1226df
+ 0x3cd41b0e 0x88f436f0 0xbd5b6cb1 0xb78c69aa
+ 0x982e0ca0 0x91f852a3 0xb331636a 0x28df67ee
+ 0x81b029a1 0x9e7375e3 0x56e874c0 0x8b93a735
+ 0xa47eaa4e 0x772ad825 0xfb83ba8b 0xc08db79a
+ 0xcb7a34be 0x14214d72 0x7d6fa82e 0xe75c7002
+ 0xa6290902 0x716d04c1 0xc75f0a97 0xb68e0912
+ 0x08b5ef1b 0x507ecac3 0x2d740b08 0x43b6c7bf
+ 0x3965675a 0xf56dc4fd 0x1ba44239 0x36753f70
+ 0x0b2452fc 0xe36bafe9 0xfc3134c3 0x2ac78286
+ 0x69ba53b8 0x225b9bd9 0xaf426f79 0x99bd2d3e
+ 0x0bcb8e18 0x28c87047 0x2045b3b9 0x730ec870
+ 0xe6558839 0x9ca3de82 0x263a41e7 0x1c8ea255
+ 0x334eb3ad 0xc36d6793 0x66add8ee 0x652c8548
+ 0x79dca1a8 0xc2526972 0xd10f03e2 0xdbae6f42
+ 0xe223bf69 0x10082495 0x74ba4cf9 0xeb71ef5f
+ 0xafae5d4e 0x7b3663e9 0x9339468c 0x31edca72
+ 0x65a07876 0xf336fc1a 0xaa505397 0x011d5253
+ 0x99b88ade 0xa688f0fa 0xedac589d 0xab4d8f45
+ 0x0ff866a1 0x61280e9b 0x65c5a63f 0x8b372073
+ 0x7a4c88df 0xc74f7959 0x19597c51 0x97c8a27f
+ 0x33eb652a 0xffd40c86 0x57a2ca0c 0xaabc6cc8
+ 0x54fd2280 0xd5b59006 0x2e00f009 0x72bd86c4
+ 0x24936e04 0x877188de 0x91b60401 0xb949b337
+ 0xdab93e69 0xdffeab2e 0xb3aa7c79 0xb8612f31
+ 0xf0c53b58 0x8896833f 0xda35944a 0x1867027a
+ 0xef6bfce9 0x8213f320 0xac477eb2 0x92368362
+ 0x606cfdc4 0x27c98907 0x50673ac5 0xec48f5f4
+ 0x39e879f8 0x80d050c8 0x9febddbe 0x5d797725
+ 0x06d8b755 0x0319d93d 0x7eae3ce5 0x8963ed64
+ 0xc91772c9 0x4e031095 0x2fd03d3e 0xe774ea89
+ 0x7dbc97ab 0xe8d8f361 0x6e167fa1 0xd1520c5a
+ 0xb3278325 0x8acaf913 0x6ea81dd4 0x9e3b2a97
+ 0x0a5b8a09 0x84000db1 0x59a30fa9 0xf0b6868d
+ 0xfb62b0ed 0x8953057f 0xdbbca3c0 0xc103b876
+ 0x47420e14 0x1eb22bed 0x58c8f65e 0x3a689da6
+ 0x8ed1a99c 0x869ddc49 0x60015d09 0x2264c797
+ 0xdc10c6ac 0x7275327e 0x8d47d2ab 0x87a75624
+ 0x3dd8fcb6 0x40e67a31 0x98114b1f 0x7e3a5976
+ 0x1d9e62a6 0x988c0398 0x0c7c0d8d 0x0aad4954
+ 0x3c40a234 0x7b752b7b 0x79f94813 0xa0b86dec
+ 0xe3f646ac 0xa993f76a 0x6f9d1f99 0xe883dabf
+ 0xb8ab1b2d 0x6766ac8d 0x6b9a793a 0x02f55fa5
+ 0x351a96ad 0xd190f768 0x35667fe0 0x6a85c938
+ 0x72444e33 0x5140a848 0xd3062250 0xe4ce902a
+ 0x44e7d9d3 0x7c8d48fe 0x4d26a61d 0xbd013c4b
+ 0x540d32bb 0x9152cafd 0x09840a30 0xd7a8663a
+ 0xd5a3ca17 0xfd5dbe65 0x655b226f 0x7cb9debc
+ 0x59d300dd 0x13737132 0xdf0d004f 0xe98bbd9e
+ 0x5626fb54 0xb6d66fbd 0x273087a8 0x032969ea
+ 0xbd69c191 0x010cdfff 0xb2a9cea5 0xb8778e4c
+ 0x8f0dd084 0xc75b4ce6 0x9c027c6f 0x36c58105
+ 0xac424eb8 0xa15d2883 0x9e73b7b8 0x54e9aade
+ 0xb9500a5a 0x97505e35 0x4c59b36c 0xb3ad1302
+ 0x31e21ed1 0x78bcd74e 0x2d9fc122 0x49bae35e
+ 0x5c8f01c0 0x8d29829c 0x0c672566 0x37938db5
+ 0x4959e71f 0x0d2365bf 0xaab666b9 0x52b2cffc
+ 0x200ee1f5 0x5dbb262b 0x9aae28df 0x3223780a
+ 0xb65218cd 0x633b797d 0x93f42423 0x3268b3ae
+ 0x141e506e 0xb1ed94b2 0x497b7973 0x9f2db9f6
+ 0x5260bf9d 0xb30e4310 0x4a3539ec 0x275d2ae2
+ 0xff43e500 0x645e30e5 0xf1527598 0xb76ec4cf
+ 0x88fc44e9 0xde68932c 0xe61aff6b 0x19d042b6
+ 0x11981ff8 0xb0d595d9 0x52764f82 0x7e0ca214
+ 0x8cc51237 0x581f2a1a 0x482420b3 0xd47ff971
+ 0xcff78344 0xc019eca7 0x3146ab02 0x107a3ee4
+ 0x16dc120d 0x33a239ec 0x0ea84236 0xebc7a1f4
+ 0xd1f2fa2a 0x9464c008 0x2b76a4fd 0x9b4acb99
+ 0x00f6a92a 0xd68b8d15 0x25e1e58d 0xe1fe3cd1
+ 0x6fbce2cd 0xf78be2dd 0x09b9c08d 0x6b32d210
+ 0xd06e7c95 0xd62f47f4 0x92c717ca 0x44fe3d2d
+ 0xaa13cc08 0x3d411f94 0xc2eba262 0x7521c9e4
+ 0x77d6cdc7 0x22d76158 0xca2efacf 0x3e51004c
+ 0xef9a82d6 0x1508d20c 0x923f18ff 0x3eaa88e6
+ 0xf2f32bc7 0xe74b8483 0x82529884 0x58b38ad8
+ 0xdd9f2a5f 0xdf54adc3 0xd4497667 0x789c000b
+ 0x935d1743 0xa52d5f1a 0x4e27adf6 0x5c3334af
+ 0x6cf71ba0 0x501f8353 0x031fd6cd 0x4831ec4f
+ 0x08c847db 0x6a6e0657 0x0bd803d4 0xd7c48cfe
+ 0x94b7e25f 0xc6516ebe 0x1001c08a 0x0e165da9
+ 0x4e39605f 0xe3f3637a 0x013daae9 0x217168b0
+ 0x6013ab5f 0xd5b7eb97 0x8ce6b6ef 0xc4259f29
+ 0x470e90a9 0x7a254ff5 0x8dcbf841 0xa2541a7f
+ 0x4880c5ea 0x28c750ea 0x043a0200 0xbeb9653c
+ 0x46e354d1 0x64f7104e 0x05a64bf3 0x7db42752
+ 0xbbd38c7b 0xca7da1d9 0x916c7ebf 0x1df5e3e1
+ 0xef0897f5 0xd0456a5c 0x629b50a3 0x8caefdc3
+ 0xddbf8b94 0xf6e6b341 0xd8ce3e02 0x27c96419
+ 0xb2659ab5 0xe8d576df 0x9f136353 0x6f5230f5
+ 0x68417adc 0x39b65378 0x4b742f21 0x96d071b1
+ 0xeb046da9 0x245ecb46 0xc17eeec3 0xd7c56615
+ 0x07df9b8c 0x647ee4f4 0xf15f7e7b 0x825b87eb
+ 0xdc67dd20 0x43c38867 0x977868ca 0x3a299ef2
+ 0xa75073f7 0x2dcd59e6 0xc6c78c75 0x63a00767
+ 0x74dfba2d 0x7880c7da 0x83f72bc6 0xa9750166
+ 0x716b3abe 0xc949a1ea 0x7e5fc036 0x574ee475
+ 0x39c3cae9 0x8c1dacdb 0x640fcc41 0xc69437e8
+ 0x5d33a950 0xa28e483a 0x4031cf9b 0x0007e3be
+ 0x6e3f277f 0xe25d3025 0xdcbc4a0a 0x7451a537
+ 0xb372169f 0x21ff0e91 0x1978aa74 0x6471624e
+ 0x01a03f20 0xeb391a3c 0x70d18ad5 0x47c9ddcf
+ 0xd9415b2f 0xd9ea29ce 0xffa0677e 0xeff7a04d
+ 0x1d384ff4 0x66195704 0x22736810 0xad754f27
+ 0x782ae9bb 0xffed05b6 0x5ae3f21d 0x5eb2c577
+ 0x0101cf91 0xed0322ad 0x56ac50c8 0xc513b1c6
+ 0x4f62ba8b 0xbaffd6b6 0x6649baa2 0x8702464e
+ 0x78947007 0xd6e97d6e 0xde7c6abf 0x2bdee498
+ 0xcee1db1a 0xb98149de 0x47f32f5c 0xc6c354fc
+ 0x6e148fad 0xb343cf2f 0xeac6a9f0 0x33dd1560
+ 0x923403bb 0x87d6e292 0x0b1cf653 0xe8b76402
+ 0x5f21a955 0x236dec28 0x214663fd 0x1917539e
+ 0x3f11ce80 0x1bb35a2c 0x38a358f1 0x15f67224
+ 0xc65394f9 0x63cd4887 0xe8e73d2b 0x51b6204a
+ 0x8eeae8f5 0x6e071c8f 0x55c23dca 0x4862eaee
+ 0x0afa0037 0xc98446f3 0x09181a1c 0x41e46e02
+ 0xcf13d6b9 0x85907776 0x30116b18 0x27b8c7b1
+ 0xd153a5ce 0xc95c90b2 0x34392718 0x8103dbe4
+ 0xe012a7be 0x6aeb8c6a 0x5bbaddbe 0x221eab21
+ 0xaf769239 0x2621a689 0xe8c41061 0x5890f76b
+ 0x2c4dadd4 0x2ad2e669 0x394209b5 0xb272b2ef
+ 0x560031cb 0x4ab7be9c 0xcc5e92e4 0xc0de0667
+ 0x7a39cf63 0x03482c6e 0xd653de11 0xe14466e1
+ 0xf2dbaf25 0xc34d1c0c 0x03eeb3e3 0x8260874f
+ 0xf6e2ef37 0x13626fba 0x15b7efe4 0x069cd153
+ 0xbf631788 0x797668a9 0x724d831a 0x0ceeb589
+ 0x9559cd31 0xb995d2d2 0x7564c4ef 0xfc45a3dc
+ 0x1cd999e3 0xbe090229 0xab4f9383 0x879156a0
+ 0x06e1d37b 0x3796487a 0xaf1e3884 0x1f9a59ef
+ 0x6c2d8a7b 0x0a8a5ffc 0x4cd60f03 0xa60bfc63
+ 0xf67c6872 0xf19b75cf 0x041cc864 0xc563566f
+ 0x58ae88a0 0x3747b0c1 0x64cd86fa 0xed185c5a
+ 0xb71533c9 0xf15672fa 0x2722d209 0xb71ec7d7
+ 0x3143a8a5 0x61c18934 0x3a899ec5 0x4274f336
+ 0xea7c52a9 0x9193cd11 0x44c471e7 0x57fff360
+ 0x53923783 0x76d57ce6 0xbff32513 0x4dbe0d39
+ 0xb9f80483 0x62ce4d25 0x5941e9fb 0x7dfedfe1
+ 0xa33f9130 0x336e6539 0x1de31e79 0xb6855a41
+ 0x4db2db67 0x02a9f1ed 0x019bcf20 0x53ad0ce3
+ 0x4d049f95 0xa9de2c6f 0xa26f6997 0x28eafacb
+ 0xa5220548 0xb4675e1b 0xe776ee88 0xc93e6c37
+ 0x7868630d 0x1690625e 0x6eba0fd4 0x78f598ff
+ 0x113fa1b7 0xcb025590 0x2ee34123 0x92241df5
+ 0x6edbf0b2 0x3bc2e0a7 0x710ce59f 0x656f0eb7
+ 0xa598424e 0xeca53268 0xb6a44542 0x5bf6674f
+ 0xad483960 0x35290b93 0xfba74c81 0x78141ea2
+ 0xd6baf9e7 0x8e5a08e6 0x4910c5b0 0x7b140d21
+ 0x1958c79e 0x0dbed125 0xcfbe41dc 0x089fc4ab
+ 0xbf014fa7 0xff961610 0x7a2ae6c3 0x560d3a9c
+ 0x2cd77620 0x3a7c15cb 0x9464d8f1 0x249a93ff
+ 0x96fe6c56 0x7231a31c 0x4bcdadd7 0x62edd9f4
+ 0x8ad1916c 0x3a5fbc8d 0x2a2ccd7a 0x558980b1
+ 0xb0137cfa 0x3cae6929 0x587c349c 0xbcfee701
+ 0xbddd49df 0xa0da6dbe 0x4cb03dac 0x5f84ba2d
+ 0x7fb3063c 0x66de2150 0xbf7dbcf2 0x1c0892aa
+ 0x4be8b0ae 0x5d9845ab 0xa21455af 0xc42f2e68
+ 0x9b6f438f 0x5eaf4941 0xabbf9079 0x94984a47
+ 0x542bdea4 0x34cf3d67 0x854010a4 0xf39a9b19
+ 0xd25ffb6a 0x04364e75 0x0af97ef8 0xe10e3620
+ 0x2184d002 0x0c0ca683 0xc19963c6 0x4c428d15
+ 0x47ae4151 0xd11ea57c 0x437a9ed6 0x50a6b8a2
+ 0x141b16e9 0xeb4ae873 0xb51180fa 0xe3dc318d
+ 0x7744a06f 0x64d297d2 0x845fac66 0x5854d172
+ 0xc14dbe9d 0xccba053f 0x4620a715 0x405d728f
+ 0x28b86cec 0xcba09cdc 0x92823f94 0xeae2664c
+ 0x48eda6ae 0x4b60f5f6 0x1772f309 0x8af285bf
+ 0x9c3ae474 0x13149ebf 0x2bc835c2 0xafcaa560
+ 0xc11b6f91 0x94861d9a 0x089c0d82 0x1e04d66d
+ 0xf0e497fb 0x6b2d8b6a 0x9d7f0cae 0x4a93ba71
+ 0x1c006123 0xed4b5f75 0x76e7826d 0x4f884ba9
+ 0xbba28011 0x1e275278 0xfa72461d 0x7e70e215
+ 0x1427ba3c 0x467e4f3c 0x781c5f92 0x357b7951
+ 0x9de2cce4 0x524a0de6 0x12e15f95 0x7b64fae0
+ 0xf27e93cf 0xc6f48158 0x9b71dbd6 0x081dc1b3
+ 0x47c9c2c8 0xf110add7 0x7881b556 0x0404bf1c
+ 0x58e7d936 0x04442173 0xe1e7f0cc 0x128ce897
+ 0x169c0a11 0xf30b5575 0xf2ac0bab 0x91515620
+ 0xe8b809b0 0x2a73d5a0 0x9ed32dae 0xcf943a47
+ 0xfc157bf9 0x1a53054d 0xf0657e2f 0xf39f6ea7
+ 0x92a5834a 0xcdca0c13 0x40a7b40e 0xba0e0cdd
+ 0x72f595c3 0x6b7eeaf3 0x4d0fd8ed 0x9a856082
+ 0xd75402c8 0xe0f8d3b9 0xee57a2a5 0xe1ccf4a7
+ 0xa4fc4fa6 0x9f2407c7 0x75f94c0e 0xbf2361de
+ 0x2d3b4782 0x72c35e50 0xb97f7d4e 0xbc880223
+ 0xb0b24073 0x08931201 0x40e0d18b 0x559db40c
+ 0x6216a921 0x031a379c 0x29bff1ac 0x1c522c12
+ 0x583bfe94 0x2519ba2a 0xd691d08e 0x905dc62f
+ 0x43b421b0 0xd45caaa0 0x5f099da2 0x012fc4a5
+ 0x509712b3 0x67e5d441 0xc843de50 0x7e1c756f
+ 0x91368900 0xc6ec0dd4 0xa41e838f 0x58eabda5
+ 0xd6ad78a9 0xa037b655 0x8af4e767 0xa9b95900
+ 0xdcf1780e 0x64e28d82 0x215ad981 0x292dfcc3
+ 0x708d8557 0x0a507562 0x486022ad 0x8165bc7e
+ 0xabffce1d 0x78fbe480 0x77b916f6 0x88f8167d
+ 0xae8b8edb 0x62698ab6 0xdbc6bbbd 0x001819a6
+ 0x8c096fb3 0x40a121e9 0x7b96a718 0xf6d256ed
+ 0xe5c0a484 0xa09bd764 0x6552b5a2 0x1847ae3f
+ 0x0669a650 0xccabc209 0x85246d20 0x61158f3c
+ 0x379d8086 0x02135988 0x1eccc6db 0xf8f38c67
+ 0x8e1b0f3d 0x0f6e87e5 0x936bbb84 0xe04839eb
+ 0xe26b3e5c 0x3f35ffda 0x4920e752 0x014c876a
+ 0x25189061 0xbe2bc4ec 0xbb2ca0f2 0xe2c1c9b0
+ 0x747df643 0x26da8dbd 0xdacc3c8a 0x7d93b22a
+ 0x922d9a0a 0xf82d65b6 0xd56e5f35 0x7aea7534
+ 0xf1808648 0xdfa7ec9a 0xff00f8c6 0x69091da7
+ 0xbb478c83 0x64e24ae6 0xf2371faf 0xcff5732a
+ 0x4da88e73 0x9c8494df 0x4c0da767 0x3e22bd67
+ 0x059298eb 0x9d7611ce 0x74b4a198 0xbcbe440c
+ 0xe2bb1a9f 0x0ba3e5f7 0x65a5cf9c 0x8b24b6f4
+ 0x7784ca5c 0x24ffc234 0xece71bbd 0x36f8e876
+ 0x1b55d68b 0x2b9163a5 0xaf8be424 0x958eeaef
+ 0x5d711c41 0x66d11cbe 0xfce42868 0x4a3c819c
+ 0xf66d295c 0x629402f7 0x64b2ee3d 0xc0b74538
+ 0xe93a735d 0x3b9e807f 0xd1d0d7c8 0x69588f34
+ 0xae92b6fe 0xf5508d03 0x45b6ccd6 0xf85a18c6
+ 0xe1a28a53 0x438f9a35 0xf4fe84dd 0xe3f95791
+ 0x16860340 0xefe72aee 0xb13575c6 0x3d730481
+ 0x3cf2a43e 0xa6ed239e 0xd7529176 0x8ad63f3f
+ 0x5efe8f4d 0xe9cad7df 0x44fefef4 0xc7198f50
+ 0x85aabf5c 0x15c175c2 0x26f7a0cf 0xf06782f0
+ 0x4dfadfa7 0xbc57a087 0x21406f0b 0x692a8f18
+ 0xd17a358b 0x19d1b2a6 0x6c35022e 0x87d8c987
+ 0xe7f2d06c 0x91c4daa6 0x4a132822 0x1e864671
+ 0x5cbf0c4d 0x6a34f073 0x1c87a8e5 0xb38f1717
+ 0x1cac430b 0xf733ee6e 0xdf73201f 0x71026328
+ 0xee976531 0x661c9d28 0xdeefcd7f 0xdefb4607
+ 0xfca9ef3a 0x3e1b9b38 0xd204c892 0x6b059f5f
+ 0xd5b8665f 0x4eec24fd 0x09b21b40 0x364c708c
+ 0xebe0d543 0xc3d64eed 0x8facb895 0x8f415f31
+ 0x3dd25b0b 0x95f4072e 0x85e6f4c1 0x3345e2a5
+ 0xa56e8dcf 0x3ed8df67 0xa8194a81 0xafe613c7
+ 0x384b25b9 0xe7661836 0x5ad6476d 0xeb0ae982
+ 0x19afdf2f 0x4efb8658 0xff07e358 0x96c469d2
+ 0xf3030add 0xf5bf5b51 0xba03b24c 0xcb77143f
+ 0x134fba20 0xa126558a 0x193cd220 0x48f43727
+ 0x156f2b18 0x4e599917 0xc3ac4eac 0xcc460648
+ 0x67974a2a 0xe2917a7a 0x02998a74 0x470c60d1
+ 0xbacbc868 0xfef38d84 0x3e4597a9 0xa1723ab7
+ 0x8ffed7b2 0xe489b151 0x34b982fa 0xf67bf8ce
+ 0x043cbb33 0xe3927c98 0x3c8fb221 0xbff0644a
+ 0x886d333c 0x1f4cd6b7 0xe9b744f0 0x443ef364
+ 0x04847d65 0xf3c2ba04 0x60a8e656 0xab4dca06
+ 0x620dbf22 0x5b0221e5 0x877973ab 0x128b5a6a
+ 0x4696b5d7 0x8f034e85 0x18796215 0x8579ec7c
+ 0xf8917eae 0xa98bffce 0xfc67e9de 0xa897445e
+ 0x2f115777 0x990bfb90 0x1de53f71 0xfa2e5c1f
+ 0x24a5b882 0x0f871a5b 0xe7fc33a0 0x6927a106
+ 0xb210bc90 0x2ef851de 0x09629147 0x2553882d
+ 0x77393353 0xeacf977e 0x470198f7 0xb7564a05
+ 0x4d575fb4 0x1d980371 0x0feeebba 0x26ba3c12
+ 0x17b21567 0xfb664d1d 0xcee1a603 0xa8881580
+ 0x8a47e853 0x6511027f 0x734f6fd7 0x2977b345
+ 0x7465e47c 0x0e3c4c8c 0x3185ac04 0x2450ea5d
+ 0xa6e97dba 0xf52b2f4b 0x328ac24f 0x5a507ad2
+ 0xac05d4f7 0xca332e1e 0x44b6cdd5 0xe22b049b
+ 0x55b885d1 0x71144ba1 0xf57284d9 0x76cb0900
+ 0x8266cfae 0x82bb0271 0xfe547080 0x53e4dac9
+ 0x0546dcb9 0xa09a8de0 0xd55d15a9 0x7a3a96ad
+ 0xd23c33ed 0x7a8fa769 0xa0542b10 0xdaf92f2c
+ 0xd6433b0e 0xad7cf7b9 0x72c54814 0x38ff5c07
+ 0xddee72d7 0x6c29582d 0xa1574da8 0x418272ea
+ 0x0a9e21f3 0xa34bb5ea 0x1e78630b 0x9238d5d2
+ 0x7cfa682f 0x6e8e841b 0xa4b3d17d 0x70b6d075
+ 0x704db3f8 0x76aa7d19 0x1cd3e85b 0x2ae7fa63
+ 0x5ff0dad0 0xdd92c129 0xce7d884a 0xa7ba03ab
+ 0x3b366560 0xfeaf75c5 0xd08856c3 0x01ffbced
+ 0x089aa8a3 0x2e4b36f1 0x03955648 0x882468ba
+ 0x534abc87 0x28c08402 0xa7512f6a 0x1fab044e
+ 0x6595e159 0x92fdef27 0xa0b6093a 0x5fdb5f3e
+ 0xd0facb7d 0x512a8b83 0xd7f31adc 0x82166318
+ 0xf9ad7f02 0x9120b349 0xab744947 0x2787d6bf
+ 0x489e3546 0x02a7ce3b 0xd3812409 0x819a092d
+ 0x94a48db8 0x49d8dff3 0xdd4e9b5f 0x330d32d0
+ 0x203cad0d 0xace20075 0xfd019f42 0x1cc56871
+ 0xe53e452b 0x51e7c9e6 0x1d6732c7 0x03694ca7
+ 0x900ecdb4 0x3251d119 0x2c4a0669 0x3243bb5e
+ 0xb434326f 0xd6eb26b8 0x8ceb7328 0xff30d7e3
+ 0x861fa43d 0x15386557 0x3fa11d24 0x86590299
+ 0xc3cbd319 0x8d1031a5 0x80db9f63 0x9d957321
+ 0xdec927f4 0x1468a2a1 0xff1b8842 0x4c403eed
+ 0x62140459 0x912ddd25 0x36252404 0x49052d26
+ 0x22205558 0x53773ca0 0x3428d400 0x51002834
+ 0x6b5baa18 0x838bcf14 0x30d09ce0 0xf1c456bd
+ 0xb1fc90c1 0x525dbb0f 0x64a9105e 0xe0a5cc89
+ 0x293f2441 0x335b1c7d 0x55842eff 0x6c7f60dc
+ 0x903fd793 0x868589ef 0x50a596a6 0x337c6988
+ 0xb7a670a9 0xa46b1a8d 0xdf8c013c 0x3dcdfd02
+ 0x01075847 0x06c3a7e6 0xc8f22594 0xfcd94f04
+ 0x8b6ddbbb 0x5a138f6a 0xf43d2cca 0xcf4df232
+ 0x088cddf4 0x9adce26d 0xee803f2c 0xedf042d5
+ 0x7d738c39 0x8f02cc34 0x3f964043 0xbfae17d7
+ 0x5f2dd670 0x177a9f36 0xf0e1dc28 0x07082ed9
+ 0x90534419 0xf03db66a 0xb8ccbbbf 0x739d2ae4
+ 0x3509b32d 0xf0105125 0x2d603572 0xbd1a6b64
+ 0x50959fe9 0x26100668 0x758e250c 0x9b372d1b
+ 0x0f1e1bde 0xd53edd46 0x0187d6e6 0xd0158da6
+ 0x05dd0922 0x3fc0a182 0xd7f70ebd 0xeeda22e1
+ 0x1c7f99ad 0x9b39bee9 0xf101d67c 0x1ffea21d
+ 0x5494b799 0x787a77ca 0xe8908c34 0xdd00d1db
+ 0x25e21bcc 0x30bf0b70 0xd8cd0350 0x96f2d414
+ 0xa9a4cb6d 0xa3f3c207 0x2db5c7bf 0x88e8837b
+ 0xb157189a 0xb9fb869e 0x48c2a7b3 0xf5e0c692
+ 0xf9103c12 0x6c590e9a 0x7e0aac34 0x97392b87
+ 0x8e6c201b 0xc6d68ddb 0xb5fbaf0a 0x1f8e411f
+ 0x6355e9d9 0x05fcca55 0x9b0250dc 0xec9c5d7d
+ 0x668075bd 0xb93078f1 0xcefa1755 0x216c5e0c
+ 0xa83ae6b5 0x748bff79 0xfee9e797 0xc6acb230
+ 0x1243bc06 0xfee350e0 0x3ee5f8e0 0x0508fb60
+ 0x87d9d24d 0x0b54ac94 0xfc37c8fc 0xe9958f2f
+ 0x3a927f73 0x04933b6a 0xa195a6dd 0xda96dca3
+ 0x9c1799c4 0xd055fc63 0x05deebbd 0x2b5400fb
+ 0xf157f110 0x80b1e79a 0xd7f1e4b7 0x5a1fab0d
+ 0xbaaa81c3 0xa42489e8 0x594a791a 0x29f18382
+ 0xe86f0358 0x5aa5f4b0 0xa682993b 0xedbfc5b7
+ 0xf1eac55d 0x9b1716bc 0x907d9d1e 0xb2205254
+ 0x4fbba0f3 0xacea63a4 0xc518d83b 0x8449fef8
+ 0x80b4f69b 0x95dc7429 0x16c22c9b 0x6e116239
+ 0x4c4bfd11 0x56f159fa 0x60cbb0a5 0xa2f4721f
+ 0xa829cf9b 0x5ddbb3af 0x2db824cf 0xe82f3fd1
+ 0xe5dcb2db 0x185fe7af 0x0775003d 0x38669aba
+ 0x7b540eea 0x94ce3d10 0xba77f357 0x63507853
+ 0xb50ebb0c 0xb614739b 0xea3a3c47 0xf2b6176a
+ 0xf805b28d 0xdd0819b7 0x9f4b2799 0x18bdadb8
+ 0x7d58d588 0xc4f0994a 0xef834870 0xef2d6ce4
+ 0x97a36a52 0xb6e581e6 0xddd9aa9b 0x6437d4e8
+ 0x43f74dc5 0x8cbbd744 0xf394a2a0 0x4a1e7f75
+ 0x395bd36f 0x27a8f9e9 0xed62f4a5 0x7c2f0484
+ 0xf394f837 0x5f69d50e 0x86ef57af 0x7af052f0
+ 0x85dee180 0x125f56fa 0x87291494 0x141931ac
+ 0xabca9ae0 0xbc1e4e4d 0x541e2edf 0xa3551bb4
+ 0xed2766fd 0xf6e778c2 0x3a82644f 0x67c47659
+ 0xb81b826c 0xb11603ee 0xba6cc507 0x691fdb74
+ 0x06507f6e 0x64ef2a0f 0xebd9b51d 0xee620487
+ 0x82991d7c 0x1493fed5 0x08af819e 0x7066de45
+ 0xdeee1600 0xde12b903 0xe572ced5 0x81b897be
+ 0x458d0db8 0xc9970232 0x7402dd05 0x44e1c70c
+ 0x1619441f 0x9ea0c392 0x1d13c3dc 0x34737cbb
+ 0xe1d726e1 0xbe7d749d 0x304892a5 0x71c7bb33
+ 0x608bb696 0xd334cfd7 0x862e360e 0x868757ad
+ 0xb7d8aa70 0x81031f5e 0xdb64b80c 0x954ff4c1
+ 0x5c66d432 0x08c77a67 0xd5e298af 0xb6074be1
+ 0xd687a163 0xac2fd525 0x14e6ab5a 0x6ca4232d
+ 0x8a921092 0x0a19e936 0xd4464ee4 0x0da28777
+ 0x6b6d4131 0x975111bc 0x3f26afae 0x5a6faf38
+ 0x867d7956 0x554aa8be 0xf9898211 0x3afcde65
+ 0x493dac6c 0x61d901b2 0xbaf3e9fe 0x2a3758fa
+ 0xc2ad3ee4 0x97d13dad 0xe84b02f9 0xaaf5ca63
+ 0x41a94864 0x6d7b71be 0xd843e866 0x83c3193b
+ 0x972d4bbf 0x55c3a234 0x0d03b540 0x53396a64
+ 0x98b5c0f3 0x36708484 0x38363c7a 0x0076dbf8
+ 0x5edbd01a 0xf6e835d6 0xccb95e4f 0x2bd2907e
+ 0x210f9312 0xf4ec9221 0x343697d6 0x3913cd41
+ 0xb02ced20 0xba991ee5 0x09c7893c 0x749da3c0
+ 0x46e5ad3b 0x871b685d 0x02358659 0xca76706d
+ 0xe61524a2 0xf46ac4a9 0x4f6c9e19 0x68a86d0c
+ 0x9d16bc4f 0xa9157a1f 0x830993b8 0x3738896c
+ 0x7c821db5 0x02de8542 0xb17e3767 0x455a0b40
+ 0x19b707eb 0xed81e63d 0x568e1e36 0xbf5cee00
+ 0xaa12957f 0x67f65ecd 0xb940789c 0x0ab3bab8
+ 0xd7e3a789 0x777b64ba 0x4e00d3be 0x46887a34
+ 0x08f0127f 0xf5027e8f 0x9cdb4671 0xb7a7eac4
+ 0x9be5cfb5 0xb1f57dbd 0xbce97b11 0x41525f56
+ 0x5e847d16 0xf71585b3 0x1ce5047b 0x1bc2fa00
+ 0x860aa4ca 0xf97ee77d 0xe7843ee6 0xf07bd865
+ 0xfa059452 0x58a59ce9 0x24f03b1b 0xd18a52c2
+ 0x180426ab 0x2ced0003 0x399234cd 0xe43f91e9
+ 0xa0516a92 0x8088d598 0xc3a41365 0xd1f044ef
+ 0xfb3808f9 0x1770e594 0xf96c4185 0xc6b67b9f
+ 0x5c01c703 0x65c6ef8d 0xd49310f3 0x0f962bd1
+ 0xfb3c96f1 0x4d501516 0xa09beeb5 0xce9df639
+ 0xf792c71f 0x392b420d 0xc03c9099 0xcab5dc42
+ 0xbdfea308 0x84c80c32 0xcd66ec3f 0x68932191
+ 0x62b69b08 0xcacb4a8b 0x0415feff 0x84673edf
+ 0xe61b5ff3 0x6107a18e 0x6a7a206b 0xed64aa34
+ 0x1bbaef36 0x22a3f0fa 0xb0945c72 0xd1a7f7f8
+ 0x65fd1b29 0xa34d99a9 0xb6f2ea53 0x055ab055
+ 0x433c3eb2 0xe591d68b 0xcabb8a71 0xfb055c2e
+ 0x37e1efec 0x558fd45e 0xa5358766 0xe0c450f3
+ 0x78ed3061 0x8713e084 0x4b0d2ec4 0x24feb10e
+ 0x6689fc4e 0x0c83f1c9 0x7490df57 0x00d618bc
+ 0x2c510caa 0xc5e2838a 0xcfae6669 0xdc2fa4b0
+ 0xa4569e3e 0xcee095c4 0xcb5f42ee 0xdc11393f
+ 0x69f1c5aa 0xa495fae6 0x64c53ea4 0x4477aeb8
+ 0x2ff43cef 0x660aa186 0x5dec9e67 0xa59f6aab
+ 0x51504061 0x28279b5a 0x4e245278 0xdbf53c73
+ 0x01a77ff9 0x7d771730 0xa8d19fc6 0xce3697dd
+ 0xecc405d8 0x22f1872a 0x683afa3f 0x725f7e03
+ 0x14c7acb2 0x845efb20 0xf3e03095 0x8c9a7d04
+ 0xa9f115d3 0xb93fa8ef 0xd2e78a32 0x91e3cc61
+ 0x805d48de 0xc9fcc672 0x225d36f0 0xb32e7627
+ 0x11b7a585 0xa7321798 0x9b40640f 0x0c3a6b7f
+ 0x3337c762 0xbbe54bb3 0xc8316a84 0x0d487a67
+ 0xa6d6b86b 0xd1fb2b92 0x15805dfe 0x5cd49b21
+ 0x9855f2c2 0x74e2a195 0xbdc0729f 0x29f680a9
+ 0x092f47ad 0x0e7091d1 0x6e7d2020 0x0a7b5d47
+ 0xc9c4065b 0xc4cacd97 0xcd7b4071 0x7986cc7a
+ 0xb1c29ef5 0x47ced57d 0xc08a8b40 0x12102685
+ 0x685caae1 0x1ebf3635 0xdfe6af15 0x8a0496f4
+ 0xb9c07f19 0x1f62a68f 0x0133de0a 0x993017d9
+ 0xd0553b5c 0x0c8f1311 0x7d979028 0x6001db26
+ 0x1caf7ffd 0x76ced0cf 0xc33d3f23 0x9fc27423
+ 0x235fc137 0xf85a079b 0x78174474 0x1d15b725
+ 0x20162abf 0x62e0712d 0xa03f9cf0 0x0f4ff140
+ 0xaa389d0d 0xd58e1171 0x8f5d21f4 0x3ad5b3c4
+ 0x03003b51 0x49b29d4f 0xa3d82796 0x9c7f3391
+ 0xe34de3a8 0xab75e6f4 0x3f06b52d 0xb8092f83
+ 0x01f14341 0x929a3b8a 0xa630aa03 0x4b7e055e
+ 0x90b06e58 0xeaf2ad79 0xe8c5b756 0xf46f44e3
+ 0x6693ff09 0x499d2790 0xd0d81c69 0x72d7a2bd
+ 0x794d242b 0x9be19084 0xddd51a72 0xf4f60698
+ 0xd1747d6a 0x24dc87dd 0x78ba7af6 0x548b43d0
+ 0xa2b03ee8 0x100ef53b 0xe836488a 0xf4b9a443
+ 0x41d61bdc 0xee4bedb1 0x8f0ec0b0 0xc0125983
+ 0xaa919a7f 0x6677db37 0x78e7d366 0xc7bef834
+ 0x967a54e7 0x5f78951a 0xc0fddf1f 0xbd5cf29a
+ 0x3fa13be8 0xca67a695 0xc13e8c23 0xaff54342
+ 0x94f4bc22 0x85512c06 0x1439cd71 0x7d13b7b5
+ 0x76f8bd59 0xffe02871 0xbd88ccb1 0x2597d721
+ 0x80a52e2e 0x1f696120 0x689e73aa 0x7d085fa0
+ 0x0e183650 0xe041d3fb 0x5a340dd0 0x26a6c10c
+ 0xe6fef6d0 0xdb18b3b8 0x2fc6df63 0xfa695c57
+ 0xfb3e6a3a 0x64fb412f 0xc1cf1e32 0x6edd945f
+ 0xcee44d66 0xdfb2ec8c 0x5eb84515 0x177f031b
+ 0x56a9db8a 0x0e247577 0x99004862 0xa5805854
+ 0x04b1afc9 0x9c649998 0x908a1424 0xb595099b
+ 0xb91fb0ce 0x8c4bdd8a 0x78de806e 0x65ff3cba
+ 0xb66aeda0 0xe22d3592 0x7c0cdebf 0xc15c0853
+ 0x80f31d27 0x84dfc7ed 0xc96a5992 0x939b3d6c
+ 0xf0ffac53 0xe4be269e 0x4d56d528 0xb0477318
+ 0x40a4b528 0xd938f1bb 0x2b25a6c2 0xc93b3c9f
+ 0x179c9571 0x999c2e91 0xe7280616 0xee6e0481
+ 0xc30eae2a 0x7d6f0458 0x0b7a52ff 0xd44e0a23
+ 0x81d661ee 0x9d0f857b 0xe7fa9d18 0xd499cb85
+ 0x4e27e30a 0xd51d1f9a 0x14195d32 0xccca7d6e
+ 0xc1703a6e 0x15664170 0x7f51c821 0xf1363619
+ 0x37dc27f5 0x6aea6223 0xd574e44c 0x4b683223
+ 0x4135ad1a 0x7694390a 0x0bf4bddf 0x9522f11b
+ 0xc20797be 0x45fb151e 0x96f2a952 0xedfd5f2c
+ 0xdfbcac7f 0x58f5dba6 0x68204d0d 0x52eeb34a
+ 0x8313fd8b 0xda2f1243 0x195a1479 0x19bb2970
+ 0x1c2131e5 0x6841c28c 0x1ec33cfd 0xd3e489de
+ 0xd9b70b18 0x81503d32 0x9642a53e 0x02470015
+ 0xb8d1087f 0x4b629e77 0xd7ec9ee0 0x795ffd91
+ 0xcfa71aeb 0x4bae649a 0x7f768123 0x69f501d5
+ 0x56c19a0c 0x4bfaac57 0x90ea664a 0x4d428e1a
+ 0xaee71c90 0x198fc316 0x549f5572 0x07a22e58
+ 0xe8f444e3 0xedc7fc23 0xe96c1595 0xc4bdad06
+ 0x751a3df5 0x3bc4fba4 0x58cd19b3 0x3665000a
+ 0xe4371d96 0x6c50d4e6 0x5d1d6a57 0xf130eabf
+ 0x48fd82ad 0x42a8bee8 0x71f89c32 0x95fba6dc
+ 0x9150b601 0x72c361b0 0x71a3c317 0x149614f9
+ 0x224e67fa 0xf6a3fea9 0x5461cefa 0x367bc566
+ 0x2226ee83 0xaa13e83f 0x8d7dc705 0x417c7afd
+ 0x8a0f2e17 0xbb4003df 0xd1c27124 0xaaaede8d
+ 0xd4ed5bcd 0xd0102aa8 0x3b519bfa 0xb82d6932
+ 0x50b8f966 0xec685a1d 0xffb18b64 0x538955b2
+ 0xac4b6cf1 0x0a86d32f 0x34e4cc05 0x02adcf17
+ 0x7c80379f 0xcfb5bcb5 0x842190e7 0x8348cd1f
+ 0xabf77742 0x3332866f 0xa56fb2e6 0x6c1fec47
+ 0xf2fbb22c 0x7230d805 0xed17d8f5 0x3426e157
+ 0x1d045cb2 0x6c1e349f 0x3a6116ca 0x4baf0bdb
+ 0xab68daad 0xc4867466 0x7bb15fd9 0x707a6a1a
+ 0x83157678 0x277cffd1 0x8d48e5d2 0xf829bd6d
+ 0x1fd2750e 0xb6bb8854 0x66d0a20a 0x38f47b92
+ 0xa3568b90 0x0d091e16 0x65a8245b 0x238e4299
+ 0xd0bc6bbe 0x8ef67730 0xf976b632 0x326d9d24
+ 0x96833335 0x1d475e95 0x1f8f41b6 0x65c9dabe
+ 0x2133b931 0x43be592d 0xb887160c 0xf21fbfce
+ 0xd83ca306 0xa0fb3fe7 0x7da09bf9 0x3f464aa6
+ 0x37a7e40a 0xbb0c85bc 0xb172ff01 0xee62de6f
+ 0x59d2d646 0x4262e938 0xcd96f5e3 0x0c1862cc
+ 0x438388c7 0x9f45d4b2 0xc65ab0b0 0xd24a381c
+ 0x1d6c6767 0xedaa1ae2 0xa93eaec0 0x662d776b
+ 0x192a88c9 0x6c9d860d 0x61106181 0x30027db0
+ 0xa5ae7b76 0x73fc43da 0xd77472b0 0xf4ceba3d
+ 0x7cd642c6 0x903dd266 0xe33f58e9 0xbd088621
+ 0x8e4c2c12 0xd8c4288e 0x24fdbb22 0xf72ee1f9
+ 0xf291bd7e 0x94e68382 0xbbdd9240 0xb59602de
+ 0x1b59afd0 0xe5417cf5 0x20bbb538 0xe28fdee3
+ 0x0bb16920 0x77d6712a 0x1a0ae5f6 0x0156c43e
+ 0x976b53c4 0xef856d7b 0x5a974cfe 0xec53404b
+ 0xc627c557 0x3318542a 0x8fd883e6 0x508562b3
+ 0xe0ab7501 0x9ae57262 0x95611b5e 0x50c699fd
+ 0x984bb8ab 0x5983ed68 0x9947a7c5 0xc0d2374a
+ 0xe0845ab6 0x9ffec0fe 0x41873bf5 0xc85c1a4c
+ 0x7ef2b12d 0x9e1a3857 0x444da53d 0xb8947919
+ 0x84c8588c 0x268f34e3 0x1974cf3d 0xfa67e03f
+ 0xc4478570 0xc1896f5c 0xf86de14a 0x9d27ddb7
+ 0x5da1c695 0x73c74ab7 0x9123a47b 0x1c9d9563
+ 0x7b96bb9f 0x98d20464 0x1f46fd8d 0x4bc35857
+ 0xc221a75f 0x04b24c86 0xbe1c7271 0x21a7b19a
+ 0x9e050b54 0x8d93d0fb 0x98d7b55b 0xe5fe9502
+ 0x9471bff8 0xb3825934 0x5f22d5b2 0x47f4ae9c
+ 0x62d7623f 0xfdeef9b6 0x38c64ff3 0x9268fd7b
+ 0xa7cfd22e 0x80eeed4c 0xf80a4a3e 0xc9a7e4f4
+ 0x6f334b52 0x48e932a5 0xef8720eb 0xb9e86512
+ 0xc4183682 0x08142405 0x0a32902d 0x34503fb5
+ 0x4c7f132b 0x8db9be38 0x82c20236 0x80a79fa5
+ 0x9a31e682 0xca61dd2c 0x2e354b63 0x8d5a4750
+ 0x7a838960 0x24dffeb5 0xc7d19837 0xebfbc508
+ 0x82e8dbdb 0xe732eaf4 0x109470c1 0xb012af6e
+ 0xe2ce17be 0x79db33be 0x281184f3 0xc813df9d
+ 0x9e6a771f 0x4a81882c 0xda5baf2c 0xfecbbb6b
+ 0x4621a151 0xf4cece92 0xfc230416 0x8d4e758e
+ 0xf69c296c 0x9fa2490a 0xeaa56785 0x3075ed95
+ 0x4c2ffe06 0x817caf32 0x5a72f33a 0xc6d99da3
+ 0x2bbc3dde 0xade463f7 0xb74af1a3 0x738d809d
+ 0xd244aeaa 0x7302a2db 0xcb6e9b1d 0xe297c027
+ 0x15dbaff6 0xce99c273 0x2810eb0e 0xafbe1f09
+ 0xd316d8ba 0x27b8af19 0xb66bdf45 0x3e3b5fbe
+ 0x318a4f05 0x2ea7807b 0xed6d40a0 0x58ba8267
+ 0x1d1c9d15 0x29af51cd 0x04a46683 0x4b759694
+ 0x20ce21e6 0x19ef8036 0x141a8064 0xca36f583
+ 0x6d47da5f 0x3a8f6b9a 0x70a99a79 0x03677150
+ 0x0feb8c70 0xf3509842 0xf33b5dde 0xbef320a3
+ 0x932f9512 0x87497bf0 0xf521a0c8 0xa813483b
+ 0xcd6fae43 0xbb7e4dce 0xc7d039b3 0x2d1e6f8b
+ 0x1b19cb9e 0x8341c193 0xeffde49d 0x4c40621b
+ 0x19d60210 0x8846c540 0xea735ec0 0x0c995dbd
+ 0x9aefe2f3 0xbd46f954 0x9b315f98 0x2819307e
+ 0xebe2c1f5 0x05919533 0xa52921ee 0xa0bd6746
+ 0xd754f5d1 0x39eb2ce6 0x8442d51e 0xb1f75159
+ 0x1b617cd1 0x046fc90a 0x6452daca 0xe8d3e3e1
+ 0x77406387 0xe3ffbfca 0x89387e91 0x7e348a53
+ 0xa5bd3b60 0xc113e95f 0x2ad5a7c4 0x45c1f445
+ 0x2a683930 0x3428246c 0x4b89cf6b 0x05e66b1a
+ 0x571737eb 0x6e55a8e1 0xbc96ce28 0x24d501f3
+ 0x242c8191 0xde8c9472 0xbff946e4 0x551b5759
+ 0x411e3420 0x0f0b9299 0x44aaaf70 0xacf2f3df
+ 0xe9c44a27 0x781ffdce 0xa39651a5 0xdb7b44a5
+ 0xed0ec4d9 0xec17fca2 0xd3ccb15f 0x2b9bd010
+ 0x0446a9ef 0x18df586c 0xe227ae08 0xbbaff527
+ 0x7958fb15 0x03bfc823 0xc09b7b6b 0xce07b0b3
+ 0x0161a359 0x8e21f733 0x8f8168bf 0xc1e2207e
+ 0xf9f65e93 0x831b4ba8 0x4b3677f9 0xf8342d03
+ 0x03c10268 0xd07233c1 0x0df67d97 0x72434732
+ 0x059c7679 0x96526a88 0xb54f9440 0x19e7327f
+ 0x6f7f52c1 0xb4b8d069 0xcc4681eb 0x26ea581b
+ 0xc26fe16e 0x4073cc56 0x6d252a42 0x689fd0fd
+ 0x5d93f1b3 0x070ad283 0xa07cb95b 0x6effe0d1
+ 0xe303ed01 0xb8e9b3f4 0x0721647a 0x31f877c6
+ 0x134518e5 0x08694d5a 0xb0e6ef3b 0xc7fdc67e
+ 0x6111276e 0x45185e0a 0xe13cb5c7 0x7c6ec9e9
+ 0xfdee9721 0xc1fb8bcc 0xe25a2bc1 0x075f717e
+ 0xd37b7698 0xa9cbfeae 0x6b7d0a28 0x1f1c8bdf
+ 0x35d0e6b2 0x8b988b79 0x54f02ea3 0x3426ae01
+ 0x5e402b08 0x840d3b8e 0x221527ff 0x906a86f8
+ 0x411ce6dc 0xe4b3056e 0x26c9ed04 0xf3d8bc97
+ 0x3b02cf67 0x11309c45 0x06ea08bd 0x1c698922
+ 0x04e1e492 0x06e0c39d 0xed2937ab 0x83f1911b
+ 0x25a94599 0x75d365f0 0x98f191e9 0x845f5e0f
+ 0x49547aa4 0x42a0ae2e 0xb7e77fb7 0xe132bfb9
+ 0x1cc087a2 0xb0435a85 0x4818ee36 0x4cd90b16
+ 0xf56d5e22 0xdc49137b 0xb5f16e70 0x8f8ac784
+ 0x84b020c7 0x83c26ace 0x090b3489 0xde14f529
+ 0x6ee716ba 0x9deabba1 0x2c230ded 0xd6a68037
+ 0xe626043f 0x33431885 0xd26423e7 0xcf259f47
+ 0x335dfa6d 0xf052f836 0xcadf2fa5 0x6f2125d9
+ 0xafbb23bf 0x19ec69ba 0x84d10bad 0x8cd3ebd5
+ 0x36f0fbb1 0xbc1cbfbe 0x96c56812 0x0b05c939
+ 0xbd79989d 0xffe74b98 0x6f99405a 0x9f10b14c
+ 0x9d8efef4 0x299d21b5 0x9dd2df5a 0xc7ea511b
+ 0xbdde106f 0xe5dc7d17 0xee136bc7 0xc4521b6b
+ 0x823d31d0 0xcc3c32eb 0xb35ffb33 0x84dd8acd
+ 0xe8ddf3d6 0x4611888c 0xfe469f52 0xf8e18215
+ 0x768747f0 0x86379e46 0xd3cf9eb7 0x86f1e47d
+ 0x30e68652 0x740203fe 0x1031b14e 0x96ce6827
+ 0x45f57455 0xe41b7656 0xaa8496d3 0xb99701d0
+ 0x485f88ed 0x1d064ef7 0xc7e3348e 0x110d938f
+ 0x0c3c9604 0x786b0b35 0x2b2aa6ad 0xdcc45e0b
+ 0xe9b29146 0xdbb00ed2 0x0527d574 0xc8029ff1
+ 0x5699dfd0 0xd627ff70 0x285fb3d8 0xcf2e6b75
+ 0xefad87da 0x4fa21893 0xa391388c 0x5760b28e
+ 0x41a95b55 0x82001638 0x6f0e2d45 0xd30f70aa
+ 0x5eca612f 0x946317f4 0x24c44ef7 0x470d26f2
+ 0xf7e65ef4 0x3a831857 0x53c5699e 0x1af6ff3f
+ 0x675b46c3 0x1bd5cfbb 0x03ab61be 0xa67a2b7b
+ 0xbae16286 0xe1522d53 0x076d8ec2 0x3a603daa
+ 0x0dbacfd9 0xd32acae8 0xe8a23399 0xdf3330bf
+ 0xe990c05d 0xfe56bcc3 0x165f868a 0xdf42a220
+ 0x6587e194 0x0a31eb94 0xa72a98fb 0x5512801d
+ 0xc5fd9c69 0xf7210367 0xcc80f30c 0xc08755bc
+ 0x3afe8202 0xc47d603e 0xd17d2990 0xa4addd73
+ 0xce89fcc5 0x55726cbd 0xeeb77a64 0x628b3d1c
+ 0x2297e332 0x6ecab8e4 0x9739c0d1 0xd53d619c
+ 0xbf1a3371 0xe29ea297 0x140436d5 0xfa4802f8
+ 0x1b277664 0x4f101407 0xde441685 0x1d36bbf4
+ 0x057d9f25 0x7949dbc2 0x57686ffc 0x12984cb7
+ 0x0721d76b 0x81ac7aac 0xeb40577c 0x43aaa8d4
+ 0xb4e06e63 0x7054a526 0x18bced57 0xa37d26a0
+ 0xac039a34 0x156e6d9f 0x07ae4487 0x0e59f4db
+ 0x28aeb416 0xc1c4dafd 0xe0357fef 0x683adca7
+ 0x93f2d62b 0x8f1f6ec6 0xd42fcbd8 0xfc4e3fad
+ 0x082e4bbe 0x578bdbee 0x42dcda04 0x7684e947
+ 0x20853da1 0x207dd044 0x56e372bb 0x5ef4c033
+ 0x83353865 0xb3b42465 0xb80c9c79 0xffedbed0
+ 0x09e45d5b 0x794fe5c7 0x498d4fbd 0xb1cd7a48
+ 0xfc89b057 0xc1d19df8 0x9654d056 0xc94cd085
+ 0xd7cb03b5 0x13a52c5b 0x52471fd3 0x990aaebe
+ 0xe8bed6a7 0xa6960d01 0x68011da1 0x021bf151
+ 0xaaa196f2 0x9e3b6188 0xbb28f2c5 0x559d3dd2
+ 0xc38861b2 0xfd7242b1 0x716c29e2 0x270236a9
+ 0xaaf33479 0x610a7d76 0xc0d564fc 0xf0bb1bd8
+ 0x31fb232b 0xf19ebb3f 0xd62acd99 0x5e45578e
+ 0x467c587f 0x0ac00140 0x9c7c1705 0x61a8a1ea
+ 0x4c5e4e5d 0x0e0d846c 0xd199939c 0xb4c615ae
+ 0x4cfe60cd 0x6b4e5cf4 0xe97ad9ec 0xf325a456
+ 0x6ca45a64 0xb88b4506 0x9f751f49 0x1d66e330
+ 0x59b40444 0x00f530b0 0x9242124d 0xac6de2f9
+ 0x7b7e7a67 0x64962ed3 0xfd0825bc 0xbdbcc113
+ 0x38d8d589 0x3cedb53e 0x17d95495 0x020b8ac2
+ 0xe9aa9bdf 0x0a5a2820 0x64670635 0x91a2a89e
+ 0x91bec6be 0xe9b4f902 0x1ef88ee7 0xec6e1208
+ 0x149e39ca 0xb140ce3b 0x3210a2a7 0x8e489c45
+ 0x59d3ebad 0x30275658 0xc20708d2 0xffdc3e00
+ 0x96c700b8 0x3d03aea6 0xf0ce7ad3 0x232a5585
+ 0xb0dc6620 0x1c1357b3 0xfb4c6d29 0xe5c5b7b7
+ 0xc4bfe2aa 0x37f7ce13 0x433eb884 0x3dde220f
+ 0xc1c34602 0xea700f6f 0x37b79490 0xad5761a3
+ 0xfc5917b1 0x22f7e1be 0xa90566d8 0x89e9db15
+ 0xf91bfa1f 0xdad2260c 0x93eba86f 0x2d94c130
+ 0x777290f1 0x2e656559 0x9be4a490 0x377a6ea0
+ 0x1b4523e4 0xdca0c8a5 0xb00eed31 0x6baeb803
+ 0x9601ee69 0x13d53e86 0xba8d6d8f 0xed6203ce
+ 0xc844f9c7 0x91e8a556 0x39974676 0x3b81329b
+ 0xdd7f10e1 0xbccb6558 0xb20de25c 0x448c44ee
+ 0x8932398a 0x76717b57 0xb20a667a 0x14e2df4a
+ 0xa57107f6 0x701b6c36 0x4b83a1ac 0xb39a1c9e
+ 0x2cc7e9fe 0xf5ae4a62 0x620687b6 0x2d6aef9d
+ 0x6672612c 0x168cdc7e 0x8b09abea 0x522692da
+ 0x6461676d 0x34ab3a9c 0x0d61a2ba 0x0590fef1
+ 0xe9b4b475 0x2dfb6081 0xbcdafb25 0xdae642aa
+ 0x9a9230fd 0xfd67f346 0xdb9d66e1 0x5b307b61
+ 0x9d4f1869 0x21133d6f 0x5157502f 0xcc8ccbc5
+ 0xb6631100 0xa33f48db 0xc0172774 0x5cb276ac
+ 0xe6e5c560 0x07e126dd 0x42bcf23a 0x8064fd70
+ 0x567ece78 0xbbc2fe32 0x9d5ee1bb 0x175b24be
+ 0xf0feac7a 0x57322618 0xfe9e893f 0xa9b2d67b
+ 0x36d03f5a 0xdf178831 0x4da346c5 0x843b1b10
+ 0x0d688dca 0x41a475c6 0x4b7adf33 0x145a00dc
+ 0xcd226a4d 0x4c40cf2c 0xd4972929 0xbad5ea65
+ 0xa96987fa 0xbe247d1c 0x49f2ce89 0xe09bbe72
+ 0xee48486e 0x34b41435 0xb41dbb86 0xe58866c9
+ 0xe848e228 0x18880947 0xd03cd275 0xca285915
+ 0x53dd0097 0xff9069f9 0xaff6a8cd 0xbfe16ac5
+ 0x5e88e076 0xac629a26 0x5a99bee9 0xea892a43
+ 0x8d1d5ce8 0x806a38e3 0xc4d99fcd 0x331a4a01
+ 0x0e586310 0xdd2dfabb 0xe7e6ad37 0x31d67fb1
+ 0xbb985560 0xc969ce24 0x3a424634 0x20a2080e
+ 0xeb1b587c 0x5cf7da4b 0xdaec0133 0xc99abb17
+ 0x63ab9c8f 0xef7e4042 0xca513c8a 0x4e15f5d9
+ 0x7cf8fc96 0x464cea5a 0x2363577d 0xd21bb7db
+ 0x1d977a0f 0xb02f4878 0x4fd1a03b 0x435b9149
+ 0xdfba062e 0xa2f7fc23 0x5ebde93c 0x28e9ed7a
+ 0x4023b147 0x9cac0cf9 0x7c5d5ca1 0xb7453148
+ 0xa52197d9 0xb85dd94b 0x72ee7e51 0xb81f4f5c
+ 0x97a4b485 0x13d8858a 0xa0aabd28 0x9d381125
+ 0x4960d2a7 0xa62787b2 0x865231c2 0xd637cc90
+ 0x6d58f3b7 0xe2759f6e 0xa28af8da 0x5a005f20
+ 0xc11c495b 0x85ecc413 0x657e7b91 0x10b39f7e
+ 0x3fcc394a 0x94b3fc3a 0xb359d60e 0x2e6c1555
+ 0x67d6d21d 0xb0457bc4 0x004f329a 0x2e131d8b
+ 0xfbfbff2a 0x2c1bcbef 0x181f26b6 0x32ebda60
+ 0xa0839e5a 0x241097df 0xb3f070a7 0xefbbd9f0
+ 0x7c3669c7 0x265f2dbc 0x0bd00e42 0x80d6c4c2
+ 0x44874336 0x0b6e7e0a 0xec590889 0xef865c09
+ 0x1a02ac8a 0xfbf78784 0xaaf89d75 0xa86c9caa
+ 0xc626528d 0xfbcec50f 0x2955f18e 0xb5e9a833
+ 0xae60f6bb 0xb3f4c51e 0x21bd6a6e 0x092a6861
+ 0x162d73dd 0xacfa4f0e 0x4efed2bd 0x88980089
+ 0xa2cee6d9 0xdf0953b8 0x6bf5208d 0x4364ed53
+ 0x1a5f19ad 0x2ec7711e 0x7d18832b 0x0f1b28a6
+ 0x0e127845 0x278a6a61 0x9e236436 0xf4646e82
+ 0x07fff0f3 0x34ae92f9 0xec3e71af 0xf7ec7c67
+ 0xdb9ddd62 0xe664e712 0xbb48a158 0x30a14ae6
+ 0x0d93b021 0x83082cc8 0x68952311 0x001b0003
+ 0xf0688e25 0x6c3b5161 0xfff18a53 0xbd1fb0c9
+ 0xe3cc9013 0x1d1e553e 0xa85cdfb0 0x358afc14
+ 0x61749007 0x6fad59bd 0xe85f4500 0x26a5ffa1
+ 0xedd69e21 0x4c1db8ce 0xaf3be18f 0xcd75c259
+ 0xd05f62ee 0x2f0ff1b7 0x717d9bd3 0x62e13392
+ 0x159ce5ce 0xcd9e9bff 0x8964600e 0x57d85abb
+ 0x3f5ead09 0x2d5d4a55 0x87da8369 0xc7944933
+ 0xcde9a717 0x55fa318d 0x112e1607 0x2ca832cb
+ 0xb1181bd5 0x7541a7d4 0xac1a1e20 0x6ad024c8
+ 0x119378ec 0x60b6cbfb 0x068e2f24 0x83acecb1
+ 0x87fd0df3 0x94c9552f 0x08c3d8dc 0x56f1b514
+ 0x717d50e9 0x9680fc39 0xa1bdb28a 0x3dfa1c7c
+ 0x8fc84774 0xb72e06d7 0x42b7ad1e 0x93646393
+ 0xd3632e4a 0x368d78f2 0x36a5ac5b 0x6576a4d8
+ 0x8bc6856c 0xd447936a 0xbec6fb22 0xab285e59
+ 0x3db2c781 0x72eda32a 0x9d654f18 0xdbd78e99
+ 0xbba310ad 0x938ecfc6 0x72d5079a 0x49e2fad4
+ 0x4b44dc75 0x81e82165 0xbe269c9c 0x2558ae80
+ 0xa3bb693e 0x107d10fd 0x8e4fd977 0x22926b4f
+ 0x68c9a7f8 0x6b7439e0 0x5c71c127 0xff5d88b3
+ 0x9d8cce8e 0x02982a71 0xf8fe1ceb 0x3ed3996b
+ 0x1e4f9957 0x63aca642 0xcc9db51b 0xbcb5af80
+ 0x7b2bf393 0x2915079f 0x87f531c5 0xfb06b13a
+ 0x550b261c 0xf01fa342 0xcdf4dd86 0x76718f50
+ 0x717c6bde 0xf460ef23 0x7f912022 0x54fe5b9b
+ 0xc7a5261b 0x073ea6e7 0x71504d55 0x91dd9b8e
+ 0x6d259452 0x2dc96e43 0x289959ca 0x128176a5
+ 0x8d004371 0x835c494e 0x0efa1879 0xddc02e95
+ 0xf0f4618e 0xc67656e2 0xd2bde6b1 0xccaa5e84
+ 0xc6592f19 0x91d01db8 0x2b697d22 0x8adfa55f
+ 0x5a49e4e7 0x897d5c43 0xd326d94f 0xf5ff0c5b
+ 0x57976ca6 0xeff0db4e 0x6d49d466 0x7c054970
+ 0xd3eb0f9f 0x0cbdce79 0x1beaf714 0xfe2df967
+ 0x6a50895e 0x013167bf 0x6139e59c 0x0662ecee
+ 0x9a8d6b53 0xfffb8649 0xce0e685f 0xea5b2a7a
+ 0x8819a629 0x5f96afb4 0x8891acfe 0x545f1097
+ 0x9f314e1b 0x248a5272 0xa40b8424 0xe42af07a
+ 0xa180f331 0x904f3c05 0x98455bc5 0x46198ed7
+ 0x03e208e5 0xcf670099 0x7a85b08c 0xba921ae2
+ 0x1e6947d0 0xddffa6ec 0xea6330d3 0xcda6957e
+ 0x19525cd3 0x311fb407 0x796c1ff4 0x3a2760fb
+ 0xde4bdd71 0xdb289b69 0x9811773c 0xa72cd839
+ 0x03da90de 0xd42912e8 0x8da1fb0a 0x985d4132
+ 0x5890ae40 0x1f7724d0 0xa336824f 0xca19df32
+ 0xf8ac73d1 0x61c370a9 0xe152b073 0xdafc6461
+ 0x23672042 0x9e6982b6 0x1256c6b4 0xe6bf2c9c
+ 0x9dae123e 0x30896b8f 0x99acf3a3 0xaa05d384
+ 0xea3b7bb7 0xe711d473 0xa9053351 0x71a85cb4
+ 0x3a0f5d25 0x2db3cb48 0x86314a6e 0xf7a2265b
+ 0xf7dc1cc3 0x548f56cf 0x4028a1ee 0x7d2e25d5
+ 0x68c87e37 0xbced6b8c 0x536cc252 0x68bab5ca
+ 0x1158c6c5 0xae0e9509 0x66fa6885 0x22bf2b9a
+ 0xa7a60a97 0x18f4f609 0x348623eb 0x773e705f
+ 0xb3d6622f 0x8f348186 0x81cb9856 0x64bf21ba
+ 0x47e1f96d 0xc95a5843 0xeff6cfce 0x08cb092c
+ 0xf214e48d 0xce272fec 0x57bf90df 0x3c425ea8
+ 0x856e1f5e 0x5c21d1b6 0x105488a3 0x553971eb
+ 0xde614ee5 0xdfa3ac81 0xc5eca5b1 0x69d02d23
+ 0x2a0fefb7 0xf9a01854 0xdd99f277 0x75014d7d
+ 0x3830e3dd 0x7dd8f1e7 0xdac5ac92 0xbf57c03a
+ 0xa5e6a6c7 0xb7c1b7a9 0xc8c8405e 0xfd1977da
+ 0x1e6a7ca4 0x299e1025 0x651a0e55 0x53d624a7
+ 0xccc9e861 0x901bce45 0x1de5a1ab 0x6140dcef
+ 0x3e09eafb 0x20c63cd0 0xff642faa 0xbc91a0a7
+ 0xe373e111 0x857236e7 0xe3e61037 0x0b6cc497
+ 0xca1da7e6 0x60e53803 0xb68663db 0x42e9956a
+ 0xbf4a1650 0xb43f25ec 0xc1232a3a 0x283c2ff3
+ 0xcd233183 0x17ccdfc0 0x03ac3e6d 0xa68ced48
+ 0xe38217d5 0x03c6472d 0x6a623afc 0xfce0d117
+ 0x448ee829 0x0909efd4 0x843a3b4a 0x9ad07683
+ 0x2250af2a 0x01ecc053 0x29684919 0x4ee0c62e
+ 0xa326a904 0x3ec83943 0xc42b0663 0x966379b2
+ 0xc672ece4 0x39391ad3 0x689a10f9 0xd3e9cbd6
+ 0x4bfa8446 0xd1ef6375 0xfe01b6a9 0xbda7d01a
+ 0x1e6879bf 0x05bdf46e 0x14ccab04 0xb02ae668
+ 0x58b51752 0x5eb8e83c 0x753d99de 0x87e4235b
+ 0x80b2afe7 0x127439fe 0x127a98a4 0xe5934c92
+ 0x86044bc0 0xa9664abb 0x91365b53 0x35b14bda
+ 0x67755842 0x7239651a 0x49e0b2e6 0xbb1d25fe
+ 0x51ca7213 0xaff2fd82 0xc1223aba 0x02941bcf
+ 0xb6ec2cfe 0xaa817dc0 0xe0475250 0x78098112
+ 0x750ae102 0x0b3135fa 0x23b648d4 0xbc9d78bd
+ 0xc5d7e046 0xe90ef47c 0x7f21eb75 0xdb304b0b
+ 0xa2c12ee2 0xb45e62ed 0x9f50feb6 0xe036ff55
+ 0x422f410b 0x2385de45 0xb37df6a5 0x4c2abf10
+ 0x6a2c7370 0xf35197ac 0x381face9 0x694761c6
+ 0xb2275097 0x208824c7 0x945300a0 0x4ad3f83d
+ 0x38a7aa12 0x00daaf41 0xcd4b2c19 0x25b2e8f7
+ 0x60d3e39b 0xb3dd8220 0x152f86ab 0xd1ec4233
+ 0x1c3df78a 0x5aeac74e 0xdeea2fe3 0xcfcf9b2e
+ 0x6efc8b2a 0x12a8c5c3 0xb56384e4 0x1b1fe549
+ 0xc55acb4d 0x78e7306a 0x733b0f70 0xf4afe6be
+ 0x6d904b03 0x7ddd7862 0x4da02602 0xfce1e904
+ 0x78773a4b 0x9083e908 0xda8a7593 0xafd8776e
+ 0x9e5ae37a 0xd6e7c557 0xad27adaa 0xd0f1a995
+ 0x1c84e046 0x3319b21a 0xd24c0d03 0x1789df77
+ 0x0f02b9ff 0xdb911f76 0xb2df7654 0x2e75a7bd
+ 0x8acc6fd3 0x3c16ec0b 0xe0d7ac22 0x3ddd1ce1
+ 0xfa9ec67a 0x48f2c409 0xf8099606 0xd73a459d
+ 0x9b2b3fa5 0x8e3c3e9c 0x8b99286a 0x006c0e07
+ 0xc299ded3 0x8a2bd400 0x74508dd4 0x609b4afc
+ 0x1a532838 0xb352a629 0xd390d8af 0x440a5798
+ 0xd31f6ad5 0x161aa48e 0x24a4359f 0xf39f49f7
+ 0xff160d2a 0x27a24637 0x84c46d40 0x988d026a
+ 0x5697a68f 0xeae970a0 0x42689e3d 0xc84ee62f
+ 0x764aabd5 0xb6d74ba5 0x8efc05a6 0xf2d0eccb
+ 0x2b4fa41c 0xad24799f 0xf73b8353 0x76bcd448
+ 0x08172d5e 0x5c6be301 0x926ffdd6 0xfa31009f
+ 0x8339c5f9 0x9dde2840 0x00c2d730 0x6402335f
+ 0xf6f84eda 0x5b0e628a 0x140dbafb 0x0533ee67
+ 0xa7523e60 0x20ca14b3 0x1145d280 0xb0c0ba41
+ 0x81f174d1 0xb80fc64e 0xe8321cfe 0x5762e501
+ 0x9e266b75 0x2695a738 0xe3104779 0x1d1ea19e
+ 0x15fd1d53 0xf0fbd4ee 0xc82f4552 0x4ea98e23
+ 0xec892d69 0x66ccadeb 0x2fdf99b4 0xafffec15
+ 0x2de5ee13 0x5e6ead7f 0x20b111cd 0x752254d1
+ 0xc0126f43 0xe2695fd8 0x38651d40 0x15b708ce
+ 0xf2c2ffdc 0xec24c68c 0x04351ddc 0xceac029b
+ 0x0525fc89 0x90e28526 0x0a23a4c2 0xbb33a5c4
+ 0x13f1fc38 0x66d79cd9 0x0acabe80 0x8d4ef5d8
+ 0x4091808e 0x02f7150b 0xf550597e 0x52703c3f
+ 0xfc954b68 0xe9ebaccb 0xd4f35b2a 0x93793446
+ 0xc40799e6 0xa963fc0c 0x92c8d8f1 0xbc8218dc
+ 0x9ec5c30a 0x8a6a2217 0x63d13dfe 0xea664e1e
+ 0x487192a7 0x1c8f8610 0x88e20f93 0xc54a6de3
+ 0x0111ae79 0x1335f02e 0xa2e2d37d 0xc2563697
+ 0x5fffcdec 0x233919ab 0x3bab1329 0x61943e99
+ 0xea7940f7 0x3cc62cf4 0xaedc5bc4 0x41b63f2c
+ 0x6dbf285f 0xb4793534 0x0e1013f2 0xc54d8c2d
+ 0x23c587f7 0x75df0092 0xc055254a 0x55db2c71
+ 0x518eaa5b 0x55c810d6 0x9c44ca37 0x034287ea
+ 0xe06a0567 0x221a0d8c 0x037a9164 0x36693ef9
+ 0xb7d270a6 0xa8d84a63 0xe8862970 0x484077b7
+ 0xab426cb7 0x37db7c9e 0xb34e1752 0x35444958
+ 0x00d48e90 0x8142602d 0x8ca28e2c 0x714598c9
+ 0xb1cce1be 0xbb98db74 0x400e1029 0x330cb2b6
+ 0x1fd3f8ce 0x2abf7516 0xc2d07e5c 0x2b1d2b80
+ 0xf06bd895 0x2fa7bc09 0xbdbdf893 0xd8466f85
+ 0x61e551b0 0x5b99bfb8 0x86ea5ee7 0xfd82ff9a
+ 0xd7c6344a 0x1fa144d8 0x650f0f02 0x71bd73cf
+ 0x2825177d 0x56c76399 0x2e0b873e 0xc3bf939d
+ 0xf8bc3c1b 0x468482e7 0x33cb98a7 0xa679eaf4
+ 0x32ba9b49 0xde86d50c 0x9eeeeee5 0x94a306e5
+ 0x432e1c9c 0x37997d0c 0xa84d981f 0xbe07b56d
+ 0x4ab6d465 0xa3cd92c4 0x5dea82ab 0xf771249d
+ 0x78f87ba5 0x8105df1c 0x3d74e1c1 0xf48cd4c1
+ 0x8ad010e1 0x9e9a2758 0x509c8953 0xeaaed79a
+ 0x97a4ecb7 0x23ffceb0 0xb3e42e61 0x5f41b4eb
+ 0x14d2804c 0x2d635ad3 0xe1314781 0x3921ec18
+ 0x3dbebec3 0x94e0df22 0xb0b4724e 0x0e7f986b
+ 0x83dd7694 0x7041a22e 0x3c942757 0xd6ff5cbb
+ 0x048b0426 0xa5d6c4cb 0x1f4e3bbd 0x78d5924e
+ 0x6a857d77 0x1d115ecc 0x73c6a888 0xefb934ee
+ 0xa7d1702b 0x6794a668 0x03715b90 0xfbab19f9
+ 0xd5a433df 0x12f4d421 0x40519650 0x636a093e
+ 0x1601be15 0xe0fbef6f 0x79d775bc 0x789c3a30
+ 0x4d9fa618 0xedf8fa70 0xb0fa402d 0x692ee91b
+ 0x5a593e5c 0x0fa3667f 0x3f51a636 0x935e28c7
+ 0x230b725a 0x4929bc83 0x76de40ad 0x2d9a5f7f
+ 0x8799e033 0xbf2700b0 0x5220159d 0x1ed71ca5
+ 0xcc66f114 0x15fd868d 0x4236645a 0xded2558e
+ 0xa561cc0d 0x02822e5b 0xd0177f80 0xf09badd9
+ 0xd5380ae3 0xcfc11a46 0x36713416 0x7f3d60cc
+ 0x4018797e 0xc6b23941 0xcb5a4861 0x614ce6df
+ 0xabfc0629 0xa519bcfc 0x911f04f0 0xe509b546
+ 0xbb411eb9 0x9e6b921c 0xbf0b1c70 0x80c2901c
+ 0x85786713 0xad2aafec 0x62711ba7 0x6edb4971
+ 0x214eb137 0x45b1b313 0x6742d5e9 0x7daf37a6
+ 0x21d6a27a 0x059424f7 0x2c8c3dfb 0xe7a06c77
+ 0x10815625 0xb4dc69e8 0x52767f66 0x44d48738
+ 0x84d26c93 0x09008893 0xfc21394a 0x82155a72
+ 0xc4fd7512 0x6d43cd2f 0xcae99e08 0x453175ae
+ 0xc6ee93a3 0x2fed0eac 0xe48fb73d 0x0afe2d2a
+ 0x5966735e 0xdc7e5fb6 0xed1ef13d 0x7e08a106
+ 0xd3ca0e6b 0x4ce5ca02 0xa0beebed 0xe982c609
+ 0x1ee9e5a2 0x24ae26cb 0xfd4c08d4 0x5e85e850
+ 0x11b54b3b 0x87209692 0x4a5b0c35 0xcd25dd6f
+ 0xd9570253 0xaad0b9fe 0xaf984fee 0x6cf7ae2d
+ 0x45d9926c 0x07a66ac6 0x8e7aacdc 0xaf587d66
+ 0x53972a4e 0x8da4a6c9 0x2bc311e5 0x36938ae8
+ 0x179b965d 0x515743f7 0xb5bbbdcd 0xd8602715
+ 0x9e43049f 0x4e78a080 0xba3f1750 0x68635cf0
+ 0x85823047 0xbb03b5fd 0xb0d747c8 0x58d214af
+ 0x94b1ba85 0x6d2cf8ac 0x2bc1faeb 0x6bd7c1e3
+ 0x127658e9 0x8b499020 0xab8f0f62 0xee665a6a
+ 0x89240e4d 0x8a95342b 0x00b38ccc 0xe6b14d9d
+ 0x32a2af71 0x4c9ecb69 0xc8de2685 0xd7385184
+ 0x8e943872 0x809b2c79 0x108511da 0x08b4f54d
+ 0x95f52442 0x26fe296f 0xf7e037c0 0xa1aecdd3
+ 0x89774a91 0xde67c55f 0x1f9816dc 0x1469a4c2
+ 0x28240be2 0x5fd0ad14 0x0949db3a 0x451b94d3
+ 0x637e6d49 0x8a4771c8 0xf65104b7 0xc3058c40
+ 0x592fe4d0 0xe26129f0 0xe66e6ce9 0x26ab39b8
+ 0x308da532 0x205afe77 0x6dc78664 0x84d4890f
+ 0x9d49fcb0 0xcac8f2ed 0xe713d798 0xfed7c75b
+ 0xe441a0d4 0xdf60df37 0xc2eed2f5 0x2d68b20e
+ 0x7827c89a 0x9d4cb9f2 0xb8912cce 0x07516335
+ 0x976ffbb6 0x5cd0de48 0xed716f54 0x6f3c9f7f
+ 0x34cf42d1 0xc1027cbb 0xde67c065 0xe0a229af
+ 0xfc8bd2e8 0xd62ca176 0x8bfb76b2 0x54a1388f
+ 0xe0650bb6 0x6d60682b 0xe16cf130 0xbd7c3ca2
+ 0xea642814 0xa25f4d44 0x27013786 0x7316aa38
+ 0x571511c8 0xf1b6b789 0xb7bfe72b 0x8fd2652c
+ 0xbfc7771a 0x51a2e551 0x3bd738c2 0x2698b495
+ 0xec69a196 0xd5ecb5c4 0x9bd3224c 0x6d9ab4cf
+ 0x326c9942 0x4d711191 0xde9be50a 0xa980ca0b
+ 0xe8e59dd0 0x4439e4ae 0x35de914d 0xee499a84
+ 0xd1ca0c9d 0xfe6ee96d 0x5b1f4fd0 0xabf0621a
+ 0x0c8220c7 0xcb6dbb1e 0xa5116036 0xe858d3c3
+ 0x728e3a56 0x3b33e818 0xbe2643c1 0x497bbcc7
+ 0xeb369828 0x9a4a01be 0x8c7e72a6 0xaf052f25
+ 0x8d3ca85b 0x4703e55e 0x45647d4c 0x86d1e3e8
+ 0x40ab59f9 0x3259b195 0xf979a147 0xb8961870
+ 0x88b024f9 0x366e26bc 0xd6811525 0x252910c2
+ 0x4223a20e 0x7fc971a3 0x4a639bf3 0xb6550c3b
+ 0xfe05e552 0xbdc98897 0x509923ff 0xf51a5abc
+ 0xc6cc0891 0x61cdac05 0x03a68664 0x1b80cc76
+ 0xe18d8ee1 0x798bb4d2 0xd7769bf9 0x9ab4c02d
+ 0x7484774b 0xa9ee2c8b 0x87d34c85 0x15697682
+ 0x9f6a4a55 0x9d7a731c 0x10014d6a 0xb9798070
+ 0xd42f79cb 0x89db59b3 0xd5b0a0b6 0xf60864a5
+ 0x2d6fb084 0x1cb607b2 0x48232701 0x9310cbc6
+ 0x5bc81c98 0x6b25016c 0x2014b99d 0x0836e60b
+ 0x0addbc4c 0x3b8bac7c 0x8d95ac77 0x1d56c3c7
+ 0x58333104 0x3d6eb719 0x676eb951 0xd5c2d1a3
+ 0x239dae86 0x92181ab8 0xbdde9741 0x7995d452
+ 0xe0020661 0x2f80c8b7 0xeedcd4fc 0xe4bde175
+ 0xb98fdf78 0x84b9228f 0x78ecb4f3 0xe99e5d46
+ 0xa33b9b96 0xe2cbc71c 0xc19e2146 0xdc0ee758
+ 0x2d8f8767 0x2036685b 0x149df155 0x2e7ab376
+ 0xb13b4266 0xf5c8a3b0 0x02ca1e19 0x1badd81b
+ 0xb9c1832a 0x73b31f75 0x69979b55 0x567070a2
+ 0x2edeb3dc 0x26b55921 0x461df49f 0xc1aba883
+ 0x25d6faec 0x5260e9bf 0xa8ccdd4c 0x04291961
+ 0xfaf7a1b8 0xbc2d36e3 0xd6c86385 0x2757fbb9
+ 0x62c7107c 0x87dac461 0x0c006454 0x0e971e49
+ 0x4749afca 0x7f1fb389 0xdc0b69d3 0xc69fab09
+ 0x12c372c9 0x78480a51 0x8ab03a94 0xb37022ca
+ 0x1d00e893 0x0989de45 0x8c819503 0x8e0e1c06
+ 0x11cfef86 0x3c2386a6 0x66c0e6c8 0x1befa478
+ 0xd2e7a4a7 0x9a8b5917 0x2cfa1816 0xaf7e6c7a
+ 0xd6c9f0ff 0x1aada3e0 0xbe36a471 0x5a91f3c7
+ 0x6c61ea95 0x5246ef7c 0x20bc86c4 0xcfd87abd
+ 0xdc61f595 0x8310a684 0x0477e35c 0xe59e776f
+ 0xfa403863 0xdaf7bcb1 0xd6084825 0xb90bb047
+ 0xeb9ff684 0x7223fbca 0x6b4af987 0x6b2553f8
+ 0xdaabc6d2 0x82e2ebc3 0xa7c1c054 0x667eb0a7
+ 0x53a0c7d4 0x3fcba743 0x38170187 0x2a2e5830
+ 0xee134608 0xcd6e0112 0xac0831f9 0x9537d532
+ 0x1e176b9c 0xe3fcb69f 0x17a2eee9 0xa9e6467f
+ 0xbf6b0246 0x6a08c0fb 0x7fb943b6 0xb8f67c0e
+ 0x2b3b4ffc 0xb155d20c 0x4eb5de53 0xf078715b
+ >;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
new file mode 100644
index 0000000..8f34369
--- /dev/null
+++ b/arch/x86/dts/minnowmax.dts
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+
+/ {
+ model = "Intel Minnowboard Max";
+ compatible = "intel,minnowmax", "intel,baytrail";
+
+ aliases {
+ serial0 = &serial;
+ };
+
+ config {
+ silent_console = <0>;
+ };
+
+ chosen {
+ stdout-path = "/serial";
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich";
+ spi-flash@0 {
+ reg = <0>;
+ compatible = "sst,25vf016b", "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ };
+ };
+
+ microcode {
+ update@0 {
+#include "microcode/m0130673322.dtsi"
+ };
+ };
+
+};
diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi
index 9b097f4..6865eed 100644
--- a/arch/x86/dts/serial.dtsi
+++ b/arch/x86/dts/serial.dtsi
@@ -1,5 +1,5 @@
/ {
- serial {
+ serial: serial {
compatible = "x86-uart";
reg = <0x3f8 8>;
reg-shift = <0>;
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h
new file mode 100644
index 0000000..d96a20f
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef _FSP_AZALIA_H_
+#define _FSP_AZALIA_H_
+
+struct __packed pch_azalia_verb_table_header {
+ uint32_t vendor_device_id;
+ uint16_t sub_system_id;
+ uint8_t revision_id; /* 0xff applies to all steppings */
+ uint8_t front_panel_support;
+ uint16_t number_of_rear_jacks;
+ uint16_t number_of_front_jacks;
+};
+
+struct __packed pch_azalia_verb_table {
+ struct pch_azalia_verb_table_header verb_table_header;
+ const uint32_t *verb_table_data;
+};
+
+struct __packed pch_azalia_config {
+ uint8_t pme_enable:1;
+ uint8_t docking_supported:1;
+ uint8_t docking_attached:1;
+ uint8_t hdmi_codec_enable:1;
+ uint8_t azalia_v_ci_enable:1;
+ uint8_t rsvdbits:3;
+ /* number of verb tables provided by platform */
+ uint8_t azalia_verb_table_num;
+ const struct pch_azalia_verb_table *azalia_verb_table;
+ /* delay timer after azalia reset */
+ uint16_t reset_wait_timer_us;
+};
+
+#endif
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
new file mode 100644
index 0000000..82862f6
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_VPD_H
+#define __FSP_VPD_H
+
+struct memory_down_data {
+ uint8_t enable_memory_down;
+ uint8_t dram_speed;
+ uint8_t dram_type;
+ uint8_t dimm_0_enable;
+ uint8_t dimm_1_enable;
+ uint8_t dimm_width;
+ uint8_t dimm_density;
+ uint8_t dimm_bus_width;
+ uint8_t dimm_sides; /* Ranks Per dimm_ */
+ uint8_t dimm_tcl; /* tCL */
+ /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
+ uint8_t dimm_trpt_rcd;
+ uint8_t dimm_twr; /* tWR in DRAM clk */
+ uint8_t dimm_twtr; /* tWTR in DRAM clk */
+ uint8_t dimm_trrd; /* tRRD in DRAM clk */
+ uint8_t dimm_trtp; /* tRTP in DRAM clk */
+ uint8_t dimm_tfaw; /* tFAW in DRAM clk */
+};
+
+struct __packed upd_region {
+ uint64_t signature; /* Offset 0x0000 */
+ uint8_t reserved0[24]; /* Offset 0x0008 */
+ uint16_t mrc_init_tseg_size; /* Offset 0x0020 */
+ uint16_t mrc_init_mmio_size; /* Offset 0x0022 */
+ uint8_t mrc_init_spd_addr1; /* Offset 0x0024 */
+ uint8_t mrc_init_spd_addr2; /* Offset 0x0025 */
+ uint8_t emmc_boot_mode; /* Offset 0x0026 */
+ uint8_t enable_sdio; /* Offset 0x0027 */
+ uint8_t enable_sdcard; /* Offset 0x0028 */
+ uint8_t enable_hsuart0; /* Offset 0x0029 */
+ uint8_t enable_hsuart1; /* Offset 0x002a */
+ uint8_t enable_spi; /* Offset 0x002b */
+ uint8_t reserved1; /* Offset 0x002c */
+ uint8_t enable_sata; /* Offset 0x002d */
+ uint8_t sata_mode; /* Offset 0x002e */
+ uint8_t enable_azalia; /* Offset 0x002f */
+ uint32_t azalia_config_ptr; /* Offset 0x0030 */
+ uint8_t enable_xhci; /* Offset 0x0034 */
+ uint8_t enable_lpe; /* Offset 0x0035 */
+ uint8_t lpss_sio_enable_pci_mode; /* Offset 0x0036 */
+ uint8_t enable_dma0; /* Offset 0x0037 */
+ uint8_t enable_dma1; /* Offset 0x0038 */
+ uint8_t enable_i2_c0; /* Offset 0x0039 */
+ uint8_t enable_i2_c1; /* Offset 0x003a */
+ uint8_t enable_i2_c2; /* Offset 0x003b */
+ uint8_t enable_i2_c3; /* Offset 0x003c */
+ uint8_t enable_i2_c4; /* Offset 0x003d */
+ uint8_t enable_i2_c5; /* Offset 0x003e */
+ uint8_t enable_i2_c6; /* Offset 0x003f */
+ uint8_t enable_pwm0; /* Offset 0x0040 */
+ uint8_t enable_pwm1; /* Offset 0x0041 */
+ uint8_t enable_hsi; /* Offset 0x0042 */
+ uint8_t igd_dvmt50_pre_alloc; /* Offset 0x0043 */
+ uint8_t aperture_size; /* Offset 0x0044 */
+ uint8_t gtt_size; /* Offset 0x0045 */
+ uint32_t serial_debug_port_address; /* Offset 0x0046 */
+ uint8_t serial_debug_port_type; /* Offset 0x004a */
+ uint8_t mrc_debug_msg; /* Offset 0x004b */
+ uint8_t isp_enable; /* Offset 0x004c */
+ uint8_t scc_enable_pci_mode; /* Offset 0x004d */
+ uint8_t igd_render_standby; /* Offset 0x004e */
+ uint8_t txe_uma_enable; /* Offset 0x004f */
+ uint8_t os_selection; /* Offset 0x0050 */
+ uint8_t emmc45_ddr50_enabled; /* Offset 0x0051 */
+ uint8_t emmc45_hs200_enabled; /* Offset 0x0052 */
+ uint8_t emmc45_retune_timer_value; /* Offset 0x0053 */
+ uint8_t unused_upd_space1[156]; /* Offset 0x0054 */
+ struct memory_down_data memory_params; /* Offset 0x00f0 */
+ uint16_t terminator; /* Offset 0x0100 */
+};
+
+#define VPD_IMAGE_ID 0x3157454956594C56 /* 'VLYVIEW1' */
+#define VPD_IMAGE_REV 0x00000303
+
+struct __packed vpd_region {
+ uint64_t sign; /* Offset 0x0000 */
+ uint32_t img_rev; /* Offset 0x0008 */
+ uint32_t upd_offset; /* Offset 0x000c */
+ uint8_t unused[16]; /* Offset 0x0010 */
+ uint32_t fsp_res_memlen; /* Offset 0x0020 */
+ uint8_t platform_type; /* Offset 0x0024 */
+ uint8_t enable_secure_boot; /* Offset 0x0025 */
+};
+#endif
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h
new file mode 100644
index 0000000..ab4e059
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_GPIO_H_
+#define _X86_ARCH_GPIO_H_
+
+/* Where in config space is the register that points to the GPIO registers? */
+#define PCI_CFG_GPIOBASE 0x44
+
+#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index cf7457f..c960525 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -43,7 +43,7 @@
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#define DEFAULT_RCBABASE 0xfed1c000
/* 4 KB per PCIe device */
-#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
+#define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE
/* Device 0:0.0 PCI configuration space (Host Bridge) */
#define EPBAR 0x40
diff --git a/arch/x86/include/asm/arch-quark/device.h b/arch/x86/include/asm/arch-quark/device.h
new file mode 100644
index 0000000..4af3ded
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/device.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _QUARK_DEVICE_H_
+#define _QUARK_DEVICE_H_
+
+#include <pci.h>
+
+#define QUARK_HOST_BRIDGE PCI_BDF(0, 0, 0)
+#define QUARK_MMC_SDIO PCI_BDF(0, 20, 0)
+#define QUARK_UART0 PCI_BDF(0, 20, 1)
+#define QUARK_USB_DEVICE PCI_BDF(0, 20, 2)
+#define QUARK_USB_EHCI PCI_BDF(0, 20, 3)
+#define QUARK_USB_OHCI PCI_BDF(0, 20, 4)
+#define QUARK_UART1 PCI_BDF(0, 20, 5)
+#define QUARK_EMAC0 PCI_BDF(0, 20, 6)
+#define QUARK_EMAC1 PCI_BDF(0, 20, 7)
+#define QUARK_SPI0 PCI_BDF(0, 21, 0)
+#define QUARK_SPI1 PCI_BDF(0, 21, 1)
+#define QUARK_I2C_GPIO PCI_BDF(0, 21, 2)
+#define QUARK_PCIE0 PCI_BDF(0, 23, 0)
+#define QUARK_PCIE1 PCI_BDF(0, 23, 1)
+#define QUARK_LEGACY_BRIDGE PCI_BDF(0, 31, 0)
+
+#endif /* _QUARK_DEVICE_H_ */
diff --git a/arch/x86/include/asm/arch-quark/gpio.h b/arch/x86/include/asm/arch-quark/gpio.h
new file mode 100644
index 0000000..ca8cba4
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/gpio.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_GPIO_H_
+#define _X86_ARCH_GPIO_H_
+
+/* Where in config space is the register that points to the GPIO registers? */
+#define PCI_CFG_GPIOBASE 0x44
+
+#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-quark/mrc.h b/arch/x86/include/asm/arch-quark/mrc.h
new file mode 100644
index 0000000..150fbea
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/mrc.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Ported from Intel released Quark UEFI BIOS
+ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef _MRC_H_
+#define _MRC_H_
+
+#define MRC_VERSION 0x0111
+
+/* architectural definitions */
+#define NUM_CHANNELS 1 /* number of channels */
+#define NUM_RANKS 2 /* number of ranks per channel */
+#define NUM_BYTE_LANES 4 /* number of byte lanes per channel */
+
+/* software limitations */
+#define MAX_CHANNELS 1
+#define MAX_RANKS 2
+#define MAX_BYTE_LANES 4
+
+#define MAX_SOCKETS 1
+#define MAX_SIDES 1
+#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)
+
+/* Specify DRAM and channel width */
+enum {
+ X8, /* DRAM width */
+ X16, /* DRAM width & Channel Width */
+ X32 /* Channel Width */
+};
+
+/* Specify DRAM speed */
+enum {
+ DDRFREQ_800,
+ DDRFREQ_1066
+};
+
+/* Specify DRAM type */
+enum {
+ DDR3,
+ DDR3L
+};
+
+/*
+ * density: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb
+ * cl: DRAM CAS Latency in clocks
+ * ras: ACT to PRE command period
+ * wtr: Delay from start of internal write transaction to internal read command
+ * rrd: ACT to ACT command period (JESD79 specific to page size 1K/2K)
+ * faw: Four activate window (JESD79 specific to page size 1K/2K)
+ *
+ * ras/wtr/rrd/faw timings are in picoseconds
+ *
+ * Refer to JEDEC spec (or DRAM datasheet) when changing these values.
+ */
+struct dram_params {
+ uint8_t density;
+ uint8_t cl;
+ uint32_t ras;
+ uint32_t wtr;
+ uint32_t rrd;
+ uint32_t faw;
+};
+
+/*
+ * Delay configuration for individual signals
+ * Vref setting
+ * Scrambler seed
+ */
+struct mrc_timings {
+ uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
+ uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
+ uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
+ uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
+ uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
+ uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
+ uint32_t wcmd[NUM_CHANNELS];
+ uint32_t scrambler_seed;
+ /* need to save for the case of frequency change */
+ uint8_t ddr_speed;
+};
+
+/* Boot mode defined as bit mask (1<<n) */
+enum {
+ BM_UNKNOWN,
+ BM_COLD = 1, /* full training */
+ BM_FAST = 2, /* restore timing parameters */
+ BM_S3 = 4, /* resume from S3 */
+ BM_WARM = 8
+};
+
+/* MRC execution status */
+#define MRC_SUCCESS 0 /* initialization ok */
+#define MRC_E_MEMTEST 1 /* memtest failed */
+
+/*
+ * Memory Reference Code parameters
+ *
+ * It includes 3 parts:
+ * - input parameters like boot mode and DRAM parameters
+ * - context parameters for MRC internal state
+ * - output parameters like initialization result and memory size
+ */
+struct mrc_params {
+ /* Input parameters */
+ uint32_t boot_mode; /* BM_COLD, BM_FAST, BM_WARM, BM_S3 */
+ /* DRAM parameters */
+ uint8_t dram_width; /* x8, x16 */
+ uint8_t ddr_speed; /* DDRFREQ_800, DDRFREQ_1066 */
+ uint8_t ddr_type; /* DDR3, DDR3L */
+ uint8_t ecc_enables; /* 0, 1 (memory size reduced to 7/8) */
+ uint8_t scrambling_enables; /* 0, 1 */
+ /* 1, 3 (1'st rank has to be populated if 2'nd rank present) */
+ uint32_t rank_enables;
+ uint32_t channel_enables; /* 1 only */
+ uint32_t channel_width; /* x16 only */
+ /* 0, 1, 2 (mode 2 forced if ecc enabled) */
+ uint32_t address_mode;
+ /* REFRESH_RATE: 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED */
+ uint8_t refresh_rate;
+ /* SR_TEMP_RANGE: 0=normal, 1=extended, others=RESERVED */
+ uint8_t sr_temp_range;
+ /*
+ * RON_VALUE: 0=34ohm, 1=40ohm, others=RESERVED
+ * (select MRS1.DIC driver impedance control)
+ */
+ uint8_t ron_value;
+ /* RTT_NOM_VALUE: 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */
+ uint8_t rtt_nom_value;
+ /* RD_ODT_VALUE: 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */
+ uint8_t rd_odt_value;
+ struct dram_params params;
+ /* Internally used context parameters */
+ uint32_t board_id; /* board layout (use x8 or x16 memory) */
+ uint32_t hte_setup; /* when set hte reconfiguration requested */
+ uint32_t menu_after_mrc;
+ uint32_t power_down_disable;
+ uint32_t tune_rcvn;
+ uint32_t channel_size[NUM_CHANNELS];
+ uint32_t column_bits[NUM_CHANNELS];
+ uint32_t row_bits[NUM_CHANNELS];
+ uint32_t mrs1; /* register content saved during training */
+ uint8_t first_run;
+ /* Output parameters */
+ /* initialization result (non zero specifies error code) */
+ uint32_t status;
+ /* total memory size in bytes (excludes ECC banks) */
+ uint32_t mem_size;
+ /* training results (also used on input) */
+ struct mrc_timings timings;
+};
+
+/*
+ * MRC memory initialization structure
+ *
+ * post_code: a 16-bit post code of a specific initialization routine
+ * boot_path: bitwise or of BM_COLD, BM_FAST, BM_WARM and BM_S3
+ * init_fn: real memory initialization routine
+ */
+struct mem_init {
+ uint16_t post_code;
+ uint16_t boot_path;
+ void (*init_fn)(struct mrc_params *mrc_params);
+};
+
+/* MRC platform data flags */
+#define MRC_FLAG_ECC_EN 0x00000001
+#define MRC_FLAG_SCRAMBLE_EN 0x00000002
+#define MRC_FLAG_MEMTEST_EN 0x00000004
+/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
+#define MRC_FLAG_TOP_TREE_EN 0x00000008
+/* If set ODR signal is asserted to DRAM devices on writes */
+#define MRC_FLAG_WR_ODT_EN 0x00000010
+
+/**
+ * mrc_init - Memory Reference Code initialization entry routine
+ *
+ * @mrc_params: parameters for MRC
+ */
+void mrc_init(struct mrc_params *mrc_params);
+
+#endif /* _MRC_H_ */
diff --git a/arch/x86/include/asm/arch-quark/msg_port.h b/arch/x86/include/asm/arch-quark/msg_port.h
new file mode 100644
index 0000000..2e78a66
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/msg_port.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _QUARK_MSG_PORT_H_
+#define _QUARK_MSG_PORT_H_
+
+/*
+ * In the Quark SoC, some chipset commands are accomplished by utilizing
+ * the internal message network within the host bridge (D0:F0). Accesses
+ * to this network are accomplished by populating the message control
+ * register (MCR), Message Control Register eXtension (MCRX) and the
+ * message data register (MDR).
+ */
+#define MSG_CTRL_REG 0xd0 /* Message Control Register */
+#define MSG_DATA_REG 0xd4 /* Message Data Register */
+#define MSG_CTRL_EXT_REG 0xd8 /* Message Control Register EXT */
+
+/* Normal Read/Write OpCodes */
+#define MSG_OP_READ 0x10
+#define MSG_OP_WRITE 0x11
+
+/* Alternative Read/Write OpCodes */
+#define MSG_OP_ALT_READ 0x06
+#define MSG_OP_ALT_WRITE 0x07
+
+/* IO Read/Write OpCodes */
+#define MSG_OP_IO_READ 0x02
+#define MSG_OP_IO_WRITE 0x03
+
+/* All byte enables */
+#define MSG_BYTE_ENABLE 0xf0
+
+#ifndef __ASSEMBLY__
+
+/**
+ * msg_port_setup - set up the message port control register
+ *
+ * @op: message bus access opcode
+ * @port: port number on the message bus
+ * @reg: register number within a port
+ */
+void msg_port_setup(int op, int port, int reg);
+
+/**
+ * msg_port_read - read a message port register using normal opcode
+ *
+ * @port: port number on the message bus
+ * @reg: register number within a port
+ *
+ * @return: message port register value
+ */
+u32 msg_port_read(u8 port, u32 reg);
+
+/**
+ * msg_port_write - write a message port register using normal opcode
+ *
+ * @port: port number on the message bus
+ * @reg: register number within a port
+ * @value: register value to write
+ */
+void msg_port_write(u8 port, u32 reg, u32 value);
+
+/**
+ * msg_port_alt_read - read a message port register using alternative opcode
+ *
+ * @port: port number on the message bus
+ * @reg: register number within a port
+ *
+ * @return: message port register value
+ */
+u32 msg_port_alt_read(u8 port, u32 reg);
+
+/**
+ * msg_port_alt_write - write a message port register using alternative opcode
+ *
+ * @port: port number on the message bus
+ * @reg: register number within a port
+ * @value: register value to write
+ */
+void msg_port_alt_write(u8 port, u32 reg, u32 value);
+
+/**
+ * msg_port_io_read - read a message port register using I/O opcode
+ *
+ * @port: port number on the message bus
+ * @reg: register number within a port
+ *
+ * @return: message port register value
+ */
+u32 msg_port_io_read(u8 port, u32 reg);
+
+/**
+ * msg_port_io_write - write a message port register using I/O opcode
+ *
+ * @port: port number on the message bus
+ * @reg: register number within a port
+ * @value: register value to write
+ */
+void msg_port_io_write(u8 port, u32 reg, u32 value);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _QUARK_MSG_PORT_H_ */
diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h
new file mode 100644
index 0000000..ceb583e
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/quark.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _QUARK_H_
+#define _QUARK_H_
+
+/* Message Bus Ports */
+#define MSG_PORT_MEM_ARBITER 0x00
+#define MSG_PORT_HOST_BRIDGE 0x03
+#define MSG_PORT_RMU 0x04
+#define MSG_PORT_MEM_MGR 0x05
+#define MSG_PORT_SOC_UNIT 0x31
+
+/* Port 0x00: Memory Arbiter Message Port Registers */
+
+/* Enhanced Configuration Space */
+#define AEC_CTRL 0x00
+
+/* Port 0x03: Host Bridge Message Port Registers */
+
+/* Host Memory I/O Boundary */
+#define HM_BOUND 0x08
+
+/* Extended Configuration Space */
+#define HEC_REG 0x09
+
+/* Port 0x04: Remote Management Unit Message Port Registers */
+
+/* ACPI PBLK Base Address Register */
+#define PBLK_BA 0x70
+
+/* SPI DMA Base Address Register */
+#define SPI_DMA_BA 0x7a
+
+/* Port 0x05: Memory Manager Message Port Registers */
+
+/* eSRAM Block Page Control */
+#define ESRAM_BLK_CTRL 0x82
+#define ESRAM_BLOCK_MODE 0x10000000
+
+/* DRAM */
+#define DRAM_BASE 0x00000000
+#define DRAM_MAX_SIZE 0x80000000
+
+/* eSRAM */
+#define ESRAM_SIZE 0x80000
+
+/* Memory BAR Enable */
+#define MEM_BAR_EN 0x00000001
+
+/* I/O BAR Enable */
+#define IO_BAR_EN 0x80000000
+
+/* 64KiB of RMU binary in flash */
+#define RMU_BINARY_SIZE 0x10000
+
+/* Legacy Bridge PCI Configuration Registers */
+#define LB_GBA 0x44
+#define LB_PM1BLK 0x48
+#define LB_GPE0BLK 0x4c
+#define LB_ACTL 0x58
+#define LB_PABCDRC 0x60
+#define LB_PEFGHRC 0x64
+#define LB_WDTBA 0x84
+#define LB_BCE 0xd4
+#define LB_BC 0xd8
+#define LB_RCBA 0xf0
+
+#endif /* _QUARK_H_ */
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
index bce58b1..3c57558 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
@@ -10,8 +10,6 @@
#ifndef __VPDHEADER_H__
#define __VPDHEADER_H__
-#define UPD_TERMINATOR 0x55AA
-
struct __packed upd_region {
u64 sign; /* Offset 0x0000 */
u64 reserved; /* Offset 0x0008 */
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h
index a9d7156..2d34d13 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h
+++ b/arch/x86/include/asm/fsp/fsp_api.h
@@ -8,6 +8,8 @@
#ifndef __FSP_API_H__
#define __FSP_API_H__
+#include <linux/linkage.h>
+
/*
* FspInit continuation function prototype.
* Control will be returned to this callback function after FspInit API call.
@@ -47,9 +49,9 @@ struct fsp_notify_params {
};
/* FspInit API function prototype */
-typedef u32 (*fsp_init_f)(struct fsp_init_params *params);
+typedef asmlinkage u32 (*fsp_init_f)(struct fsp_init_params *params);
/* FspNotify API function prototype */
-typedef u32 (*fsp_notify_f)(struct fsp_notify_params *params);
+typedef asmlinkage u32 (*fsp_notify_f)(struct fsp_notify_params *params);
#endif
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h b/arch/x86/include/asm/fsp/fsp_bootmode.h
index c3f8b49..c3f8b49 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h
+++ b/arch/x86/include/asm/fsp/fsp_bootmode.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h b/arch/x86/include/asm/fsp/fsp_ffs.h
index eaec2b4..eaec2b4 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h
+++ b/arch/x86/include/asm/fsp/fsp_ffs.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h b/arch/x86/include/asm/fsp/fsp_fv.h
index a024451..a024451 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h
+++ b/arch/x86/include/asm/fsp/fsp_fv.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h
index 6cca7f5..6cca7f5 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h
+++ b/arch/x86/include/asm/fsp/fsp_hob.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h b/arch/x86/include/asm/fsp/fsp_infoheader.h
index 4a4d627..4a4d627 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h
+++ b/arch/x86/include/asm/fsp/fsp_infoheader.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h b/arch/x86/include/asm/fsp/fsp_platform.h
index 61286ce..61286ce 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h
+++ b/arch/x86/include/asm/fsp/fsp_platform.h
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h
index ebdbd03..c6c7dc0 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h
+++ b/arch/x86/include/asm/fsp/fsp_support.h
@@ -16,7 +16,7 @@
#include "fsp_platform.h"
#include "fsp_infoheader.h"
#include "fsp_bootmode.h"
-#include "fsp_vpd.h"
+#include <asm/arch/fsp/fsp_vpd.h>
struct shared_data {
struct fsp_header *fsp_hdr;
@@ -26,6 +26,8 @@ struct shared_data {
#define FSP_LOWMEM_BASE 0x100000UL
#define FSP_HIGHMEM_BASE 0x100000000ULL
+#define UPD_TERMINATOR 0x55AA
+
/**
* FSP Continuation assembly helper routine
@@ -61,7 +63,7 @@ void fsp_continue(struct shared_data *shared_data, u32 status,
*
* @retval: the offset of FSP header. If signature is invalid, returns 0.
*/
-u32 find_fsp_header(void);
+struct fsp_header *find_fsp_header(void);
/**
* FSP initialization wrapper function.
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h b/arch/x86/include/asm/fsp/fsp_types.h
index f32d827..f32d827 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h
+++ b/arch/x86/include/asm/fsp/fsp_types.h
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index c30dd4c..a153dd1 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -1,4 +1,3 @@
-
/*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB, daniel@omicron.se
@@ -9,6 +8,14 @@
#ifndef _PCI_I386_H_
#define _PCI_I386_H_
+/* bus mapping constants (used for PCI core initialization) */
+#define PCI_REG_ADDR 0xcf8
+#define PCI_REG_DATA 0xcfc
+
+#define PCI_CFG_EN 0x80000000
+
+#ifndef __ASSEMBLY__
+
#define DEFINE_PCI_DEVICE_TABLE(_table) \
const struct pci_device_id _table[]
@@ -49,4 +56,6 @@ void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value);
void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value);
void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value);
-#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* _PCI_I386_H_ */
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index b98afa8..c743efd 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -26,15 +26,9 @@ unsigned long get_tbclk_mhz(void);
void timer_set_base(uint64_t base);
int pcat_timer_init(void);
-/* Architecture specific DRAM init */
-int dram_init(void);
-
/* cpu/.../interrupts.c */
int cpu_init_interrupts(void);
-/* board/.../... */
-int dram_init(void);
-
int cleanup_before_linux(void);
int x86_cleanup_before_linux(void);
void x86_enable_caches(void);
@@ -45,6 +39,9 @@ ulong board_get_usable_ram_top(ulong total_size);
void dram_init_banksize(void);
int default_print_cpuinfo(void);
+/* Set up a UART which can be used with printch(), printhex8(), etc. */
+int setup_early_uart(void);
+
void setup_pcat_compatibility(void);
void isa_unmap_rom(u32 addr);
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 32d7b98..c17f7f0 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -25,6 +25,7 @@ obj-y += string.o
obj-$(CONFIG_SYS_X86_TSC_TIMER) += tsc_timer.o
obj-$(CONFIG_VIDEO_VGA) += video.o
obj-$(CONFIG_CMD_ZBOOT) += zimage.o
+obj-$(CONFIG_HAVE_FSP) += fsp/
extra-$(CONFIG_USE_PRIVATE_LIBGCC) := lib.a
diff --git a/arch/x86/lib/cmd_hob.c b/arch/x86/lib/cmd_hob.c
index a0ef037..915746a 100644
--- a/arch/x86/lib/cmd_hob.c
+++ b/arch/x86/lib/cmd_hob.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <command.h>
#include <linux/compiler.h>
-#include <asm/arch/fsp/fsp_support.h>
+#include <asm/fsp/fsp_support.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
new file mode 100644
index 0000000..5b12c12
--- /dev/null
+++ b/arch/x86/lib/fsp/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2015 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += fsp_car.o
+obj-y += fsp_common.o
+obj-y += fsp_dram.o
+obj-y += fsp_support.o
diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/lib/fsp/fsp_car.S
index 5e09568..5e09568 100644
--- a/arch/x86/cpu/queensbay/tnc_car.S
+++ b/arch/x86/lib/fsp/fsp_car.S
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
new file mode 100644
index 0000000..f668259
--- /dev/null
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/post.h>
+#include <asm/processor.h>
+#include <asm/fsp/fsp_support.h>
+
+int print_cpuinfo(void)
+{
+ post_code(POST_CPU_INFO);
+ return default_print_cpuinfo();
+}
+
+void reset_cpu(ulong addr)
+{
+ /* cold reset */
+ outb(0x06, PORT_RESET);
+}
+
+
+int board_pci_post_scan(struct pci_controller *hose)
+{
+ u32 status;
+
+ /* call into FspNotify */
+ debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
+ status = fsp_notify(NULL, INIT_PHASE_PCI);
+ if (status != FSP_SUCCESS)
+ debug("fail, error code %x\n", status);
+ else
+ debug("OK\n");
+
+ return 0;
+}
+
+void board_final_cleanup(void)
+{
+ u32 status;
+
+ /* call into FspNotify */
+ debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
+ status = fsp_notify(NULL, INIT_PHASE_BOOT);
+ if (status != FSP_SUCCESS)
+ debug("fail, error code %x\n", status);
+ else
+ debug("OK\n");
+
+ return;
+}
diff --git a/arch/x86/cpu/queensbay/tnc_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index df79a39..4c0a7c8 100644
--- a/arch/x86/cpu/queensbay/tnc_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -5,7 +5,7 @@
*/
#include <common.h>
-#include <asm/arch/fsp/fsp_support.h>
+#include <asm/fsp/fsp_support.h>
#include <asm/e820.h>
#include <asm/post.h>
diff --git a/arch/x86/cpu/queensbay/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index aed3e2b..5f96da1 100644
--- a/arch/x86/cpu/queensbay/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -6,7 +6,7 @@
*/
#include <common.h>
-#include <asm/arch/fsp/fsp_support.h>
+#include <asm/fsp/fsp_support.h>
#include <asm/post.h>
/**
@@ -30,7 +30,7 @@ static bool compare_guid(const struct efi_guid *guid1,
return false;
}
-u32 __attribute__((optimize("O0"))) find_fsp_header(void)
+struct fsp_header *__attribute__((optimize("O0"))) find_fsp_header(void)
{
/*
* This function may be called before the a stack is established,
@@ -84,7 +84,7 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void)
fsp = 0;
}
- return (u32)fsp;
+ return (struct fsp_header *)fsp;
}
void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list)
@@ -124,25 +124,29 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
struct fsp_init_params *params_ptr;
struct upd_region *fsp_upd;
- fsp_hdr = (struct fsp_header *)find_fsp_header();
+#ifdef CONFIG_DEBUG_UART
+ setup_early_uart();
+#endif
+
+ fsp_hdr = find_fsp_header();
if (fsp_hdr == NULL) {
/* No valid FSP info header was found */
panic("Invalid FSP header");
}
- fsp_upd = (struct upd_region *)&shared_data.fsp_upd;
+ fsp_upd = &shared_data.fsp_upd;
memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
/* Reserve a gap in stack top */
rt_buf.common.stack_top = (u32 *)stack_top - 32;
rt_buf.common.boot_mode = boot_mode;
- rt_buf.common.upd_data = (struct upd_region *)fsp_upd;
+ rt_buf.common.upd_data = fsp_upd;
/* Get VPD region start */
fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base +
fsp_hdr->cfg_region_off);
- /* Verifify the VPD data region is valid */
+ /* Verify the VPD data region is valid */
assert((fsp_vpd->img_rev == VPD_IMAGE_REV) &&
(fsp_vpd->sign == VPD_IMAGE_ID));
@@ -150,7 +154,7 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
sizeof(struct upd_region));
- /* Verifify the UPD data region is valid */
+ /* Verify the UPD data region is valid */
assert(fsp_upd->terminator == UPD_TERMINATOR);
/* Override any UPD setting if required */
diff --git a/arch/x86/lib/pci_type1.c b/arch/x86/lib/pci_type1.c
index 13942a3..a251adc 100644
--- a/arch/x86/lib/pci_type1.c
+++ b/arch/x86/lib/pci_type1.c
@@ -12,6 +12,7 @@
#include <common.h>
#include <asm/io.h>
#include <pci.h>
+#include <asm/pci.h>
#define cfg_read(val, addr, op) (*val = op((int)(addr)))
#define cfg_write(val, addr, op) op((val), (int)(addr))
@@ -21,7 +22,7 @@ static int \
type1_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
- outl(dev | (offset & 0xfc) | 0x80000000, (int)hose->cfg_addr); \
+ outl(dev | (offset & 0xfc) | PCI_CFG_EN, (int)hose->cfg_addr); \
cfg_##rw(val, hose->cfg_data + (offset & mask), op); \
return 0; \
}
@@ -34,10 +35,6 @@ TYPE1_PCI_OP(write, byte, u8, outb, 3)
TYPE1_PCI_OP(write, word, u16, outw, 2)
TYPE1_PCI_OP(write, dword, u32, outl, 0)
-/* bus mapping constants (used for PCI core initialization) */
-#define PCI_REG_ADDR 0x00000cf8
-#define PCI_REG_DATA 0x00000cfc
-
void pci_setup_type1(struct pci_controller *hose)
{
pci_set_ops(hose,