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-rw-r--r--arch/x86/Kconfig15
-rw-r--r--arch/x86/cpu/Makefile1
-rw-r--r--arch/x86/cpu/baytrail/Kconfig9
-rw-r--r--arch/x86/cpu/baytrail/Makefile10
-rw-r--r--arch/x86/cpu/baytrail/early_uart.c77
-rw-r--r--arch/x86/cpu/baytrail/fsp_configs.c156
-rw-r--r--arch/x86/cpu/baytrail/pci.c46
-rw-r--r--arch/x86/cpu/baytrail/valleyview.c38
-rw-r--r--arch/x86/dts/Makefile3
-rw-r--r--arch/x86/dts/microcode/m0130673322.dtsi3284
-rw-r--r--arch/x86/dts/minnowmax.dts45
-rw-r--r--arch/x86/dts/serial.dtsi2
-rw-r--r--arch/x86/include/asm/arch-baytrail/fsp/azalia.h39
-rw-r--r--arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h95
-rw-r--r--arch/x86/include/asm/arch-baytrail/gpio.h13
15 files changed, 3831 insertions, 2 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index c2af607..defdce7 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -41,6 +41,17 @@ config TARGET_CROWNBAY
Intel Platform Controller Hub EG20T, other system components and
peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
+config TARGET_MINNOWMAX
+ bool "Support Intel Minnowboard MAX"
+ help
+ This is the Intel Minnowboard MAX. It contains an Atom E3800
+ processor in a small form factor with Ethernet, micro-SD, USB 2,
+ USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
+ It requires some binary blobs - see README.x86 for details.
+
+ Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+ by U-Boot matches that value.
+
endchoice
config RAMBASE
@@ -382,6 +393,8 @@ config FSP_TEMP_RAM_ADDR
Stack top address which is used in FspInit after DRAM is ready and
CAR is disabled.
+source "arch/x86/cpu/baytrail/Kconfig"
+
source "arch/x86/cpu/coreboot/Kconfig"
source "arch/x86/cpu/ivybridge/Kconfig"
@@ -394,6 +407,8 @@ source "board/google/chromebook_link/Kconfig"
source "board/intel/crownbay/Kconfig"
+source "board/intel/minnowmax/Kconfig"
+
config PCIE_ECAM_BASE
hex
default 0xe0000000
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 62e43c0..5acf8bb 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -12,6 +12,7 @@ extra-y = start.o
obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
obj-y += interrupts.o cpu.o call64.o
+obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
obj-$(CONFIG_SYS_COREBOOT) += coreboot/
obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig
new file mode 100644
index 0000000..e86cc01
--- /dev/null
+++ b/arch/x86/cpu/baytrail/Kconfig
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2015 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+config INTEL_BAYTRAIL
+ bool
+ select HAVE_FSP
diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
new file mode 100644
index 0000000..8914e8b
--- /dev/null
+++ b/arch/x86/cpu/baytrail/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2015 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += early_uart.o
+obj-y += fsp_configs.o
+obj-y += pci.o
+obj-y += valleyview.o
diff --git a/arch/x86/cpu/baytrail/early_uart.c b/arch/x86/cpu/baytrail/early_uart.c
new file mode 100644
index 0000000..4199210
--- /dev/null
+++ b/arch/x86/cpu/baytrail/early_uart.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+
+#define PCI_DEV_CONFIG(segbus, dev, fn) ( \
+ (((segbus) & 0xfff) << 20) | \
+ (((dev) & 0x1f) << 15) | \
+ (((fn) & 0x07) << 12))
+
+/* Platform Controller Unit */
+#define LPC_DEV 0x1f
+#define LPC_FUNC 0
+
+/* Enable UART */
+#define UART_CONT 0x80
+
+/* SCORE Pad definitions */
+#define UART_RXD_PAD 82
+#define UART_TXD_PAD 83
+
+/* Pad base: PAD_CONF0[n]= PAD_BASE + 16 * n */
+#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE)
+
+/* IO Memory */
+#define IO_BASE_ADDRESS 0xfed0c000
+#define IO_BASE_OFFSET_GPSCORE 0x0000
+#define IO_BASE_OFFSET_GPNCORE 0x1000
+#define IO_BASE_OFFSET_GPSSUS 0x2000
+#define IO_BASE_SIZE 0x4000
+
+static inline unsigned int score_pconf0(int pad_num)
+{
+ return GPSCORE_PAD_BASE + pad_num * 16;
+}
+
+static void score_select_func(int pad, int func)
+{
+ uint32_t reg;
+ uint32_t pconf0_addr = score_pconf0(pad);
+
+ reg = readl(pconf0_addr);
+ reg &= ~0x7;
+ reg |= func & 0x7;
+ writel(reg, pconf0_addr);
+}
+
+static void pci_write_config32(int dev, unsigned int where, u32 value)
+{
+ unsigned long addr;
+
+ addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
+ writel(value, addr);
+}
+
+/* This can be called after memory-mapped PCI is working */
+int setup_early_uart(void)
+{
+ /* Enable the legacy UART hardware. */
+ pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, 1);
+
+ /*
+ * Set up the pads to the UART function. This allows the signals to
+ * leave the chip
+ */
+ score_select_func(UART_RXD_PAD, 1);
+ score_select_func(UART_TXD_PAD, 1);
+
+ /* TODO(sjg@chromium.org): Call debug_uart_init() */
+
+ return 0;
+}
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
new file mode 100644
index 0000000..86b6926
--- /dev/null
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#include <common.h>
+#include <asm/arch/fsp/azalia.h>
+#include <asm/fsp/fsp_support.h>
+
+/* ALC262 Verb Table - 10EC0262 */
+static const uint32_t verb_table_data13[] = {
+ /* Pin Complex (NID 0x11) */
+ 0x01171cf0,
+ 0x01171d11,
+ 0x01171e11,
+ 0x01171f41,
+ /* Pin Complex (NID 0x12) */
+ 0x01271cf0,
+ 0x01271d11,
+ 0x01271e11,
+ 0x01271f41,
+ /* Pin Complex (NID 0x14) */
+ 0x01471c10,
+ 0x01471d40,
+ 0x01471e01,
+ 0x01471f01,
+ /* Pin Complex (NID 0x15) */
+ 0x01571cf0,
+ 0x01571d11,
+ 0x01571e11,
+ 0x01571f41,
+ /* Pin Complex (NID 0x16) */
+ 0x01671cf0,
+ 0x01671d11,
+ 0x01671e11,
+ 0x01671f41,
+ /* Pin Complex (NID 0x18) */
+ 0x01871c20,
+ 0x01871d98,
+ 0x01871ea1,
+ 0x01871f01,
+ /* Pin Complex (NID 0x19) */
+ 0x01971c21,
+ 0x01971d98,
+ 0x01971ea1,
+ 0x01971f02,
+ /* Pin Complex (NID 0x1A) */
+ 0x01a71c2f,
+ 0x01a71d30,
+ 0x01a71e81,
+ 0x01a71f01,
+ /* Pin Complex */
+ 0x01b71c1f,
+ 0x01b71d40,
+ 0x01b71e21,
+ 0x01b71f02,
+ /* Pin Complex */
+ 0x01c71cf0,
+ 0x01c71d11,
+ 0x01c71e11,
+ 0x01c71f41,
+ /* Pin Complex */
+ 0x01d71c01,
+ 0x01d71dc6,
+ 0x01d71e14,
+ 0x01d71f40,
+ /* Pin Complex */
+ 0x01e71cf0,
+ 0x01e71d11,
+ 0x01e71e11,
+ 0x01e71f41,
+ /* Pin Complex */
+ 0x01f71cf0,
+ 0x01f71d11,
+ 0x01f71e11,
+ 0x01f71f41,
+};
+
+/*
+ * This needs to be in ROM since if we put it in CAR, FSP init loses it when
+ * it drops CAR.
+ *
+ * TODO(sjg@chromium.org): Move to device tree when FSP allows it
+ *
+ * VerbTable: (RealTek ALC262)
+ * Revision ID = 0xFF, support all steps
+ * Codec Verb Table For AZALIA
+ * Codec Address: CAd value (0/1/2)
+ * Codec Vendor: 0x10EC0262
+ */
+static const struct pch_azalia_verb_table azalia_verb_table[] = {
+ {
+ {
+ 0x10ec0262,
+ 0x0000,
+ 0xff,
+ 0x01,
+ 0x000b,
+ 0x0002,
+ },
+ verb_table_data13
+ }
+};
+
+const struct pch_azalia_config azalia_config = {
+ .pme_enable = 1,
+ .docking_supported = 1,
+ .docking_attached = 0,
+ .hdmi_codec_enable = 1,
+ .azalia_v_ci_enable = 1,
+ .rsvdbits = 0,
+ .azalia_verb_table_num = 1,
+ .azalia_verb_table = azalia_verb_table,
+ .reset_wait_timer_us = 300
+};
+
+void update_fsp_upd(struct upd_region *fsp_upd)
+{
+ struct memory_down_data *mem;
+
+ /*
+ * Configure everything here to avoid the poor hard-pressed user
+ * needing to run Intel's binary configuration tool. It may also allow
+ * us to support the 1GB single core variant easily.
+ *
+ * TODO(sjg@chromium.org): Move to device tree
+ */
+ fsp_upd->mrc_init_tseg_size = 8;
+ fsp_upd->mrc_init_mmio_size = 0x800;
+ fsp_upd->emmc_boot_mode = 0xff;
+ fsp_upd->enable_sdio = 1;
+ fsp_upd->enable_sdcard = 1;
+ fsp_upd->enable_hsuart0 = 1;
+ fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
+ fsp_upd->enable_i2_c0 = 0;
+ fsp_upd->enable_i2_c2 = 0;
+ fsp_upd->enable_i2_c3 = 0;
+ fsp_upd->enable_i2_c4 = 0;
+ fsp_upd->enable_xhci = 0;
+ fsp_upd->igd_render_standby = 1;
+
+ mem = &fsp_upd->memory_params;
+ mem->enable_memory_down = 1;
+ mem->dram_speed = 1;
+ mem->dimm_width = 1;
+ mem->dimm_density = 2;
+ mem->dimm_tcl = 0xb;
+ mem->dimm_trpt_rcd = 0xb;
+ mem->dimm_twr = 0xc;
+ mem->dimm_twtr = 6;
+ mem->dimm_trrd = 6;
+ mem->dimm_trtp = 6;
+ mem->dimm_tfaw = 0x14;
+}
diff --git a/arch/x86/cpu/baytrail/pci.c b/arch/x86/cpu/baytrail/pci.c
new file mode 100644
index 0000000..6c291f9
--- /dev/null
+++ b/arch/x86/cpu/baytrail/pci.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_pci_setup_hose(struct pci_controller *hose)
+{
+ hose->first_busno = 0;
+ hose->last_busno = 0;
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 0,
+ CONFIG_PCI_MEM_BUS,
+ CONFIG_PCI_MEM_PHYS,
+ CONFIG_PCI_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 1,
+ CONFIG_PCI_IO_BUS,
+ CONFIG_PCI_IO_PHYS,
+ CONFIG_PCI_IO_SIZE,
+ PCI_REGION_IO);
+
+ pci_set_region(hose->regions + 2,
+ CONFIG_PCI_PREF_BUS,
+ CONFIG_PCI_PREF_PHYS,
+ CONFIG_PCI_PREF_SIZE,
+ PCI_REGION_PREFETCH);
+
+ pci_set_region(hose->regions + 3,
+ 0,
+ 0,
+ gd->ram_size,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+ hose->region_count = 4;
+}
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
new file mode 100644
index 0000000..a3e837d
--- /dev/null
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <pci_ids.h>
+#include <asm/post.h>
+
+static struct pci_device_id mmc_supported[] = {
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
+};
+
+int cpu_mmc_init(bd_t *bis)
+{
+ printf("mmc init\n");
+ return pci_mmc_init("ValleyView SDHCI", mmc_supported,
+ ARRAY_SIZE(mmc_supported));
+}
+
+int arch_cpu_init(void)
+{
+ int ret;
+
+ post_code(POST_CPU_INIT);
+#ifdef CONFIG_SYS_X86_TSC_TIMER
+ timer_set_base(rdtsc());
+#endif
+
+ ret = x86_cpu_init_f();
+ if (ret)
+ return ret;
+
+ return 0;
+}
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 97ed884..4e0171a 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -1,5 +1,6 @@
dtb-y += chromebook_link.dtb \
- crownbay.dtb
+ crownbay.dtb \
+ minnowmax.dtb
targets += $(dtb-y)
diff --git a/arch/x86/dts/microcode/m0130673322.dtsi b/arch/x86/dts/microcode/m0130673322.dtsi
new file mode 100644
index 0000000..90bf2fb
--- /dev/null
+++ b/arch/x86/dts/microcode/m0130673322.dtsi
@@ -0,0 +1,3284 @@
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x322>;
+intel,date-code = <0x4012014>;
+intel,processor-signature = <0x30673>;
+intel,checksum = <0x17b0d914>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x22030000 0x14200104 0x73060300
+ 0x14d9b017 0x01000000 0x01000000 0xd0cb0000
+ 0x00cc0000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x22030000
+ 0x00000000 0x00000000 0x31031420 0x11320000
+ 0x01000000 0x73060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xf4320000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x0ae10178 0x7c98f9d1 0x41962d85 0x19391270
+ 0xcf3c0336 0xc1f13d6f 0xe46abaf6 0x3b65ca6b
+ 0xdb666815 0x5a17bfc4 0x4fca009d 0x099ae8b3
+ 0x198e2c7d 0x7c665bbf 0xc07a1a7a 0x7dbcee26
+ 0x867296b2 0xc885b6ce 0xe602baff 0x68544b14
+ 0xc928c400 0x3add156d 0x531946f9 0x92a03216
+ 0xda352322 0xd967ee1f 0x3c5170a7 0xf6de834e
+ 0x5a2ed8b3 0x9fb8f050 0x450de17f 0xfd5ef070
+ 0x4954575f 0xa3a071ab 0xb56e2afb 0xe2b48302
+ 0x6655a958 0x57c9a438 0x1b2f688a 0x09309bc4
+ 0x0be95612 0x529c1633 0xc48515d9 0x29eb78df
+ 0x9933409f 0xda58dea9 0x58c805fd 0xbc110f5a
+ 0x40780ec0 0x6ad59bb3 0xc7387fb8 0x591c1490
+ 0xf9335932 0x32130e0b 0xef4b3c96 0xacd903f2
+ 0x5b362539 0xe7f85529 0xcb17c41f 0xe7e440d8
+ 0xfaf7e925 0x969b76fb 0x5edab8c7 0xf00012e8
+ 0x121c2971 0xe5b18959 0xadfd07c0 0x1f09c9d7
+ 0x9781006a 0x39550073 0x6c438b6d 0x436f60bc
+ 0x11000000 0x8514b971 0x40df7b4a 0x6a6b7285
+ 0x7978ef59 0x319bddf5 0x04c68e5a 0xe1c28b10
+ 0x172f63dc 0x306fb95d 0x31d881e8 0x69f8e08d
+ 0x617a99e1 0x1ab6b574 0x2951fa5b 0xcc7e3e94
+ 0xff379d19 0x5c035dec 0xe28ed726 0x22b8a5ac
+ 0xd08b3ac5 0x45c03b9e 0xcea4083c 0xc26758aa
+ 0xbe7cf81e 0x43d898f3 0x5c45a635 0xc9cac095
+ 0xb89aea20 0x2c02b40e 0xe3a8b48d 0xeabfb60e
+ 0x776ed2a9 0x080ae6d5 0x7f64b1df 0x00e40ee6
+ 0x0f1c10f4 0x792e5423 0x787f5459 0x63a8b02c
+ 0x3fd6a255 0x049cae26 0x0949f5ff 0x9aebb236
+ 0xecc01775 0x91b57b84 0xe0e45ea3 0x5a8bf79e
+ 0x356a843a 0x2406795f 0x8aaae5d8 0x6a8c877c
+ 0xa8b2b8f4 0x04cf8f49 0x422d9e2c 0xf09f9896
+ 0xe9b92215 0x9c98fb44 0x88556b7f 0x519d6f4c
+ 0x9e8a016b 0xcb18d16c 0x419b4ee7 0x080b49c8
+ 0xc51b875e 0x46aabc9c 0x262d27eb 0x93ea189d
+ 0xdd0da69d 0x3e5b17e8 0xcc78509a 0x00b07e6e
+ 0x363d5a70 0x64572070 0x8a84abc4 0x1cb03838
+ 0x965fd76a 0x540aafc9 0x83a91654 0x1a722e67
+ 0x4bf98ce1 0x2b3c2ff9 0x972cebd4 0xf3a68395
+ 0x2613e422 0xf8d031d7 0xb1c79a0f 0xfd44f65b
+ 0xa7012a9b 0xd9a15a60 0xc311fc0c 0x6f52f878
+ 0x3d68381d 0xd2a035d7 0xb790c50e 0x9f1e5010
+ 0x41877064 0xa9d1e4ae 0xfe9abbd5 0x60c2c748
+ 0x8167e5ad 0x022dbfb3 0x75abe483 0x51c37170
+ 0x09b8590d 0xc1bb323d 0x2c7336b1 0xd4d0d49b
+ 0xc7f6152b 0x7919d596 0x1e1ff62e 0xc49604a0
+ 0x33857369 0xeaa3f382 0x98b8cd86 0x176e1bf3
+ 0x1a68867b 0x6af0a11c 0x69a82b25 0x48c72525
+ 0xa00aae2d 0xb09f67f4 0x1a99f83d 0x7266cca3
+ 0x8d03a7da 0x2e1d7c49 0x01ac68ae 0x93188770
+ 0x0609e769 0x982ed28d 0xe40999e0 0x8932ebab
+ 0x5637ad5a 0x2725e8ad 0x56d7caaf 0xc351faa2
+ 0x09dbd737 0x0d2f3bf0 0x0623330d 0xdd547489
+ 0xcca7e722 0xa9096d13 0x95b17818 0xc092cb81
+ 0x72c6eefc 0x1811c37e 0x78161497 0x8be0c4c6
+ 0xd63aeb19 0x91ab68df 0x8f2e5e4d 0xf4c74566
+ 0x7677a553 0x19698ac3 0xedca0620 0x77f32470
+ 0x031e011b 0x751f6696 0xb277d06e 0x3eae2742
+ 0x133e621a 0x38fa3172 0x9398cc1c 0xf42a507b
+ 0x4547d933 0x63a91eb0 0xf5bcf6a4 0x926ba056
+ 0x0adf5bce 0x140f53e4 0x7ff6bb5c 0x87dd79ba
+ 0xbba240ac 0x694f743d 0x709cdb20 0x5b4d4401
+ 0xc9693610 0x55f9f268 0x1142bc3f 0xf8fe3689
+ 0x04a93c4c 0x33dedc46 0xdc73c725 0x2f5ba264
+ 0x5b7a6a69 0x024b64f5 0x6e8bfa12 0x62bf2aa7
+ 0x520f5a07 0x3c7c4292 0xb7ad2613 0x1f78fc87
+ 0xd5284e4e 0x2c730f33 0x8861e947 0x8bacef7d
+ 0xbafa2608 0x14ed0b5b 0x3b9bfb02 0x24ced271
+ 0x002b2941 0x22d4431c 0x855f4248 0x5ec46e29
+ 0x6f1f42fb 0x5dd24fe0 0x290961f6 0xf392dbaf
+ 0xa1a8d9c2 0x61e18f4e 0xfda59a70 0x5498daa5
+ 0x5ae7ea6f 0xf058c635 0x6817ebee 0x8e30dc8b
+ 0x7c8d79be 0x5fb15b9b 0xeed64741 0xe2642a94
+ 0x680d7e6e 0x3cbad7aa 0x808c415f 0xe9323aa2
+ 0xaadf5b25 0xf60abf13 0xd5c47967 0xc248d0b3
+ 0x0f232cbd 0x84092449 0x5744384b 0x5e153ded
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+ 0x68c87e37 0xbced6b8c 0x536cc252 0x68bab5ca
+ 0x1158c6c5 0xae0e9509 0x66fa6885 0x22bf2b9a
+ 0xa7a60a97 0x18f4f609 0x348623eb 0x773e705f
+ 0xb3d6622f 0x8f348186 0x81cb9856 0x64bf21ba
+ 0x47e1f96d 0xc95a5843 0xeff6cfce 0x08cb092c
+ 0xf214e48d 0xce272fec 0x57bf90df 0x3c425ea8
+ 0x856e1f5e 0x5c21d1b6 0x105488a3 0x553971eb
+ 0xde614ee5 0xdfa3ac81 0xc5eca5b1 0x69d02d23
+ 0x2a0fefb7 0xf9a01854 0xdd99f277 0x75014d7d
+ 0x3830e3dd 0x7dd8f1e7 0xdac5ac92 0xbf57c03a
+ 0xa5e6a6c7 0xb7c1b7a9 0xc8c8405e 0xfd1977da
+ 0x1e6a7ca4 0x299e1025 0x651a0e55 0x53d624a7
+ 0xccc9e861 0x901bce45 0x1de5a1ab 0x6140dcef
+ 0x3e09eafb 0x20c63cd0 0xff642faa 0xbc91a0a7
+ 0xe373e111 0x857236e7 0xe3e61037 0x0b6cc497
+ 0xca1da7e6 0x60e53803 0xb68663db 0x42e9956a
+ 0xbf4a1650 0xb43f25ec 0xc1232a3a 0x283c2ff3
+ 0xcd233183 0x17ccdfc0 0x03ac3e6d 0xa68ced48
+ 0xe38217d5 0x03c6472d 0x6a623afc 0xfce0d117
+ 0x448ee829 0x0909efd4 0x843a3b4a 0x9ad07683
+ 0x2250af2a 0x01ecc053 0x29684919 0x4ee0c62e
+ 0xa326a904 0x3ec83943 0xc42b0663 0x966379b2
+ 0xc672ece4 0x39391ad3 0x689a10f9 0xd3e9cbd6
+ 0x4bfa8446 0xd1ef6375 0xfe01b6a9 0xbda7d01a
+ 0x1e6879bf 0x05bdf46e 0x14ccab04 0xb02ae668
+ 0x58b51752 0x5eb8e83c 0x753d99de 0x87e4235b
+ 0x80b2afe7 0x127439fe 0x127a98a4 0xe5934c92
+ 0x86044bc0 0xa9664abb 0x91365b53 0x35b14bda
+ 0x67755842 0x7239651a 0x49e0b2e6 0xbb1d25fe
+ 0x51ca7213 0xaff2fd82 0xc1223aba 0x02941bcf
+ 0xb6ec2cfe 0xaa817dc0 0xe0475250 0x78098112
+ 0x750ae102 0x0b3135fa 0x23b648d4 0xbc9d78bd
+ 0xc5d7e046 0xe90ef47c 0x7f21eb75 0xdb304b0b
+ 0xa2c12ee2 0xb45e62ed 0x9f50feb6 0xe036ff55
+ 0x422f410b 0x2385de45 0xb37df6a5 0x4c2abf10
+ 0x6a2c7370 0xf35197ac 0x381face9 0x694761c6
+ 0xb2275097 0x208824c7 0x945300a0 0x4ad3f83d
+ 0x38a7aa12 0x00daaf41 0xcd4b2c19 0x25b2e8f7
+ 0x60d3e39b 0xb3dd8220 0x152f86ab 0xd1ec4233
+ 0x1c3df78a 0x5aeac74e 0xdeea2fe3 0xcfcf9b2e
+ 0x6efc8b2a 0x12a8c5c3 0xb56384e4 0x1b1fe549
+ 0xc55acb4d 0x78e7306a 0x733b0f70 0xf4afe6be
+ 0x6d904b03 0x7ddd7862 0x4da02602 0xfce1e904
+ 0x78773a4b 0x9083e908 0xda8a7593 0xafd8776e
+ 0x9e5ae37a 0xd6e7c557 0xad27adaa 0xd0f1a995
+ 0x1c84e046 0x3319b21a 0xd24c0d03 0x1789df77
+ 0x0f02b9ff 0xdb911f76 0xb2df7654 0x2e75a7bd
+ 0x8acc6fd3 0x3c16ec0b 0xe0d7ac22 0x3ddd1ce1
+ 0xfa9ec67a 0x48f2c409 0xf8099606 0xd73a459d
+ 0x9b2b3fa5 0x8e3c3e9c 0x8b99286a 0x006c0e07
+ 0xc299ded3 0x8a2bd400 0x74508dd4 0x609b4afc
+ 0x1a532838 0xb352a629 0xd390d8af 0x440a5798
+ 0xd31f6ad5 0x161aa48e 0x24a4359f 0xf39f49f7
+ 0xff160d2a 0x27a24637 0x84c46d40 0x988d026a
+ 0x5697a68f 0xeae970a0 0x42689e3d 0xc84ee62f
+ 0x764aabd5 0xb6d74ba5 0x8efc05a6 0xf2d0eccb
+ 0x2b4fa41c 0xad24799f 0xf73b8353 0x76bcd448
+ 0x08172d5e 0x5c6be301 0x926ffdd6 0xfa31009f
+ 0x8339c5f9 0x9dde2840 0x00c2d730 0x6402335f
+ 0xf6f84eda 0x5b0e628a 0x140dbafb 0x0533ee67
+ 0xa7523e60 0x20ca14b3 0x1145d280 0xb0c0ba41
+ 0x81f174d1 0xb80fc64e 0xe8321cfe 0x5762e501
+ 0x9e266b75 0x2695a738 0xe3104779 0x1d1ea19e
+ 0x15fd1d53 0xf0fbd4ee 0xc82f4552 0x4ea98e23
+ 0xec892d69 0x66ccadeb 0x2fdf99b4 0xafffec15
+ 0x2de5ee13 0x5e6ead7f 0x20b111cd 0x752254d1
+ 0xc0126f43 0xe2695fd8 0x38651d40 0x15b708ce
+ 0xf2c2ffdc 0xec24c68c 0x04351ddc 0xceac029b
+ 0x0525fc89 0x90e28526 0x0a23a4c2 0xbb33a5c4
+ 0x13f1fc38 0x66d79cd9 0x0acabe80 0x8d4ef5d8
+ 0x4091808e 0x02f7150b 0xf550597e 0x52703c3f
+ 0xfc954b68 0xe9ebaccb 0xd4f35b2a 0x93793446
+ 0xc40799e6 0xa963fc0c 0x92c8d8f1 0xbc8218dc
+ 0x9ec5c30a 0x8a6a2217 0x63d13dfe 0xea664e1e
+ 0x487192a7 0x1c8f8610 0x88e20f93 0xc54a6de3
+ 0x0111ae79 0x1335f02e 0xa2e2d37d 0xc2563697
+ 0x5fffcdec 0x233919ab 0x3bab1329 0x61943e99
+ 0xea7940f7 0x3cc62cf4 0xaedc5bc4 0x41b63f2c
+ 0x6dbf285f 0xb4793534 0x0e1013f2 0xc54d8c2d
+ 0x23c587f7 0x75df0092 0xc055254a 0x55db2c71
+ 0x518eaa5b 0x55c810d6 0x9c44ca37 0x034287ea
+ 0xe06a0567 0x221a0d8c 0x037a9164 0x36693ef9
+ 0xb7d270a6 0xa8d84a63 0xe8862970 0x484077b7
+ 0xab426cb7 0x37db7c9e 0xb34e1752 0x35444958
+ 0x00d48e90 0x8142602d 0x8ca28e2c 0x714598c9
+ 0xb1cce1be 0xbb98db74 0x400e1029 0x330cb2b6
+ 0x1fd3f8ce 0x2abf7516 0xc2d07e5c 0x2b1d2b80
+ 0xf06bd895 0x2fa7bc09 0xbdbdf893 0xd8466f85
+ 0x61e551b0 0x5b99bfb8 0x86ea5ee7 0xfd82ff9a
+ 0xd7c6344a 0x1fa144d8 0x650f0f02 0x71bd73cf
+ 0x2825177d 0x56c76399 0x2e0b873e 0xc3bf939d
+ 0xf8bc3c1b 0x468482e7 0x33cb98a7 0xa679eaf4
+ 0x32ba9b49 0xde86d50c 0x9eeeeee5 0x94a306e5
+ 0x432e1c9c 0x37997d0c 0xa84d981f 0xbe07b56d
+ 0x4ab6d465 0xa3cd92c4 0x5dea82ab 0xf771249d
+ 0x78f87ba5 0x8105df1c 0x3d74e1c1 0xf48cd4c1
+ 0x8ad010e1 0x9e9a2758 0x509c8953 0xeaaed79a
+ 0x97a4ecb7 0x23ffceb0 0xb3e42e61 0x5f41b4eb
+ 0x14d2804c 0x2d635ad3 0xe1314781 0x3921ec18
+ 0x3dbebec3 0x94e0df22 0xb0b4724e 0x0e7f986b
+ 0x83dd7694 0x7041a22e 0x3c942757 0xd6ff5cbb
+ 0x048b0426 0xa5d6c4cb 0x1f4e3bbd 0x78d5924e
+ 0x6a857d77 0x1d115ecc 0x73c6a888 0xefb934ee
+ 0xa7d1702b 0x6794a668 0x03715b90 0xfbab19f9
+ 0xd5a433df 0x12f4d421 0x40519650 0x636a093e
+ 0x1601be15 0xe0fbef6f 0x79d775bc 0x789c3a30
+ 0x4d9fa618 0xedf8fa70 0xb0fa402d 0x692ee91b
+ 0x5a593e5c 0x0fa3667f 0x3f51a636 0x935e28c7
+ 0x230b725a 0x4929bc83 0x76de40ad 0x2d9a5f7f
+ 0x8799e033 0xbf2700b0 0x5220159d 0x1ed71ca5
+ 0xcc66f114 0x15fd868d 0x4236645a 0xded2558e
+ 0xa561cc0d 0x02822e5b 0xd0177f80 0xf09badd9
+ 0xd5380ae3 0xcfc11a46 0x36713416 0x7f3d60cc
+ 0x4018797e 0xc6b23941 0xcb5a4861 0x614ce6df
+ 0xabfc0629 0xa519bcfc 0x911f04f0 0xe509b546
+ 0xbb411eb9 0x9e6b921c 0xbf0b1c70 0x80c2901c
+ 0x85786713 0xad2aafec 0x62711ba7 0x6edb4971
+ 0x214eb137 0x45b1b313 0x6742d5e9 0x7daf37a6
+ 0x21d6a27a 0x059424f7 0x2c8c3dfb 0xe7a06c77
+ 0x10815625 0xb4dc69e8 0x52767f66 0x44d48738
+ 0x84d26c93 0x09008893 0xfc21394a 0x82155a72
+ 0xc4fd7512 0x6d43cd2f 0xcae99e08 0x453175ae
+ 0xc6ee93a3 0x2fed0eac 0xe48fb73d 0x0afe2d2a
+ 0x5966735e 0xdc7e5fb6 0xed1ef13d 0x7e08a106
+ 0xd3ca0e6b 0x4ce5ca02 0xa0beebed 0xe982c609
+ 0x1ee9e5a2 0x24ae26cb 0xfd4c08d4 0x5e85e850
+ 0x11b54b3b 0x87209692 0x4a5b0c35 0xcd25dd6f
+ 0xd9570253 0xaad0b9fe 0xaf984fee 0x6cf7ae2d
+ 0x45d9926c 0x07a66ac6 0x8e7aacdc 0xaf587d66
+ 0x53972a4e 0x8da4a6c9 0x2bc311e5 0x36938ae8
+ 0x179b965d 0x515743f7 0xb5bbbdcd 0xd8602715
+ 0x9e43049f 0x4e78a080 0xba3f1750 0x68635cf0
+ 0x85823047 0xbb03b5fd 0xb0d747c8 0x58d214af
+ 0x94b1ba85 0x6d2cf8ac 0x2bc1faeb 0x6bd7c1e3
+ 0x127658e9 0x8b499020 0xab8f0f62 0xee665a6a
+ 0x89240e4d 0x8a95342b 0x00b38ccc 0xe6b14d9d
+ 0x32a2af71 0x4c9ecb69 0xc8de2685 0xd7385184
+ 0x8e943872 0x809b2c79 0x108511da 0x08b4f54d
+ 0x95f52442 0x26fe296f 0xf7e037c0 0xa1aecdd3
+ 0x89774a91 0xde67c55f 0x1f9816dc 0x1469a4c2
+ 0x28240be2 0x5fd0ad14 0x0949db3a 0x451b94d3
+ 0x637e6d49 0x8a4771c8 0xf65104b7 0xc3058c40
+ 0x592fe4d0 0xe26129f0 0xe66e6ce9 0x26ab39b8
+ 0x308da532 0x205afe77 0x6dc78664 0x84d4890f
+ 0x9d49fcb0 0xcac8f2ed 0xe713d798 0xfed7c75b
+ 0xe441a0d4 0xdf60df37 0xc2eed2f5 0x2d68b20e
+ 0x7827c89a 0x9d4cb9f2 0xb8912cce 0x07516335
+ 0x976ffbb6 0x5cd0de48 0xed716f54 0x6f3c9f7f
+ 0x34cf42d1 0xc1027cbb 0xde67c065 0xe0a229af
+ 0xfc8bd2e8 0xd62ca176 0x8bfb76b2 0x54a1388f
+ 0xe0650bb6 0x6d60682b 0xe16cf130 0xbd7c3ca2
+ 0xea642814 0xa25f4d44 0x27013786 0x7316aa38
+ 0x571511c8 0xf1b6b789 0xb7bfe72b 0x8fd2652c
+ 0xbfc7771a 0x51a2e551 0x3bd738c2 0x2698b495
+ 0xec69a196 0xd5ecb5c4 0x9bd3224c 0x6d9ab4cf
+ 0x326c9942 0x4d711191 0xde9be50a 0xa980ca0b
+ 0xe8e59dd0 0x4439e4ae 0x35de914d 0xee499a84
+ 0xd1ca0c9d 0xfe6ee96d 0x5b1f4fd0 0xabf0621a
+ 0x0c8220c7 0xcb6dbb1e 0xa5116036 0xe858d3c3
+ 0x728e3a56 0x3b33e818 0xbe2643c1 0x497bbcc7
+ 0xeb369828 0x9a4a01be 0x8c7e72a6 0xaf052f25
+ 0x8d3ca85b 0x4703e55e 0x45647d4c 0x86d1e3e8
+ 0x40ab59f9 0x3259b195 0xf979a147 0xb8961870
+ 0x88b024f9 0x366e26bc 0xd6811525 0x252910c2
+ 0x4223a20e 0x7fc971a3 0x4a639bf3 0xb6550c3b
+ 0xfe05e552 0xbdc98897 0x509923ff 0xf51a5abc
+ 0xc6cc0891 0x61cdac05 0x03a68664 0x1b80cc76
+ 0xe18d8ee1 0x798bb4d2 0xd7769bf9 0x9ab4c02d
+ 0x7484774b 0xa9ee2c8b 0x87d34c85 0x15697682
+ 0x9f6a4a55 0x9d7a731c 0x10014d6a 0xb9798070
+ 0xd42f79cb 0x89db59b3 0xd5b0a0b6 0xf60864a5
+ 0x2d6fb084 0x1cb607b2 0x48232701 0x9310cbc6
+ 0x5bc81c98 0x6b25016c 0x2014b99d 0x0836e60b
+ 0x0addbc4c 0x3b8bac7c 0x8d95ac77 0x1d56c3c7
+ 0x58333104 0x3d6eb719 0x676eb951 0xd5c2d1a3
+ 0x239dae86 0x92181ab8 0xbdde9741 0x7995d452
+ 0xe0020661 0x2f80c8b7 0xeedcd4fc 0xe4bde175
+ 0xb98fdf78 0x84b9228f 0x78ecb4f3 0xe99e5d46
+ 0xa33b9b96 0xe2cbc71c 0xc19e2146 0xdc0ee758
+ 0x2d8f8767 0x2036685b 0x149df155 0x2e7ab376
+ 0xb13b4266 0xf5c8a3b0 0x02ca1e19 0x1badd81b
+ 0xb9c1832a 0x73b31f75 0x69979b55 0x567070a2
+ 0x2edeb3dc 0x26b55921 0x461df49f 0xc1aba883
+ 0x25d6faec 0x5260e9bf 0xa8ccdd4c 0x04291961
+ 0xfaf7a1b8 0xbc2d36e3 0xd6c86385 0x2757fbb9
+ 0x62c7107c 0x87dac461 0x0c006454 0x0e971e49
+ 0x4749afca 0x7f1fb389 0xdc0b69d3 0xc69fab09
+ 0x12c372c9 0x78480a51 0x8ab03a94 0xb37022ca
+ 0x1d00e893 0x0989de45 0x8c819503 0x8e0e1c06
+ 0x11cfef86 0x3c2386a6 0x66c0e6c8 0x1befa478
+ 0xd2e7a4a7 0x9a8b5917 0x2cfa1816 0xaf7e6c7a
+ 0xd6c9f0ff 0x1aada3e0 0xbe36a471 0x5a91f3c7
+ 0x6c61ea95 0x5246ef7c 0x20bc86c4 0xcfd87abd
+ 0xdc61f595 0x8310a684 0x0477e35c 0xe59e776f
+ 0xfa403863 0xdaf7bcb1 0xd6084825 0xb90bb047
+ 0xeb9ff684 0x7223fbca 0x6b4af987 0x6b2553f8
+ 0xdaabc6d2 0x82e2ebc3 0xa7c1c054 0x667eb0a7
+ 0x53a0c7d4 0x3fcba743 0x38170187 0x2a2e5830
+ 0xee134608 0xcd6e0112 0xac0831f9 0x9537d532
+ 0x1e176b9c 0xe3fcb69f 0x17a2eee9 0xa9e6467f
+ 0xbf6b0246 0x6a08c0fb 0x7fb943b6 0xb8f67c0e
+ 0x2b3b4ffc 0xb155d20c 0x4eb5de53 0xf078715b
+ >;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
new file mode 100644
index 0000000..8f34369
--- /dev/null
+++ b/arch/x86/dts/minnowmax.dts
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+
+/ {
+ model = "Intel Minnowboard Max";
+ compatible = "intel,minnowmax", "intel,baytrail";
+
+ aliases {
+ serial0 = &serial;
+ };
+
+ config {
+ silent_console = <0>;
+ };
+
+ chosen {
+ stdout-path = "/serial";
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich";
+ spi-flash@0 {
+ reg = <0>;
+ compatible = "sst,25vf016b", "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ };
+ };
+
+ microcode {
+ update@0 {
+#include "microcode/m0130673322.dtsi"
+ };
+ };
+
+};
diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi
index 9b097f4..6865eed 100644
--- a/arch/x86/dts/serial.dtsi
+++ b/arch/x86/dts/serial.dtsi
@@ -1,5 +1,5 @@
/ {
- serial {
+ serial: serial {
compatible = "x86-uart";
reg = <0x3f8 8>;
reg-shift = <0>;
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/azalia.h b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h
new file mode 100644
index 0000000..d96a20f
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/fsp/azalia.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef _FSP_AZALIA_H_
+#define _FSP_AZALIA_H_
+
+struct __packed pch_azalia_verb_table_header {
+ uint32_t vendor_device_id;
+ uint16_t sub_system_id;
+ uint8_t revision_id; /* 0xff applies to all steppings */
+ uint8_t front_panel_support;
+ uint16_t number_of_rear_jacks;
+ uint16_t number_of_front_jacks;
+};
+
+struct __packed pch_azalia_verb_table {
+ struct pch_azalia_verb_table_header verb_table_header;
+ const uint32_t *verb_table_data;
+};
+
+struct __packed pch_azalia_config {
+ uint8_t pme_enable:1;
+ uint8_t docking_supported:1;
+ uint8_t docking_attached:1;
+ uint8_t hdmi_codec_enable:1;
+ uint8_t azalia_v_ci_enable:1;
+ uint8_t rsvdbits:3;
+ /* number of verb tables provided by platform */
+ uint8_t azalia_verb_table_num;
+ const struct pch_azalia_verb_table *azalia_verb_table;
+ /* delay timer after azalia reset */
+ uint16_t reset_wait_timer_us;
+};
+
+#endif
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
new file mode 100644
index 0000000..82862f6
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_VPD_H
+#define __FSP_VPD_H
+
+struct memory_down_data {
+ uint8_t enable_memory_down;
+ uint8_t dram_speed;
+ uint8_t dram_type;
+ uint8_t dimm_0_enable;
+ uint8_t dimm_1_enable;
+ uint8_t dimm_width;
+ uint8_t dimm_density;
+ uint8_t dimm_bus_width;
+ uint8_t dimm_sides; /* Ranks Per dimm_ */
+ uint8_t dimm_tcl; /* tCL */
+ /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
+ uint8_t dimm_trpt_rcd;
+ uint8_t dimm_twr; /* tWR in DRAM clk */
+ uint8_t dimm_twtr; /* tWTR in DRAM clk */
+ uint8_t dimm_trrd; /* tRRD in DRAM clk */
+ uint8_t dimm_trtp; /* tRTP in DRAM clk */
+ uint8_t dimm_tfaw; /* tFAW in DRAM clk */
+};
+
+struct __packed upd_region {
+ uint64_t signature; /* Offset 0x0000 */
+ uint8_t reserved0[24]; /* Offset 0x0008 */
+ uint16_t mrc_init_tseg_size; /* Offset 0x0020 */
+ uint16_t mrc_init_mmio_size; /* Offset 0x0022 */
+ uint8_t mrc_init_spd_addr1; /* Offset 0x0024 */
+ uint8_t mrc_init_spd_addr2; /* Offset 0x0025 */
+ uint8_t emmc_boot_mode; /* Offset 0x0026 */
+ uint8_t enable_sdio; /* Offset 0x0027 */
+ uint8_t enable_sdcard; /* Offset 0x0028 */
+ uint8_t enable_hsuart0; /* Offset 0x0029 */
+ uint8_t enable_hsuart1; /* Offset 0x002a */
+ uint8_t enable_spi; /* Offset 0x002b */
+ uint8_t reserved1; /* Offset 0x002c */
+ uint8_t enable_sata; /* Offset 0x002d */
+ uint8_t sata_mode; /* Offset 0x002e */
+ uint8_t enable_azalia; /* Offset 0x002f */
+ uint32_t azalia_config_ptr; /* Offset 0x0030 */
+ uint8_t enable_xhci; /* Offset 0x0034 */
+ uint8_t enable_lpe; /* Offset 0x0035 */
+ uint8_t lpss_sio_enable_pci_mode; /* Offset 0x0036 */
+ uint8_t enable_dma0; /* Offset 0x0037 */
+ uint8_t enable_dma1; /* Offset 0x0038 */
+ uint8_t enable_i2_c0; /* Offset 0x0039 */
+ uint8_t enable_i2_c1; /* Offset 0x003a */
+ uint8_t enable_i2_c2; /* Offset 0x003b */
+ uint8_t enable_i2_c3; /* Offset 0x003c */
+ uint8_t enable_i2_c4; /* Offset 0x003d */
+ uint8_t enable_i2_c5; /* Offset 0x003e */
+ uint8_t enable_i2_c6; /* Offset 0x003f */
+ uint8_t enable_pwm0; /* Offset 0x0040 */
+ uint8_t enable_pwm1; /* Offset 0x0041 */
+ uint8_t enable_hsi; /* Offset 0x0042 */
+ uint8_t igd_dvmt50_pre_alloc; /* Offset 0x0043 */
+ uint8_t aperture_size; /* Offset 0x0044 */
+ uint8_t gtt_size; /* Offset 0x0045 */
+ uint32_t serial_debug_port_address; /* Offset 0x0046 */
+ uint8_t serial_debug_port_type; /* Offset 0x004a */
+ uint8_t mrc_debug_msg; /* Offset 0x004b */
+ uint8_t isp_enable; /* Offset 0x004c */
+ uint8_t scc_enable_pci_mode; /* Offset 0x004d */
+ uint8_t igd_render_standby; /* Offset 0x004e */
+ uint8_t txe_uma_enable; /* Offset 0x004f */
+ uint8_t os_selection; /* Offset 0x0050 */
+ uint8_t emmc45_ddr50_enabled; /* Offset 0x0051 */
+ uint8_t emmc45_hs200_enabled; /* Offset 0x0052 */
+ uint8_t emmc45_retune_timer_value; /* Offset 0x0053 */
+ uint8_t unused_upd_space1[156]; /* Offset 0x0054 */
+ struct memory_down_data memory_params; /* Offset 0x00f0 */
+ uint16_t terminator; /* Offset 0x0100 */
+};
+
+#define VPD_IMAGE_ID 0x3157454956594C56 /* 'VLYVIEW1' */
+#define VPD_IMAGE_REV 0x00000303
+
+struct __packed vpd_region {
+ uint64_t sign; /* Offset 0x0000 */
+ uint32_t img_rev; /* Offset 0x0008 */
+ uint32_t upd_offset; /* Offset 0x000c */
+ uint8_t unused[16]; /* Offset 0x0010 */
+ uint32_t fsp_res_memlen; /* Offset 0x0020 */
+ uint8_t platform_type; /* Offset 0x0024 */
+ uint8_t enable_secure_boot; /* Offset 0x0025 */
+};
+#endif
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h
new file mode 100644
index 0000000..ab4e059
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_GPIO_H_
+#define _X86_ARCH_GPIO_H_
+
+/* Where in config space is the register that points to the GPIO registers? */
+#define PCI_CFG_GPIOBASE 0x44
+
+#endif /* _X86_ARCH_GPIO_H_ */