diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/tegra30/Kconfig | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/tegra-common/board.c | 64 | ||||
| -rw-r--r-- | arch/arm/dts/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/dts/tegra30-apalis.dts | 304 | ||||
| -rw-r--r-- | arch/arm/dts/tegra30-colibri.dts | 4 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra114/mc.h | 37 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra114/tegra.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra20/mc.h | 36 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra20/tegra.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra30/mc.h | 38 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra30/tegra.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/mach-types.h | 13 |
12 files changed, 453 insertions, 51 deletions
diff --git a/arch/arm/cpu/armv7/tegra30/Kconfig b/arch/arm/cpu/armv7/tegra30/Kconfig index 54aec4e..3abdc7b 100644 --- a/arch/arm/cpu/armv7/tegra30/Kconfig +++ b/arch/arm/cpu/armv7/tegra30/Kconfig @@ -3,6 +3,9 @@ if TEGRA30 choice prompt "Tegra30 board select" +config TARGET_APALIS_T30 + bool "Toradex Apalis T30 board" + config TARGET_BEAVER bool "NVIDIA Tegra30 Beaver evaluation board" @@ -20,6 +23,7 @@ endchoice config SYS_SOC default "tegra30" +source "board/toradex/apalis_t30/Kconfig" source "board/nvidia/beaver/Kconfig" source "board/nvidia/cardhu/Kconfig" source "board/toradex/colibri_t30/Kconfig" diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c index 433da09..b6a84a5 100644 --- a/arch/arm/cpu/tegra-common/board.c +++ b/arch/arm/cpu/tegra-common/board.c @@ -9,6 +9,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> +#include <asm/arch/mc.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/pmc.h> @@ -27,55 +28,6 @@ enum { UART_COUNT = 5, }; -#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ - defined(CONFIG_TEGRA114) -/* - * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0, - * so we are using this value to identify memory size. - */ -unsigned int query_sdram_size(void) -{ - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; - u32 reg; - - reg = readl(&pmc->pmc_scratch20); - debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg); - -#if defined(CONFIG_TEGRA20) - /* bits 30:28 in OdmData are used for RAM size on T20 */ - reg &= 0x70000000; - - switch ((reg) >> 28) { - case 1: - return 0x10000000; /* 256 MB */ - case 0: - case 2: - default: - return 0x20000000; /* 512 MB */ - case 3: - return 0x40000000; /* 1GB */ - } -#else /* Tegra30/Tegra114 */ - /* bits 31:28 in OdmData are used for RAM size on T30 */ - switch ((reg) >> 28) { - case 0: - case 1: - default: - return 0x10000000; /* 256 MB */ - case 2: - return 0x20000000; /* 512 MB */ - case 3: - return 0x30000000; /* 768 MB */ - case 4: - return 0x40000000; /* 1GB */ - case 8: - return 0x7ff00000; /* 2GB - 1MB */ - } -#endif -} -#else -#include <asm/arch/mc.h> - /* Read the RAM size directly from the memory controller */ unsigned int query_sdram_size(void) { @@ -83,12 +35,22 @@ unsigned int query_sdram_size(void) u32 size_mb; size_mb = readl(&mc->mc_emem_cfg); +#if defined(CONFIG_TEGRA20) + debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", size_mb); + size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024); +#else debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb); + size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024 * 1024); +#endif - return size_mb * 1024 * 1024; -} +#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) + /* External memory limited to 2047 MB due to IROM/HI-VEC */ + if (size_mb == SZ_2G) size_mb -= SZ_1M; #endif + return size_mb; +} + int dram_init(void) { /* We do not initialise DRAM here. We just query the size */ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c37580e..c346063 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -22,6 +22,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-ventana.dtb \ tegra20-whistler.dtb \ tegra20-colibri_t20_iris.dtb \ + tegra30-apalis.dtb \ tegra30-beaver.dtb \ tegra30-cardhu.dtb \ tegra30-colibri.dtb \ diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts new file mode 100644 index 0000000..5bad3e7 --- /dev/null +++ b/arch/arm/dts/tegra30-apalis.dts @@ -0,0 +1,304 @@ +/dts-v1/; + +#include "tegra30.dtsi" + +/ { + model = "Toradex Apalis T30"; + compatible = "toradex,apalis_t30", "nvidia,tegra30"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c500"; + i2c3 = "/i2c@7000c700"; + sdhci0 = "/sdhci@78000600"; + sdhci1 = "/sdhci@78000400"; + sdhci2 = "/sdhci@78000000"; + usb0 = "/usb@7d000000"; + usb1 = "/usb@7d004000"; + usb2 = "/usb@7d008000"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + pcie-controller@00003000 { + status = "okay"; + avdd-pexa-supply = <&vdd2_reg>; + vdd-pexa-supply = <&vdd2_reg>; + avdd-pexb-supply = <&vdd2_reg>; + vdd-pexb-supply = <&vdd2_reg>; + avdd-pex-pll-supply = <&vdd2_reg>; + avdd-plle-supply = <&ldo6_reg>; + vddio-pex-ctl-supply = <&sys_3v3_reg>; + hvdd-pex-supply = <&sys_3v3_reg>; + + pci@1,0 { + nvidia,num-lanes = <4>; + }; + + pci@2,0 { + nvidia,num-lanes = <1>; + }; + + pci@3,0 { + status = "okay"; + nvidia,num-lanes = <1>; + }; + }; + + /* + * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* GEN2_I2C: unused */ + + /* + * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on + * carrier board) + */ + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&sys_3v3_reg>; + vcc2-supply = <&sys_3v3_reg>; + vcc3-supply = <&vio_reg>; + vcc4-supply = <&sys_3v3_reg>; + vcc5-supply = <&sys_3v3_reg>; + vcc6-supply = <&vio_reg>; + vcc7-supply = <&charge_pump_5v0_reg>; + vccio-supply = <&sys_3v3_reg>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + /* SW1: +V1.35_VDDIO_DDR */ + vdd1_reg: vdd1 { + regulator-name = "vddio_ddr_1v35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + /* SW2: +V1.05 */ + vdd2_reg: vdd2 { + regulator-name = + "vdd_pexa,vdd_pexb,vdd_sata"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + /* SW CTRL: +V1.0_VDD_CPU */ + vddctrl_reg: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + }; + + /* SWIO: +V1.8 */ + vio_reg: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* LDO1: unused */ + + /* + * EN_+V3.3 switching via FET: + * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN + * see also v3_3 fixed supply + */ + ldo2_reg: ldo2 { + regulator-name = "en_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* +V1.2_CSI */ + ldo3_reg: ldo3 { + regulator-name = + "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + /* +V1.2_VDD_RTC */ + ldo4_reg: ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* + * +V2.8_AVDD_VDAC: + * only required for analog RGB + */ + ldo5_reg: ldo5 { + regulator-name = "avdd_vdac"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + /* + * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V + * but LDO6 can't set voltage in 50mV + * granularity + */ + ldo6_reg: ldo6 { + regulator-name = "avdd_plle"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + /* +V1.2_AVDD_PLL */ + ldo7_reg: ldo7 { + regulator-name = "avdd_pll"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* +V1.0_VDD_DDR_HS */ + ldo8_reg: ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + }; + + /* SPI1: Apalis SPI1 */ + spi@7000d400 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + /* SPI4: CAN2 */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + /* SPI5: Apalis SPI2 */ + spi@7000dc00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + /* SPI6: CAN1 */ + spi@7000de00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + sdhci@78000000 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio 229 1>; /* PCC5, SD1_CD# */ + }; + + sdhci@78000400 { + status = "okay"; + bus-width = <8>; + cd-gpios = <&gpio 171 1>; /* PV3, MMC1_CD# */ + }; + + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ + usb@7d000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,vbus-gpio = <&gpio 157 0>; /* PT5, USBO1_EN */ + }; + + /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ + usb@7d004000 { + status = "okay"; + nvidia,vbus-gpio = <&gpio 233 0>; /* PDD1, USBH_EN */ + phy_type = "utmi"; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ + usb@7d008000 { + status = "okay"; + nvidia,vbus-gpio = <&gpio 233 0>; /* PDD1, USBH_EN */ + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + sys_3v3_reg: regulator@100 { + compatible = "regulator-fixed"; + reg = <100>; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + charge_pump_5v0_reg: regulator@101 { + compatible = "regulator-fixed"; + reg = <101>; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; +}; diff --git a/arch/arm/dts/tegra30-colibri.dts b/arch/arm/dts/tegra30-colibri.dts index df79c26..572520a 100644 --- a/arch/arm/dts/tegra30-colibri.dts +++ b/arch/arm/dts/tegra30-colibri.dts @@ -6,6 +6,10 @@ model = "Toradex Colibri T30"; compatible = "toradex,colibri_t30", "nvidia,tegra30"; + chosen { + stdout-path = &uarta; + }; + aliases { i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; diff --git a/arch/arm/include/asm/arch-tegra114/mc.h b/arch/arm/include/asm/arch-tegra114/mc.h new file mode 100644 index 0000000..044b1e0 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/mc.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA114_MC_H_ +#define _TEGRA114_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[4]; /* offset 0x00 - 0x0C */ + u32 mc_smmu_config; /* offset 0x10 */ + u32 mc_smmu_tlb_config; /* offset 0x14 */ + u32 mc_smmu_ptc_config; /* offset 0x18 */ + u32 mc_smmu_ptb_asid; /* offset 0x1C */ + u32 mc_smmu_ptb_data; /* offset 0x20 */ + u32 reserved1[3]; /* offset 0x24 - 0x2C */ + u32 mc_smmu_tlb_flush; /* offset 0x30 */ + u32 mc_smmu_ptc_flush; /* offset 0x34 */ + u32 reserved2[6]; /* offset 0x38 - 0x4C */ + u32 mc_emem_cfg; /* offset 0x50 */ + u32 mc_emem_adr_cfg; /* offset 0x54 */ + u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ + u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ + u32 reserved3[12]; /* offset 0x60 - 0x8C */ + u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ + u32 reserved4[338]; /* offset 0x100 - 0x644 */ + u32 mc_video_protect_bom; /* offset 0x648 */ + u32 mc_video_protect_size_mb; /* offset 0x64c */ + u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ +}; + +#endif /* _TEGRA114_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h index 5d426b5..c3d061e 100644 --- a/arch/arm/include/asm/arch-tegra114/tegra.h +++ b/arch/arm/include/asm/arch-tegra114/tegra.h @@ -19,6 +19,7 @@ #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ +#define NV_PA_MC_BASE 0x70019000 #include <asm/arch-tegra/tegra.h> diff --git a/arch/arm/include/asm/arch-tegra20/mc.h b/arch/arm/include/asm/arch-tegra20/mc.h new file mode 100644 index 0000000..9c6e3ff --- /dev/null +++ b/arch/arm/include/asm/arch-tegra20/mc.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA20_MC_H_ +#define _TEGRA20_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[3]; /* offset 0x00 - 0x08 */ + u32 mc_emem_cfg; /* offset 0x0C */ + u32 mc_emem_adr_cfg; /* offset 0x10 */ + u32 mc_emem_arb_cfg0; /* offset 0x14 */ + u32 mc_emem_arb_cfg1; /* offset 0x18 */ + u32 mc_emem_arb_cfg2; /* offset 0x1C */ + u32 reserved1; /* offset 0x20 */ + u32 mc_gart_cfg; /* offset 0x24 */ + u32 mc_gart_entry_addr; /* offset 0x28 */ + u32 mc_gart_entry_data; /* offset 0x2C */ + u32 mc_gart_error_req; /* offset 0x30 */ + u32 mc_gart_error_addr; /* offset 0x34 */ + u32 reserved2; /* offset 0x38 */ + u32 mc_timeout_ctrl; /* offset 0x3C */ + u32 reserved3[6]; /* offset 0x40 - 0x54 */ + u32 mc_decerr_emem_others_status; /* offset 0x58 */ + u32 mc_decerr_emem_others_adr; /* offset 0x5C */ + u32 reserved4[40]; /* offset 0x60 - 0xFC */ + u32 reserved5[93]; /* offset 0x100 - 0x270 */ +}; + +#endif /* _TEGRA20_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h index 18856ac..22774ab 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra.h +++ b/arch/arm/include/asm/arch-tegra20/tegra.h @@ -9,6 +9,7 @@ #define _TEGRA20_H_ #define NV_PA_SDRAM_BASE 0x00000000 +#define NV_PA_MC_BASE 0x7000F000 #include <asm/arch-tegra/tegra.h> diff --git a/arch/arm/include/asm/arch-tegra30/mc.h b/arch/arm/include/asm/arch-tegra30/mc.h new file mode 100644 index 0000000..242a1fc --- /dev/null +++ b/arch/arm/include/asm/arch-tegra30/mc.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA30_MC_H_ +#define _TEGRA30_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[4]; /* offset 0x00 - 0x0C */ + u32 mc_smmu_config; /* offset 0x10 */ + u32 mc_smmu_tlb_config; /* offset 0x14 */ + u32 mc_smmu_ptc_config; /* offset 0x18 */ + u32 mc_smmu_ptb_asid; /* offset 0x1C */ + u32 mc_smmu_ptb_data; /* offset 0x20 */ + u32 reserved1[3]; /* offset 0x24 - 0x2C */ + u32 mc_smmu_tlb_flush; /* offset 0x30 */ + u32 mc_smmu_ptc_flush; /* offset 0x34 */ + u32 mc_smmu_asid_security; /* offset 0x38 */ + u32 reserved2[5]; /* offset 0x3C - 0x4C */ + u32 mc_emem_cfg; /* offset 0x50 */ + u32 mc_emem_adr_cfg; /* offset 0x54 */ + u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ + u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ + u32 reserved3[12]; /* offset 0x60 - 0x8C */ + u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ + u32 reserved4[338]; /* offset 0x100 - 0x644 */ + u32 mc_video_protect_bom; /* offset 0x648 */ + u32 mc_video_protect_size_mb; /* offset 0x64c */ + u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ +}; + +#endif /* _TEGRA30_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h index c02c5d8..9367179 100644 --- a/arch/arm/include/asm/arch-tegra30/tegra.h +++ b/arch/arm/include/asm/arch-tegra30/tegra.h @@ -17,6 +17,7 @@ #ifndef _TEGRA30_H_ #define _TEGRA30_H_ +#define NV_PA_MC_BASE 0x7000F000 #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */ #include <asm/arch-tegra/tegra.h> diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 560924e..d4a447b 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1107,6 +1107,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_ARMADILLO_800EVA 3863 #define MACH_TYPE_KZM9G 4140 #define MACH_TYPE_COLIBRI_T30 4493 +#define MACH_TYPE_APALIS_T30 4513 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -14248,6 +14249,18 @@ extern unsigned int __machine_arch_type; # define machine_is_colibri_t30() (0) #endif +#ifdef CONFIG_MACH_APALIS_T30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APALIS_T30 +# endif +# define machine_is_apalis_t30() (machine_arch_type == MACH_TYPE_APALIS_T30) +#else +# define machine_is_apalis_t30() (0) +#endif + /* * These have not yet been registered */ |