diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 32 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 10 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/iomux.h | 11 |
4 files changed, 48 insertions, 7 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index abe2d81..700d190 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -733,6 +733,15 @@ static void ungate_sata_clock(void) /* Enable SATA clock. */ setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); } +#else +static void ungate_disp_axi_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Enable display axi clock. */ + setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_DISP_AXI_MASK); +} #endif static void ungate_pcie_clock(void) @@ -758,6 +767,9 @@ int enable_pcie_clock(void) (struct anatop_regs *)ANATOP_BASE_ADDR; struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + /* PCIe reference clock sourced from AXI. */ + clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); + /* * Here be dragons! * @@ -773,22 +785,30 @@ int enable_pcie_clock(void) #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F +#ifndef CONFIG_MX6SX + /* lvds_clk1 is sourced from sata ref on imx6q/dl/solo */ clrsetbits_le32(&anatop_regs->ana_misc1, ANADIG_ANA_MISC1_LVDSCLK1_IBEN | ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb); - /* PCIe reference clock sourced from AXI. */ - clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); - /* Party time! Ungate the clock to the PCIe. */ -#ifndef CONFIG_MX6SX ungate_sata_clock(); -#endif ungate_pcie_clock(); return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | - BM_ANADIG_PLL_ENET_ENABLE_PCIE); + BM_ANADIG_PLL_ENET_ENABLE_PCIE); +#else + /* lvds_clk1 is sourced from pcie ref on imx6sx */ + clrsetbits_le32(&anatop_regs->ana_misc1, + ANADIG_ANA_MISC1_LVDSCLK1_IBEN | + ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, + ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xa); + + ungate_disp_axi_clock(); + ungate_pcie_clock(); + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_PCIE); +#endif } #ifdef CONFIG_SECURE_BOOT diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index e4393b3..fa1d6e6 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -427,6 +427,16 @@ void vadc_power_down(void) val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK, writel(val, &iomux->gpr[5]); } + +void pcie_power_up(void) +{ + set_ldo_voltage(LDO_PU, 1100); /* Set VDDPU to 1.1V */ +} + +void pcie_power_off(void) +{ + set_ldo_voltage(LDO_PU, 0); /* Set VDDPU to 1.1V */ +} #endif static void imx_set_vddpu_power_down(void) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 1692866..fad04f6 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -1104,6 +1104,8 @@ extern void check_cpu_temperature(void); #ifdef CONFIG_MX6SX extern void vadc_power_up(void); extern void vadc_power_down(void); +extern void pcie_power_up(void); +extern void pcie_power_off(void); #endif /* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index c3003c1..dba2186 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -19,6 +19,12 @@ #define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) /* + * IOMUXC_GPR5 bit fields + */ +#define IOMUXC_GPR5_PCIE_BTNRST (1 << 19) +#define IOMUXC_GPR5_PCIE_PERST (1 << 18) + +/* * IOMUXC_GPR8 bit fields */ #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK (0x3f << 0) @@ -35,12 +41,15 @@ /* * IOMUXC_GPR12 bit fields */ +#define IOMUXC_GPR12_RX_EQ_2 (0x2 << 0) +#define IOMUXC_GPR12_RX_EQ_MASK (0x7 << 0) #define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4) #define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4) #define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) #define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12) -#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x2 << 12) +#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12) #define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) +#define IOMUXC_GPR12_TEST_POWERDOWN (1 << 30) /* * IOMUXC_GPR13 bit fields |