diff options
Diffstat (limited to 'arch')
135 files changed, 6226 insertions, 925 deletions
diff --git a/arch/Kconfig b/arch/Kconfig new file mode 100644 index 0000000..8620a4f --- /dev/null +++ b/arch/Kconfig @@ -0,0 +1,66 @@ +choice + prompt "Architecture select" + default SANDBOX + +config ARC + bool "ARC architecture" + +config ARM + bool "ARM architecture" + +config AVR32 + bool "AVR32 architecture" + +config BLACKFIN + bool "Blackfin architecture" + +config M68K + bool "M68000 architecture" + +config MICROBLAZE + bool "MicroBlaze architecture" + +config MIPS + bool "MIPS architecture" + +config NDS32 + bool "NDS32 architecture" + +config NIOS2 + bool "Nios II architecture" + +config OPENRISC + bool "OpenRISC architecture" + +config PPC + bool "PowerPC architecture" + +config SANDBOX + bool "Sandbox" + +config SH + bool "SuperH architecture" + +config SPARC + bool "SPARC architecture" + +config X86 + bool "x86 architecture" + +endchoice + +source "arch/arc/Kconfig" +source "arch/arm/Kconfig" +source "arch/avr32/Kconfig" +source "arch/blackfin/Kconfig" +source "arch/m68k/Kconfig" +source "arch/microblaze/Kconfig" +source "arch/mips/Kconfig" +source "arch/nds32/Kconfig" +source "arch/nios2/Kconfig" +source "arch/openrisc/Kconfig" +source "arch/powerpc/Kconfig" +source "arch/sandbox/Kconfig" +source "arch/sh/Kconfig" +source "arch/sparc/Kconfig" +source "arch/x86/Kconfig" diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig new file mode 100644 index 0000000..51d5aff --- /dev/null +++ b/arch/arc/Kconfig @@ -0,0 +1,29 @@ +menu "ARC architecture" + depends on ARC + +config SYS_ARCH + string + default "arc" + +choice + prompt "Target select" + +config TARGET_TB100 + bool "Support tb100" + +config TARGET_ARCANGEL4 + bool "Support arcangel4" + +config TARGET_ARCANGEL4_BE + bool "Support arcangel4-be" + +config TARGET_AXS101 + bool "Support axs101" + +endchoice + +source "board/abilis/tb100/Kconfig" +source "board/synopsys/Kconfig" +source "board/synopsys/axs101/Kconfig" + +endmenu diff --git a/arch/arc/config.mk b/arch/arc/config.mk index a3b8df7..e408800 100644 --- a/arch/arc/config.mk +++ b/arch/arc/config.mk @@ -21,7 +21,7 @@ ifeq ($(CROSS_COMPILE),) CROSS_COMPILE := $(ARC_CROSS_COMPILE) endif -PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -DCONFIG_ARC -gdwarf-2 +PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2 # Needed for relocation LDFLAGS_FINAL += -pie diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig new file mode 100644 index 0000000..e385eda --- /dev/null +++ b/arch/arm/Kconfig @@ -0,0 +1,1002 @@ +menu "ARM architecture" + depends on ARM + +config SYS_ARCH + string + default "arm" + +choice + prompt "Target select" + +config TARGET_INTEGRATORAP_CM720T + bool "Support integratorap_cm720t" + +config TARGET_INTEGRATORAP_CM920T + bool "Support integratorap_cm920t" + +config TARGET_INTEGRATORCP_CM920T + bool "Support integratorcp_cm920t" + +config TARGET_A320EVB + bool "Support a320evb" + +config TARGET_AT91RM9200EK + bool "Support at91rm9200ek" + +config TARGET_EB_CPUX9K2 + bool "Support eb_cpux9k2" + +config TARGET_CPUAT91 + bool "Support cpuat91" + +config TARGET_EDB93XX + bool "Support edb93xx" + +config TARGET_SCB9328 + bool "Support scb9328" + +config TARGET_CM4008 + bool "Support cm4008" + +config TARGET_CM41XX + bool "Support cm41xx" + +config TARGET_VCMA9 + bool "Support VCMA9" + +config TARGET_SMDK2410 + bool "Support smdk2410" + +config TARGET_INTEGRATORAP_CM926EJS + bool "Support integratorap_cm926ejs" + +config TARGET_INTEGRATORCP_CM926EJS + bool "Support integratorcp_cm926ejs" + +config TARGET_ASPENITE + bool "Support aspenite" + +config TARGET_GPLUGD + bool "Support gplugd" + +config TARGET_AFEB9260 + bool "Support afeb9260" + +config TARGET_AT91SAM9260EK + bool "Support at91sam9260ek" + +config TARGET_AT91SAM9261EK + bool "Support at91sam9261ek" + +config TARGET_AT91SAM9263EK + bool "Support at91sam9263ek" + +config TARGET_AT91SAM9M10G45EK + bool "Support at91sam9m10g45ek" + +config TARGET_AT91SAM9N12EK + bool "Support at91sam9n12ek" + +config TARGET_AT91SAM9RLEK + bool "Support at91sam9rlek" + +config TARGET_AT91SAM9X5EK + bool "Support at91sam9x5ek" + +config TARGET_SNAPPER9260 + bool "Support snapper9260" + +config TARGET_VL_MA2SC + bool "Support vl_ma2sc" + +config TARGET_SBC35_A9G20 + bool "Support sbc35_a9g20" + +config TARGET_TNY_A9260 + bool "Support tny_a9260" + +config TARGET_USB_A9263 + bool "Support usb_a9263" + +config TARGET_ETHERNUT5 + bool "Support ethernut5" + +config TARGET_TOP9000 + bool "Support top9000" + +config TARGET_MEESC + bool "Support meesc" + +config TARGET_OTC570 + bool "Support otc570" + +config TARGET_CPU9260 + bool "Support cpu9260" + +config TARGET_PM9261 + bool "Support pm9261" + +config TARGET_PM9263 + bool "Support pm9263" + +config TARGET_PM9G45 + bool "Support pm9g45" + +config TARGET_CORVUS + bool "Support corvus" + +config TARGET_TAURUS + bool "Support taurus" + +config TARGET_STAMP9G20 + bool "Support stamp9g20" + +config TARGET_CAM_ENC_4XX + bool "Support cam_enc_4xx" + +config TARGET_IPAM390 + bool "Support ipam390" + +config TARGET_DA830EVM + bool "Support da830evm" + +config TARGET_DA850EVM + bool "Support da850evm" + +config TARGET_HAWKBOARD + bool "Support hawkboard" + +config TARGET_DAVINCI_DM355EVM + bool "Support davinci_dm355evm" + +config TARGET_DAVINCI_DM355LEOPARD + bool "Support davinci_dm355leopard" + +config TARGET_DAVINCI_DM365EVM + bool "Support davinci_dm365evm" + +config TARGET_DAVINCI_DM6467EVM + bool "Support davinci_dm6467evm" + +config TARGET_DAVINCI_DVEVM + bool "Support davinci_dvevm" + +config TARGET_EA20 + bool "Support ea20" + +config TARGET_DAVINCI_SCHMOOGIE + bool "Support davinci_schmoogie" + +config TARGET_DAVINCI_SFFSDR + bool "Support davinci_sffsdr" + +config TARGET_DAVINCI_SONATA + bool "Support davinci_sonata" + +config TARGET_ENBW_CMC + bool "Support enbw_cmc" + +config TARGET_CALIMAIN + bool "Support calimain" + +config TARGET_LSXL + bool "Support lsxl" + +config TARGET_POGO_E02 + bool "Support pogo_e02" + +config TARGET_DNS325 + bool "Support dns325" + +config TARGET_ICONNECT + bool "Support iconnect" + +config TARGET_TK71 + bool "Support tk71" + +config TARGET_KM_KIRKWOOD + bool "Support km_kirkwood" + +config TARGET_NET2BIG_V2 + bool "Support net2big_v2" + +config TARGET_NETSPACE_V2 + bool "Support netspace_v2" + +config TARGET_WIRELESS_SPACE + bool "Support wireless_space" + +config TARGET_DREAMPLUG + bool "Support dreamplug" + +config TARGET_GURUPLUG + bool "Support guruplug" + +config TARGET_MV88F6281GTW_GE + bool "Support mv88f6281gtw_ge" + +config TARGET_OPENRD + bool "Support openrd" + +config TARGET_RD6281A + bool "Support rd6281a" + +config TARGET_SHEEVAPLUG + bool "Support sheevaplug" + +config TARGET_IB62X0 + bool "Support ib62x0" + +config TARGET_DOCKSTAR + bool "Support dockstar" + +config TARGET_GOFLEXHOME + bool "Support goflexhome" + +config TARGET_DEVKIT3250 + bool "Support devkit3250" + +config TARGET_JADECPU + bool "Support jadecpu" + +config TARGET_MX25PDK + bool "Support mx25pdk" + +config TARGET_TX25 + bool "Support tx25" + +config TARGET_ZMX25 + bool "Support zmx25" + +config TARGET_APF27 + bool "Support apf27" + +config TARGET_IMX27LITE + bool "Support imx27lite" + +config TARGET_MAGNESIUM + bool "Support magnesium" + +config TARGET_APX4DEVKIT + bool "Support apx4devkit" + +config TARGET_XFI3 + bool "Support xfi3" + +config TARGET_M28EVK + bool "Support m28evk" + +config TARGET_MX23EVK + bool "Support mx23evk" + +config TARGET_MX28EVK + bool "Support mx28evk" + +config TARGET_MX23_OLINUXINO + bool "Support mx23_olinuxino" + +config TARGET_BG0900 + bool "Support bg0900" + +config TARGET_SANSA_FUZE_PLUS + bool "Support sansa_fuze_plus" + +config TARGET_SC_SPS_1 + bool "Support sc_sps_1" + +config TARGET_NHK8815 + bool "Support nhk8815" + +config TARGET_OMAP5912OSK + bool "Support omap5912osk" + +config TARGET_EDMINIV2 + bool "Support edminiv2" + +config TARGET_DKB + bool "Support dkb" + +config TARGET_SPEAR300 + bool "Support spear300" + +config TARGET_SPEAR310 + bool "Support spear310" + +config TARGET_SPEAR320 + bool "Support spear320" + +config TARGET_SPEAR600 + bool "Support spear600" + +config TARGET_X600 + bool "Support x600" + +config TARGET_VERSATILEAB + bool "Support versatileab" + +config TARGET_VERSATILEPB + bool "Support versatilepb" + +config TARGET_VERSATILEQEMU + bool "Support versatileqemu" + +config TARGET_INTEGRATORCP_CM1136 + bool "Support integratorcp_cm1136" + +config TARGET_IMX31_PHYCORE + bool "Support imx31_phycore" + +config TARGET_QONG + bool "Support qong" + +config TARGET_MX31ADS + bool "Support mx31ads" + +config TARGET_MX31PDK + bool "Support mx31pdk" + +config TARGET_TT01 + bool "Support tt01" + +config TARGET_IMX31_LITEKIT + bool "Support imx31_litekit" + +config TARGET_WOODBURN + bool "Support woodburn" + +config TARGET_WOODBURN_SD + bool "Support woodburn_sd" + +config TARGET_FLEA3 + bool "Support flea3" + +config TARGET_MX35PDK + bool "Support mx35pdk" + +config TARGET_RPI_B + bool "Support rpi_b" + +config TARGET_TNETV107X_EVM + bool "Support tnetv107x_evm" + +config TARGET_INTEGRATORAP_CM946ES + bool "Support integratorap_cm946es" + +config TARGET_INTEGRATORCP_CM946ES + bool "Support integratorcp_cm946es" + +config TARGET_VEXPRESS_CA15_TC2 + bool "Support vexpress_ca15_tc2" + +config TARGET_VEXPRESS_CA5X2 + bool "Support vexpress_ca5x2" + +config TARGET_VEXPRESS_CA9X4 + bool "Support vexpress_ca9x4" + +config TARGET_KWB + bool "Support kwb" + +config TARGET_TSERIES + bool "Support tseries" + +config TARGET_CM_T335 + bool "Support cm_t335" + +config TARGET_PEPPER + bool "Support pepper" + +config TARGET_AM335X_IGEP0033 + bool "Support am335x_igep0033" + +config TARGET_PCM051 + bool "Support pcm051" + +config TARGET_DRACO + bool "Support draco" + +config TARGET_DXR2 + bool "Support dxr2" + +config TARGET_PXM2 + bool "Support pxm2" + +config TARGET_RUT + bool "Support rut" + +config TARGET_PENGWYN + bool "Support pengwyn" + +config TARGET_AM335X_EVM + bool "Support am335x_evm" + +config TARGET_AM43XX_EVM + bool "Support am43xx_evm" + +config TARGET_TI814X_EVM + bool "Support ti814x_evm" + +config TARGET_TI816X_EVM + bool "Support ti816x_evm" + +config TARGET_SAMA5D3_XPLAINED + bool "Support sama5d3_xplained" + +config TARGET_SAMA5D3XEK + bool "Support sama5d3xek" + +config TARGET_BCM28155_AP + bool "Support bcm28155_ap" + +config TARGET_ARNDALE + bool "Support arndale" + +config TARGET_ORIGEN + bool "Support origen" + +config TARGET_SMDK5250 + bool "Support smdk5250" + +config TARGET_SNOW + bool "Support snow" + +config TARGET_PEACH_PIT + bool "Support peach-pit" + +config TARGET_SMDK5420 + bool "Support smdk5420" + +config TARGET_SMDKV310 + bool "Support smdkv310" + +config TARGET_TRATS + bool "Support trats" + +config TARGET_TRATS2 + bool "Support trats2" + +config TARGET_S5PC210_UNIVERSAL + bool "Support s5pc210_universal" + +config TARGET_HIGHBANK + bool "Support highbank" + +config TARGET_K2E_EVM + bool "Support k2e_evm" + +config TARGET_K2HK_EVM + bool "Support k2hk_evm" + +config TARGET_M53EVK + bool "Support m53evk" + +config TARGET_IMA3_MX53 + bool "Support ima3-mx53" + +config TARGET_MX51EVK + bool "Support mx51evk" + +config TARGET_MX53ARD + bool "Support mx53ard" + +config TARGET_MX53EVK + bool "Support mx53evk" + +config TARGET_MX53LOCO + bool "Support mx53loco" + +config TARGET_MX53SMD + bool "Support mx53smd" + +config TARGET_MX51_EFIKAMX + bool "Support mx51_efikamx" + +config TARGET_VISION2 + bool "Support vision2" + +config TARGET_UDOO + bool "Support udoo" + +config TARGET_WANDBOARD + bool "Support wandboard" + +config TARGET_TITANIUM + bool "Support titanium" + +config TARGET_NITROGEN6X + bool "Support nitrogen6x" + +config TARGET_CGTQMX6EVAL + bool "Support cgtqmx6eval" + +config TARGET_EMBESTMX6BOARDS + bool "Support embestmx6boards" + +config TARGET_MX6QARM2 + bool "Support mx6qarm2" + +config TARGET_MX6QSABREAUTO + bool "Support mx6qsabreauto" + +config TARGET_MX6SABRESD + bool "Support mx6sabresd" + +config TARGET_MX6SLEVK + bool "Support mx6slevk" + +config TARGET_GW_VENTANA + bool "Support gw_ventana" + +config TARGET_HUMMINGBOARD + bool "Support hummingboard" + +config TARGET_OMAP3_OVERO + bool "Support omap3_overo" + +config TARGET_OMAP3_PANDORA + bool "Support omap3_pandora" + +config TARGET_ECO5PK + bool "Support eco5pk" + +config TARGET_DIG297 + bool "Support dig297" + +config TARGET_CM_T35 + bool "Support cm_t35" + +config TARGET_TRICORDER + bool "Support tricorder" + +config TARGET_MCX + bool "Support mcx" + +config TARGET_OMAP3_IGEP00X0 + bool "Support omap3_igep00x0" + +config TARGET_AM3517_EVM + bool "Support am3517_evm" + +config TARGET_OMAP3_LOGIC + bool "Support omap3_logic" + +config TARGET_OMAP3_ZOOM1 + bool "Support omap3_zoom1" + +config TARGET_OMAP3_MVBLX + bool "Support omap3_mvblx" + +config TARGET_NOKIA_RX51 + bool "Support nokia_rx51" + +config TARGET_TAO3530 + bool "Support tao3530" + +config TARGET_TWISTER + bool "Support twister" + +config TARGET_MT_VENTOUX + bool "Support mt_ventoux" + +config TARGET_AM3517_CRANE + bool "Support am3517_crane" + +config TARGET_OMAP3_BEAGLE + bool "Support omap3_beagle" + +config TARGET_OMAP3_EVM + bool "Support omap3_evm" + +config TARGET_OMAP3_EVM_QUICK_MMC + bool "Support omap3_evm_quick_mmc" + +config TARGET_OMAP3_EVM_QUICK_NAND + bool "Support omap3_evm_quick_nand" + +config TARGET_OMAP3_SDP3430 + bool "Support omap3_sdp3430" + +config TARGET_DEVKIT8000 + bool "Support devkit8000" + +config TARGET_DUOVERO + bool "Support duovero" + +config TARGET_OMAP4_PANDA + bool "Support omap4_panda" + +config TARGET_OMAP4_SDP4430 + bool "Support omap4_sdp4430" + +config TARGET_CM_T54 + bool "Support cm_t54" + +config TARGET_DRA7XX_EVM + bool "Support dra7xx_evm" + +config TARGET_OMAP5_UEVM + bool "Support omap5_uevm" + +config TARGET_ARMADILLO_800EVA + bool "Support armadillo-800eva" + +config TARGET_KZM9G + bool "Support kzm9g" + +config TARGET_ALT + bool "Support alt" + +config TARGET_KOELSCH + bool "Support koelsch" + +config TARGET_LAGER + bool "Support lager" + +config TARGET_S5P_GONI + bool "Support s5p_goni" + +config TARGET_SMDKC100 + bool "Support smdkc100" + +config TARGET_SOCFPGA_CYCLONE5 + bool "Support socfpga_cyclone5" + +config TARGET_SUN4I + bool "Support sun4i" + +config TARGET_SUN5I + bool "Support sun5i" + +config TARGET_SUN7I + bool "Support sun7i" + +config TARGET_SNOWBALL + bool "Support snowball" + +config TARGET_U8500_HREF + bool "Support u8500_href" + +config TARGET_VF610TWR + bool "Support vf610twr" + +config TARGET_ZYNQ_MICROZED + bool "Support zynq_microzed" + +config TARGET_ZYNQ_ZC70X + bool "Support zynq_zc70x" + +config TARGET_ZYNQ_ZC770 + bool "Support zynq_zc770" + +config TARGET_ZYNQ_ZED + bool "Support zynq_zed" + +config TARGET_MEDCOM_WIDE + bool "Support medcom-wide" + +config TARGET_PLUTUX + bool "Support plutux" + +config TARGET_TEC + bool "Support tec" + +config TARGET_PAZ00 + bool "Support paz00" + +config TARGET_TRIMSLICE + bool "Support trimslice" + +config TARGET_HARMONY + bool "Support harmony" + +config TARGET_SEABOARD + bool "Support seaboard" + +config TARGET_VENTANA + bool "Support ventana" + +config TARGET_WHISTLER + bool "Support whistler" + +config TARGET_COLIBRI_T20_IRIS + bool "Support colibri_t20_iris" + +config TARGET_TEC_NG + bool "Support tec-ng" + +config TARGET_BEAVER + bool "Support beaver" + +config TARGET_CARDHU + bool "Support cardhu" + +config TARGET_DALMORE + bool "Support dalmore" + +config TARGET_JETSON_TK1 + bool "Support jetson-tk1" + +config TARGET_VENICE2 + bool "Support venice2" + +config TARGET_VEXPRESS_AEMV8A + bool "Support vexpress_aemv8a" + +config TARGET_VEXPRESS_AEMV8A_SEMI + bool "Support vexpress_aemv8a_semi" + +config TARGET_LS2085A_EMU + bool "Support ls2085a_emu" + +config TARGET_LS2085A_SIMU + bool "Support ls2085a_simu" + +config TARGET_BALLOON3 + bool "Support balloon3" + +config TARGET_H2200 + bool "Support h2200" + +config TARGET_PALMLD + bool "Support palmld" + +config TARGET_PALMTC + bool "Support palmtc" + +config TARGET_PALMTREO680 + bool "Support palmtreo680" + +config TARGET_PXA255_IDP + bool "Support pxa255_idp" + +config TARGET_TRIZEPSIV + bool "Support trizepsiv" + +config TARGET_VPAC270 + bool "Support vpac270" + +config TARGET_XAENIAX + bool "Support xaeniax" + +config TARGET_ZIPITZ2 + bool "Support zipitz2" + +config TARGET_LP8X4X + bool "Support lp8x4x" + +config TARGET_COLIBRI_PXA270 + bool "Support colibri_pxa270" + +config TARGET_JORNADA + bool "Support jornada" + +endchoice + +source "board/8dtech/eco5pk/Kconfig" +source "board/Barix/ipam390/Kconfig" +source "board/BuR/kwb/Kconfig" +source "board/BuR/tseries/Kconfig" +source "board/BuS/eb_cpux9k2/Kconfig" +source "board/BuS/vl_ma2sc/Kconfig" +source "board/CarMediaLab/flea3/Kconfig" +source "board/LaCie/edminiv2/Kconfig" +source "board/LaCie/net2big_v2/Kconfig" +source "board/LaCie/netspace_v2/Kconfig" +source "board/LaCie/wireless_space/Kconfig" +source "board/Marvell/aspenite/Kconfig" +source "board/Marvell/dkb/Kconfig" +source "board/Marvell/dreamplug/Kconfig" +source "board/Marvell/gplugd/Kconfig" +source "board/Marvell/guruplug/Kconfig" +source "board/Marvell/mv88f6281gtw_ge/Kconfig" +source "board/Marvell/openrd/Kconfig" +source "board/Marvell/rd6281a/Kconfig" +source "board/Marvell/sheevaplug/Kconfig" +source "board/Seagate/dockstar/Kconfig" +source "board/Seagate/goflexhome/Kconfig" +source "board/afeb9260/Kconfig" +source "board/ait/cam_enc_4xx/Kconfig" +source "board/altera/socfpga/Kconfig" +source "board/armadeus/apf27/Kconfig" +source "board/armltd/integrator/Kconfig" +source "board/armltd/versatile/Kconfig" +source "board/armltd/vexpress/Kconfig" +source "board/armltd/vexpress64/Kconfig" +source "board/atmark-techno/armadillo-800eva/Kconfig" +source "board/atmel/at91rm9200ek/Kconfig" +source "board/atmel/at91sam9260ek/Kconfig" +source "board/atmel/at91sam9261ek/Kconfig" +source "board/atmel/at91sam9263ek/Kconfig" +source "board/atmel/at91sam9m10g45ek/Kconfig" +source "board/atmel/at91sam9n12ek/Kconfig" +source "board/atmel/at91sam9rlek/Kconfig" +source "board/atmel/at91sam9x5ek/Kconfig" +source "board/atmel/sama5d3_xplained/Kconfig" +source "board/atmel/sama5d3xek/Kconfig" +source "board/avionic-design/medcom-wide/Kconfig" +source "board/avionic-design/plutux/Kconfig" +source "board/avionic-design/tec-ng/Kconfig" +source "board/avionic-design/tec/Kconfig" +source "board/balloon3/Kconfig" +source "board/barco/titanium/Kconfig" +source "board/bluegiga/apx4devkit/Kconfig" +source "board/bluewater/snapper9260/Kconfig" +source "board/boundary/nitrogen6x/Kconfig" +source "board/broadcom/bcm28155_ap/Kconfig" +source "board/buffalo/lsxl/Kconfig" +source "board/calao/sbc35_a9g20/Kconfig" +source "board/calao/tny_a9260/Kconfig" +source "board/calao/usb_a9263/Kconfig" +source "board/cirrus/edb93xx/Kconfig" +source "board/cloudengines/pogo_e02/Kconfig" +source "board/cm4008/Kconfig" +source "board/cm41xx/Kconfig" +source "board/comelit/dig297/Kconfig" +source "board/compal/paz00/Kconfig" +source "board/compulab/cm_t335/Kconfig" +source "board/compulab/cm_t35/Kconfig" +source "board/compulab/cm_t54/Kconfig" +source "board/compulab/trimslice/Kconfig" +source "board/congatec/cgtqmx6eval/Kconfig" +source "board/corscience/tricorder/Kconfig" +source "board/creative/xfi3/Kconfig" +source "board/d-link/dns325/Kconfig" +source "board/davedenx/qong/Kconfig" +source "board/davinci/da8xxevm/Kconfig" +source "board/davinci/dm355evm/Kconfig" +source "board/davinci/dm355leopard/Kconfig" +source "board/davinci/dm365evm/Kconfig" +source "board/davinci/dm6467evm/Kconfig" +source "board/davinci/dvevm/Kconfig" +source "board/davinci/ea20/Kconfig" +source "board/davinci/schmoogie/Kconfig" +source "board/davinci/sffsdr/Kconfig" +source "board/davinci/sonata/Kconfig" +source "board/denx/m28evk/Kconfig" +source "board/denx/m53evk/Kconfig" +source "board/egnite/ethernut5/Kconfig" +source "board/embest/mx6boards/Kconfig" +source "board/emk/top9000/Kconfig" +source "board/enbw/enbw_cmc/Kconfig" +source "board/esd/meesc/Kconfig" +source "board/esd/otc570/Kconfig" +source "board/esg/ima3-mx53/Kconfig" +source "board/eukrea/cpu9260/Kconfig" +source "board/eukrea/cpuat91/Kconfig" +source "board/faraday/a320evb/Kconfig" +source "board/freescale/ls2085a/Kconfig" +source "board/freescale/mx23evk/Kconfig" +source "board/freescale/mx25pdk/Kconfig" +source "board/freescale/mx28evk/Kconfig" +source "board/freescale/mx31ads/Kconfig" +source "board/freescale/mx31pdk/Kconfig" +source "board/freescale/mx35pdk/Kconfig" +source "board/freescale/mx51evk/Kconfig" +source "board/freescale/mx53ard/Kconfig" +source "board/freescale/mx53evk/Kconfig" +source "board/freescale/mx53loco/Kconfig" +source "board/freescale/mx53smd/Kconfig" +source "board/freescale/mx6qarm2/Kconfig" +source "board/freescale/mx6qsabreauto/Kconfig" +source "board/freescale/mx6sabresd/Kconfig" +source "board/freescale/mx6slevk/Kconfig" +source "board/freescale/vf610twr/Kconfig" +source "board/gateworks/gw_ventana/Kconfig" +source "board/genesi/mx51_efikamx/Kconfig" +source "board/gumstix/duovero/Kconfig" +source "board/gumstix/pepper/Kconfig" +source "board/h2200/Kconfig" +source "board/hale/tt01/Kconfig" +source "board/highbank/Kconfig" +source "board/htkw/mcx/Kconfig" +source "board/icpdas/lp8x4x/Kconfig" +source "board/imx31_phycore/Kconfig" +source "board/iomega/iconnect/Kconfig" +source "board/isee/igep0033/Kconfig" +source "board/isee/igep00x0/Kconfig" +source "board/jornada/Kconfig" +source "board/karo/tk71/Kconfig" +source "board/karo/tx25/Kconfig" +source "board/keymile/km_arm/Kconfig" +source "board/kmc/kzm9g/Kconfig" +source "board/logicpd/am3517evm/Kconfig" +source "board/logicpd/imx27lite/Kconfig" +source "board/logicpd/imx31_litekit/Kconfig" +source "board/logicpd/omap3som/Kconfig" +source "board/logicpd/zoom1/Kconfig" +source "board/matrix_vision/mvblx/Kconfig" +source "board/mpl/vcma9/Kconfig" +source "board/nokia/rx51/Kconfig" +source "board/nvidia/beaver/Kconfig" +source "board/nvidia/cardhu/Kconfig" +source "board/nvidia/dalmore/Kconfig" +source "board/nvidia/harmony/Kconfig" +source "board/nvidia/jetson-tk1/Kconfig" +source "board/nvidia/seaboard/Kconfig" +source "board/nvidia/venice2/Kconfig" +source "board/nvidia/ventana/Kconfig" +source "board/nvidia/whistler/Kconfig" +source "board/olimex/mx23_olinuxino/Kconfig" +source "board/omicron/calimain/Kconfig" +source "board/overo/Kconfig" +source "board/palmld/Kconfig" +source "board/palmtc/Kconfig" +source "board/palmtreo680/Kconfig" +source "board/pandora/Kconfig" +source "board/phytec/pcm051/Kconfig" +source "board/ppcag/bg0900/Kconfig" +source "board/pxa255_idp/Kconfig" +source "board/raidsonic/ib62x0/Kconfig" +source "board/raspberrypi/rpi_b/Kconfig" +source "board/renesas/alt/Kconfig" +source "board/renesas/koelsch/Kconfig" +source "board/renesas/lager/Kconfig" +source "board/ronetix/pm9261/Kconfig" +source "board/ronetix/pm9263/Kconfig" +source "board/ronetix/pm9g45/Kconfig" +source "board/samsung/arndale/Kconfig" +source "board/samsung/goni/Kconfig" +source "board/samsung/origen/Kconfig" +source "board/samsung/smdk2410/Kconfig" +source "board/samsung/smdk5250/Kconfig" +source "board/samsung/smdk5420/Kconfig" +source "board/samsung/smdkc100/Kconfig" +source "board/samsung/smdkv310/Kconfig" +source "board/samsung/trats/Kconfig" +source "board/samsung/trats2/Kconfig" +source "board/samsung/universal_c210/Kconfig" +source "board/sandisk/sansa_fuze_plus/Kconfig" +source "board/scb9328/Kconfig" +source "board/schulercontrol/sc_sps_1/Kconfig" +source "board/siemens/corvus/Kconfig" +source "board/siemens/draco/Kconfig" +source "board/siemens/pxm2/Kconfig" +source "board/siemens/rut/Kconfig" +source "board/siemens/taurus/Kconfig" +source "board/silica/pengwyn/Kconfig" +source "board/solidrun/hummingboard/Kconfig" +source "board/spear/spear300/Kconfig" +source "board/spear/spear310/Kconfig" +source "board/spear/spear320/Kconfig" +source "board/spear/spear600/Kconfig" +source "board/spear/x600/Kconfig" +source "board/st-ericsson/snowball/Kconfig" +source "board/st-ericsson/u8500/Kconfig" +source "board/st/nhk8815/Kconfig" +source "board/sunxi/Kconfig" +source "board/syteco/jadecpu/Kconfig" +source "board/syteco/zmx25/Kconfig" +source "board/taskit/stamp9g20/Kconfig" +source "board/technexion/tao3530/Kconfig" +source "board/technexion/twister/Kconfig" +source "board/teejet/mt_ventoux/Kconfig" +source "board/ti/am335x/Kconfig" +source "board/ti/am3517crane/Kconfig" +source "board/ti/am43xx/Kconfig" +source "board/ti/beagle/Kconfig" +source "board/ti/dra7xx/Kconfig" +source "board/ti/evm/Kconfig" +source "board/ti/ks2_evm/Kconfig" +source "board/ti/omap5912osk/Kconfig" +source "board/ti/omap5_uevm/Kconfig" +source "board/ti/panda/Kconfig" +source "board/ti/sdp3430/Kconfig" +source "board/ti/sdp4430/Kconfig" +source "board/ti/ti814x/Kconfig" +source "board/ti/ti816x/Kconfig" +source "board/ti/tnetv107xevm/Kconfig" +source "board/timll/devkit3250/Kconfig" +source "board/timll/devkit8000/Kconfig" +source "board/toradex/colibri_pxa270/Kconfig" +source "board/toradex/colibri_t20_iris/Kconfig" +source "board/trizepsiv/Kconfig" +source "board/ttcontrol/vision2/Kconfig" +source "board/udoo/Kconfig" +source "board/vpac270/Kconfig" +source "board/wandboard/Kconfig" +source "board/woodburn/Kconfig" +source "board/xaeniax/Kconfig" +source "board/xilinx/zynq/Kconfig" +source "board/zipitz2/Kconfig" + +endmenu diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 5fa1825..c339e6d 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -22,7 +22,7 @@ PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \ # Support generic board on ARM __HAVE_ARCH_GENERIC_BOARD := y -PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ +PLATFORM_CPPFLAGS += -D__ARM__ # Choose between ARM/Thumb instruction sets ifeq ($(CONFIG_SYS_THUMB_BUILD),y) @@ -113,7 +113,7 @@ endif ifdef CONFIG_ARM64 OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn else -OBJCOPYFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn +OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn endif ifdef CONFIG_OF_EMBED diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index da80240..881e2de 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -13,6 +13,7 @@ #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/kirkwood.h> +#include <mvebu_mmc.h> #define BUFLEN 16 @@ -377,3 +378,11 @@ int cpu_eth_init(bd_t *bis) return 0; } #endif + +#ifdef CONFIG_MVEBU_MMC +int board_mmc_init(bd_t *bis) +{ + mvebu_mmc_init(bis); + return 0; +} +#endif /* CONFIG_MVEBU_MMC */ diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 232118d..703ce8c 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -21,6 +21,11 @@ endif ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),) obj-y += nonsec_virt.o obj-y += virt-v7.o +obj-y += virt-dt.o +endif + +ifneq ($(CONFIG_ARMV7_PSCI),) +obj-y += psci.o endif obj-$(CONFIG_KONA) += kona-common/ diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile index c4af252..f8519c0 100644 --- a/arch/arm/cpu/armv7/keystone/Makefile +++ b/arch/arm/cpu/armv7/keystone/Makefile @@ -8,9 +8,12 @@ obj-y += init.o obj-y += psc.o obj-y += clock.o +obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o +obj-$(CONFIG_SOC_K2E) += clock-k2e.o obj-y += cmd_clock.o obj-y += cmd_mon.o -obj-y += keystone_nav.o +obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o obj-y += msmc.o obj-$(CONFIG_SPL_BUILD) += spl.o obj-y += ddr3.o +obj-y += keystone.o diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c new file mode 100644 index 0000000..42092e1 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/clock-k2e.c @@ -0,0 +1,101 @@ +/* + * Keystone2: get clk rate for K2E + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/arch/clock_defs.h> + +const struct keystone_pll_regs keystone_pll_regs[] = { + [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, + [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, + [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, +}; + +/** + * pll_freq_get - get pll frequency + * Fout = Fref * NF(mult) / NR(prediv) / OD + * @pll: pll identifier + */ +static unsigned long pll_freq_get(int pll) +{ + unsigned long mult = 1, prediv = 1, output_div = 2; + unsigned long ret; + u32 tmp, reg; + + if (pll == CORE_PLL) { + ret = external_clk[sys_clk]; + if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { + /* PLL mode */ + tmp = __raw_readl(KS2_MAINPLLCTL0); + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | + (pllctl_reg_read(pll, mult) & + PLLM_MULT_LO_MASK)) + 1; + output_div = ((pllctl_reg_read(pll, secctl) >> + PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1; + + ret = ret / prediv / output_div * mult; + } + } else { + switch (pll) { + case PASS_PLL: + ret = external_clk[pa_clk]; + reg = KS2_PASSPLLCTL0; + break; + case DDR3_PLL: + ret = external_clk[ddr3_clk]; + reg = KS2_DDR3APLLCTL0; + break; + default: + return 0; + } + + tmp = __raw_readl(reg); + + if (!(tmp & PLLCTL_BYPASS)) { + /* Bypass disabled */ + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; + output_div = ((tmp >> PLL_CLKOD_SHIFT) & + PLL_CLKOD_MASK) + 1; + ret = ((ret / prediv) * mult) / output_div; + } + } + + return ret; +} + +unsigned long clk_get_rate(unsigned int clk) +{ + switch (clk) { + case core_pll_clk: return pll_freq_get(CORE_PLL); + case pass_pll_clk: return pll_freq_get(PASS_PLL); + case ddr3_pll_clk: return pll_freq_get(DDR3_PLL); + case sys_clk0_1_clk: + case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); + case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); + case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); + case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); + case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; + case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; + case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; + case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; + case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; + case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; + case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; + case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; + case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; + case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; + case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; + default: + break; + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/keystone/clock-k2hk.c b/arch/arm/cpu/armv7/keystone/clock-k2hk.c new file mode 100644 index 0000000..96a9f72 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/clock-k2hk.c @@ -0,0 +1,113 @@ +/* + * Keystone2: get clk rate for K2HK + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/arch/clock_defs.h> + +const struct keystone_pll_regs keystone_pll_regs[] = { + [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, + [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, + [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, + [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, + [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, +}; + +/** + * pll_freq_get - get pll frequency + * Fout = Fref * NF(mult) / NR(prediv) / OD + * @pll: pll identifier + */ +static unsigned long pll_freq_get(int pll) +{ + unsigned long mult = 1, prediv = 1, output_div = 2; + unsigned long ret; + u32 tmp, reg; + + if (pll == CORE_PLL) { + ret = external_clk[sys_clk]; + if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { + /* PLL mode */ + tmp = __raw_readl(KS2_MAINPLLCTL0); + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | + (pllctl_reg_read(pll, mult) & + PLLM_MULT_LO_MASK)) + 1; + output_div = ((pllctl_reg_read(pll, secctl) >> + PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1; + + ret = ret / prediv / output_div * mult; + } + } else { + switch (pll) { + case PASS_PLL: + ret = external_clk[pa_clk]; + reg = KS2_PASSPLLCTL0; + break; + case TETRIS_PLL: + ret = external_clk[tetris_clk]; + reg = KS2_ARMPLLCTL0; + break; + case DDR3A_PLL: + ret = external_clk[ddr3a_clk]; + reg = KS2_DDR3APLLCTL0; + break; + case DDR3B_PLL: + ret = external_clk[ddr3b_clk]; + reg = KS2_DDR3BPLLCTL0; + break; + default: + return 0; + } + + tmp = __raw_readl(reg); + + if (!(tmp & PLLCTL_BYPASS)) { + /* Bypass disabled */ + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; + output_div = ((tmp >> PLL_CLKOD_SHIFT) & + PLL_CLKOD_MASK) + 1; + ret = ((ret / prediv) * mult) / output_div; + } + } + + return ret; +} + +unsigned long clk_get_rate(unsigned int clk) +{ + switch (clk) { + case core_pll_clk: return pll_freq_get(CORE_PLL); + case pass_pll_clk: return pll_freq_get(PASS_PLL); + case tetris_pll_clk: return pll_freq_get(TETRIS_PLL); + case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL); + case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL); + case sys_clk0_1_clk: + case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); + case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); + case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); + case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); + case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; + case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; + case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; + case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; + case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; + case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; + case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; + case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; + case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; + case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; + case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; + default: + break; + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c index bfa4c9d..03c1d9f 100644 --- a/arch/arm/cpu/armv7/keystone/clock.c +++ b/arch/arm/cpu/armv7/keystone/clock.c @@ -8,9 +8,6 @@ */ #include <common.h> -#include <asm-generic/errno.h> -#include <asm/io.h> -#include <asm/processor.h> #include <asm/arch/clock.h> #include <asm/arch/clock_defs.h> @@ -24,106 +21,6 @@ static void wait_for_completion(const struct pll_init_data *data) } } -struct pll_regs { - u32 reg0, reg1; -}; - -static const struct pll_regs pll_regs[] = { - [CORE_PLL] = { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1}, - [PASS_PLL] = { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1}, - [TETRIS_PLL] = { K2HK_ARMPLLCTL0, K2HK_ARMPLLCTL1}, - [DDR3A_PLL] = { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1}, - [DDR3B_PLL] = { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1}, -}; - -/* Fout = Fref * NF(mult) / NR(prediv) / OD */ -static unsigned long pll_freq_get(int pll) -{ - unsigned long mult = 1, prediv = 1, output_div = 2; - unsigned long ret; - u32 tmp, reg; - - if (pll == CORE_PLL) { - ret = external_clk[sys_clk]; - if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { - /* PLL mode */ - tmp = __raw_readl(K2HK_MAINPLLCTL0); - prediv = (tmp & PLL_DIV_MASK) + 1; - mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | - (pllctl_reg_read(pll, mult) & - PLLM_MULT_LO_MASK)) + 1; - output_div = ((pllctl_reg_read(pll, secctl) >> - PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1; - - ret = ret / prediv / output_div * mult; - } - } else { - switch (pll) { - case PASS_PLL: - ret = external_clk[pa_clk]; - reg = K2HK_PASSPLLCTL0; - break; - case TETRIS_PLL: - ret = external_clk[tetris_clk]; - reg = K2HK_ARMPLLCTL0; - break; - case DDR3A_PLL: - ret = external_clk[ddr3a_clk]; - reg = K2HK_DDR3APLLCTL0; - break; - case DDR3B_PLL: - ret = external_clk[ddr3b_clk]; - reg = K2HK_DDR3BPLLCTL0; - break; - default: - return 0; - } - - tmp = __raw_readl(reg); - - if (!(tmp & PLLCTL_BYPASS)) { - /* Bypass disabled */ - prediv = (tmp & PLL_DIV_MASK) + 1; - mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; - output_div = ((tmp >> PLL_CLKOD_SHIFT) & - PLL_CLKOD_MASK) + 1; - ret = ((ret / prediv) * mult) / output_div; - } - } - - return ret; -} - -unsigned long clk_get_rate(unsigned int clk) -{ - switch (clk) { - case core_pll_clk: return pll_freq_get(CORE_PLL); - case pass_pll_clk: return pll_freq_get(PASS_PLL); - case tetris_pll_clk: return pll_freq_get(TETRIS_PLL); - case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL); - case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL); - case sys_clk0_1_clk: - case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); - case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); - case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); - case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); - case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; - case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; - case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; - case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; - case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; - case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; - case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; - case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; - case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; - case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; - case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; - default: - break; - } - return 0; -} - void init_pll(const struct pll_init_data *data) { u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj; @@ -139,7 +36,7 @@ void init_pll(const struct pll_init_data *data) tmp = pllctl_reg_read(data->pll, secctl); if (tmp & (PLLCTL_BYPASS)) { - setbits_le32(pll_regs[data->pll].reg1, + setbits_le32(keystone_pll_regs[data->pll].reg1, BIT(MAIN_ENSAT_OFFSET)); pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN | @@ -159,21 +56,24 @@ void init_pll(const struct pll_init_data *data) pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); - clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK, - (pllm << 6)); + clrsetbits_le32(keystone_pll_regs[data->pll].reg0, + PLLM_MULT_HI_SMASK, (pllm << 6)); /* Set the BWADJ (12 bit field) */ tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */ - clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK, + clrsetbits_le32(keystone_pll_regs[data->pll].reg0, + PLL_BWADJ_LO_SMASK, (tmp_ctl << PLL_BWADJ_LO_SHIFT)); - clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK, + clrsetbits_le32(keystone_pll_regs[data->pll].reg1, + PLL_BWADJ_HI_MASK, (tmp_ctl >> 8)); /* * Set the pll divider (6 bit field) * * PLLD[5:0] is located in MAINPLLCTL0 */ - clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld); + clrsetbits_le32(keystone_pll_regs[data->pll].reg0, + PLL_DIV_MASK, plld); /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */ pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK, @@ -206,17 +106,18 @@ void init_pll(const struct pll_init_data *data) tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN); +#ifndef CONFIG_SOC_K2E } else if (data->pll == TETRIS_PLL) { bwadj = pllm >> 1; /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */ - setbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS); + setbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS); /* * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass) * only applicable for Kepler */ - clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN); + clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN); /* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */ - setbits_le32(pll_regs[data->pll].reg1 , + setbits_le32(keystone_pll_regs[data->pll].reg1 , PLL_PLLRST | PLLCTL_ENSAT); /* @@ -229,13 +130,13 @@ void init_pll(const struct pll_init_data *data) (pllm << 6) | (plld & PLL_DIV_MASK) | (pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS; - __raw_writel(tmp, pll_regs[data->pll].reg0); + __raw_writel(tmp, keystone_pll_regs[data->pll].reg0); /* Set BWADJ[11:8] bits */ - tmp = __raw_readl(pll_regs[data->pll].reg1); + tmp = __raw_readl(keystone_pll_regs[data->pll].reg1); tmp &= ~(PLL_BWADJ_HI_MASK); tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK); - __raw_writel(tmp, pll_regs[data->pll].reg1); + __raw_writel(tmp, keystone_pll_regs[data->pll].reg1); /* * 5 Wait for at least 5 us based on the reference * clock (PLL reset time) @@ -243,26 +144,27 @@ void init_pll(const struct pll_init_data *data) sdelay(21000); /* Wait for a minimum of 7 us*/ /* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */ - clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST); + clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST); /* * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1) * (PLL lock time) */ sdelay(105000); /* 8 disable bypass */ - clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS); + clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS); /* * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass) * only applicable for Kepler */ - setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN); + setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN); +#endif } else { - setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT); + setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT); /* * process keeps state of Bypass bit while programming * all other DDR PLL settings */ - tmp = __raw_readl(pll_regs[data->pll].reg0); + tmp = __raw_readl(keystone_pll_regs[data->pll].reg0); tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */ /* @@ -274,10 +176,10 @@ void init_pll(const struct pll_init_data *data) (pllm << PLL_MULT_SHIFT) | (plld & PLL_DIV_MASK) | (pllod << PLL_CLKOD_SHIFT); - __raw_writel(tmp, pll_regs[data->pll].reg0); + __raw_writel(tmp, keystone_pll_regs[data->pll].reg0); /* Set BWADJ[11:8] bits */ - tmp = __raw_readl(pll_regs[data->pll].reg1); + tmp = __raw_readl(keystone_pll_regs[data->pll].reg1); tmp &= ~(PLL_BWADJ_HI_MASK); tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK); @@ -285,20 +187,20 @@ void init_pll(const struct pll_init_data *data) if (data->pll == PASS_PLL) tmp |= PLLCTL_PAPLL; - __raw_writel(tmp, pll_regs[data->pll].reg1); + __raw_writel(tmp, keystone_pll_regs[data->pll].reg1); /* Reset bit: bit 14 for both DDR3 & PASS PLL */ tmp = PLL_PLLRST; /* Set RESET bit = 1 */ - setbits_le32(pll_regs[data->pll].reg1, tmp); + setbits_le32(keystone_pll_regs[data->pll].reg1, tmp); /* Wait for a minimum of 7 us*/ sdelay(21000); /* Clear RESET bit */ - clrbits_le32(pll_regs[data->pll].reg1, tmp); + clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp); sdelay(105000); /* clear BYPASS (Enable PLL Mode) */ - clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS); + clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS); sdelay(21000); /* Wait for a minimum of 7 us*/ } diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c index afd30f3..d97c95b 100644 --- a/arch/arm/cpu/armv7/keystone/cmd_clock.c +++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c @@ -14,10 +14,10 @@ #include <asm/arch/psc_defs.h> struct pll_init_data cmd_pll_data = { - .pll = MAIN_PLL, - .pll_m = 16, - .pll_d = 1, - .pll_od = 2, + .pll = MAIN_PLL, + .pll_m = 16, + .pll_d = 1, + .pll_od = 2, }; int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -27,12 +27,19 @@ int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (strncmp(argv[1], "pa", 2) == 0) cmd_pll_data.pll = PASS_PLL; +#ifndef CONFIG_SOC_K2E else if (strncmp(argv[1], "arm", 3) == 0) cmd_pll_data.pll = TETRIS_PLL; +#endif +#ifdef CONFIG_SOC_K2HK else if (strncmp(argv[1], "ddr3a", 5) == 0) cmd_pll_data.pll = DDR3A_PLL; else if (strncmp(argv[1], "ddr3b", 5) == 0) cmd_pll_data.pll = DDR3B_PLL; +#else + else if (strncmp(argv[1], "ddr3", 4) == 0) + cmd_pll_data.pll = DDR3_PLL; +#endif else goto pll_cmd_usage; @@ -51,11 +58,20 @@ pll_cmd_usage: return cmd_usage(cmdtp); } +#ifdef CONFIG_SOC_K2HK U_BOOT_CMD( pllset, 5, 0, do_pll_cmd, "set pll multiplier and pre divider", "<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n" ); +#endif +#ifdef CONFIG_SOC_K2E +U_BOOT_CMD( + pllset, 5, 0, do_pll_cmd, + "set pll multiplier and pre divider", + "<pa|ddr3> <mult> <div> <OD>\n" +); +#endif int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -79,7 +95,12 @@ U_BOOT_CMD( getclk, 2, 0, do_getclk_cmd, "get clock rate", "<clk index>\n" - "See the 'enum clk_e' in the k2hk clock.h for clk indexes\n" +#ifdef CONFIG_SOC_K2HK + "See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n" +#endif +#ifdef CONFIG_SOC_K2E + "See the 'enum clk_e' in the clock-k2e.h for clk indexes\n" +#endif ); int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c index 4875db7..2391e79 100644 --- a/arch/arm/cpu/armv7/keystone/ddr3.c +++ b/arch/arm/cpu/armv7/keystone/ddr3.c @@ -7,10 +7,11 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <asm/arch/hardware.h> #include <asm/io.h> +#include <common.h> +#include <asm/arch/ddr3.h> -void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) +void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) { unsigned int tmp; @@ -57,7 +58,7 @@ void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) ; } -void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) +void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) { __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET); __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET); @@ -67,3 +68,21 @@ void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET); __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET); } + +void ddr3_reset_ddrphy(void) +{ + u32 tmp; + + /* Assert DDR3A PHY reset */ + tmp = readl(KS2_DDR3APLLCTL1); + tmp |= KS2_DDR3_PLLCTRL_PHY_RESET; + writel(tmp, KS2_DDR3APLLCTL1); + + /* wait 10us to catch the reset */ + udelay(10); + + /* Release DDR3A PHY reset */ + tmp = readl(KS2_DDR3APLLCTL1); + tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET; + __raw_writel(tmp, KS2_DDR3APLLCTL1); +} diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c index 4df5ae1..a8f8aee 100644 --- a/arch/arm/cpu/armv7/keystone/init.c +++ b/arch/arm/cpu/armv7/keystone/init.c @@ -10,13 +10,14 @@ #include <common.h> #include <ns16550.h> #include <asm/io.h> +#include <asm/arch/msmc.h> #include <asm/arch/clock.h> #include <asm/arch/hardware.h> void chip_configuration_unlock(void) { - __raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0); - __raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1); + __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0); + __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1); } int arch_cpu_init(void) @@ -24,11 +25,12 @@ int arch_cpu_init(void) chip_configuration_unlock(); icache_enable(); -#ifdef CONFIG_SOC_K2HK - share_all_segments(8); - share_all_segments(9); - share_all_segments(10); /* QM PDSP */ - share_all_segments(11); /* PCIE */ + msmc_share_all_segments(8); /* TETRIS */ + msmc_share_all_segments(9); /* NETCP */ + msmc_share_all_segments(10); /* QM PDSP */ + msmc_share_all_segments(11); /* PCIE 0 */ +#ifdef CONFIG_SOC_K2E + msmc_share_all_segments(13); /* PCIE 1 */ #endif /* diff --git a/arch/arm/cpu/armv7/keystone/keystone.c b/arch/arm/cpu/armv7/keystone/keystone.c new file mode 100644 index 0000000..11a9357 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/keystone.c @@ -0,0 +1,87 @@ +/* + * Keystone EVM : Board initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mon.h> +#include <asm/arch/psc_defs.h> +#include <asm/arch/hardware.h> +#include <asm/arch/hardware.h> + +/** + * cpu_to_bus - swap bytes of the 32-bit data if the device is BE + * @ptr - array of data + * @length - lenght of data array + */ +int cpu_to_bus(u32 *ptr, u32 length) +{ + u32 i; + + if (!(readl(KS2_DEVSTAT) & 0x1)) + for (i = 0; i < length; i++, ptr++) + *ptr = cpu_to_be32(*ptr); + + return 0; +} + +static int turn_off_myself(void) +{ + printf("Turning off ourselves\r\n"); + mon_power_off(0); + + psc_disable_module(KS2_LPSC_TETRIS); + psc_disable_domain(KS2_TETRIS_PWR_DOMAIN); + + asm volatile ("isb\n" + "dsb\n" + "wfi\n"); + + printf("What! Should not see that\n"); + return 0; +} + +static void turn_off_all_dsps(int num_dsps) +{ + int i; + + for (i = 0; i < num_dsps; i++) { + if (psc_disable_module(i + KS2_LPSC_GEM_0)) + printf("Cannot disable module for #%d DSP", i); + + if (psc_disable_domain(i + 8)) + printf("Cannot disable domain for #%d DSP", i); + } +} + +int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return turn_off_myself(); +} + +U_BOOT_CMD( + killme, 1, 0, do_killme_cmd, + "turn off main ARM core", + "turn off main ARM core. Should not live after that :(\n" +); + +int misc_init_r(void) +{ + char *env; + long ks2_debug = 0; + + env = getenv("ks2_debug"); + + if (env) + ks2_debug = simple_strtol(env, NULL, 0); + + if ((ks2_debug & DBG_LEAVE_DSPS_ON) == 0) + turn_off_all_dsps(KS2_NUM_DSPS); + + return 0; +} diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c index f3f1621..7d8e597 100644 --- a/arch/arm/cpu/armv7/keystone/msmc.c +++ b/arch/arm/cpu/armv7/keystone/msmc.c @@ -8,7 +8,7 @@ */ #include <common.h> -#include <asm/arch/hardware.h> +#include <asm/arch/msmc.h> struct mpax { u32 mpaxl; @@ -56,9 +56,9 @@ struct msms_regs { }; -void share_all_segments(int priv_id) +void msmc_share_all_segments(int priv_id) { - struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE; + struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE; int j; for (j = 0; j < 8; j++) { diff --git a/arch/arm/cpu/armv7/keystone/psc.c b/arch/arm/cpu/armv7/keystone/psc.c index c844dc8..fa5422f 100644 --- a/arch/arm/cpu/armv7/keystone/psc.c +++ b/arch/arm/cpu/armv7/keystone/psc.c @@ -16,10 +16,6 @@ #define DEVICE_REG32_R(addr) __raw_readl((u32 *)(addr)) #define DEVICE_REG32_W(addr, val) __raw_writel(val, (u32 *)(addr)) -#ifdef CONFIG_SOC_K2HK -#define DEVICE_PSC_BASE K2HK_PSC_BASE -#endif - int psc_delay(void) { udelay(10); @@ -55,7 +51,7 @@ int psc_wait(u32 domain_num) retry = 0; do { - ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT); + ptstat = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PSTAT); ptstat = ptstat & (1 << domain_num); } while ((ptstat != 0) && ((retry += psc_delay()) < PSC_PTSTAT_TIMEOUT_LIMIT)); @@ -71,7 +67,7 @@ u32 psc_get_domain_num(u32 mod_num) u32 domain_num; /* Get the power domain associated with the module number */ - domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE + + domain_num = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); domain_num = PSC_REG_MDCFG_GET_PD(domain_num); @@ -106,7 +102,7 @@ int psc_set_state(u32 mod_num, u32 state) * Get the power domain associated with the module number, and reset * isolation functionality */ - v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num)); + v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); domain_num = PSC_REG_MDCFG_GET_PD(v); reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v); @@ -123,24 +119,24 @@ int psc_set_state(u32 mod_num, u32 state) * change is made if the new state is power down. */ if (state == PSC_REG_VAL_MDCTL_NEXT_ON) { - pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + + pdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num)); pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_ON); - DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), + DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl); } /* Set the next state for the module to enabled/disabled */ - mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num)); + mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state); mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso); - DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl); + DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl); /* Trigger the enable */ - ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD); + ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD); ptcmd |= (u32)(1<<domain_num); - DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd); + DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd); /* Wait on the complete */ return psc_wait(domain_num); @@ -161,7 +157,7 @@ int psc_enable_module(u32 mod_num) u32 mdctl; /* Set the bit to apply reset */ - mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num)); + mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON) return 0; @@ -180,11 +176,11 @@ int psc_disable_module(u32 mod_num) u32 mdctl; /* Set the bit to apply reset */ - mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num)); + mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); if ((mdctl & 0x3f) == 0) return 0; mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0); - DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl); + DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl); return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE); } @@ -203,11 +199,11 @@ int psc_set_reset_iso(u32 mod_num) u32 mdctl; /* Set the reset isolation bit */ - mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num)); + mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1); - DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl); + DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl); - v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num)); + v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1) return 0; @@ -224,14 +220,14 @@ int psc_disable_domain(u32 domain_num) u32 pdctl; u32 ptcmd; - pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num)); + pdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num)); pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF); pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP); - DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl); + DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl); - ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD); + ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD); ptcmd |= (u32)(1 << domain_num); - DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd); + DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd); return psc_wait(domain_num); } diff --git a/arch/arm/cpu/armv7/keystone/spl.c b/arch/arm/cpu/armv7/keystone/spl.c index e07b64d..d4b0e9b 100644 --- a/arch/arm/cpu/armv7/keystone/spl.c +++ b/arch/arm/cpu/armv7/keystone/spl.c @@ -18,10 +18,18 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_K2HK_EVM static struct pll_init_data spl_pll_config[] = { CORE_PLL_799, TETRIS_PLL_500, }; +#endif + +#ifdef CONFIG_K2E_EVM +static struct pll_init_data spl_pll_config[] = { + CORE_PLL_800, +}; +#endif void spl_init_keystone_plls(void) { diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 6367e09..745670e 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -10,10 +10,13 @@ #include <linux/linkage.h> #include <asm/gic.h> #include <asm/armv7.h> +#include <asm/proc-armv/ptrace.h> .arch_extension sec .arch_extension virt + .pushsection ._secure.text, "ax" + .align 5 /* the vector table for secure state and HYP mode */ _monitor_vectors: @@ -22,43 +25,95 @@ _monitor_vectors: adr pc, _secure_monitor .word 0 .word 0 - adr pc, _hyp_trap + .word 0 .word 0 .word 0 +.macro is_cpu_virt_capable tmp + mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1 + and \tmp, \tmp, #CPUID_ARM_VIRT_MASK @ mask virtualization bits + cmp \tmp, #(1 << CPUID_ARM_VIRT_SHIFT) +.endm + /* * secure monitor handler * U-boot calls this "software interrupt" in start.S * This is executed on a "smc" instruction, we use a "smc #0" to switch * to non-secure state. - * We use only r0 and r1 here, due to constraints in the caller. + * r0, r1, r2: passed to the callee + * ip: target PC */ _secure_monitor: - mrc p15, 0, r1, c1, c1, 0 @ read SCR - bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits - orr r1, r1, #0x31 @ enable NS, AW, FW bits +#ifdef CONFIG_ARMV7_PSCI + ldr r5, =_psci_vectors @ Switch to the next monitor + mcr p15, 0, r5, c12, c0, 1 + isb -#ifdef CONFIG_ARMV7_VIRT - mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 - and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits - cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT) - orreq r1, r1, #0x100 @ allow HVC instruction + @ Obtain a secure stack, and configure the PSCI backend + bl psci_arch_init #endif - mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) - + mrc p15, 0, r5, c1, c1, 0 @ read SCR + bic r5, r5, #0x4a @ clear IRQ, EA, nET bits + orr r5, r5, #0x31 @ enable NS, AW, FW bits + @ FIQ preserved for secure mode + mov r6, #SVC_MODE @ default mode is SVC + is_cpu_virt_capable r4 #ifdef CONFIG_ARMV7_VIRT - mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value - mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR + orreq r5, r5, #0x100 @ allow HVC instruction + moveq r6, #HYP_MODE @ Enter the kernel as HYP #endif - movs pc, lr @ return to non-secure SVC - -_hyp_trap: - mrs lr, elr_hyp @ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1 - mov pc, lr @ do no switch modes, but - @ return to caller + mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set) + isb + bne 1f + + @ Reset CNTVOFF to 0 before leaving monitor mode + mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1 + ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits + movne r4, #0 + mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero +1: + mov lr, ip + mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F + tst lr, #1 @ Check for Thumb PC + orrne ip, ip, #T_BIT @ Set T if Thumb + orr ip, ip, r6 @ Slot target mode in + msr spsr_cxfs, ip @ Set full SPSR + movs pc, lr @ ERET to non-secure + +ENTRY(_do_nonsec_entry) + mov ip, r0 + mov r0, r1 + mov r1, r2 + mov r2, r3 + smc #0 +ENDPROC(_do_nonsec_entry) + +.macro get_cbar_addr addr +#ifdef CONFIG_ARM_GIC_BASE_ADDRESS + ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS +#else + mrc p15, 4, \addr, c15, c0, 0 @ read CBAR + bfc \addr, #0, #15 @ clear reserved bits +#endif +.endm + +.macro get_gicd_addr addr + get_cbar_addr \addr + add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset +.endm + +.macro get_gicc_addr addr, tmp + get_cbar_addr \addr + is_cpu_virt_capable \tmp + movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9 + moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7 + add \addr, \addr, \tmp +.endm + +#ifndef CONFIG_ARMV7_PSCI /* * Secondary CPUs start here and call the code for the core specific parts * of the non-secure and HYP mode transition. The GIC distributor specific @@ -66,31 +121,21 @@ _hyp_trap: * Then they go back to wfi and wait to be woken up by the kernel again. */ ENTRY(_smp_pen) - mrs r0, cpsr - orr r0, r0, #0xc0 - msr cpsr, r0 @ disable interrupts - ldr r1, =_start - mcr p15, 0, r1, c12, c0, 0 @ set VBAR + cpsid i + cpsid f bl _nonsec_init - mov r12, r0 @ save GICC address -#ifdef CONFIG_ARMV7_VIRT - bl _switch_to_hyp -#endif - - ldr r1, [r12, #GICC_IAR] @ acknowledge IPI - str r1, [r12, #GICC_EOIR] @ signal end of interrupt adr r0, _smp_pen @ do not use this address again b smp_waitloop @ wait for IPIs, board specific ENDPROC(_smp_pen) +#endif /* * Switch a core to non-secure state. * * 1. initialize the GIC per-core interface * 2. allow coprocessor access in non-secure modes - * 3. switch the cpu mode (by calling "smc #0") * * Called from smp_pen by secondary cores and directly by the BSP. * Do not assume that the stack is available and only use registers @@ -100,38 +145,23 @@ ENDPROC(_smp_pen) * though, but we check this in C before calling this function. */ ENTRY(_nonsec_init) -#ifdef CONFIG_ARM_GIC_BASE_ADDRESS - ldr r2, =CONFIG_ARM_GIC_BASE_ADDRESS -#else - mrc p15, 4, r2, c15, c0, 0 @ read CBAR - bfc r2, #0, #15 @ clear reserved bits -#endif - add r3, r2, #GIC_DIST_OFFSET @ GIC dist i/f offset + get_gicd_addr r3 + mvn r1, #0 @ all bits to 1 str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts - mrc p15, 0, r0, c0, c0, 0 @ read MIDR - ldr r1, =MIDR_PRIMARY_PART_MASK - and r0, r0, r1 @ mask out variant and revision + get_gicc_addr r3, r1 - ldr r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK - cmp r0, r1 @ check for Cortex-A7 - - ldr r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK - cmpne r0, r1 @ check for Cortex-A15 - - movne r1, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9 - moveq r1, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7 - add r3, r2, r1 @ r3 = GIC CPU i/f addr - - mov r1, #1 @ set GICC_CTLR[enable] + mov r1, #3 @ Enable both groups str r1, [r3, #GICC_CTLR] @ and clear all other bits mov r1, #0xff str r1, [r3, #GICC_PMR] @ set priority mask register + mrc p15, 0, r0, c1, c1, 2 movw r1, #0x3fff - movt r1, #0x0006 - mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec + movt r1, #0x0004 + orr r0, r0, r1 + mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec /* The CNTFRQ register of the generic timer needs to be * programmed in secure state. Some primary bootloaders / firmware @@ -149,21 +179,9 @@ ENTRY(_nonsec_init) adr r1, _monitor_vectors mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors - - mrc p15, 0, ip, c12, c0, 0 @ save secure copy of VBAR - isb - smc #0 @ call into MONITOR mode - - mcr p15, 0, ip, c12, c0, 0 @ write non-secure copy of VBAR - - mov r1, #1 - str r1, [r3, #GICC_CTLR] @ enable non-secure CPU i/f - add r2, r2, #GIC_DIST_OFFSET - str r1, [r2, #GICD_CTLR] @ allow private interrupts mov r0, r3 @ return GICC address - bx lr ENDPROC(_nonsec_init) @@ -175,18 +193,10 @@ ENTRY(smp_waitloop) ldr r1, [r1] cmp r0, r1 @ make sure we dont execute this code beq smp_waitloop @ again (due to a spurious wakeup) - mov pc, r1 + mov r0, r1 + b _do_nonsec_entry ENDPROC(smp_waitloop) .weak smp_waitloop #endif -ENTRY(_switch_to_hyp) - mov r0, lr - mov r1, sp @ save SVC copy of LR and SP - isb - hvc #0 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1 - mov sp, r1 - mov lr, r0 @ restore SVC copy of LR and SP - - bx lr -ENDPROC(_switch_to_hyp) + .popsection diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 5f50a19..1b4477f 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -123,7 +123,8 @@ void s_init(void) hw_data_init(); #ifdef CONFIG_SPL_BUILD - if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0)) + if (warm_reset() && + (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0))) force_emif_self_refresh(); #endif watchdog_init(); diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index 5bc7e1f..fc4290c 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -87,9 +87,13 @@ void gpmc_init(void) STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; - u32 size = GPMC_SIZE_16M; u32 base = CONFIG_SYS_FLASH_BASE; -#elif defined(CONFIG_NAND) + u32 size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : + /* > 64MB */ ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : + /* > 32MB */ ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : + /* > 16MB */ ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : + /* min 16MB */ GPMC_SIZE_16M))); +#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) /* configure GPMC for NAND */ const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, M_NAND_GPMC_CONFIG2, @@ -99,8 +103,9 @@ void gpmc_init(void) M_NAND_GPMC_CONFIG6, 0 }; - u32 size = GPMC_SIZE_256M; u32 base = CONFIG_SYS_NAND_BASE; + u32 size = GPMC_SIZE_16M; + #elif defined(CONFIG_CMD_ONENAND) const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1, ONENAND_GPMC_CONFIG2, @@ -110,8 +115,8 @@ void gpmc_init(void) ONENAND_GPMC_CONFIG6, 0 }; - u32 base = PISMO1_ONEN_BASE; - u32 size = PISMO1_ONEN_SIZE; + u32 size = GPMC_SIZE_128M; + u32 base = CONFIG_SYS_ONENAND_BASE; #else const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 }; u32 size = 0; diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c deleted file mode 100644 index 1832aff..0000000 --- a/arch/arm/cpu/armv7/omap3/mem.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * - * Author : - * Manikandan Pillai <mani.pillai@ti.com> - * - * Initial Code from: - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/sys_proto.h> -#include <command.h> - -struct gpmc *gpmc_cfg; - -#if defined(CONFIG_CMD_NAND) -static const u32 gpmc_m_nand[GPMC_MAX_REG] = { - M_NAND_GPMC_CONFIG1, - M_NAND_GPMC_CONFIG2, - M_NAND_GPMC_CONFIG3, - M_NAND_GPMC_CONFIG4, - M_NAND_GPMC_CONFIG5, - M_NAND_GPMC_CONFIG6, 0 -}; -#endif /* CONFIG_CMD_NAND */ - -#if defined(CONFIG_CMD_ONENAND) -static const u32 gpmc_onenand[GPMC_MAX_REG] = { - ONENAND_GPMC_CONFIG1, - ONENAND_GPMC_CONFIG2, - ONENAND_GPMC_CONFIG3, - ONENAND_GPMC_CONFIG4, - ONENAND_GPMC_CONFIG5, - ONENAND_GPMC_CONFIG6, 0 -}; -#endif /* CONFIG_CMD_ONENAND */ - -/******************************************************** - * mem_ok() - test used to see if timings are correct - * for a part. Helps in guessing which part - * we are currently using. - *******************************************************/ -u32 mem_ok(u32 cs) -{ - u32 val1, val2, addr; - u32 pattern = 0x12345678; - - addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs); - - writel(0x0, addr + 0x400); /* clear pos A */ - writel(pattern, addr); /* pattern to pos B */ - writel(0x0, addr + 4); /* remove pattern off the bus */ - val1 = readl(addr + 0x400); /* get pos A value */ - val2 = readl(addr); /* get val2 */ - writel(0x0, addr + 0x400); /* clear pos A */ - - if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */ - return 0; - else - return 1; -} - -void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, - u32 size) -{ - writel(0, &cs->config7); - sdelay(1000); - /* Delay for settling */ - writel(gpmc_config[0], &cs->config1); - writel(gpmc_config[1], &cs->config2); - writel(gpmc_config[2], &cs->config3); - writel(gpmc_config[3], &cs->config4); - writel(gpmc_config[4], &cs->config5); - writel(gpmc_config[5], &cs->config6); - - /* - * Enable the config. size is the CS size and goes in - * bits 11:8. We set bit 6 to enable this CS and the base - * address goes into bits 5:0. - */ - writel((size << 8) | (GPMC_CS_ENABLE << 6) | - ((base >> 24) & GPMC_BASEADDR_MASK), - &cs->config7); - sdelay(2000); -} - -/***************************************************** - * gpmc_init(): init gpmc bus - * Init GPMC for x16, MuxMode (SDRAM in x32). - * This code can only be executed from SRAM or SDRAM. - *****************************************************/ -void gpmc_init(void) -{ - /* putting a blanket check on GPMC based on ZeBu for now */ - gpmc_cfg = (struct gpmc *)GPMC_BASE; -#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND) - const u32 *gpmc_config = NULL; - u32 base = 0; - u32 size = 0; -#endif - u32 config = 0; - - /* global settings */ - writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */ - writel(0, &gpmc_cfg->timeout_control);/* timeout disable */ - - config = readl(&gpmc_cfg->config); - config &= (~0xf00); - writel(config, &gpmc_cfg->config); - - /* - * Disable the GPMC0 config set by ROM code - * It conflicts with our MPDB (both at 0x08000000) - */ - writel(0, &gpmc_cfg->cs[0].config7); - sdelay(1000); - -#if defined(CONFIG_CMD_NAND) /* CS 0 */ - gpmc_config = gpmc_m_nand; - - base = PISMO1_NAND_BASE; - size = PISMO1_NAND_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); -#endif - -#if defined(CONFIG_CMD_ONENAND) - gpmc_config = gpmc_onenand; - base = PISMO1_ONEN_BASE; - size = PISMO1_ONEN_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); -#endif -} diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S new file mode 100644 index 0000000..bf11a34 --- /dev/null +++ b/arch/arm/cpu/armv7/psci.S @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2013,2014 - ARM Ltd + * Author: Marc Zyngier <marc.zyngier@arm.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <config.h> +#include <linux/linkage.h> +#include <asm/psci.h> + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + .globl _psci_vectors +_psci_vectors: + b default_psci_vector @ reset + b default_psci_vector @ undef + b _smc_psci @ smc + b default_psci_vector @ pabort + b default_psci_vector @ dabort + b default_psci_vector @ hyp + b default_psci_vector @ irq + b psci_fiq_enter @ fiq + +ENTRY(psci_fiq_enter) + movs pc, lr +ENDPROC(psci_fiq_enter) +.weak psci_fiq_enter + +ENTRY(default_psci_vector) + movs pc, lr +ENDPROC(default_psci_vector) +.weak default_psci_vector + +ENTRY(psci_cpu_suspend) +ENTRY(psci_cpu_off) +ENTRY(psci_cpu_on) +ENTRY(psci_migrate) + mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented) + mov pc, lr +ENDPROC(psci_migrate) +ENDPROC(psci_cpu_on) +ENDPROC(psci_cpu_off) +ENDPROC(psci_cpu_suspend) +.weak psci_cpu_suspend +.weak psci_cpu_off +.weak psci_cpu_on +.weak psci_migrate + +_psci_table: + .word ARM_PSCI_FN_CPU_SUSPEND + .word psci_cpu_suspend + .word ARM_PSCI_FN_CPU_OFF + .word psci_cpu_off + .word ARM_PSCI_FN_CPU_ON + .word psci_cpu_on + .word ARM_PSCI_FN_MIGRATE + .word psci_migrate + .word 0 + .word 0 + +_smc_psci: + push {r4-r7,lr} + + @ Switch to secure + mrc p15, 0, r7, c1, c1, 0 + bic r4, r7, #1 + mcr p15, 0, r4, c1, c1, 0 + isb + + adr r4, _psci_table +1: ldr r5, [r4] @ Load PSCI function ID + ldr r6, [r4, #4] @ Load target PC + cmp r5, #0 @ If reach the end, bail out + moveq r0, #ARM_PSCI_RET_INVAL @ Return -2 (Invalid) + beq 2f + cmp r0, r5 @ If not matching, try next entry + addne r4, r4, #8 + bne 1b + + blx r6 @ Execute PSCI function + + @ Switch back to non-secure +2: mcr p15, 0, r7, c1, c1, 0 + + pop {r4-r7, lr} + movs pc, lr @ Return to the kernel + + .popsection diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile index fad004c..dd7de41 100644 --- a/arch/arm/cpu/armv7/rmobile/Makefile +++ b/arch/arm/cpu/armv7/rmobile/Makefile @@ -13,5 +13,6 @@ obj-$(CONFIG_GLOBAL_TIMER) += timer.o obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o +obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c index 7a7c97d..b98137e 100644 --- a/arch/arm/cpu/armv7/rmobile/cpu_info.c +++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c @@ -53,6 +53,7 @@ static const struct { { 0x40, "R8A7740" }, { 0x45, "R8A7790" }, { 0x47, "R8A7791" }, + { 0x4C, "R8A7794" }, { 0x0, "CPU" }, }; diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c new file mode 100644 index 0000000..e123663 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c @@ -0,0 +1,1513 @@ +/* + * arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c + * This file is r8a7794 processor support - PFC hardware block. + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <sh_pfc.h> +#include <asm/gpio.h> + +#define CPU_32_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + +#define CPU_26_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ + PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx) + +#define CPU_28_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ + PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \ + PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx) + +/* + * GP_0_0_DATA -> GP_6_25_DATA + * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30],GP1[31] + * GP5[28],GP5[29]),GP5[30],GP5[31],GP6[26],GP6[27],GP6[28], + * GP6[29]),GP6[30],GP6[31]) + */ +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT(fn, pfx##_0_, sfx), \ + CPU_26_PORT(fn, pfx##_1_, sfx), \ + CPU_32_PORT(fn, pfx##_2_, sfx), \ + CPU_32_PORT(fn, pfx##_3_, sfx), \ + CPU_32_PORT(fn, pfx##_4_, sfx), \ + CPU_28_PORT(fn, pfx##_5_, sfx), \ + CPU_26_PORT(fn, pfx##_6_, sfx) + +#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ + GP##pfx##_IN, GP##pfx##_OUT) + +#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT +#define _GP_INDT(pfx, sfx) GP##pfx##_DATA + +#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) + + +#define PORT_10_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ + PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ + PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ + PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +#define CPU_32_PORT_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ + PORT_10_REV(fn, pfx, sfx) + +#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) + +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ + FN_##ipsr, FN_##fn) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + GP_ALL(IN), + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28, + FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, + FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18, + FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27, + FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4, + FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14, + FN_IP2_17_16, + + /* GPSR1 */ + FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30, + FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10, + FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18, + FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31, + FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0, + + /* GPSR2 */ + FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12, + FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23, + FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2, + FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14, + FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24, + FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2, + FN_IP6_5_4, FN_IP6_7_6, + + /* GPSR3 */ + FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13, + FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20, + FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, + FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18, + FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, + FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17, + FN_IP8_22_20, + + /* GPSR4 */ + FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3, + FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17, + FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0, + FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15, + FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27, + FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8, + FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16, + + /* GPSR5 */ + FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0, + FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13, + FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24, + FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9, + FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21, + FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, + + /* GPSR6 */ + FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2, + FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD, + FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0, + FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14, + FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20, + + /* + * From IPSR0 to IPSR5 have been removed because they does not use. + */ + + /* IPSR6 */ + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, + FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB, + FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0, + FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2, + FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4, + FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6, + FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB, + FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD, + FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N, + FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N, + FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, + FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK, + FN_ADIDATA, FN_AD_DI, + + /* IPSR7 */ + FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0, + FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, + FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3, + FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, + FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3, + FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, + FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, + FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, + FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0, + FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B, + FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B, + FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK, + FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD, + + /* IPSR8 */ + FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC, + FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, + FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX, + FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B, + FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, + FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7, + FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B, + FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, + FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK, + FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, + FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD, + FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, + FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B, + FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, + FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + /* IPSR11 */ + FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, + FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, + FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B, + FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6, + FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC, + FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78, + FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78, + FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7, + FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N, + FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, + FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, + FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, + FN_ADICLK_B, FN_AD_CLK_B, + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ + + /* MOD_SEL */ + FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, + FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1, + FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1, + FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0, + FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1, + FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0, + FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, + FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1, + FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0, + FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4, + FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, + FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, + FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1, + FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1, + + /* MOD_SEL2 */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0, + FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0, + FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0, + FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0, + FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0, + FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0, + FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, + FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, + FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1, + FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, + FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1, + FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1, + FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1, + FN_SEL_RDS_2, FN_SEL_RDS_3, + + /* MOD_SEL3 */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0, + FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, + FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0, + FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0, + FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0, + FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0, + FN_SEL_SSI9_1, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK, + + USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, + + SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK, + SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK, + + SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK, + SD1_DATA2_MARK, SD1_DATA3_MARK, + + /* + * From IPSR0 to IPSR5 have been removed because they does not use. + */ + + /* IPSR6 */ + DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK, + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK, + DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK, + CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, + AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK, + VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK, + AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK, + VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK, + AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK, + I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK, + VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK, + AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, + IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, + I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK, + VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK, + ADIDATA_MARK, AD_DI_MARK, + + /* IPSR7 */ + ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK, + AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK, + MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK, + AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, + CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK, + ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK, + AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK, + MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK, + ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK, + SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, + IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK, + VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK, + SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, + AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK, + SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK, + DREQ0_N_MARK, SCIFB1_RXD_MARK, + + /* IPSR8 */ + ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK, + AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK, + I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK, + HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK, + AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK, + SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK, + HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK, + AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK, + HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK, + I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK, + AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK, + SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK, + CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, + DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK, + I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK, + TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK, + I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK, + FMCLK_C_MARK, RDS_CLK_MARK, + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + /* IPSR11 */ + SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK, + CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, + DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK, + SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK, + SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK, + DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK, + SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, + CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK, + DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK, + DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, + AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK, + MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK, + PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, + ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, + PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK, + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ + + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(A2_MARK, FN_A2), + PINMUX_DATA(WE0_N_MARK, FN_WE0_N), + PINMUX_DATA(WE1_N_MARK, FN_WE1_N), + PINMUX_DATA(DACK0_MARK, FN_DACK0), + PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), + PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC), + PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN), + PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC), + PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK), + PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD), + PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0), + PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1), + PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2), + PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3), + PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD), + PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP), + PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK), + PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD), + PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0), + PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1), + PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2), + PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3), + + /* + * From IPSR0 to IPSR5 have been removed because they does not use. + */ + + /* IPSR6 */ + PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC), + PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE), + PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28), + PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE), + PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29), + PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP), + PINMUX_IPSR_DATA(IP6_5_4, QPOLA), + PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30), + PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE), + PINMUX_IPSR_DATA(IP6_7_6, QPOLB), + PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31), + PINMUX_IPSR_DATA(IP6_8, VI0_CLK), + PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK), + PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0), + PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV), + PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1), + PINMUX_IPSR_DATA(IP6_10, AVB_RXD0), + PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2), + PINMUX_IPSR_DATA(IP6_11, AVB_RXD1), + PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3), + PINMUX_IPSR_DATA(IP6_12, AVB_RXD2), + PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4), + PINMUX_IPSR_DATA(IP6_13, AVB_RXD3), + PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5), + PINMUX_IPSR_DATA(IP6_14, AVB_RXD4), + PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6), + PINMUX_IPSR_DATA(IP6_15, AVB_RXD5), + PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7), + PINMUX_IPSR_DATA(IP6_16, AVB_RXD6), + PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7), + PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER), + PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP6_25_23, AVB_COL), + PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0), + PINMUX_IPSR_DATA(IP6_31_29, VI0_G0), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3), + PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0), + + /* IPSR7 */ + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_2_0, VI0_G1), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3), + PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_5_3, VI0_G2), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_8_6, VI0_G3), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_11_9, VI0_G4), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3), + PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_14_12, VI0_G5), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3), + PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_17_15, VI0_G6), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2), + PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_20_18, VI0_G7), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3), + PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_23_21, VI0_R0), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3), + PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_26_24, VI0_R1), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1), + PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_29_27, VI0_R2), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4), + PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1), + PINMUX_IPSR_DATA(IP7_31, DREQ0_N), + PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD), + + /* IPSR8 */ + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0), + PINMUX_IPSR_DATA(IP8_2_0, VI0_R3), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4), + PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP8_5_3, VI0_R4), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP8_8_6, VI0_R5), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N), + PINMUX_IPSR_DATA(IP8_11_9, VI0_R6), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4), + PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N), + PINMUX_IPSR_DATA(IP8_14_12, VI0_R7), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4), + PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS), + PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2), + PINMUX_IPSR_DATA(IP8_19_17, PWM5), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1), + PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3), + PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2), + PINMUX_IPSR_DATA(IP8_22_20, TPUTO0), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0), + PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), + PINMUX_IPSR_DATA(IP8_25_23, PWM5_B), + PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), + PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), + PINMUX_IPSR_DATA(IP8_28_26, IRQ5), + PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2), + PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), + PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0), + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + /* IPSR11 */ + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), + PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0), + PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), + PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1), + PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12), + PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), + PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC), + PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13), + PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), + PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC), + PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14), + PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), + PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15), + PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2), + PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP), + PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2), + PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_DATA(IP11_20_18, IRQ8), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3), + PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N), + PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N), + PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), + PINMUX_IPSR_DATA(IP11_29_27, PWM0_B), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1), + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ +}; + +static struct pinmux_gpio pinmux_gpios[] = { + PINMUX_GPIO_GP_ALL(), + + GPIO_FN(A2), GPIO_FN(WE0_N), GPIO_FN(WE1_N), GPIO_FN(DACK0), + GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC), GPIO_FN(USB1_PWEN), + GPIO_FN(USB1_OVC), GPIO_FN(SD0_CLK), GPIO_FN(SD0_CMD), + GPIO_FN(SD0_DATA0), GPIO_FN(SD0_DATA1), GPIO_FN(SD0_DATA2), + GPIO_FN(SD0_DATA3), GPIO_FN(SD0_CD), GPIO_FN(SD0_WP), + GPIO_FN(SD1_CLK), GPIO_FN(SD1_CMD), GPIO_FN(SD1_DATA0), + GPIO_FN(SD1_DATA1), GPIO_FN(SD1_DATA2), GPIO_FN(SD1_DATA3), + + /* + * From IPSR0 to IPSR5 have been removed because they does not use + */ + + /* IPSR6 */ + GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE), + GPIO_FN(CC50_STATE28), GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), + GPIO_FN(QCPV_QDE), GPIO_FN(CC50_STATE29), GPIO_FN(DU0_DISP), + GPIO_FN(QPOLA), GPIO_FN(CC50_STATE30), GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), + GPIO_FN(CC50_STATE31), GPIO_FN(VI0_CLK), GPIO_FN(AVB_RX_CLK), + GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(AVB_RX_DV), + GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(AVB_RXD0), GPIO_FN(VI0_DATA2_VI0_B2), + GPIO_FN(AVB_RXD1), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(AVB_RXD2), + GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(AVB_RXD3), GPIO_FN(VI0_DATA5_VI0_B5), + GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RXD5), + GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RXD6), GPIO_FN(VI0_CLKENB), + GPIO_FN(I2C3_SCL), GPIO_FN(SCIFA5_RXD_C), GPIO_FN(IETX_C), + GPIO_FN(AVB_RXD7), GPIO_FN(VI0_FIELD), GPIO_FN(I2C3_SDA), + GPIO_FN(SCIFA5_TXD_C), GPIO_FN(IECLK_C), GPIO_FN(AVB_RX_ER), + GPIO_FN(VI0_HSYNC_N), GPIO_FN(SCIF0_RXD_B), GPIO_FN(I2C0_SCL_C), + GPIO_FN(IERX_C), GPIO_FN(AVB_COL), GPIO_FN(VI0_VSYNC_N), + GPIO_FN(SCIF0_TXD_B), GPIO_FN(I2C0_SDA_C), GPIO_FN(AUDIO_CLKOUT_B), + GPIO_FN(AVB_TX_EN), GPIO_FN(ETH_MDIO), GPIO_FN(VI0_G0), + GPIO_FN(MSIOF2_RXD_B), GPIO_FN(IIC0_SCL_D), GPIO_FN(AVB_TX_CLK), + GPIO_FN(ADIDATA), GPIO_FN(AD_DI), + + /* IPSR7 */ + GPIO_FN(ETH_CRS_DV), GPIO_FN(VI0_G1), GPIO_FN(MSIOF2_TXD_B), + GPIO_FN(IIC0_SDA_D), GPIO_FN(AVB_TXD0), GPIO_FN(ADICS_SAMP), + GPIO_FN(AD_DO), GPIO_FN(ETH_RX_ER), GPIO_FN(VI0_G2), + GPIO_FN(MSIOF2_SCK_B), GPIO_FN(CAN0_RX_B), GPIO_FN(AVB_TXD1), + GPIO_FN(ADICLK), GPIO_FN(AD_CLK), GPIO_FN(ETH_RXD0), GPIO_FN(VI0_G3), + GPIO_FN(MSIOF2_SYNC_B), GPIO_FN(CAN0_TX_B), GPIO_FN(AVB_TXD2), + GPIO_FN(ADICHS0), GPIO_FN(AD_NCS_N), GPIO_FN(ETH_RXD1), + GPIO_FN(VI0_G4), GPIO_FN(MSIOF2_SS1_B), GPIO_FN(SCIF4_RXD_D), + GPIO_FN(AVB_TXD3), GPIO_FN(ADICHS1), GPIO_FN(ETH_LINK), GPIO_FN(VI0_G5), + GPIO_FN(MSIOF2_SS2_B), GPIO_FN(SCIF4_TXD_D), GPIO_FN(AVB_TXD4), + GPIO_FN(ADICHS2), GPIO_FN(ETH_REFCLK), GPIO_FN(VI0_G6), + GPIO_FN(SCIF2_SCK_C), GPIO_FN(AVB_TXD5), GPIO_FN(SSI_SCK5_B), + GPIO_FN(ETH_TXD1), GPIO_FN(VI0_G7), GPIO_FN(SCIF2_RXD_C), + GPIO_FN(IIC1_SCL_D), GPIO_FN(AVB_TXD6), GPIO_FN(SSI_WS5_B), + GPIO_FN(ETH_TX_EN), GPIO_FN(VI0_R0), GPIO_FN(SCIF2_TXD_C), + GPIO_FN(IIC1_SDA_D), GPIO_FN(AVB_TXD7), GPIO_FN(SSI_SDATA5_B), + GPIO_FN(ETH_MAGIC), GPIO_FN(VI0_R1), GPIO_FN(SCIF3_SCK_B), + GPIO_FN(AVB_TX_ER), GPIO_FN(SSI_SCK6_B), GPIO_FN(ETH_TXD0), + GPIO_FN(VI0_R2), GPIO_FN(SCIF3_RXD_B), GPIO_FN(I2C4_SCL_E), + GPIO_FN(AVB_GTX_CLK), GPIO_FN(SSI_WS6_B), GPIO_FN(DREQ0_N), + GPIO_FN(SCIFB1_RXD), + + /* IPSR8 */ + GPIO_FN(ETH_MDC), GPIO_FN(VI0_R3), GPIO_FN(SCIF3_TXD_B), + GPIO_FN(I2C4_SDA_E), GPIO_FN(AVB_MDC), GPIO_FN(SSI_SDATA6_B), + GPIO_FN(HSCIF0_HRX), GPIO_FN(VI0_R4), GPIO_FN(I2C1_SCL_C), + GPIO_FN(AUDIO_CLKA_B), GPIO_FN(AVB_MDIO), GPIO_FN(SSI_SCK78_B), + GPIO_FN(HSCIF0_HTX), GPIO_FN(VI0_R5), GPIO_FN(I2C1_SDA_C), + GPIO_FN(AUDIO_CLKB_B), GPIO_FN(AVB_LINK), GPIO_FN(SSI_WS78_B), + GPIO_FN(HSCIF0_HCTS_N), GPIO_FN(VI0_R6), GPIO_FN(SCIF0_RXD_D), + GPIO_FN(I2C0_SCL_E), GPIO_FN(AVB_MAGIC), GPIO_FN(SSI_SDATA7_B), + GPIO_FN(HSCIF0_HRTS_N), GPIO_FN(VI0_R7), GPIO_FN(SCIF0_TXD_D), + GPIO_FN(I2C0_SDA_E), GPIO_FN(AVB_PHY_INT), GPIO_FN(SSI_SDATA8_B), + GPIO_FN(HSCIF0_HSCK), GPIO_FN(SCIF_CLK_B), GPIO_FN(AVB_CRS), + GPIO_FN(AUDIO_CLKC_B), GPIO_FN(I2C0_SCL), GPIO_FN(SCIF0_RXD_C), + GPIO_FN(PWM5), GPIO_FN(TCLK1_B), GPIO_FN(AVB_GTXREFCLK), + GPIO_FN(CAN1_RX_D), GPIO_FN(TPUTO0_B), GPIO_FN(I2C0_SDA), + GPIO_FN(SCIF0_TXD_C), GPIO_FN(TPUTO0), GPIO_FN(CAN_CLK), + GPIO_FN(DVC_MUTE), GPIO_FN(CAN1_TX_D), GPIO_FN(I2C1_SCL), + GPIO_FN(SCIF4_RXD), GPIO_FN(PWM5_B), GPIO_FN(DU1_DR0), + GPIO_FN(RIF1_SYNC_B), GPIO_FN(TS_SDATA_D), GPIO_FN(TPUTO1_B), + GPIO_FN(I2C1_SDA), GPIO_FN(SCIF4_TXD), GPIO_FN(IRQ5), + GPIO_FN(DU1_DR1), GPIO_FN(RIF1_CLK_B), GPIO_FN(TS_SCK_D), + GPIO_FN(BPFCLK_C), GPIO_FN(MSIOF0_RXD), GPIO_FN(SCIF5_RXD), + GPIO_FN(I2C2_SCL_C), GPIO_FN(DU1_DR2), GPIO_FN(RIF1_D0_B), + GPIO_FN(TS_SDEN_D), GPIO_FN(FMCLK_C), GPIO_FN(RDS_CLK), + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + /* IPSR11 */ + GPIO_FN(SSI_WS5), GPIO_FN(SCIFA3_RXD), GPIO_FN(I2C3_SCL_C), + GPIO_FN(DU1_DOTCLKOUT0), GPIO_FN(CAN_DEBUGOUT11), GPIO_FN(SSI_SDATA5), + GPIO_FN(SCIFA3_TXD), GPIO_FN(I2C3_SDA_C), GPIO_FN(DU1_DOTCLKOUT1), + GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6), GPIO_FN(SCIFA1_SCK_B), + GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(CAN_DEBUGOUT13), + GPIO_FN(SSI_WS6), GPIO_FN(SCIFA1_RXD_B), GPIO_FN(I2C4_SCL_C), + GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(CAN_DEBUGOUT14), + GPIO_FN(SSI_SDATA6), GPIO_FN(SCIFA1_TXD_B), GPIO_FN(I2C4_SDA_C), + GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), GPIO_FN(CAN_DEBUGOUT15), + GPIO_FN(SSI_SCK78), GPIO_FN(SCIFA2_SCK_B), GPIO_FN(IIC0_SDA_C), + GPIO_FN(DU1_DISP), GPIO_FN(SSI_WS78), GPIO_FN(SCIFA2_RXD_B), + GPIO_FN(IIC0_SCL_C), GPIO_FN(DU1_CDE), GPIO_FN(SSI_SDATA7), + GPIO_FN(SCIFA2_TXD_B), GPIO_FN(IRQ8), GPIO_FN(AUDIO_CLKA_D), + GPIO_FN(CAN_CLK_D), GPIO_FN(PCMOE_N), GPIO_FN(SSI_SCK0129), + GPIO_FN(MSIOF1_RXD_B), GPIO_FN(SCIF5_RXD_D), GPIO_FN(ADIDATA_B), + GPIO_FN(AD_DI_B), GPIO_FN(PCMWE_N), GPIO_FN(SSI_WS0129), + GPIO_FN(MSIOF1_TXD_B), GPIO_FN(SCIF5_TXD_D), GPIO_FN(ADICS_SAMP_B), + GPIO_FN(AD_DO_B), GPIO_FN(SSI_SDATA0), GPIO_FN(MSIOF1_SCK_B), + GPIO_FN(PWM0_B), GPIO_FN(ADICLK_B), GPIO_FN(AD_CLK_B), + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP2_17_16, + GP_0_30_FN, FN_IP2_15_14, + GP_0_29_FN, FN_IP2_13_12, + GP_0_28_FN, FN_IP2_11_10, + GP_0_27_FN, FN_IP2_9_8, + GP_0_26_FN, FN_IP2_7_6, + GP_0_25_FN, FN_IP2_5_4, + GP_0_24_FN, FN_IP2_3_2, + GP_0_23_FN, FN_IP2_1_0, + GP_0_22_FN, FN_IP1_31_30, + GP_0_21_FN, FN_IP1_29_28, + GP_0_20_FN, FN_IP1_27, + GP_0_19_FN, FN_IP1_26, + GP_0_18_FN, FN_A2, + GP_0_17_FN, FN_IP1_24, + GP_0_16_FN, FN_IP1_23_22, + GP_0_15_FN, FN_IP1_21_20, + GP_0_14_FN, FN_IP1_19_18, + GP_0_13_FN, FN_IP1_17_15, + GP_0_12_FN, FN_IP1_14_13, + GP_0_11_FN, FN_IP1_12_11, + GP_0_10_FN, FN_IP1_10_8, + GP_0_9_FN, FN_IP1_7_6, + GP_0_8_FN, FN_IP1_5_4, + GP_0_7_FN, FN_IP1_3_2, + GP_0_6_FN, FN_IP1_1_0, + GP_0_5_FN, FN_IP0_31_30, + GP_0_4_FN, FN_IP0_29_28, + GP_0_3_FN, FN_IP0_27_26, + GP_0_2_FN, FN_IP0_25, + GP_0_1_FN, FN_IP0_24, + GP_0_0_FN, FN_IP0_23_22, } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_FN, FN_DACK0, + GP_1_24_FN, FN_IP7_31, + GP_1_23_FN, FN_IP4_1_0, + GP_1_22_FN, FN_WE1_N, + GP_1_21_FN, FN_WE0_N, + GP_1_20_FN, FN_IP3_31, + GP_1_19_FN, FN_IP3_30, + GP_1_18_FN, FN_IP3_29_27, + GP_1_17_FN, FN_IP3_26_24, + GP_1_16_FN, FN_IP3_23_21, + GP_1_15_FN, FN_IP3_20_18, + GP_1_14_FN, FN_IP3_17_15, + GP_1_13_FN, FN_IP3_14_13, + GP_1_12_FN, FN_IP3_12, + GP_1_11_FN, FN_IP3_11, + GP_1_10_FN, FN_IP3_10, + GP_1_9_FN, FN_IP3_9_8, + GP_1_8_FN, FN_IP3_7_6, + GP_1_7_FN, FN_IP3_5_4, + GP_1_6_FN, FN_IP3_3_2, + GP_1_5_FN, FN_IP3_1_0, + GP_1_4_FN, FN_IP2_31_30, + GP_1_3_FN, FN_IP2_29_27, + GP_1_2_FN, FN_IP2_26_24, + GP_1_1_FN, FN_IP2_23_21, + GP_1_0_FN, FN_IP2_20_18, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + GP_2_31_FN, FN_IP6_7_6, + GP_2_30_FN, FN_IP6_5_4, + GP_2_29_FN, FN_IP6_3_2, + GP_2_28_FN, FN_IP6_1_0, + GP_2_27_FN, FN_IP5_31_30, + GP_2_26_FN, FN_IP5_29_28, + GP_2_25_FN, FN_IP5_27_26, + GP_2_24_FN, FN_IP5_25_24, + GP_2_23_FN, FN_IP5_23_22, + GP_2_22_FN, FN_IP5_21_20, + GP_2_21_FN, FN_IP5_19_18, + GP_2_20_FN, FN_IP5_17_16, + GP_2_19_FN, FN_IP5_15_14, + GP_2_18_FN, FN_IP5_13_12, + GP_2_17_FN, FN_IP5_11_9, + GP_2_16_FN, FN_IP5_8_6, + GP_2_15_FN, FN_IP5_5_4, + GP_2_14_FN, FN_IP5_3_2, + GP_2_13_FN, FN_IP5_1_0, + GP_2_12_FN, FN_IP4_31_30, + GP_2_11_FN, FN_IP4_29_28, + GP_2_10_FN, FN_IP4_27_26, + GP_2_9_FN, FN_IP4_25_23, + GP_2_8_FN, FN_IP4_22_20, + GP_2_7_FN, FN_IP4_19_18, + GP_2_6_FN, FN_IP4_17_16, + GP_2_5_FN, FN_IP4_15_14, + GP_2_4_FN, FN_IP4_13_12, + GP_2_3_FN, FN_IP4_11_10, + GP_2_2_FN, FN_IP4_9_8, + GP_2_1_FN, FN_IP4_7_5, + GP_2_0_FN, FN_IP4_4_2 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP8_22_20, + GP_3_30_FN, FN_IP8_19_17, + GP_3_29_FN, FN_IP8_16_15, + GP_3_28_FN, FN_IP8_14_12, + GP_3_27_FN, FN_IP8_11_9, + GP_3_26_FN, FN_IP8_8_6, + GP_3_25_FN, FN_IP8_5_3, + GP_3_24_FN, FN_IP8_2_0, + GP_3_23_FN, FN_IP7_29_27, + GP_3_22_FN, FN_IP7_26_24, + GP_3_21_FN, FN_IP7_23_21, + GP_3_20_FN, FN_IP7_20_18, + GP_3_19_FN, FN_IP7_17_15, + GP_3_18_FN, FN_IP7_14_12, + GP_3_17_FN, FN_IP7_11_9, + GP_3_16_FN, FN_IP7_8_6, + GP_3_15_FN, FN_IP7_5_3, + GP_3_14_FN, FN_IP7_2_0, + GP_3_13_FN, FN_IP6_31_29, + GP_3_12_FN, FN_IP6_28_26, + GP_3_11_FN, FN_IP6_25_23, + GP_3_10_FN, FN_IP6_22_20, + GP_3_9_FN, FN_IP6_19_17, + GP_3_8_FN, FN_IP6_16, + GP_3_7_FN, FN_IP6_15, + GP_3_6_FN, FN_IP6_14, + GP_3_5_FN, FN_IP6_13, + GP_3_4_FN, FN_IP6_12, + GP_3_3_FN, FN_IP6_11, + GP_3_2_FN, FN_IP6_10, + GP_3_1_FN, FN_IP6_9, + GP_3_0_FN, FN_IP6_8 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP11_17_16, + GP_4_30_FN, FN_IP11_15_14, + GP_4_29_FN, FN_IP11_13_11, + GP_4_28_FN, FN_IP11_10_8, + GP_4_27_FN, FN_IP11_7_6, + GP_4_26_FN, FN_IP11_5_3, + GP_4_25_FN, FN_IP11_2_0, + GP_4_24_FN, FN_IP10_31_30, + GP_4_23_FN, FN_IP10_29_27, + GP_4_22_FN, FN_IP10_26_24, + GP_4_21_FN, FN_IP10_23_21, + GP_4_20_FN, FN_IP10_20_18, + GP_4_19_FN, FN_IP10_17_15, + GP_4_18_FN, FN_IP10_14_12, + GP_4_17_FN, FN_IP10_11_9, + GP_4_16_FN, FN_IP10_8_6, + GP_4_15_FN, FN_IP10_5_3, + GP_4_14_FN, FN_IP10_2_0, + GP_4_13_FN, FN_IP9_30_28, + GP_4_12_FN, FN_IP9_27_25, + GP_4_11_FN, FN_IP9_24_22, + GP_4_10_FN, FN_IP9_21_19, + GP_4_9_FN, FN_IP9_18_17, + GP_4_8_FN, FN_IP9_16_15, + GP_4_7_FN, FN_IP9_14_12, + GP_4_6_FN, FN_IP9_11_9, + GP_4_5_FN, FN_IP9_8_6, + GP_4_4_FN, FN_IP9_5_3, + GP_4_3_FN, FN_IP9_2_0, + GP_4_2_FN, FN_IP8_31_29, + GP_4_1_FN, FN_IP8_28_26, + GP_4_0_FN, FN_IP8_25_23 } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_27_FN, FN_USB1_OVC, + GP_5_26_FN, FN_USB1_PWEN, + GP_5_25_FN, FN_USB0_OVC, + GP_5_24_FN, FN_USB0_PWEN, + GP_5_23_FN, FN_IP13_26_24, + GP_5_22_FN, FN_IP13_23_21, + GP_5_21_FN, FN_IP13_20_18, + GP_5_20_FN, FN_IP13_17_15, + GP_5_19_FN, FN_IP13_14_12, + GP_5_18_FN, FN_IP13_11_9, + GP_5_17_FN, FN_IP13_8_6, + GP_5_16_FN, FN_IP13_5_3, + GP_5_15_FN, FN_IP13_2_0, + GP_5_14_FN, FN_IP12_29_27, + GP_5_13_FN, FN_IP12_26_24, + GP_5_12_FN, FN_IP12_23_21, + GP_5_11_FN, FN_IP12_20_18, + GP_5_10_FN, FN_IP12_17_15, + GP_5_9_FN, FN_IP12_14_13, + GP_5_8_FN, FN_IP12_12_11, + GP_5_7_FN, FN_IP12_10_9, + GP_5_6_FN, FN_IP12_8_6, + GP_5_5_FN, FN_IP12_5_3, + GP_5_4_FN, FN_IP12_2_0, + GP_5_3_FN, FN_IP11_29_27, + GP_5_2_FN, FN_IP11_26_24, + GP_5_1_FN, FN_IP11_23_21, + GP_5_0_FN, FN_IP11_20_18 } + }, + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_25_FN, FN_IP0_21_20, + GP_6_24_FN, FN_IP0_19_18, + GP_6_23_FN, FN_IP0_17, + GP_6_22_FN, FN_IP0_16, + GP_6_21_FN, FN_IP0_15, + GP_6_20_FN, FN_IP0_14, + GP_6_19_FN, FN_IP0_13, + GP_6_18_FN, FN_IP0_12, + GP_6_17_FN, FN_IP0_11, + GP_6_16_FN, FN_IP0_10, + GP_6_15_FN, FN_IP0_9_8, + GP_6_14_FN, FN_IP0_0, + GP_6_13_FN, FN_SD1_DATA3, + GP_6_12_FN, FN_SD1_DATA2, + GP_6_11_FN, FN_SD1_DATA1, + GP_6_10_FN, FN_SD1_DATA0, + GP_6_9_FN, FN_SD1_CMD, + GP_6_8_FN, FN_SD1_CLK, + GP_6_7_FN, FN_SD0_WP, + GP_6_6_FN, FN_SD0_CD, + GP_6_5_FN, FN_SD0_DATA3, + GP_6_4_FN, FN_SD0_DATA2, + GP_6_3_FN, FN_SD0_DATA1, + GP_6_2_FN, FN_SD0_DATA0, + GP_6_1_FN, FN_SD0_CMD, + GP_6_0_FN, FN_SD0_CLK } + }, + + /* + * From IPSR0 to IPSR5 have been removed because they does not use. + */ + + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, + 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, + 2, 2) { + /* IP6_31_29 [3] */ + FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, + FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0, + /* IP6_28_26 [3] */ + FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, + FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0, + /* IP6_25_23 [3] */ + FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, + FN_AVB_COL, 0, 0, 0, + /* IP6_22_20 [3] */ + FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, + FN_AVB_RX_ER, 0, 0, 0, + /* IP6_19_17 [3] */ + FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, + FN_AVB_RXD7, 0, 0, 0, + /* IP6_16 [1] */ + FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, + /* IP6_15 [1] */ + FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5, + /* IP6_14 [1] */ + FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, + /* IP6_13 [1] */ + FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3, + /* IP6_12 [1] */ + FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, + /* IP6_11 [1] */ + FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1, + /* IP6_10 [1] */ + FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, + /* IP6_9 [1] */ + FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV, + /* IP6_8 [1] */ + FN_VI0_CLK, FN_AVB_RX_CLK, + /* IP6_7_6 [2] */ + FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0, + /* IP6_5_4 [2] */ + FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0, + /* IP6_3_2 [2] */ + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, + /* IP6_1_0 [2] */ + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, + 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP7_31 [1] */ + FN_DREQ0_N, FN_SCIFB1_RXD, + /* IP7_30 [1] */ + 0, 0, + /* IP7_29_27 [3] */ + FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, + FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0, + /* IP7_26_24 [3] */ + FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, + FN_SSI_SCK6_B, 0, 0, 0, + /* IP7_23_21 [3] */ + FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D, + FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0, + /* IP7_20_18 [3] */ + FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D, + FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0, + /* IP7_17_15 [3] */ + FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, + FN_SSI_SCK5_B, 0, 0, 0, + /* IP7_14_12 [3] */ + FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, + FN_AVB_TXD4, FN_ADICHS2, 0, 0, + /* IP7_11_9 [3] */ + FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, + FN_AVB_TXD3, FN_ADICHS1, 0, 0, + /* IP7_8_6 [3] */ + FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, + FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0, + /* IP7_5_3 [3] */ + FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, + FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0, + /* IP7_2_0 [3] */ + FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, + FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, + 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) { + /* IP8_31_29 [3] */ + FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, + FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, + /* IP8_28_26 [3] */ + FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, + FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0, + /* IP8_25_23 [3] */ + FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, + FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0, + /* IP8_22_20 [3] */ + FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, + FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0, + /* IP8_19_17 [3] */ + FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, + FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0, + /* IP8_16_15 [2] */ + FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, + /* IP8_14_12 [3] */ + FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E, + FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0, + /* IP8_11_9 [3] */ + FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, + FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0, + /* IP8_8_6 [3] */ + FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, + FN_AVB_LINK, FN_SSI_WS78_B, 0, 0, + /* IP8_5_3 [3] */ + FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, + FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0, + /* IP8_2_0 [3] */ + FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, + FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, } + }, + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, + 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) { + /* IP11_31_30 [2] */ + 0, 0, 0, 0, + /* IP11_29_27 [3] */ + FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, + FN_AD_CLK_B, 0, 0, 0, + /* IP11_26_24 [3] */ + FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B, + FN_AD_DO_B, 0, 0, 0, + /* IP11_23_21 [3] */ + FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, + FN_AD_DI_B, FN_PCMWE_N, 0, 0, + /* IP11_20_18 [3] */ + FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, + FN_CAN_CLK_D, FN_PCMOE_N, 0, 0, + /* IP11_17_16 [2] */ + FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, + /* IP11_15_14 [2] */ + FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, + /* IP11_13_11 [3] */ + FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0, + /* IP11_10_8 [3] */ + FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, + FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0, + /* IP11_7_6 [2] */ + FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, + FN_CAN_DEBUGOUT13, + /* IP11_5_3 [3] */ + FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1, + FN_CAN_DEBUGOUT12, 0, 0, 0, + /* IP11_2_0 [3] */ + FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, + FN_CAN_DEBUGOUT11, 0, 0, 0, } + }, + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ + + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, + 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, + 2, 1) { + /* SEL_ADG [2] */ + FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, + /* SEL_ADI [1] */ + FN_SEL_ADI_0, FN_SEL_ADI_1, + /* SEL_CAN [2] */ + FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, + /* SEL_DARC [3] */ + FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, + FN_SEL_DARC_4, 0, 0, 0, + /* SEL_DR0 [1] */ + FN_SEL_DR0_0, FN_SEL_DR0_1, + /* SEL_DR1 [1] */ + FN_SEL_DR1_0, FN_SEL_DR1_1, + /* SEL_DR2 [1] */ + FN_SEL_DR2_0, FN_SEL_DR2_1, + /* SEL_DR3 [1] */ + FN_SEL_DR3_0, FN_SEL_DR3_1, + /* SEL_ETH [1] */ + FN_SEL_ETH_0, FN_SEL_ETH_1, + /* SLE_FSN [1] */ + FN_SEL_FSN_0, FN_SEL_FSN_1, + /* SEL_IC200 [3] */ + FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, + FN_SEL_I2C00_4, 0, 0, 0, + /* SEL_I2C01 [3] */ + FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, + FN_SEL_I2C01_4, 0, 0, 0, + /* SEL_I2C02 [3] */ + FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, + FN_SEL_I2C02_4, 0, 0, 0, + /* SEL_I2C03 [3] */ + FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, + FN_SEL_I2C03_4, 0, 0, 0, + /* SEL_I2C04 [3] */ + FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, + FN_SEL_I2C04_4, 0, 0, 0, + /* SEL_IIC00 [2] */ + FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3, + /* SEL_AVB [1] */ + FN_SEL_AVB_0, FN_SEL_AVB_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, + 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, + 2, 2, 2, 1, 1, 2) { + /* SEL_IEB [2] */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, + /* SEL_IIC0 [2] */ + FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, + /* SEL_LBS [1] */ + FN_SEL_LBS_0, FN_SEL_LBS_1, + /* SEL_MSI1 [1] */ + FN_SEL_MSI1_0, FN_SEL_MSI1_1, + /* SEL_MSI2 [1] */ + FN_SEL_MSI2_0, FN_SEL_MSI2_1, + /* SEL_RAD [1] */ + FN_SEL_RAD_0, FN_SEL_RAD_1, + /* SEL_RCN [1] */ + FN_SEL_RCN_0, FN_SEL_RCN_1, + /* SEL_RSP [1] */ + FN_SEL_RSP_0, FN_SEL_RSP_1, + /* SEL_SCIFA0 [2] */ + FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, + FN_SEL_SCIFA0_3, + /* SEL_SCIFA1 [2] */ + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, + /* SEL_SCIFA2 [1] */ + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + /* SEL_SCIFA3 [1] */ + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, + /* SEL_SCIFA4 [2] */ + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, + FN_SEL_SCIFA4_3, + /* SEL_SCIFA5 [2] */ + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, + FN_SEL_SCIFA5_3, + /* SEL_SPDM [1] */ + FN_SEL_SPDM_0, FN_SEL_SPDM_1, + /* SEL_TMU [1] */ + FN_SEL_TMU_0, FN_SEL_TMU_1, + /* SEL_TSIF0 [2] */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + /* SEL_CAN0 [2] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + /* SEL_CAN1 [2] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + /* SEL_HSCIF0 [1] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, + /* SEL_HSCIF1 [1] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + /* SEL_RDS [2] */ + FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, + 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { + /* SEL_SCIF0 [2] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + /* SEL_SCIF1 [2] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0, + /* SEL_SCIF2 [2] */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0, + /* SEL_SCIF3 [1] */ + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, + /* SEL_SCIF4 [3] */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + FN_SEL_SCIF4_4, 0, 0, 0, + /* SEL_SCIF5 [2] */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, + /* SEL_SSI1 [1] */ + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + /* SEL_SSI2 [1] */ + FN_SEL_SSI2_0, FN_SEL_SSI2_1, + /* SEL_SSI4 [1] */ + FN_SEL_SSI4_0, FN_SEL_SSI4_1, + /* SEL_SSI5 [1] */ + FN_SEL_SSI5_0, FN_SEL_SSI5_1, + /* SEL_SSI6 [1] */ + FN_SEL_SSI6_0, FN_SEL_SSI6_1, + /* SEL_SSI7 [1] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + /* SEL_SSI8 [1] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, + /* SEL_SSI9 [1] */ + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, } + }, + { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, + { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_IN, GP_1_25_OUT, + GP_1_24_IN, GP_1_24_OUT, + GP_1_23_IN, GP_1_23_OUT, + GP_1_22_IN, GP_1_22_OUT, + GP_1_21_IN, GP_1_21_OUT, + GP_1_20_IN, GP_1_20_OUT, + GP_1_19_IN, GP_1_19_OUT, + GP_1_18_IN, GP_1_18_OUT, + GP_1_17_IN, GP_1_17_OUT, + GP_1_16_IN, GP_1_16_OUT, + GP_1_15_IN, GP_1_15_OUT, + GP_1_14_IN, GP_1_14_OUT, + GP_1_13_IN, GP_1_13_OUT, + GP_1_12_IN, GP_1_12_OUT, + GP_1_11_IN, GP_1_11_OUT, + GP_1_10_IN, GP_1_10_OUT, + GP_1_9_IN, GP_1_9_OUT, + GP_1_8_IN, GP_1_8_OUT, + GP_1_7_IN, GP_1_7_OUT, + GP_1_6_IN, GP_1_6_OUT, + GP_1_5_IN, GP_1_5_OUT, + GP_1_4_IN, GP_1_4_OUT, + GP_1_3_IN, GP_1_3_OUT, + GP_1_2_IN, GP_1_2_OUT, + GP_1_1_IN, GP_1_1_OUT, + GP_1_0_IN, GP_1_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } }, + { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } }, + { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } }, + { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_27_IN, GP_5_27_OUT, + GP_5_26_IN, GP_5_26_OUT, + GP_5_25_IN, GP_5_25_OUT, + GP_5_24_IN, GP_5_24_OUT, + GP_5_23_IN, GP_5_23_OUT, + GP_5_22_IN, GP_5_22_OUT, + GP_5_21_IN, GP_5_21_OUT, + GP_5_20_IN, GP_5_20_OUT, + GP_5_19_IN, GP_5_19_OUT, + GP_5_18_IN, GP_5_18_OUT, + GP_5_17_IN, GP_5_17_OUT, + GP_5_16_IN, GP_5_16_OUT, + GP_5_15_IN, GP_5_15_OUT, + GP_5_14_IN, GP_5_14_OUT, + GP_5_13_IN, GP_5_13_OUT, + GP_5_12_IN, GP_5_12_OUT, + GP_5_11_IN, GP_5_11_OUT, + GP_5_10_IN, GP_5_10_OUT, + GP_5_9_IN, GP_5_9_OUT, + GP_5_8_IN, GP_5_8_OUT, + GP_5_7_IN, GP_5_7_OUT, + GP_5_6_IN, GP_5_6_OUT, + GP_5_5_IN, GP_5_5_OUT, + GP_5_4_IN, GP_5_4_OUT, + GP_5_3_IN, GP_5_3_OUT, + GP_5_2_IN, GP_5_2_OUT, + GP_5_1_IN, GP_5_1_OUT, + GP_5_0_IN, GP_5_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_25_IN, GP_6_25_OUT, + GP_6_24_IN, GP_6_24_OUT, + GP_6_23_IN, GP_6_23_OUT, + GP_6_22_IN, GP_6_22_OUT, + GP_6_21_IN, GP_6_21_OUT, + GP_6_20_IN, GP_6_20_OUT, + GP_6_19_IN, GP_6_19_OUT, + GP_6_18_IN, GP_6_18_OUT, + GP_6_17_IN, GP_6_17_OUT, + GP_6_16_IN, GP_6_16_OUT, + GP_6_15_IN, GP_6_15_OUT, + GP_6_14_IN, GP_6_14_OUT, + GP_6_13_IN, GP_6_13_OUT, + GP_6_12_IN, GP_6_12_OUT, + GP_6_11_IN, GP_6_11_OUT, + GP_6_10_IN, GP_6_10_OUT, + GP_6_9_IN, GP_6_9_OUT, + GP_6_8_IN, GP_6_8_OUT, + GP_6_7_IN, GP_6_7_OUT, + GP_6_6_IN, GP_6_6_OUT, + GP_6_5_IN, GP_6_5_OUT, + GP_6_4_IN, GP_6_4_OUT, + GP_6_3_IN, GP_6_3_OUT, + GP_6_2_IN, GP_6_2_OUT, + GP_6_1_IN, GP_6_1_OUT, + GP_6_0_IN, GP_6_0_OUT, } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } }, + { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { + 0, 0, 0, 0, + 0, 0, GP_1_25_DATA, GP_1_24_DATA, + GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, + GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, + GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, + GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, + GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, + GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } + }, + { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } }, + { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } }, + { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } }, + { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { + 0, 0, 0, 0, + GP_5_27_DATA, GP_5_26_DATA, GP_5_25_DATA, GP_5_24_DATA, + GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA, + GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA, + GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA, + GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA, + GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, + GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA } + }, + { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { + 0, 0, 0, 0, + 0, 0, GP_6_25_DATA, GP_6_24_DATA, + GP_6_23_DATA, GP_6_22_DATA, GP_6_21_DATA, GP_6_20_DATA, + GP_6_19_DATA, GP_6_18_DATA, GP_6_17_DATA, GP_6_16_DATA, + GP_6_15_DATA, GP_6_14_DATA, GP_6_13_DATA, GP_6_12_DATA, + GP_6_11_DATA, GP_6_10_DATA, GP_6_9_DATA, GP_6_8_DATA, + GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA, + GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA } + }, + { }, +}; + +static struct pinmux_info r8a7794_pinmux_info = { + .name = "r8a7794_pfc", + + .unlock_reg = 0xe6060000, /* PMMR */ + + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_FN_AD_CLK_B, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void r8a7794_pinmux_init(void) +{ + register_pinmux(&r8a7794_pinmux_info); +} diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index a64bfa1..6c70639 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -11,6 +11,8 @@ obj-y += timer.o obj-y += board.o obj-y += clock.o obj-y += pinmux.o +obj-$(CONFIG_SUN4I) += clock_sun4i.o +obj-$(CONFIG_SUN5I) += clock_sun4i.o obj-$(CONFIG_SUN7I) += clock_sun4i.o ifndef CONFIG_SPL_BUILD @@ -18,6 +20,8 @@ obj-y += cpu_info.o endif ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SUN4I) += dram.o +obj-$(CONFIG_SUN5I) += dram.o obj-$(CONFIG_SUN7I) += dram.o ifdef CONFIG_SPL_FEL obj-y += start.o diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 49c9448..8f2cef3 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -11,6 +11,7 @@ */ #include <common.h> +#include <i2c.h> #include <netdev.h> #include <miiphy.h> #include <serial.h> @@ -24,6 +25,8 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/timer.h> +#include <linux/compiler.h> + #ifdef CONFIG_SPL_BUILD /* Pointer to the global data structure for SPL */ DECLARE_GLOBAL_DATA_PTR; @@ -47,15 +50,38 @@ u32 spl_boot_mode(void) int gpio_init(void) { +#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)) sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); sunxi_gpio_set_pull(SUNXI_GPB(23), 1); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX); + sunxi_gpio_set_pull(SUNXI_GPB(20), 1); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX); + sunxi_gpio_set_pull(SUNXI_GPG(4), 1); +#else +#error Unsupported console port number. Please fix pin mux settings in board.c +#endif return 0; } void reset_cpu(ulong addr) { + static const struct sunxi_wdog *wdog = + &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; + + /* Set the watchdog for its shortest interval (.5s) and wait */ + writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); + writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); + + while (1) { + /* sun5i sometimes gets stuck without this */ + writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); + } } /* do some early init */ @@ -72,11 +98,16 @@ void s_init(void) clock_init(); timer_init(); gpio_init(); + i2c_init_board(); #ifdef CONFIG_SPL_BUILD gd = &gdata; preloader_console_init(); +#ifdef CONFIG_SPL_I2C_SUPPORT + /* Needed early by sunxi_board_init if PMU is enabled */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif sunxi_board_init(); #endif } @@ -96,7 +127,15 @@ void enable_caches(void) */ int cpu_eth_init(bd_t *bis) { - int rc; + __maybe_unused int rc; + +#ifdef CONFIG_SUNXI_EMAC + rc = sunxi_emac_initialize(bis); + if (rc < 0) { + printf("sunxi: failed to initialize emac\n"); + return rc; + } +#endif #ifdef CONFIG_SUNXI_GMAC rc = sunxi_gmac_initialize(bis); diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index 5a7da3c..b8b16cf 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -36,8 +36,7 @@ void clock_init_safe(void) CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, &ccm->cpu_ahb_apb0_cfg); #ifdef CONFIG_SUN7I - writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0), - &ccm->ahb_gate0); + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); #endif writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); } diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c index b4c3d5c..5cf35ac 100644 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -13,7 +13,22 @@ #ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { +#ifdef CONFIG_SUN4I + puts("CPU: Allwinner A10 (SUN4I)\n"); +#elif defined CONFIG_SUN5I + u32 val = readl(SUNXI_SID_BASE + 0x08); + switch ((val >> 12) & 0xf) { + case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break; + case 3: puts("CPU: Allwinner A13 (SUN5I)\n"); break; + case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break; + default: puts("CPU: Allwinner A1X (SUN5I)\n"); + } +#elif defined CONFIG_SUN7I puts("CPU: Allwinner A20 (SUN7I)\n"); +#else +#warning Please update cpu_info.c with correct CPU information + puts("CPU: SUNXI Family\n"); +#endif return 0; } #endif diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c index b43c4b4..0f1ceec 100644 --- a/arch/arm/cpu/armv7/sunxi/dram.c +++ b/arch/arm/cpu/armv7/sunxi/dram.c @@ -53,16 +53,37 @@ static void mctl_ddr3_reset(void) struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - clrbits_le32(&dram->mcr, DRAM_MCR_RESET); - udelay(2); - setbits_le32(&dram->mcr, DRAM_MCR_RESET); +#ifdef CONFIG_SUN4I + struct sunxi_timer_reg *timer = + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE; + u32 reg_val; + + writel(0, &timer->cpu_cfg); + reg_val = readl(&timer->cpu_cfg); + + if ((reg_val & CPU_CFG_CHIP_VER_MASK) != + CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) { + setbits_le32(&dram->mcr, DRAM_MCR_RESET); + udelay(2); + clrbits_le32(&dram->mcr, DRAM_MCR_RESET); + } else +#endif + { + clrbits_le32(&dram->mcr, DRAM_MCR_RESET); + udelay(2); + setbits_le32(&dram->mcr, DRAM_MCR_RESET); + } } static void mctl_set_drive(void) { struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; +#ifdef CONFIG_SUN7I clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), +#else + clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), +#endif DRAM_MCR_MODE_EN(0x3) | 0xffc); } @@ -134,6 +155,26 @@ static void mctl_enable_dllx(u32 phase) } static u32 hpcr_value[32] = { +#ifdef CONFIG_SUN5I + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x1031, 0x1031, 0x0735, 0x1035, + 0x1035, 0x0731, 0x1031, 0, + 0x0301, 0x0301, 0x0301, 0x0301, + 0x0301, 0x0301, 0x0301, 0 +#endif +#ifdef CONFIG_SUN4I + 0x0301, 0x0301, 0x0301, 0x0301, + 0x0301, 0x0301, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x1031, 0x1031, 0x0735, 0x5031, + 0x1035, 0x0731, 0x1031, 0x0735, + 0x1035, 0x1031, 0x0731, 0x1035, + 0x1031, 0x0301, 0x0301, 0x0731 +#endif #ifdef CONFIG_SUN7I 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, @@ -223,22 +264,38 @@ static void mctl_setup_dram_clock(u32 clk) clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); #endif +#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) /* setup MBUS clock */ reg_val = CCM_MBUS_CTRL_GATE | +#ifdef CONFIG_SUN7I CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) | CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) | CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2)); +#else /* defined(CONFIG_SUN5I) */ + CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) | + CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) | + CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2)); +#endif writel(reg_val, &ccm->mbus_clk_cfg); +#endif /* * open DRAMC AHB & DLL register clock * close it first */ +#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); +#else + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); +#endif udelay(22); /* then open it */ +#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); +#else + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); +#endif udelay(22); } @@ -385,6 +442,13 @@ static void dramc_clock_output_en(u32 on) else clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); #endif +#ifdef CONFIG_SUN4I + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + if (on) + setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT); + else + clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT); +#endif } static const u16 tRFC_table[2][6] = { @@ -420,12 +484,25 @@ unsigned long dramc_init(struct dram_para *para) /* setup DRAM relative clock */ mctl_setup_dram_clock(para->clock); +#ifdef CONFIG_SUN5I + /* Disable any pad power save control */ + writel(0, &dram->ppwrsctl); +#endif + /* reset external DRAM */ +#ifndef CONFIG_SUN7I + mctl_ddr3_reset(); +#endif mctl_set_drive(); /* dram clock off */ dramc_clock_output_en(0); +#ifdef CONFIG_SUN4I + /* select dram controller 1 */ + writel(DRAM_CSEL_MAGIC, &dram->csel); +#endif + mctl_itm_disable(); mctl_enable_dll0(para->tpr3); @@ -482,6 +559,9 @@ unsigned long dramc_init(struct dram_para *para) mctl_ddr3_reset(); else setbits_le32(&dram->mcr, DRAM_MCR_RESET); +#else + /* dram clock on */ + dramc_clock_output_en(1); #endif udelay(1); @@ -490,6 +570,22 @@ unsigned long dramc_init(struct dram_para *para) mctl_enable_dllx(para->tpr3); +#ifdef CONFIG_SUN4I + /* set odt impedance divide ratio */ + reg_val = ((para->zq) >> 8) & 0xfffff; + reg_val |= ((para->zq) & 0xff) << 20; + reg_val |= (para->zq) & 0xf0000000; + writel(reg_val, &dram->zqcr0); +#endif + +#ifdef CONFIG_SUN4I + /* set I/O configure register */ + reg_val = 0x00cc0000; + reg_val |= (para->odt_en) & 0x3; + reg_val |= ((para->odt_en) & 0x3) << 30; + writel(reg_val, &dram->iocr); +#endif + /* set refresh period */ dramc_set_autorefresh_cycle(para->clock, para->type - 2, density); diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds index 364e35c..928b7c1 100644 --- a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds @@ -27,6 +27,11 @@ SECTIONS } . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); . = .; . = ALIGN(4); diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds index 5008028..53f0cbd 100644 --- a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds @@ -27,6 +27,7 @@ SECTIONS .text : { __start = .; + *(.vectors) arch/arm/cpu/armv7/start.o (.text) *(.text*) } > .sram @@ -38,6 +39,11 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } > .sram + + . = ALIGN(4); __image_copy_end = .; _end = .; diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c new file mode 100644 index 0000000..0b0d6a7 --- /dev/null +++ b/arch/arm/cpu/armv7/virt-dt.c @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2013 - ARM Ltd + * Author: Marc Zyngier <marc.zyngier@arm.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <stdio_dev.h> +#include <linux/ctype.h> +#include <linux/types.h> +#include <asm/global_data.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/armv7.h> +#include <asm/psci.h> + +static int fdt_psci(void *fdt) +{ +#ifdef CONFIG_ARMV7_PSCI + int nodeoff; + int tmp; + + nodeoff = fdt_path_offset(fdt, "/cpus"); + if (nodeoff < 0) { + printf("couldn't find /cpus\n"); + return nodeoff; + } + + /* add 'enable-method = "psci"' to each cpu node */ + for (tmp = fdt_first_subnode(fdt, nodeoff); + tmp >= 0; + tmp = fdt_next_subnode(fdt, tmp)) { + const struct fdt_property *prop; + int len; + + prop = fdt_get_property(fdt, tmp, "device_type", &len); + if (!prop) + continue; + if (len < 4) + continue; + if (strcmp(prop->data, "cpu")) + continue; + + fdt_setprop_string(fdt, tmp, "enable-method", "psci"); + } + + nodeoff = fdt_path_offset(fdt, "/psci"); + if (nodeoff < 0) { + nodeoff = fdt_path_offset(fdt, "/"); + if (nodeoff < 0) + return nodeoff; + + nodeoff = fdt_add_subnode(fdt, nodeoff, "psci"); + if (nodeoff < 0) + return nodeoff; + } + + tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci"); + if (tmp) + return tmp; + tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc"); + if (tmp) + return tmp; + tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", ARM_PSCI_FN_CPU_SUSPEND); + if (tmp) + return tmp; + tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF); + if (tmp) + return tmp; + tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON); + if (tmp) + return tmp; + tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE); + if (tmp) + return tmp; +#endif + return 0; +} + +int armv7_update_dt(void *fdt) +{ +#ifndef CONFIG_ARMV7_SECURE_BASE + /* secure code lives in RAM, keep it alive */ + fdt_add_mem_rsv(fdt, (unsigned long)__secure_start, + __secure_end - __secure_start); +#endif + + return fdt_psci(fdt); +} diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 2cd604f..651ca40 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -13,17 +13,10 @@ #include <asm/armv7.h> #include <asm/gic.h> #include <asm/io.h> +#include <asm/secure.h> unsigned long gic_dist_addr; -static unsigned int read_cpsr(void) -{ - unsigned int reg; - - asm volatile ("mrs %0, cpsr\n" : "=r" (reg)); - return reg; -} - static unsigned int read_id_pfr1(void) { unsigned int reg; @@ -37,25 +30,8 @@ static unsigned long get_gicd_base_address(void) #ifdef CONFIG_ARM_GIC_BASE_ADDRESS return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; #else - unsigned midr; unsigned periphbase; - /* check whether we are an Cortex-A15 or A7. - * The actual HYP switch should work with all CPUs supporting - * the virtualization extension, but we need the GIC address, - * which we know only for sure for those two CPUs. - */ - asm("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr)); - switch (midr & MIDR_PRIMARY_PART_MASK) { - case MIDR_CORTEX_A9_R0P1: - case MIDR_CORTEX_A15_R0P0: - case MIDR_CORTEX_A7_R0P0: - break; - default: - printf("nonsec: could not determine GIC address.\n"); - return -1; - } - /* get the GIC base address from the CBAR register */ asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase)); @@ -72,6 +48,18 @@ static unsigned long get_gicd_base_address(void) #endif } +static void relocate_secure_section(void) +{ +#ifdef CONFIG_ARMV7_SECURE_BASE + size_t sz = __secure_end - __secure_start; + + memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz); + flush_dcache_range(CONFIG_ARMV7_SECURE_BASE, + CONFIG_ARMV7_SECURE_BASE + sz + 1); + invalidate_icache_all(); +#endif +} + static void kick_secondary_cpus_gic(unsigned long gicdaddr) { /* kick all CPUs (except this one) by writing to GICD_SGIR */ @@ -83,35 +71,7 @@ void __weak smp_kick_all_cpus(void) kick_secondary_cpus_gic(gic_dist_addr); } -int armv7_switch_hyp(void) -{ - unsigned int reg; - - /* check whether we are in HYP mode already */ - if ((read_cpsr() & 0x1f) == 0x1a) { - debug("CPU already in HYP mode\n"); - return 0; - } - - /* check whether the CPU supports the virtualization extensions */ - reg = read_id_pfr1(); - if ((reg & CPUID_ARM_VIRT_MASK) != 1 << CPUID_ARM_VIRT_SHIFT) { - printf("HYP mode: Virtualization extensions not implemented.\n"); - return -1; - } - - /* call the HYP switching code on this CPU also */ - _switch_to_hyp(); - - if ((read_cpsr() & 0x1F) != 0x1a) { - printf("HYP mode: switch not successful.\n"); - return -1; - } - - return 0; -} - -int armv7_switch_nonsec(void) +int armv7_init_nonsec(void) { unsigned int reg; unsigned itlinesnr, i; @@ -147,11 +107,13 @@ int armv7_switch_nonsec(void) for (i = 1; i <= itlinesnr; i++) writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i); - smp_set_core_boot_addr((unsigned long)_smp_pen, -1); +#ifndef CONFIG_ARMV7_PSCI + smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1); smp_kick_all_cpus(); +#endif /* call the non-sec switching code on this CPU also */ - _nonsec_init(); - + relocate_secure_section(); + secure_ram_addr(_nonsec_init)(); return 0; } diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c index e0ed3bf..1ea086d 100644 --- a/arch/arm/cpu/armv7/zynq/ddrc.c +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -34,7 +34,7 @@ void zynq_ddrc_init(void) /* ECC is enabled when memory is in 16bit mode and it is enabled */ if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) && (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) { - puts("Memory: ECC enabled\n"); + puts("ECC enabled "); /* * Clear the first 1MB because it is not initialized from * first stage bootloader. To get ECC to work all memory has @@ -42,6 +42,6 @@ void zynq_ddrc_init(void) */ memset((void *)0, 0, 1 * 1024 * 1024); } else { - puts("Memory: ECC disabled\n"); + puts("ECC disabled "); } } diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index a7728e0..7336162 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -7,6 +7,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <config.h> + OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) ENTRY(_start) @@ -23,6 +25,34 @@ SECTIONS *(.text*) } +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) || defined(CONFIG_ARMV7_PSCI) + +#ifndef CONFIG_ARMV7_SECURE_BASE +#define CONFIG_ARMV7_SECURE_BASE +#endif + + .__secure_start : { + . = ALIGN(0x1000); + *(.__secure_start) + } + + .secure_text CONFIG_ARMV7_SECURE_BASE : + AT(ADDR(.__secure_start) + SIZEOF(.__secure_start)) + { + *(._secure.text) + } + + . = LOADADDR(.__secure_start) + + SIZEOF(.__secure_start) + + SIZEOF(.secure_text); + + __secure_end_lma = .; + .__secure_end : AT(__secure_end_lma) { + *(.__secure_end) + LONG(0x1d1071c); /* Must output something to reset LMA */ + } +#endif + . = ALIGN(4); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 4d89952..97bbfe2 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -33,11 +33,7 @@ #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a #define MT47H128M16RT25E_RATIO 0x80 -#define MT47H128M16RT25E_INVERT_CLKOUT 0x00 #define MT47H128M16RT25E_RD_DQS 0x12 -#define MT47H128M16RT25E_WR_DQS 0x00 -#define MT47H128M16RT25E_PHY_WRLVL 0x00 -#define MT47H128M16RT25E_PHY_GATELVL 0x00 #define MT47H128M16RT25E_PHY_WR_DATA 0x40 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h index e7e8c58..b2412b5 100644 --- a/arch/arm/include/asm/arch-am33xx/mem.h +++ b/arch/arm/include/asm/arch-am33xx/mem.h @@ -59,13 +59,6 @@ /* max number of GPMC regs */ #define GPMC_MAX_REG 7 -#define PISMO1_NOR 1 -#define PISMO1_NAND 2 -#define PISMO2_CS0 3 -#define PISMO2_CS1 4 -#define PISMO1_ONENAND 5 #define DBG_MPDB 6 -#define PISMO2_NAND_CS0 7 -#define PISMO2_NAND_CS1 8 #endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h new file mode 100644 index 0000000..4147811 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h @@ -0,0 +1,68 @@ +/* + * K2E: Clock management APIs + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_K2E_H +#define __ASM_ARCH_CLOCK_K2E_H + +enum ext_clk_e { + sys_clk, + alt_core_clk, + pa_clk, + ddr3_clk, + mcm_clk, + pcie_clk, + sgmii_clk, + xgmii_clk, + usb_clk, + ext_clk_count /* number of external clocks */ +}; + +extern unsigned int external_clk[ext_clk_count]; + +enum clk_e { + core_pll_clk, + pass_pll_clk, + ddr3_pll_clk, + sys_clk0_clk, + sys_clk0_1_clk, + sys_clk0_2_clk, + sys_clk0_3_clk, + sys_clk0_4_clk, + sys_clk0_6_clk, + sys_clk0_8_clk, + sys_clk0_12_clk, + sys_clk0_24_clk, + sys_clk1_clk, + sys_clk1_3_clk, + sys_clk1_4_clk, + sys_clk1_6_clk, + sys_clk1_12_clk, + sys_clk2_clk, + sys_clk3_clk +}; + +#define KS2_CLK1_6 sys_clk0_6_clk + +/* PLL identifiers */ +enum pll_type_e { + CORE_PLL, + PASS_PLL, + DDR3_PLL, +}; + +#define CORE_PLL_800 {CORE_PLL, 16, 1, 2} +#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} +#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2} +#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2} +#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} +#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} +#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} +#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} + +#endif diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h index 6a69a8d..784a0be 100644 --- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h @@ -10,10 +10,6 @@ #ifndef __ASM_ARCH_CLOCK_K2HK_H #define __ASM_ARCH_CLOCK_K2HK_H -#include <asm/arch/hardware.h> - -#ifndef __ASSEMBLY__ - enum ext_clk_e { sys_clk, alt_core_clk, @@ -56,7 +52,7 @@ enum clk_e { sys_clk3_clk }; -#define K2HK_CLK1_6 sys_clk0_6_clk +#define KS2_CLK1_6 sys_clk0_6_clk /* PLL identifiers */ enum pll_type_e { @@ -66,15 +62,6 @@ enum pll_type_e { DDR3A_PLL, DDR3B_PLL, }; -#define MAIN_PLL CORE_PLL - -/* PLL configuration data */ -struct pll_init_data { - int pll; - int pll_m; /* PLL Multiplier */ - int pll_d; /* PLL divider */ - int pll_od; /* PLL output divider */ -}; #define CORE_PLL_799 {CORE_PLL, 13, 1, 2} #define CORE_PLL_983 {CORE_PLL, 16, 1, 2} @@ -98,12 +85,4 @@ struct pll_init_data { #define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2} #define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6} -void init_plls(int num_pll, struct pll_init_data *config); -void init_pll(const struct pll_init_data *data); -unsigned long clk_get_rate(unsigned int clk); -unsigned long clk_round_rate(unsigned int clk, unsigned long hz); -int clk_set_rate(unsigned int clk, unsigned long hz); - -#endif - #endif diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h index 324501b..1513c76 100644 --- a/arch/arm/include/asm/arch-keystone/clock.h +++ b/arch/arm/include/asm/arch-keystone/clock.h @@ -10,8 +10,40 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H +#ifndef __ASSEMBLY__ + #ifdef CONFIG_SOC_K2HK #include <asm/arch/clock-k2hk.h> #endif +#ifdef CONFIG_SOC_K2E +#include <asm/arch/clock-k2e.h> +#endif + +#define MAIN_PLL CORE_PLL + +#include <asm/types.h> + +struct keystone_pll_regs { + u32 reg0; + u32 reg1; +}; + +/* PLL configuration data */ +struct pll_init_data { + int pll; + int pll_m; /* PLL Multiplier */ + int pll_d; /* PLL divider */ + int pll_od; /* PLL output divider */ +}; + +extern const struct keystone_pll_regs keystone_pll_regs[]; + +void init_plls(int num_pll, struct pll_init_data *config); +void init_pll(const struct pll_init_data *data); +unsigned long clk_get_rate(unsigned int clk); +unsigned long clk_round_rate(unsigned int clk, unsigned long hz); +int clk_set_rate(unsigned int clk, unsigned long hz); + +#endif #endif diff --git a/arch/arm/include/asm/arch-keystone/clock_defs.h b/arch/arm/include/asm/arch-keystone/clock_defs.h index b251aff..e545341 100644 --- a/arch/arm/include/asm/arch-keystone/clock_defs.h +++ b/arch/arm/include/asm/arch-keystone/clock_defs.h @@ -50,7 +50,7 @@ struct pllctl_regs { }; static struct pllctl_regs *pllctl_regs[] = { - (struct pllctl_regs *)(CLOCK_BASE + 0x100) + (struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100) }; #define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h new file mode 100644 index 0000000..4d229a2 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/ddr3.h @@ -0,0 +1,56 @@ +/* + * DDR3 + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DDR3_H_ +#define _DDR3_H_ + +#include <asm/arch/hardware.h> + +struct ddr3_phy_config { + unsigned int pllcr; + unsigned int pgcr1_mask; + unsigned int pgcr1_val; + unsigned int ptr0; + unsigned int ptr1; + unsigned int ptr2; + unsigned int ptr3; + unsigned int ptr4; + unsigned int dcr_mask; + unsigned int dcr_val; + unsigned int dtpr0; + unsigned int dtpr1; + unsigned int dtpr2; + unsigned int mr0; + unsigned int mr1; + unsigned int mr2; + unsigned int dtcr; + unsigned int pgcr2; + unsigned int zq0cr1; + unsigned int zq1cr1; + unsigned int zq2cr1; + unsigned int pir_v1; + unsigned int pir_v2; +}; + +struct ddr3_emif_config { + unsigned int sdcfg; + unsigned int sdtim1; + unsigned int sdtim2; + unsigned int sdtim3; + unsigned int sdtim4; + unsigned int zqcfg; + unsigned int sdrfc; +}; + +void ddr3_init(void); +void ddr3_reset_ddrphy(void); +void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); +void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); + +#endif diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h new file mode 100644 index 0000000..62172a4 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h @@ -0,0 +1,44 @@ +/* + * K2E: SoC definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_HARDWARE_K2E_H +#define __ASM_ARCH_HARDWARE_K2E_H + +/* PA SS Registers */ +#define KS2_PASS_BASE 0x24000000 + +/* Power and Sleep Controller (PSC) Domains */ +#define KS2_LPSC_MOD_RST 0 +#define KS2_LPSC_USB_1 1 +#define KS2_LPSC_USB 2 +#define KS2_LPSC_EMIF25_SPI 3 +#define KS2_LPSC_TSIP 4 +#define KS2_LPSC_DEBUGSS_TRC 5 +#define KS2_LPSC_TETB_TRC 6 +#define KS2_LPSC_PKTPROC 7 +#define KS2_LPSC_PA KS2_LPSC_PKTPROC +#define KS2_LPSC_SGMII 8 +#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII +#define KS2_LPSC_CRYPTO 9 +#define KS2_LPSC_PCIE 10 +#define KS2_LPSC_VUSR0 12 +#define KS2_LPSC_CHIP_SRSS 13 +#define KS2_LPSC_MSMC 14 +#define KS2_LPSC_EMIF4F_DDR3 23 +#define KS2_LPSC_PCIE_1 27 +#define KS2_LPSC_XGE 50 + +/* Chip Interrupt Controller */ +#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ +#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ + +/* Number of DSP cores */ +#define KS2_NUM_DSPS 1 + +#endif diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h index 50ce649..eb132f7 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -6,136 +6,82 @@ * * SPDX-License-Identifier: GPL-2.0+ */ + #ifndef __ASM_ARCH_HARDWARE_K2HK_H #define __ASM_ARCH_HARDWARE_K2HK_H -#define K2HK_PLL_CNTRL_BASE 0x02310000 -#define CLOCK_BASE K2HK_PLL_CNTRL_BASE -#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8) -#define KS2_RSTCTRL_KEY 0x5a69 -#define KS2_RSTCTRL_MASK 0xffff0000 -#define KS2_RSTCTRL_SWRST 0xfffe0000 - -#define K2HK_PSC_BASE 0x02350000 -#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 -#define JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) -#define K2HK_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) - -#define K2HK_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c) - -#define ARM_PLL_EN BIT(13) +#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c) -#define K2HK_SPI0_BASE 0x21000400 -#define K2HK_SPI1_BASE 0x21000600 -#define K2HK_SPI2_BASE 0x21000800 -#define K2HK_SPI_BASE K2HK_SPI0_BASE - -/* Chip configuration unlock codes and registers */ -#define KEYSTONE_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) -#define KEYSTONE_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c) -#define KEYSTONE_KICK0_MAGIC 0x83e70b13 -#define KEYSTONE_KICK1_MAGIC 0x95a4f1e0 +#define KS2_ARM_PLL_EN BIT(13) /* PA SS Registers */ -#define KS2_PASS_BASE 0x02000000 +#define KS2_PASS_BASE 0x02000000 /* PLL control registers */ -#define K2HK_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) -#define K2HK_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354) -#define K2HK_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) -#define K2HK_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) -#define K2HK_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) -#define K2HK_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) -#define K2HK_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) -#define K2HK_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) -#define K2HK_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) -#define K2HK_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) +#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) +#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) /* Power and Sleep Controller (PSC) Domains */ -#define K2HK_LPSC_MOD 0 -#define K2HK_LPSC_DUMMY1 1 -#define K2HK_LPSC_USB 2 -#define K2HK_LPSC_EMIF25_SPI 3 -#define K2HK_LPSC_TSIP 4 -#define K2HK_LPSC_DEBUGSS_TRC 5 -#define K2HK_LPSC_TETB_TRC 6 -#define K2HK_LPSC_PKTPROC 7 -#define KS2_LPSC_PA K2HK_LPSC_PKTPROC -#define K2HK_LPSC_SGMII 8 -#define KS2_LPSC_CPGMAC K2HK_LPSC_SGMII -#define K2HK_LPSC_CRYPTO 9 -#define K2HK_LPSC_PCIE 10 -#define K2HK_LPSC_SRIO 11 -#define K2HK_LPSC_VUSR0 12 -#define K2HK_LPSC_CHIP_SRSS 13 -#define K2HK_LPSC_MSMC 14 -#define K2HK_LPSC_GEM_0 15 -#define K2HK_LPSC_GEM_1 16 -#define K2HK_LPSC_GEM_2 17 -#define K2HK_LPSC_GEM_3 18 -#define K2HK_LPSC_GEM_4 19 -#define K2HK_LPSC_GEM_5 20 -#define K2HK_LPSC_GEM_6 21 -#define K2HK_LPSC_GEM_7 22 -#define K2HK_LPSC_EMIF4F_DDR3A 23 -#define K2HK_LPSC_EMIF4F_DDR3B 24 -#define K2HK_LPSC_TAC 25 -#define K2HK_LPSC_RAC 26 -#define K2HK_LPSC_RAC_1 27 -#define K2HK_LPSC_FFTC_A 28 -#define K2HK_LPSC_FFTC_B 29 -#define K2HK_LPSC_FFTC_C 30 -#define K2HK_LPSC_FFTC_D 31 -#define K2HK_LPSC_FFTC_E 32 -#define K2HK_LPSC_FFTC_F 33 -#define K2HK_LPSC_AI2 34 -#define K2HK_LPSC_TCP3D_0 35 -#define K2HK_LPSC_TCP3D_1 36 -#define K2HK_LPSC_TCP3D_2 37 -#define K2HK_LPSC_TCP3D_3 38 -#define K2HK_LPSC_VCP2X4_A 39 -#define K2HK_LPSC_CP2X4_B 40 -#define K2HK_LPSC_VCP2X4_C 41 -#define K2HK_LPSC_VCP2X4_D 42 -#define K2HK_LPSC_VCP2X4_E 43 -#define K2HK_LPSC_VCP2X4_F 44 -#define K2HK_LPSC_VCP2X4_G 45 -#define K2HK_LPSC_VCP2X4_H 46 -#define K2HK_LPSC_BCP 47 -#define K2HK_LPSC_DXB 48 -#define K2HK_LPSC_VUSR1 49 -#define K2HK_LPSC_XGE 50 -#define K2HK_LPSC_ARM_SREFLEX 51 -#define K2HK_LPSC_TETRIS 52 +#define KS2_LPSC_MOD 0 +#define KS2_LPSC_DUMMY1 1 +#define KS2_LPSC_USB 2 +#define KS2_LPSC_EMIF25_SPI 3 +#define KS2_LPSC_TSIP 4 +#define KS2_LPSC_DEBUGSS_TRC 5 +#define KS2_LPSC_TETB_TRC 6 +#define KS2_LPSC_PKTPROC 7 +#define KS2_LPSC_PA KS2_LPSC_PKTPROC +#define KS2_LPSC_SGMII 8 +#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII +#define KS2_LPSC_CRYPTO 9 +#define KS2_LPSC_PCIE 10 +#define KS2_LPSC_SRIO 11 +#define KS2_LPSC_VUSR0 12 +#define KS2_LPSC_CHIP_SRSS 13 +#define KS2_LPSC_MSMC 14 +#define KS2_LPSC_GEM_1 16 +#define KS2_LPSC_GEM_2 17 +#define KS2_LPSC_GEM_3 18 +#define KS2_LPSC_GEM_4 19 +#define KS2_LPSC_GEM_5 20 +#define KS2_LPSC_GEM_6 21 +#define KS2_LPSC_GEM_7 22 +#define KS2_LPSC_EMIF4F_DDR3A 23 +#define KS2_LPSC_EMIF4F_DDR3B 24 +#define KS2_LPSC_TAC 25 +#define KS2_LPSC_RAC 26 +#define KS2_LPSC_RAC_1 27 +#define KS2_LPSC_FFTC_A 28 +#define KS2_LPSC_FFTC_B 29 +#define KS2_LPSC_FFTC_C 30 +#define KS2_LPSC_FFTC_D 31 +#define KS2_LPSC_FFTC_E 32 +#define KS2_LPSC_FFTC_F 33 +#define KS2_LPSC_AI2 34 +#define KS2_LPSC_TCP3D_0 35 +#define KS2_LPSC_TCP3D_1 36 +#define KS2_LPSC_TCP3D_2 37 +#define KS2_LPSC_TCP3D_3 38 +#define KS2_LPSC_VCP2X4_A 39 +#define KS2_LPSC_CP2X4_B 40 +#define KS2_LPSC_VCP2X4_C 41 +#define KS2_LPSC_VCP2X4_D 42 +#define KS2_LPSC_VCP2X4_E 43 +#define KS2_LPSC_VCP2X4_F 44 +#define KS2_LPSC_VCP2X4_G 45 +#define KS2_LPSC_VCP2X4_H 46 +#define KS2_LPSC_BCP 47 +#define KS2_LPSC_DXB 48 +#define KS2_LPSC_VUSR1 49 +#define KS2_LPSC_XGE 50 +#define KS2_LPSC_ARM_SREFLEX 51 -/* DDR3A definitions */ -#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000 -#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000 -#define K2HK_DDR3A_DDRPHYC 0x02329000 /* DDR3B definitions */ -#define K2HK_DDR3B_EMIF_CTRL_BASE 0x21020000 -#define K2HK_DDR3B_EMIF_DATA_BASE 0x60000000 -#define K2HK_DDR3B_DDRPHYC 0x02328000 - -/* Queue manager */ -#define DEVICE_QM_MANAGER_BASE 0x02a02000 -#define DEVICE_QM_DESC_SETUP_BASE 0x02a03000 -#define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a80000 -#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 -#define DEVICE_QM_QUEUE_STATUS_BASE 0x02a40000 -#define DEVICE_QM_NUM_LINKRAMS 2 -#define DEVICE_QM_NUM_MEMREGIONS 20 - -#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000 -#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400 -#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800 -#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000 - -#define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24 -#define DEVICE_PA_CDMA_RX_NUM_FLOWS 32 -#define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9 +#define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000 +#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000 +#define KS2_DDR3B_DDRPHYC 0x02328000 -/* MSMC control */ -#define K2HK_MSMC_CTRL_BASE 0x0bc00000 +/* Number of DSP cores */ +#define KS2_NUM_DSPS 8 #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index ffdecbf..ddeb06e 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -22,42 +22,6 @@ typedef volatile unsigned int dv_reg; typedef volatile unsigned int *dv_reg_p; -struct ddr3_phy_config { - unsigned int pllcr; - unsigned int pgcr1_mask; - unsigned int pgcr1_val; - unsigned int ptr0; - unsigned int ptr1; - unsigned int ptr2; - unsigned int ptr3; - unsigned int ptr4; - unsigned int dcr_mask; - unsigned int dcr_val; - unsigned int dtpr0; - unsigned int dtpr1; - unsigned int dtpr2; - unsigned int mr0; - unsigned int mr1; - unsigned int mr2; - unsigned int dtcr; - unsigned int pgcr2; - unsigned int zq0cr1; - unsigned int zq1cr1; - unsigned int zq2cr1; - unsigned int pir_v1; - unsigned int pir_v2; -}; - -struct ddr3_emif_config { - unsigned int sdcfg; - unsigned int sdtim1; - unsigned int sdtim2; - unsigned int sdtim3; - unsigned int sdtim4; - unsigned int zqcfg; - unsigned int sdrfc; -}; - #endif #define BIT(x) (1 << (x)) @@ -105,6 +69,11 @@ struct ddr3_emif_config { #define NOSRA_MASK 0x08000000 #define ECC_MASK 0x00000001 +/* DDR3 definitions */ +#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000 +#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000 +#define KS2_DDR3A_DDRPHYC 0x02329000 + #define KS2_DDR3_MIDR_OFFSET 0x00 #define KS2_DDR3_STATUS_OFFSET 0x04 #define KS2_DDR3_SDCFG_OFFSET 0x08 @@ -116,39 +85,103 @@ struct ddr3_emif_config { #define KS2_DDR3_PMCTL_OFFSET 0x38 #define KS2_DDR3_ZQCFG_OFFSET 0xC8 +#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000 + #define KS2_UART0_BASE 0x02530c00 #define KS2_UART1_BASE 0x02531000 +/* Boot Config */ +#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 +#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) +#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) + +/* PSC */ +#define KS2_PSC_BASE 0x02350000 +#define KS2_LPSC_GEM_0 15 +#define KS2_LPSC_TETRIS 52 +#define KS2_TETRIS_PWR_DOMAIN 31 + +/* Chip configuration unlock codes and registers */ +#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) +#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c) +#define KS2_KICK0_MAGIC 0x83e70b13 +#define KS2_KICK1_MAGIC 0x95a4f1e0 + +/* PLL control registers */ +#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) +#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354) +#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) +#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) +#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) +#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) +#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) +#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) + +#define KS2_PLL_CNTRL_BASE 0x02310000 +#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE +#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4) +#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8) +#define KS2_RSTCTRL_KEY 0x5a69 +#define KS2_RSTCTRL_MASK 0xffff0000 +#define KS2_RSTCTRL_SWRST 0xfffe0000 + +/* SPI */ +#define KS2_SPI0_BASE 0x21000400 +#define KS2_SPI1_BASE 0x21000600 +#define KS2_SPI2_BASE 0x21000800 +#define KS2_SPI_BASE KS2_SPI0_BASE + /* AEMIF */ #define KS2_AEMIF_CNTRL_BASE 0x21000a00 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE +/* Flag from ks2_debug options to check if DSPs need to stay ON */ +#define DBG_LEAVE_DSPS_ON 0x1 + +/* Queue manager */ +#define KS2_QM_MANAGER_BASE 0x02a02000 +#define KS2_QM_DESC_SETUP_BASE 0x02a03000 +#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000 +#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 +#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000 + +/* MSMC control */ +#define KS2_MSMC_CTRL_BASE 0x0bc00000 + #ifdef CONFIG_SOC_K2HK #include <asm/arch/hardware-k2hk.h> #endif +#ifdef CONFIG_SOC_K2E +#include <asm/arch/hardware-k2e.h> +#endif + #ifndef __ASSEMBLY__ static inline int cpu_is_k2hk(void) { - unsigned int jtag_id = __raw_readl(JTAG_ID_REG); + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); unsigned int part_no = (jtag_id >> 12) & 0xffff; return (part_no == 0xb981) ? 1 : 0; } +static inline int cpu_is_k2e(void) +{ + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); + unsigned int part_no = (jtag_id >> 12) & 0xffff; + + return (part_no == 0xb9a6) ? 1 : 0; +} + static inline int cpu_revision(void) { - unsigned int jtag_id = __raw_readl(JTAG_ID_REG); + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); unsigned int rev = (jtag_id >> 28) & 0xf; return rev; } -void share_all_segments(int priv_id); int cpu_to_bus(u32 *ptr, u32 length); -void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); -void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); -void init_ddr3(void); void sdelay(unsigned long); #endif diff --git a/arch/arm/include/asm/arch-keystone/mon.h b/arch/arm/include/asm/arch-keystone/mon.h new file mode 100644 index 0000000..33a2876 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/mon.h @@ -0,0 +1,15 @@ +/* + * K2HK: secure kernel command header file + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MON_H_ +#define _MON_H_ + +int mon_power_off(int core_id); + +#endif diff --git a/arch/arm/include/asm/arch-keystone/msmc.h b/arch/arm/include/asm/arch-keystone/msmc.h new file mode 100644 index 0000000..c320db5 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/msmc.h @@ -0,0 +1,17 @@ +/* + * MSMC controller + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MSMC_H_ +#define _MSMC_H_ + +#include <asm/arch/hardware.h> + +void msmc_share_all_segments(int priv_id); + +#endif diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h index 7a688e4..f7bfa0e 100644 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ b/arch/arm/include/asm/arch-kirkwood/config.h @@ -129,7 +129,8 @@ */ #ifdef CONFIG_CMD_I2C #ifndef CONFIG_SYS_I2C_SOFT -#define CONFIG_I2C_MVTWSI +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI #endif #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h index bc207f5..3ea51d7 100644 --- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h +++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h @@ -39,6 +39,7 @@ #define KW_EGIGA0_BASE (KW_REGISTER(0x72000)) #define KW_EGIGA1_BASE (KW_REGISTER(0x76000)) #define KW_SATA_BASE (KW_REGISTER(0x80000)) +#define KW_SDIO_BASE (KW_REGISTER(0x90000)) /* Kirkwood Sata controller has two ports */ #define KW_SATA_PORT0_OFFSET 0x2000 diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 4d06ef8..53cc2b0 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -98,7 +98,6 @@ struct ctrl_id { #define DEBUG_BASE 0x08000000 /* debug board */ #define NAND_BASE 0x30000000 /* NAND addr */ /* (actual size small port) */ -#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ #define ONENAND_MAP 0x20000000 /* OneNand addr */ /* (actual size small port) */ /* SMS */ diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index d2dfb1e..0b78c1c 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -427,20 +427,7 @@ enum { /* max number of GPMC regs */ #define GPMC_MAX_REG 7 -#define PISMO1_NOR 1 -#define PISMO1_NAND 2 -#define PISMO2_CS0 3 -#define PISMO2_CS1 4 -#define PISMO1_ONENAND 5 #define DBG_MPDB 6 -#define PISMO2_NAND_CS0 7 -#define PISMO2_NAND_CS1 8 - -/* make it readable for the gpmc_init */ -#define PISMO1_NOR_BASE FLASH_BASE -#define PISMO1_NAND_BASE NAND_BASE -#define PISMO2_CS0_BASE PISMO2_MAP1 -#define PISMO1_ONEN_BASE ONENAND_MAP #define DBG_MPDB_BASE DEBUG_BASE #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-rmobile/gpio.h b/arch/arm/include/asm/arch-rmobile/gpio.h index 560e9f4..d25ea61 100644 --- a/arch/arm/include/asm/arch-rmobile/gpio.h +++ b/arch/arm/include/asm/arch-rmobile/gpio.h @@ -13,6 +13,9 @@ void r8a7790_pinmux_init(void); #elif defined(CONFIG_R8A7791) #include "r8a7791-gpio.h" void r8a7791_pinmux_init(void); +#elif defined(CONFIG_R8A7794) +#include "r8a7794-gpio.h" +void r8a7794_pinmux_init(void); #endif #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h new file mode 100644 index 0000000..a45a67c --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h @@ -0,0 +1,176 @@ +#ifndef __ASM_R8A7794_H__ +#define __ASM_R8A7794_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU + */ +enum { + GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, + GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, + GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, + GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, + GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, + GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, + GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, + GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, + + GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, + GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, + GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, + GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, + GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, + GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, + GPIO_GP_1_24, GPIO_GP_1_25, + + GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, + GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, + GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, + GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, + GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, + GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, + GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, + GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31, + + GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, + GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, + GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, + GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, + GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, + GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, + GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, + GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, + + GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, + GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, + GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, + GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, + GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, + GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, + GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, + GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, + + GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, + GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, + GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, + GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, + GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, + GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, + GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, + + GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, + GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, + GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11, + GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15, + GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19, + GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23, + GPIO_GP_6_24, GPIO_GP_6_25, + + GPIO_FN_A2, GPIO_FN_WE0_N, GPIO_FN_WE1_N, GPIO_FN_DACK0, + GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN, + GPIO_FN_USB1_OVC, GPIO_FN_SD0_CLK, GPIO_FN_SD0_CMD, + GPIO_FN_SD0_DATA0, GPIO_FN_SD0_DATA1, GPIO_FN_SD0_DATA2, + GPIO_FN_SD0_DATA3, GPIO_FN_SD0_CD, GPIO_FN_SD0_WP, + GPIO_FN_SD1_CLK, GPIO_FN_SD1_CMD, GPIO_FN_SD1_DATA0, + GPIO_FN_SD1_DATA1, GPIO_FN_SD1_DATA2, GPIO_FN_SD1_DATA3, + + /* + * From IPSR0 to IPSR5 have been removed because they does not use. + */ + + /* IPSR6 */ + GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE, GPIO_FN_CC50_STATE28, + GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, + GPIO_FN_CC50_STATE29, GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, + GPIO_FN_CC50_STATE30, GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, + GPIO_FN_CC50_STATE31, GPIO_FN_VI0_CLK, GPIO_FN_AVB_RX_CLK, + GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_AVB_RX_DV, GPIO_FN_VI0_DATA1_VI0_B1, + GPIO_FN_AVB_RXD0, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_AVB_RXD1, + GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_AVB_RXD2, GPIO_FN_VI0_DATA4_VI0_B4, + GPIO_FN_AVB_RXD3, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_AVB_RXD4, + GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA7_VI0_B7, + GPIO_FN_AVB_RXD6, GPIO_FN_VI0_CLKENB, GPIO_FN_I2C3_SCL, + GPIO_FN_SCIFA5_RXD_C, GPIO_FN_IETX_C, GPIO_FN_AVB_RXD7, + GPIO_FN_VI0_FIELD, GPIO_FN_I2C3_SDA, GPIO_FN_SCIFA5_TXD_C, + GPIO_FN_IECLK_C, GPIO_FN_AVB_RX_ER, GPIO_FN_VI0_HSYNC_N, + GPIO_FN_SCIF0_RXD_B, GPIO_FN_I2C0_SCL_C, GPIO_FN_IERX_C, + GPIO_FN_AVB_COL, GPIO_FN_VI0_VSYNC_N, GPIO_FN_SCIF0_TXD_B, + GPIO_FN_I2C0_SDA_C, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_AVB_TX_EN, + GPIO_FN_ETH_MDIO, GPIO_FN_VI0_G0, GPIO_FN_MSIOF2_RXD_B, + GPIO_FN_IIC0_SCL_D, GPIO_FN_AVB_TX_CLK, GPIO_FN_ADIDATA, GPIO_FN_AD_DI, + + /* IPSR7 */ + GPIO_FN_ETH_CRS_DV, GPIO_FN_VI0_G1, GPIO_FN_MSIOF2_TXD_B, + GPIO_FN_IIC0_SDA_D, GPIO_FN_AVB_TXD0, GPIO_FN_ADICS_SAMP, GPIO_FN_AD_DO, + GPIO_FN_ETH_RX_ER, GPIO_FN_VI0_G2, GPIO_FN_MSIOF2_SCK_B, + GPIO_FN_CAN0_RX_B, GPIO_FN_AVB_TXD1, GPIO_FN_ADICLK, GPIO_FN_AD_CLK, + GPIO_FN_ETH_RXD0, GPIO_FN_VI0_G3, GPIO_FN_MSIOF2_SYNC_B, + GPIO_FN_CAN0_TX_B, GPIO_FN_AVB_TXD2, GPIO_FN_ADICHS0, GPIO_FN_AD_NCS_N, + GPIO_FN_ETH_RXD1, GPIO_FN_VI0_G4, GPIO_FN_MSIOF2_SS1_B, + GPIO_FN_SCIF4_RXD_D, GPIO_FN_AVB_TXD3, GPIO_FN_ADICHS1, + GPIO_FN_ETH_LINK, GPIO_FN_VI0_G5, GPIO_FN_MSIOF2_SS2_B, + GPIO_FN_SCIF4_TXD_D, GPIO_FN_AVB_TXD4, GPIO_FN_ADICHS2, + GPIO_FN_ETH_REFCLK, GPIO_FN_VI0_G6, GPIO_FN_SCIF2_SCK_C, + GPIO_FN_AVB_TXD5, GPIO_FN_SSI_SCK5_B, GPIO_FN_ETH_TXD1, GPIO_FN_VI0_G7, + GPIO_FN_SCIF2_RXD_C, GPIO_FN_IIC1_SCL_D, GPIO_FN_AVB_TXD6, + GPIO_FN_SSI_WS5_B, GPIO_FN_ETH_TX_EN, GPIO_FN_VI0_R0, + GPIO_FN_SCIF2_TXD_C, GPIO_FN_IIC1_SDA_D, GPIO_FN_AVB_TXD7, + GPIO_FN_SSI_SDATA5_B, GPIO_FN_ETH_MAGIC, GPIO_FN_VI0_R1, + GPIO_FN_SCIF3_SCK_B, GPIO_FN_AVB_TX_ER, GPIO_FN_SSI_SCK6_B, + GPIO_FN_ETH_TXD0, GPIO_FN_VI0_R2, GPIO_FN_SCIF3_RXD_B, + GPIO_FN_I2C4_SCL_E, GPIO_FN_AVB_GTX_CLK, GPIO_FN_SSI_WS6_B, + GPIO_FN_DREQ0_N, GPIO_FN_SCIFB1_RXD, + + /* IPSR8 */ + GPIO_FN_ETH_MDC, GPIO_FN_VI0_R3, GPIO_FN_SCIF3_TXD_B, + GPIO_FN_I2C4_SDA_E, GPIO_FN_AVB_MDC, GPIO_FN_SSI_SDATA6_B, + GPIO_FN_HSCIF0_HRX, GPIO_FN_VI0_R4, GPIO_FN_I2C1_SCL_C, + GPIO_FN_AUDIO_CLKA_B, GPIO_FN_AVB_MDIO, GPIO_FN_SSI_SCK78_B, + GPIO_FN_HSCIF0_HTX, GPIO_FN_VI0_R5, GPIO_FN_I2C1_SDA_C, + GPIO_FN_AUDIO_CLKB_B, GPIO_FN_AVB_LINK, GPIO_FN_SSI_WS78_B, + GPIO_FN_HSCIF0_HCTS_N, GPIO_FN_VI0_R6, GPIO_FN_SCIF0_RXD_D, + GPIO_FN_I2C0_SCL_E, GPIO_FN_AVB_MAGIC, GPIO_FN_SSI_SDATA7_B, + GPIO_FN_HSCIF0_HRTS_N, GPIO_FN_VI0_R7, GPIO_FN_SCIF0_TXD_D, + GPIO_FN_I2C0_SDA_E, GPIO_FN_AVB_PHY_INT, GPIO_FN_SSI_SDATA8_B, + GPIO_FN_HSCIF0_HSCK, GPIO_FN_SCIF_CLK_B, GPIO_FN_AVB_CRS, + GPIO_FN_AUDIO_CLKC_B, GPIO_FN_I2C0_SCL, GPIO_FN_SCIF0_RXD_C, + GPIO_FN_PWM5, GPIO_FN_TCLK1_B, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN1_RX_D, + GPIO_FN_TPUTO0_B, GPIO_FN_I2C0_SDA, GPIO_FN_SCIF0_TXD_C, GPIO_FN_TPUTO0, + GPIO_FN_CAN_CLK, GPIO_FN_DVC_MUTE, GPIO_FN_CAN1_TX_D, GPIO_FN_I2C1_SCL, + GPIO_FN_SCIF4_RXD, GPIO_FN_PWM5_B, GPIO_FN_DU1_DR0, GPIO_FN_RIF1_SYNC_B, + GPIO_FN_TS_SDATA_D, GPIO_FN_TPUTO1_B, GPIO_FN_I2C1_SDA, + GPIO_FN_SCIF4_TXD, GPIO_FN_IRQ5, GPIO_FN_DU1_DR1, GPIO_FN_RIF1_CLK_B, + GPIO_FN_TS_SCK_D, GPIO_FN_BPFCLK_C, GPIO_FN_MSIOF0_RXD, + GPIO_FN_SCIF5_RXD, GPIO_FN_I2C2_SCL_C, GPIO_FN_DU1_DR2, + GPIO_FN_RIF1_D0_B, GPIO_FN_TS_SDEN_D, GPIO_FN_FMCLK_C, GPIO_FN_RDS_CLK, + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + /* IPSR11 */ + GPIO_FN_SSI_WS5, GPIO_FN_SCIFA3_RXD, GPIO_FN_I2C3_SCL_C, + GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5, + GPIO_FN_SCIFA3_TXD, GPIO_FN_I2C3_SDA_C, GPIO_FN_DU1_DOTCLKOUT1, + GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SCK6, GPIO_FN_SCIFA1_SCK_B, + GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_SSI_WS6, + GPIO_FN_SCIFA1_RXD_B, GPIO_FN_I2C4_SCL_C, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, + GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_SDATA6, GPIO_FN_SCIFA1_TXD_B, + GPIO_FN_I2C4_SDA_C, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, + GPIO_FN_CAN_DEBUGOUT15, GPIO_FN_SSI_SCK78, GPIO_FN_SCIFA2_SCK_B, + GPIO_FN_IIC0_SDA_C, GPIO_FN_DU1_DISP, GPIO_FN_SSI_WS78, + GPIO_FN_SCIFA2_RXD_B, GPIO_FN_IIC0_SCL_C, GPIO_FN_DU1_CDE, + GPIO_FN_SSI_SDATA7, GPIO_FN_SCIFA2_TXD_B, GPIO_FN_IRQ8, + GPIO_FN_AUDIO_CLKA_D, GPIO_FN_CAN_CLK_D, GPIO_FN_PCMOE_N, + GPIO_FN_SSI_SCK0129, GPIO_FN_MSIOF1_RXD_B, GPIO_FN_SCIF5_RXD_D, + GPIO_FN_ADIDATA_B, GPIO_FN_AD_DI_B, GPIO_FN_PCMWE_N, GPIO_FN_SSI_WS0129, + GPIO_FN_MSIOF1_TXD_B, GPIO_FN_SCIF5_TXD_D, GPIO_FN_ADICS_SAMP_B, + GPIO_FN_AD_DO_B, GPIO_FN_SSI_SDATA0, GPIO_FN_MSIOF1_SCK_B, + GPIO_FN_PWM0_B, GPIO_FN_ADICLK_B, GPIO_FN_AD_CLK_B, + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ +}; + +#endif /* __ASM_R8A7794_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794.h b/arch/arm/include/asm/arch-rmobile/r8a7794.h new file mode 100644 index 0000000..94276dd --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7794.h @@ -0,0 +1,14 @@ +/* + * arch/arm/include/asm/arch-rmobile/r8a7794.h + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_R8A7794_H +#define __ASM_ARCH_R8A7794_H + +#include "rcar-base.h" + +#endif /* __ASM_ARCH_R8A7794_H */ diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h index 41240f3..027e9b1 100644 --- a/arch/arm/include/asm/arch-rmobile/rcar-base.h +++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h @@ -10,7 +10,7 @@ #define __ASM_ARCH_RCAR_BASE_H /* - * R-Car (R8A7790/R8A7791) I/O Addresses + * R-Car (R8A7790/R8A7791/R8A7794) I/O Addresses */ #define RWDT_BASE 0xE6020000 #define SWDT_BASE 0xE6030000 @@ -116,7 +116,7 @@ #define SYS_AXI_SAT1_BASE 0xFF8009C0 #define SYS_AXI_SDM0_BASE 0xFF800A00 #define SYS_AXI_SDM1_BASE 0xFF800A40 -#define SYS_AXI_TRAB_BASE 0xFF800B00 +#define SYS_AXI_TRAB_BASE 0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */ #define SYS_AXI_UDM0_BASE 0xFF800B80 #define SYS_AXI_UDM1_BASE 0xFF800BC0 diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h index ebddd7a..2cc38e1 100644 --- a/arch/arm/include/asm/arch-rmobile/rmobile.h +++ b/arch/arm/include/asm/arch-rmobile/rmobile.h @@ -10,6 +10,8 @@ #include <asm/arch/r8a7790.h> #elif defined(CONFIG_R8A7791) #include <asm/arch/r8a7791.h> +#elif defined(CONFIG_R8A7794) +#include <asm/arch/r8a7794.h> #else #error "SOC Name not defined" #endif diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h index 01fe0f2..ce4186f 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h @@ -139,9 +139,9 @@ static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; } -static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void) +static inline struct s3c24x0_sdi *s3c24x0_get_base_sdi(void) { - return (struct s3c2410_sdi *)S3C2410_SDI_BASE; + return (struct s3c24x0_sdi *)S3C2410_SDI_BASE; } #endif /*__S3C2410_H__*/ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h index 15a7cb4..3f44bdc 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h @@ -137,9 +137,9 @@ static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; } -static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void) +static inline struct s3c24x0_sdi *s3c24x0_get_base_sdi(void) { - return (struct s3c2440_sdi *)S3C2440_SDI_BASE; + return (struct s3c24x0_sdi *)S3C2440_SDI_BASE; } #endif /*__S3C2440_H__*/ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h index 86d720c..ed9df34 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h @@ -675,7 +675,7 @@ struct s3c2400_mmc { /* SD INTERFACE (see S3C2410 manual chapter 19) */ -struct s3c2410_sdi { +struct s3c24x0_sdi { u32 sdicon; u32 sdipre; u32 sdicarg; @@ -691,14 +691,19 @@ struct s3c2410_sdi { u32 sdidcnt; u32 sdidsta; u32 sdifsta; -#ifdef __BIG_ENDIAN - u8 res[3]; - u8 sdidat; +#ifdef CONFIG_S3C2410 + u32 sdidat; + u32 sdiimsk; #else - u8 sdidat; - u8 res[3]; -#endif u32 sdiimsk; + u32 sdidat; +#endif }; +#ifdef CONFIG_CMD_MMC +#include <mmc.h> +int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *), + int (*getwp)(struct mmc *)); +#endif + #endif /*__S3C24X0_H__*/ diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 892479c..f7f3d8c 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -143,5 +143,7 @@ int sunxi_gpio_set_cfgpin(u32 pin, u32 val); int sunxi_gpio_get_cfgpin(u32 pin); int sunxi_gpio_set_drv(u32 pin, u32 val); int sunxi_gpio_set_pull(u32 pin, u32 val); +int sunxi_name_to_gpio(const char *name); +#define name_to_gpio(name) sunxi_name_to_gpio(name) #endif /* _SUNXI_GPIO_H */ diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h new file mode 100644 index 0000000..dc5406b --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -0,0 +1,15 @@ +/* + * Copyright 2014 - Hans de Goede <hdegoede@redhat.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _SUNXI_I2C_H_ +#define _SUNXI_I2C_H_ + +#include <asm/arch/cpu.h> + +#define CONFIG_I2C_MVTWSI_BASE SUNXI_TWI0_BASE +/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ +#define CONFIG_SYS_TCLK 24000000 + +#endif diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h index 6aacfd7..58e14fd 100644 --- a/arch/arm/include/asm/arch-sunxi/timer.h +++ b/arch/arm/include/asm/arch-sunxi/timer.h @@ -11,6 +11,11 @@ #ifndef _SUNXI_TIMER_H_ #define _SUNXI_TIMER_H_ +#define WDT_CTRL_RESTART (0x1 << 0) +#define WDT_CTRL_KEY (0x0a57 << 1) +#define WDT_MODE_EN (0x1 << 0) +#define WDT_MODE_RESET_EN (0x1 << 1) + #ifndef __ASSEMBLY__ #include <linux/types.h> diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index 395444e..323f282 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -78,13 +78,18 @@ void v7_outer_cache_inval_range(u32 start, u32 end); #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) -int armv7_switch_nonsec(void); -int armv7_switch_hyp(void); +int armv7_init_nonsec(void); +int armv7_update_dt(void *fdt); /* defined in assembly file */ unsigned int _nonsec_init(void); +void _do_nonsec_entry(void *target_pc, unsigned long r0, + unsigned long r1, unsigned long r2); void _smp_pen(void); -void _switch_to_hyp(void); + +extern char __secure_start[]; +extern char __secure_end[]; + #endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */ #endif /* ! __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index d3433da..5f2a5f4 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -7,7 +7,9 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#ifdef __aarch64__ #define CONFIG_SYS_GENERIC_GLOBAL_DATA +#endif #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index d1344ee..1838234 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -595,6 +595,14 @@ static inline u32 omap_revision(void) return *omap_si_rev; } +#define OMAP44xx 0x44000000 + +static inline u8 is_omap44xx(void) +{ + extern u32 *const omap_si_rev; + return (*omap_si_rev & 0xFF000000) == OMAP44xx; +}; + #define OMAP54xx 0x54000000 static inline u8 is_omap54xx(void) diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h index 21aef58..71df5a9 100644 --- a/arch/arm/include/asm/proc-armv/ptrace.h +++ b/arch/arm/include/asm/proc-armv/ptrace.h @@ -38,12 +38,14 @@ struct pt_regs { #define IRQ_MODE 0x12 #define SVC_MODE 0x13 #define ABT_MODE 0x17 +#define HYP_MODE 0x1a #define UND_MODE 0x1b #define SYSTEM_MODE 0x1f #define MODE_MASK 0x1f #define T_BIT 0x20 #define F_BIT 0x40 #define I_BIT 0x80 +#define A_BIT 0x100 #define CC_V_BIT (1 << 28) #define CC_C_BIT (1 << 29) #define CC_Z_BIT (1 << 30) diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h new file mode 100644 index 0000000..704b4b0 --- /dev/null +++ b/arch/arm/include/asm/psci.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2013 - ARM Ltd + * Author: Marc Zyngier <marc.zyngier@arm.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __ARM_PSCI_H__ +#define __ARM_PSCI_H__ + +/* PSCI interface */ +#define ARM_PSCI_FN_BASE 0x95c1ba5e +#define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n)) + +#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0) +#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1) +#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2) +#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3) + +#define ARM_PSCI_RET_SUCCESS 0 +#define ARM_PSCI_RET_NI (-1) +#define ARM_PSCI_RET_INVAL (-2) +#define ARM_PSCI_RET_DENIED (-3) + +#endif /* __ARM_PSCI_H__ */ diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h new file mode 100644 index 0000000..effdb18 --- /dev/null +++ b/arch/arm/include/asm/secure.h @@ -0,0 +1,26 @@ +#ifndef __ASM_SECURE_H +#define __ASM_SECURE_H + +#include <config.h> + +#ifdef CONFIG_ARMV7_SECURE_BASE +/* + * Warning, horror ahead. + * + * The target code lives in our "secure ram", but u-boot doesn't know + * that, and has blindly added reloc_off to every relocation + * entry. Gahh. Do the opposite conversion. This hack also prevents + * GCC from generating code veeners, which u-boot doesn't relocate at + * all... + */ +#define secure_ram_addr(_fn) ({ \ + DECLARE_GLOBAL_DATA_PTR; \ + void *__fn = _fn; \ + typeof(_fn) *__tmp = (__fn - gd->reloc_off); \ + __tmp; \ + }) +#else +#define secure_ram_addr(_fn) (_fn) +#endif + +#endif diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index e40691d..d4f1578 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -17,13 +17,14 @@ #include <common.h> #include <fdt_support.h> +#include <asm/armv7.h> DECLARE_GLOBAL_DATA_PTR; -int arch_fixup_memory_node(void *blob) +int arch_fixup_fdt(void *blob) { bd_t *bd = gd->bd; - int bank; + int bank, ret; u64 start[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; @@ -32,5 +33,12 @@ int arch_fixup_memory_node(void *blob) size[bank] = bd->bi_dram[bank].size; } - return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); + ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) + if (ret) + return ret; + + ret = armv7_update_dt(blob); +#endif + return ret; } diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 47ee070..178e8fb 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -20,6 +20,7 @@ #include <libfdt.h> #include <fdt_support.h> #include <asm/bootm.h> +#include <asm/secure.h> #include <linux/compiler.h> #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) @@ -184,27 +185,17 @@ static void setup_end_tag(bd_t *bd) __weak void setup_board_tags(struct tag **in_params) {} +#ifdef CONFIG_ARM64 static void do_nonsec_virt_switch(void) { -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) - if (armv7_switch_nonsec() == 0) -#ifdef CONFIG_ARMV7_VIRT - if (armv7_switch_hyp() == 0) - debug("entered HYP mode\n"); -#else - debug("entered non-secure state\n"); -#endif -#endif - -#ifdef CONFIG_ARM64 smp_kick_all_cpus(); flush_dcache_all(); /* flush cache before swtiching to EL2 */ armv8_switch_to_el2(); #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 armv8_switch_to_el1(); #endif -#endif } +#endif /* Subcommand: PREP */ static void boot_prep_linux(bootm_headers_t *images) @@ -242,7 +233,6 @@ static void boot_prep_linux(bootm_headers_t *images) printf("FDT and ATAGS support not compiled in - hanging\n"); hang(); } - do_nonsec_virt_switch(); } /* Subcommand: GO */ @@ -260,8 +250,10 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) announce_and_cleanup(fake); - if (!fake) + if (!fake) { + do_nonsec_virt_switch(); kernel_entry(images->ft_addr); + } #else unsigned long machid = gd->bd->bi_arch_number; char *s; @@ -287,9 +279,16 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) else r2 = gd->bd->bi_boot_params; - if (!fake) + if (!fake) { +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) + armv7_init_nonsec(); + secure_ram_addr(_do_nonsec_entry)(kernel_entry, + 0, machid, r2); +#else kernel_entry(0, machid, r2); #endif + } +#endif } /* Main Entry point for arm bootm implementation @@ -360,7 +359,7 @@ void boot_prep_vxworks(bootm_headers_t *images) if (images->ft_addr) { off = fdt_path_offset(images->ft_addr, "/memory"); if (off < 0) { - if (arch_fixup_memory_node(images->ft_addr)) + if (arch_fixup_fdt(images->ft_addr)) puts("## WARNING: fixup memory failed!\n"); } } diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index dfc2de9..29cdad0 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -67,10 +67,22 @@ ENTRY(_main) ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) #endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ + mov r2, sp sub sp, sp, #GD_SIZE /* allocate one GD above SP */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ mov r9, sp /* GD is above SP */ + mov r1, sp mov r0, #0 +clr_gd: + cmp r1, r2 /* while not at end of GD */ + strlo r0, [r1] /* clear 32-bit GD word */ + addlo r1, r1, #4 /* move to next */ + blo clr_gd +#if defined(CONFIG_SYS_MALLOC_F_LEN) && !defined(CONFIG_SPL_BUILD) + sub sp, sp, #CONFIG_SYS_MALLOC_F_LEN + str sp, [r9, #GD_MALLOC_BASE] +#endif + /* mov r0, #0 not needed due to above code */ bl board_init_f #if ! defined(CONFIG_SPL_BUILD) diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index 758b013..f6b7c03 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -103,7 +103,7 @@ void show_regs (struct pt_regs *regs) "UK12_26", "UK13_26", "UK14_26", "UK15_26", "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32", "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK8_32", "UK9_32", "HYP_32", "UND_32", "UK12_32", "UK13_32", "UK14_32", "SYS_32", }; diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c index 5b30bcb..a1205c3 100644 --- a/arch/arm/lib/sections.c +++ b/arch/arm/lib/sections.c @@ -25,4 +25,6 @@ char __image_copy_start[0] __attribute__((section(".__image_copy_start"))); char __image_copy_end[0] __attribute__((section(".__image_copy_end"))); char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start"))); char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end"))); +char __secure_start[0] __attribute__((section(".__secure_start"))); +char __secure_end[0] __attribute__((section(".__secure_end"))); char _end[0] __attribute__((section(".__end"))); diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig new file mode 100644 index 0000000..46337ae --- /dev/null +++ b/arch/avr32/Kconfig @@ -0,0 +1,51 @@ +menu "AVR32 architecture" + depends on AVR32 + +config SYS_ARCH + string + default "avr32" + +choice + prompt "Target select" + +config TARGET_ATNGW100 + bool "Support atngw100" + +config TARGET_ATNGW100MKII + bool "Support atngw100mkii" + +config TARGET_ATSTK1002 + bool "Support atstk1002" + +config TARGET_ATSTK1003 + bool "Support atstk1003" + +config TARGET_ATSTK1004 + bool "Support atstk1004" + +config TARGET_ATSTK1006 + bool "Support atstk1006" + +config TARGET_FAVR_32_EZKIT + bool "Support favr-32-ezkit" + +config TARGET_GRASSHOPPER + bool "Support grasshopper" + +config TARGET_MIMC200 + bool "Support mimc200" + +config TARGET_HAMMERHEAD + bool "Support hammerhead" + +endchoice + +source "board/atmel/atngw100/Kconfig" +source "board/atmel/atngw100mkii/Kconfig" +source "board/atmel/atstk1000/Kconfig" +source "board/earthlcd/favr-32-ezkit/Kconfig" +source "board/in-circuit/grasshopper/Kconfig" +source "board/mimc/mimc200/Kconfig" +source "board/miromico/hammerhead/Kconfig" + +endmenu diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk index 28a371c..469185e 100644 --- a/arch/avr32/config.mk +++ b/arch/avr32/config.mk @@ -9,7 +9,6 @@ ifeq ($(CROSS_COMPILE),) CROSS_COMPILE := avr32-linux- endif -PLATFORM_CPPFLAGS += -DCONFIG_AVR32 CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig new file mode 100644 index 0000000..bb8a133 --- /dev/null +++ b/arch/blackfin/Kconfig @@ -0,0 +1,150 @@ +menu "Blackfin architecture" + depends on BLACKFIN + +config SYS_ARCH + string + default "blackfin" + +choice + prompt "Target select" + +config TARGET_BCT_BRETTL2 + bool "Support bct-brettl2" + +config TARGET_BF506F_EZKIT + bool "Support bf506f-ezkit" + +config TARGET_BF518F_EZBRD + bool "Support bf518f-ezbrd" + +config TARGET_BF525_UCR2 + bool "Support bf525-ucr2" + +config TARGET_BF526_EZBRD + bool "Support bf526-ezbrd" + +config TARGET_BF527_AD7160_EVAL + bool "Support bf527-ad7160-eval" + +config TARGET_BF527_EZKIT + bool "Support bf527-ezkit" + +config TARGET_BF527_SDP + bool "Support bf527-sdp" + +config TARGET_BF533_EZKIT + bool "Support bf533-ezkit" + +config TARGET_BF533_STAMP + bool "Support bf533-stamp" + +config TARGET_BF537_MINOTAUR + bool "Support bf537-minotaur" + +config TARGET_BF537_PNAV + bool "Support bf537-pnav" + +config TARGET_BF537_SRV1 + bool "Support bf537-srv1" + +config TARGET_BF537_STAMP + bool "Support bf537-stamp" + +config TARGET_BF538F_EZKIT + bool "Support bf538f-ezkit" + +config TARGET_BF548_EZKIT + bool "Support bf548-ezkit" + +config TARGET_BF561_ACVILON + bool "Support bf561-acvilon" + +config TARGET_BF561_EZKIT + bool "Support bf561-ezkit" + +config TARGET_BF609_EZKIT + bool "Support bf609-ezkit" + +config TARGET_BLACKSTAMP + bool "Support blackstamp" + +config TARGET_BLACKVME + bool "Support blackvme" + +config TARGET_BR4 + bool "Support br4" + +config TARGET_CM_BF527 + bool "Support cm-bf527" + +config TARGET_CM_BF533 + bool "Support cm-bf533" + +config TARGET_CM_BF537E + bool "Support cm-bf537e" + +config TARGET_CM_BF537U + bool "Support cm-bf537u" + +config TARGET_CM_BF548 + bool "Support cm-bf548" + +config TARGET_CM_BF561 + bool "Support cm-bf561" + +config TARGET_DNP5370 + bool "Support dnp5370" + +config TARGET_IBF_DSP561 + bool "Support ibf-dsp561" + +config TARGET_IP04 + bool "Support ip04" + +config TARGET_PR1 + bool "Support pr1" + +config TARGET_TCM_BF518 + bool "Support tcm-bf518" + +config TARGET_TCM_BF537 + bool "Support tcm-bf537" + +endchoice + +source "board/bct-brettl2/Kconfig" +source "board/bf506f-ezkit/Kconfig" +source "board/bf518f-ezbrd/Kconfig" +source "board/bf525-ucr2/Kconfig" +source "board/bf526-ezbrd/Kconfig" +source "board/bf527-ad7160-eval/Kconfig" +source "board/bf527-ezkit/Kconfig" +source "board/bf527-sdp/Kconfig" +source "board/bf533-ezkit/Kconfig" +source "board/bf533-stamp/Kconfig" +source "board/bf537-minotaur/Kconfig" +source "board/bf537-pnav/Kconfig" +source "board/bf537-srv1/Kconfig" +source "board/bf537-stamp/Kconfig" +source "board/bf538f-ezkit/Kconfig" +source "board/bf548-ezkit/Kconfig" +source "board/bf561-acvilon/Kconfig" +source "board/bf561-ezkit/Kconfig" +source "board/bf609-ezkit/Kconfig" +source "board/blackstamp/Kconfig" +source "board/blackvme/Kconfig" +source "board/br4/Kconfig" +source "board/cm-bf527/Kconfig" +source "board/cm-bf533/Kconfig" +source "board/cm-bf537e/Kconfig" +source "board/cm-bf537u/Kconfig" +source "board/cm-bf548/Kconfig" +source "board/cm-bf561/Kconfig" +source "board/dnp5370/Kconfig" +source "board/ibf-dsp561/Kconfig" +source "board/ip04/Kconfig" +source "board/pr1/Kconfig" +source "board/tcm-bf518/Kconfig" +source "board/tcm-bf537/Kconfig" + +endmenu diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk index fcaa44f..7b17b75 100644 --- a/arch/blackfin/config.mk +++ b/arch/blackfin/config.mk @@ -21,7 +21,6 @@ endif CONFIG_BFIN_BOOT_MODE := $(strip $(CONFIG_BFIN_BOOT_MODE:"%"=%)) PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic -PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN LDFLAGS_FINAL += --gc-sections LDFLAGS += -m elf32bfin diff --git a/arch/blackfin/cpu/jtag-console.c b/arch/blackfin/cpu/jtag-console.c index 7cddb85..b8be318 100644 --- a/arch/blackfin/cpu/jtag-console.c +++ b/arch/blackfin/cpu/jtag-console.c @@ -112,11 +112,11 @@ static void jtag_send(const char *raw_str, uint32_t len) if (cooked_str != raw_str) free((char *)cooked_str); } -static void jtag_putc(const char c) +static void jtag_putc(struct stdio_dev *dev, const char c) { jtag_send(&c, 1); } -static void jtag_puts(const char *s) +static void jtag_puts(struct stdio_dev *dev, const char *s) { jtag_send(s, strlen(s)); } @@ -133,7 +133,7 @@ static int jtag_tstc_dbg(void) } /* Higher layers want to know when any data is available */ -static int jtag_tstc(void) +static int jtag_tstc(struct stdio_dev *dev) { return jtag_tstc_dbg() || leftovers_len; } @@ -142,7 +142,7 @@ static int jtag_tstc(void) * [32bit length][actual data] */ static uint32_t leftovers; -static int jtag_getc(void) +static int jtag_getc(struct stdio_dev *dev) { int ret; uint32_t emudat; @@ -173,7 +173,7 @@ static int jtag_getc(void) leftovers = emudat; } - return jtag_getc(); + return jtag_getc(dev); } int drv_jtag_console_init(void) diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig new file mode 100644 index 0000000..6cda7db --- /dev/null +++ b/arch/m68k/Kconfig @@ -0,0 +1,98 @@ +menu "M68000 architecture" + depends on M68K + +config SYS_ARCH + string + default "m68k" + +choice + prompt "Target select" + +config TARGET_M52277EVB + bool "Support M52277EVB" + +config TARGET_M5235EVB + bool "Support M5235EVB" + +config TARGET_COBRA5272 + bool "Support cobra5272" + +config TARGET_EB_CPU5282 + bool "Support eb_cpu5282" + +config TARGET_TASREG + bool "Support TASREG" + +config TARGET_M5208EVBE + bool "Support M5208EVBE" + +config TARGET_M5249EVB + bool "Support M5249EVB" + +config TARGET_M5253DEMO + bool "Support M5253DEMO" + +config TARGET_M5253EVBE + bool "Support M5253EVBE" + +config TARGET_M5272C3 + bool "Support M5272C3" + +config TARGET_M5275EVB + bool "Support M5275EVB" + +config TARGET_M5282EVB + bool "Support M5282EVB" + +config TARGET_ASTRO_MCF5373L + bool "Support astro_mcf5373l" + +config TARGET_M53017EVB + bool "Support M53017EVB" + +config TARGET_M5329EVB + bool "Support M5329EVB" + +config TARGET_M5373EVB + bool "Support M5373EVB" + +config TARGET_M54418TWR + bool "Support M54418TWR" + +config TARGET_M54451EVB + bool "Support M54451EVB" + +config TARGET_M54455EVB + bool "Support M54455EVB" + +config TARGET_M5475EVB + bool "Support M5475EVB" + +config TARGET_M5485EVB + bool "Support M5485EVB" + +endchoice + +source "board/BuS/eb_cpu5282/Kconfig" +source "board/astro/mcf5373l/Kconfig" +source "board/cobra5272/Kconfig" +source "board/esd/tasreg/Kconfig" +source "board/freescale/m5208evbe/Kconfig" +source "board/freescale/m52277evb/Kconfig" +source "board/freescale/m5235evb/Kconfig" +source "board/freescale/m5249evb/Kconfig" +source "board/freescale/m5253demo/Kconfig" +source "board/freescale/m5253evbe/Kconfig" +source "board/freescale/m5272c3/Kconfig" +source "board/freescale/m5275evb/Kconfig" +source "board/freescale/m5282evb/Kconfig" +source "board/freescale/m53017evb/Kconfig" +source "board/freescale/m5329evb/Kconfig" +source "board/freescale/m5373evb/Kconfig" +source "board/freescale/m54418twr/Kconfig" +source "board/freescale/m54451evb/Kconfig" +source "board/freescale/m54455evb/Kconfig" +source "board/freescale/m547xevb/Kconfig" +source "board/freescale/m548xevb/Kconfig" + +endmenu diff --git a/arch/m68k/config.mk b/arch/m68k/config.mk index 33b3d51..3b3a7e8 100644 --- a/arch/m68k/config.mk +++ b/arch/m68k/config.mk @@ -11,7 +11,7 @@ endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000 -PLATFORM_CPPFLAGS += -DCONFIG_M68K -D__M68K__ +PLATFORM_CPPFLAGS += -D__M68K__ PLATFORM_LDFLAGS += -n PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections PLATFORM_RELFLAGS += -ffixed-d7 -msep-data diff --git a/arch/m68k/cpu/mcf52x2/config.mk b/arch/m68k/cpu/mcf52x2/config.mk index 34ad99e..f66000b 100644 --- a/arch/m68k/cpu/mcf52x2/config.mk +++ b/arch/m68k/cpu/mcf52x2/config.mk @@ -7,14 +7,14 @@ # SPDX-License-Identifier: GPL-2.0+ # -cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -is5208:=$(shell grep CONFIG_M5208 $(srctree)/include/$(cfg)) -is5249:=$(shell grep CONFIG_M5249 $(srctree)/include/$(cfg)) -is5253:=$(shell grep CONFIG_M5253 $(srctree)/include/$(cfg)) -is5271:=$(shell grep CONFIG_M5271 $(srctree)/include/$(cfg)) -is5272:=$(shell grep CONFIG_M5272 $(srctree)/include/$(cfg)) -is5275:=$(shell grep CONFIG_M5275 $(srctree)/include/$(cfg)) -is5282:=$(shell grep CONFIG_M5282 $(srctree)/include/$(cfg)) +cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h +is5208:=$(shell grep CONFIG_M5208 $(cfg)) +is5249:=$(shell grep CONFIG_M5249 $(cfg)) +is5253:=$(shell grep CONFIG_M5253 $(cfg)) +is5271:=$(shell grep CONFIG_M5271 $(cfg)) +is5272:=$(shell grep CONFIG_M5272 $(cfg)) +is5275:=$(shell grep CONFIG_M5275 $(cfg)) +is5282:=$(shell grep CONFIG_M5282 $(cfg)) ifneq (,$(findstring CONFIG_M5208,$(is5208))) PLATFORM_CPPFLAGS += -mcpu=5208 diff --git a/arch/m68k/cpu/mcf532x/config.mk b/arch/m68k/cpu/mcf532x/config.mk index af94354..2efb60f 100644 --- a/arch/m68k/cpu/mcf532x/config.mk +++ b/arch/m68k/cpu/mcf532x/config.mk @@ -7,9 +7,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -is5301x:=$(shell grep CONFIG_MCF5301x $(srctree)/include/$(cfg)) -is532x:=$(shell grep CONFIG_MCF532x $(srctree)/include/$(cfg)) +cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h +is5301x:=$(shell grep CONFIG_MCF5301x $(cfg)) +is532x:=$(shell grep CONFIG_MCF532x $(cfg)) ifneq (,$(findstring CONFIG_MCF5301x,$(is5301x))) PLATFORM_CPPFLAGS += -mcpu=53015 -fPIC diff --git a/arch/m68k/cpu/mcf5445x/config.mk b/arch/m68k/cpu/mcf5445x/config.mk index 5fd0d4d..13f8a9f 100644 --- a/arch/m68k/cpu/mcf5445x/config.mk +++ b/arch/m68k/cpu/mcf5445x/config.mk @@ -9,8 +9,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -is5441x:=$(shell grep CONFIG_MCF5441x $(srctree)/include/$(cfg)) +cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h +is5441x:=$(shell grep CONFIG_MCF5441x $(cfg)) ifneq (,$(findstring CONFIG_MCF5441x,$(is5441x))) PLATFORM_CPPFLAGS += -mcpu=54418 -fPIC diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig new file mode 100644 index 0000000..ddaa45f --- /dev/null +++ b/arch/microblaze/Kconfig @@ -0,0 +1,18 @@ +menu "MicroBlaze architecture" + depends on MICROBLAZE + +config SYS_ARCH + string + default "microblaze" + +choice + prompt "Target select" + +config TARGET_MICROBLAZE_GENERIC + bool "Support microblaze-generic" + +endchoice + +source "board/xilinx/microblaze-generic/Kconfig" + +endmenu diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig new file mode 100644 index 0000000..5bf0df4 --- /dev/null +++ b/arch/mips/Kconfig @@ -0,0 +1,37 @@ +menu "MIPS architecture" + depends on MIPS + +config SYS_ARCH + string + default "mips" + +choice + prompt "Target select" + +config TARGET_QEMU_MIPS + bool "Support qemu-mips" + +config TARGET_MALTA + bool "Support malta" + +config TARGET_VCT + bool "Support vct" + +config TARGET_DBAU1X00 + bool "Support dbau1x00" + +config TARGET_PB1X00 + bool "Support pb1x00" + +config TARGET_QEMU_MIPS64 + bool "Support qemu-mips64" + +endchoice + +source "board/dbau1x00/Kconfig" +source "board/imgtec/malta/Kconfig" +source "board/micronas/vct/Kconfig" +source "board/pb1x00/Kconfig" +source "board/qemu-mips/Kconfig" + +endmenu diff --git a/arch/mips/config.mk b/arch/mips/config.mk index f4a234a..a2d07af 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -25,7 +25,7 @@ endif # Default to EB if no endianess is configured ENDIANNESS ?= -EB -PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ +PLATFORM_CPPFLAGS += -D__MIPS__ __HAVE_ARCH_GENERIC_BOARD := y diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig new file mode 100644 index 0000000..743a8fe --- /dev/null +++ b/arch/nds32/Kconfig @@ -0,0 +1,26 @@ +menu "NDS32 architecture" + depends on NDS32 + +config SYS_ARCH + string + default "nds32" + +choice + prompt "Target select" + +config TARGET_ADP_AG101 + bool "Support adp-ag101" + +config TARGET_ADP_AG101P + bool "Support adp-ag101p" + +config TARGET_ADP_AG102 + bool "Support adp-ag102" + +endchoice + +source "board/AndesTech/adp-ag101/Kconfig" +source "board/AndesTech/adp-ag101p/Kconfig" +source "board/AndesTech/adp-ag102/Kconfig" + +endmenu diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk index 1024852..5ac9f90 100644 --- a/arch/nds32/config.mk +++ b/arch/nds32/config.mk @@ -17,6 +17,6 @@ CONFIG_STANDALONE_LOAD_ADDR = 0x300000 \ PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -mrelax PLATFORM_RELFLAGS += -gdwarf-2 -PLATFORM_CPPFLAGS += -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-10 -fpie +PLATFORM_CPPFLAGS += -D__nds32__ -G0 -ffixed-10 -fpie LDFLAGS_u-boot = --gc-sections --relax diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig new file mode 100644 index 0000000..b703646 --- /dev/null +++ b/arch/nios2/Kconfig @@ -0,0 +1,26 @@ +menu "Nios II architecture" + depends on NIOS2 + +config SYS_ARCH + string + default "nios2" + +choice + prompt "Target select" + +config TARGET_NIOS2_GENERIC + bool "Support nios2-generic" + +config TARGET_PCI5441 + bool "Support PCI5441" + +config TARGET_PK1C20 + bool "Support PK1C20" + +endchoice + +source "board/altera/nios2-generic/Kconfig" +source "board/psyent/pci5441/Kconfig" +source "board/psyent/pk1c20/Kconfig" + +endmenu diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk index 65a5a40..82bd887 100644 --- a/arch/nios2/config.mk +++ b/arch/nios2/config.mk @@ -12,7 +12,7 @@ endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x02000000 -PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__ +PLATFORM_CPPFLAGS += -D__NIOS2__ PLATFORM_CPPFLAGS += -G0 LDFLAGS_FINAL += --gc-sections diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig new file mode 100644 index 0000000..cc54a2e --- /dev/null +++ b/arch/openrisc/Kconfig @@ -0,0 +1,18 @@ +menu "OpenRISC architecture" + depends on OPENRISC + +config SYS_ARCH + string + default "openrisc" + +choice + prompt "Target select" + +config TARGET_OPENRISC_GENERIC + bool "Support openrisc-generic" + +endchoice + +source "board/openrisc/openrisc-generic/Kconfig" + +endmenu diff --git a/arch/openrisc/config.mk b/arch/openrisc/config.mk index 9902b9a..cd95f24 100644 --- a/arch/openrisc/config.mk +++ b/arch/openrisc/config.mk @@ -11,6 +11,6 @@ endif # r10 used for global object pointer, already set in OR32 GCC but just to be # clear -PLATFORM_CPPFLAGS += -DCONFIG_OPENRISC -D__OR1K__ -ffixed-r10 +PLATFORM_CPPFLAGS += -D__OR1K__ -ffixed-r10 CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig new file mode 100644 index 0000000..3325af3 --- /dev/null +++ b/arch/powerpc/Kconfig @@ -0,0 +1,58 @@ +menu "PowerPC architecture" + depends on PPC + +config SYS_ARCH + string + default "powerpc" + +choice + prompt "CPU select" + +config 74xx_7xx + bool "74xx" + +config MPC512X + bool "MPC512X" + +config 5xx + bool "MPC5xx" + +config MPC5xxx + bool "MPC5xxx" + +config MPC824X + bool "MPC824X" + +config MPC8260 + bool "MPC8260" + +config MPC83xx + bool "MPC83xx" + +config MPC85xx + bool "MPC85xx" + +config MPC86xx + bool "MPC86xx" + +config 8xx + bool "MPC8xx" + +config 4xx + bool "PPC4xx" + +endchoice + +source "arch/powerpc/cpu/74xx_7xx/Kconfig" +source "arch/powerpc/cpu/mpc512x/Kconfig" +source "arch/powerpc/cpu/mpc5xx/Kconfig" +source "arch/powerpc/cpu/mpc5xxx/Kconfig" +source "arch/powerpc/cpu/mpc824x/Kconfig" +source "arch/powerpc/cpu/mpc8260/Kconfig" +source "arch/powerpc/cpu/mpc83xx/Kconfig" +source "arch/powerpc/cpu/mpc85xx/Kconfig" +source "arch/powerpc/cpu/mpc86xx/Kconfig" +source "arch/powerpc/cpu/mpc8xx/Kconfig" +source "arch/powerpc/cpu/ppc4xx/Kconfig" + +endmenu diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index fb7096e..6329b6c 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -13,7 +13,7 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections \ -meabi -PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ -ffixed-r2 +PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2 PLATFORM_LDFLAGS += -n # Support generic board on PPC diff --git a/arch/powerpc/cpu/74xx_7xx/Kconfig b/arch/powerpc/cpu/74xx_7xx/Kconfig new file mode 100644 index 0000000..6ce464d --- /dev/null +++ b/arch/powerpc/cpu/74xx_7xx/Kconfig @@ -0,0 +1,49 @@ +menu "74xx_7xx CPU" + depends on 74xx_7xx + +config SYS_CPU + string + default "74xx_7xx" + +choice + prompt "Target select" + +config TARGET_P3G4 + bool "Support P3G4" + +config TARGET_ZUMA + bool "Support ZUMA" + +config TARGET_PPMC7XX + bool "Support ppmc7xx" + +config TARGET_ELPPC + bool "Support ELPPC" + +config TARGET_CPCI750 + bool "Support CPCI750" + +config TARGET_MPC7448HPC2 + bool "Support mpc7448hpc2" + +config TARGET_DB64360 + bool "Support DB64360" + +config TARGET_DB64460 + bool "Support DB64460" + +config TARGET_P3MX + bool "Support p3mx" + +endchoice + +source "board/Marvell/db64360/Kconfig" +source "board/Marvell/db64460/Kconfig" +source "board/eltec/elppc/Kconfig" +source "board/esd/cpci750/Kconfig" +source "board/evb64260/Kconfig" +source "board/freescale/mpc7448hpc2/Kconfig" +source "board/ppmc7xx/Kconfig" +source "board/prodrive/p3mx/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/74xx_7xx/config.mk b/arch/powerpc/cpu/74xx_7xx/config.mk index 96812a0..4cd1a26 100644 --- a/arch/powerpc/cpu/74xx_7xx/config.mk +++ b/arch/powerpc/cpu/74xx_7xx/config.mk @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -mstring +PLATFORM_CPPFLAGS += -mstring diff --git a/arch/powerpc/cpu/mpc512x/Kconfig b/arch/powerpc/cpu/mpc512x/Kconfig new file mode 100644 index 0000000..bfc4eae --- /dev/null +++ b/arch/powerpc/cpu/mpc512x/Kconfig @@ -0,0 +1,34 @@ +menu "mpc512x CPU" + depends on MPC512X + +config SYS_CPU + string + default "mpc512x" + +choice + prompt "Target select" + +config TARGET_PDM360NG + bool "Support pdm360ng" + +config TARGET_ARIA + bool "Support aria" + +config TARGET_MECP5123 + bool "Support mecp5123" + +config TARGET_MPC5121ADS + bool "Support mpc5121ads" + +config TARGET_AC14XX + bool "Support ac14xx" + +endchoice + +source "board/davedenx/aria/Kconfig" +source "board/esd/mecp5123/Kconfig" +source "board/freescale/mpc5121ads/Kconfig" +source "board/ifm/ac14xx/Kconfig" +source "board/pdm360ng/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc512x/config.mk b/arch/powerpc/cpu/mpc512x/config.mk index 03759e6..5bf1b2a 100644 --- a/arch/powerpc/cpu/mpc512x/config.mk +++ b/arch/powerpc/cpu/mpc512x/config.mk @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 -msoft-float -mcpu=603e +PLATFORM_CPPFLAGS += -DCONFIG_E300 -msoft-float -mcpu=603e diff --git a/arch/powerpc/cpu/mpc512x/serial.c b/arch/powerpc/cpu/mpc512x/serial.c index 42e0dc9..4105a28 100644 --- a/arch/powerpc/cpu/mpc512x/serial.c +++ b/arch/powerpc/cpu/mpc512x/serial.c @@ -384,7 +384,7 @@ struct stdio_dev *open_port(int num, int baudrate) sprintf(env_val, "%d", baudrate); setenv(env_var, env_val); - if (port->start()) + if (port->start(port)) return NULL; set_bit(num, &initialized); @@ -407,7 +407,7 @@ int close_port(int num) if (!port) return -1; - ret = port->stop(); + ret = port->stop(port); clear_bit(num, &initialized); return ret; @@ -418,7 +418,7 @@ int write_port(struct stdio_dev *port, char *buf) if (!port || !buf) return -1; - port->puts(buf); + port->puts(port, buf); return 0; } @@ -433,8 +433,8 @@ int read_port(struct stdio_dev *port, char *buf, int size) if (!size) return 0; - while (port->tstc()) { - buf[cnt++] = port->getc(); + while (port->tstc(port)) { + buf[cnt++] = port->getc(port); if (cnt > size) break; } diff --git a/arch/powerpc/cpu/mpc5xx/Kconfig b/arch/powerpc/cpu/mpc5xx/Kconfig new file mode 100644 index 0000000..79579d7 --- /dev/null +++ b/arch/powerpc/cpu/mpc5xx/Kconfig @@ -0,0 +1,22 @@ +menu "mpc5xx CPU" + depends on 5xx + +config SYS_CPU + string + default "mpc5xx" + +choice + prompt "Target select" + +config TARGET_CMI_MPC5XX + bool "Support cmi_mpc5xx" + +config TARGET_PATI + bool "Support PATI" + +endchoice + +source "board/cmi/Kconfig" +source "board/mpl/pati/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc5xx/config.mk b/arch/powerpc/cpu/mpc5xx/config.mk index 31e2dc9..dd2ec37 100644 --- a/arch/powerpc/cpu/mpc5xx/config.mk +++ b/arch/powerpc/cpu/mpc5xx/config.mk @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -DCONFIG_5xx -mpowerpc -msoft-float +PLATFORM_CPPFLAGS += -mpowerpc -msoft-float diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig new file mode 100644 index 0000000..b2f0bad --- /dev/null +++ b/arch/powerpc/cpu/mpc5xxx/Kconfig @@ -0,0 +1,154 @@ +menu "mpc5xxx CPU" + depends on MPC5xxx + +config SYS_CPU + string + default "mpc5xxx" + +choice + prompt "Target select" + +config TARGET_A3M071 + bool "Support a3m071" + +config TARGET_A4M072 + bool "Support a4m072" + +config TARGET_BC3450 + bool "Support BC3450" + +config TARGET_CANMB + bool "Support canmb" + +config TARGET_CM5200 + bool "Support cm5200" + +config TARGET_GALAXY5200 + bool "Support galaxy5200" + +config TARGET_ICECUBE + bool "Support IceCube" + +config TARGET_INKA4X0 + bool "Support inka4x0" + +config TARGET_IPEK01 + bool "Support ipek01" + +config TARGET_JUPITER + bool "Support jupiter" + +config TARGET_MCC200 + bool "Support mcc200" + +config TARGET_MOTIONPRO + bool "Support motionpro" + +config TARGET_MUNICES + bool "Support munices" + +config TARGET_PM520 + bool "Support PM520" + +config TARGET_TOTAL5200 + bool "Support Total5200" + +config TARGET_V38B + bool "Support v38b" + +config TARGET_TOP5200 + bool "Support TOP5200" + +config TARGET_CPCI5200 + bool "Support cpci5200" + +config TARGET_MECP5200 + bool "Support mecp5200" + +config TARGET_PF5200 + bool "Support pf5200" + +config TARGET_O2D + bool "Support O2D" + +config TARGET_O2D300 + bool "Support O2D300" + +config TARGET_O2DNT2 + bool "Support O2DNT2" + +config TARGET_O2I + bool "Support O2I" + +config TARGET_O2MNT + bool "Support O2MNT" + +config TARGET_O3DNT + bool "Support O3DNT" + +config TARGET_DIGSY_MTC + bool "Support digsy_mtc" + +config TARGET_HMI1001 + bool "Support hmi1001" + +config TARGET_MUCMC52 + bool "Support mucmc52" + +config TARGET_UC101 + bool "Support uc101" + +config TARGET_MVBC_P + bool "Support MVBC_P" + +config TARGET_MVSMR + bool "Support MVSMR" + +config TARGET_PCM030 + bool "Support pcm030" + +config TARGET_AEV + bool "Support aev" + +config TARGET_CHARON + bool "Support charon" + +config TARGET_TB5200 + bool "Support TB5200" + +config TARGET_TQM5200 + bool "Support TQM5200" + +endchoice + +source "board/a3m071/Kconfig" +source "board/a4m072/Kconfig" +source "board/bc3450/Kconfig" +source "board/canmb/Kconfig" +source "board/cm5200/Kconfig" +source "board/emk/top5200/Kconfig" +source "board/esd/cpci5200/Kconfig" +source "board/esd/mecp5200/Kconfig" +source "board/esd/pf5200/Kconfig" +source "board/galaxy5200/Kconfig" +source "board/icecube/Kconfig" +source "board/ifm/o2dnt2/Kconfig" +source "board/inka4x0/Kconfig" +source "board/intercontrol/digsy_mtc/Kconfig" +source "board/ipek01/Kconfig" +source "board/jupiter/Kconfig" +source "board/manroland/hmi1001/Kconfig" +source "board/manroland/mucmc52/Kconfig" +source "board/manroland/uc101/Kconfig" +source "board/matrix_vision/mvbc_p/Kconfig" +source "board/matrix_vision/mvsmr/Kconfig" +source "board/mcc200/Kconfig" +source "board/motionpro/Kconfig" +source "board/munices/Kconfig" +source "board/phytec/pcm030/Kconfig" +source "board/pm520/Kconfig" +source "board/total5200/Kconfig" +source "board/tqc/tqm5200/Kconfig" +source "board/v38b/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc5xxx/config.mk b/arch/powerpc/cpu/mpc5xxx/config.mk index 3384f6f..bcff214 100644 --- a/arch/powerpc/cpu/mpc5xxx/config.mk +++ b/arch/powerpc/cpu/mpc5xxx/config.mk @@ -5,5 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx \ - -mstring -mcpu=603e -mmultiple +PLATFORM_CPPFLAGS += -mstring -mcpu=603e -mmultiple diff --git a/arch/powerpc/cpu/mpc824x/Kconfig b/arch/powerpc/cpu/mpc824x/Kconfig new file mode 100644 index 0000000..309833f --- /dev/null +++ b/arch/powerpc/cpu/mpc824x/Kconfig @@ -0,0 +1,49 @@ +menu "mpc824x CPU" + depends on MPC824X + +config SYS_CPU + string + default "mpc824x" + +choice + prompt "Target select" + +config TARGET_A3000 + bool "Support A3000" + +config TARGET_CPC45 + bool "Support CPC45" + +config TARGET_CU824 + bool "Support CU824" + +config TARGET_EXALION + bool "Support eXalion" + +config TARGET_MUSENKI + bool "Support MUSENKI" + +config TARGET_MVBLUE + bool "Support MVBLUE" + +config TARGET_SANDPOINT8240 + bool "Support Sandpoint8240" + +config TARGET_SANDPOINT8245 + bool "Support Sandpoint8245" + +config TARGET_UTX8245 + bool "Support utx8245" + +endchoice + +source "board/a3000/Kconfig" +source "board/cpc45/Kconfig" +source "board/cu824/Kconfig" +source "board/eXalion/Kconfig" +source "board/musenki/Kconfig" +source "board/mvblue/Kconfig" +source "board/sandpoint/Kconfig" +source "board/utx8245/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc824x/config.mk b/arch/powerpc/cpu/mpc824x/config.mk index a224bc8..ecfb07e 100644 --- a/arch/powerpc/cpu/mpc824x/config.mk +++ b/arch/powerpc/cpu/mpc824x/config.mk @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -mstring -mcpu=603e -msoft-float +PLATFORM_CPPFLAGS += -mstring -mcpu=603e -msoft-float diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig new file mode 100644 index 0000000..1a8707d --- /dev/null +++ b/arch/powerpc/cpu/mpc8260/Kconfig @@ -0,0 +1,94 @@ +menu "mpc8260 CPU" + depends on MPC8260 + +config SYS_CPU + string + default "mpc8260" + +choice + prompt "Target select" + +config TARGET_ATC + bool "Support atc" + +config TARGET_COGENT_MPC8260 + bool "Support cogent_mpc8260" + +config TARGET_CPU86 + bool "Support CPU86" + +config TARGET_CPU87 + bool "Support CPU87" + +config TARGET_EP8260 + bool "Support ep8260" + +config TARGET_EP82XXM + bool "Support ep82xxm" + +config TARGET_GW8260 + bool "Support gw8260" + +config TARGET_HYMOD + bool "Support hymod" + +config TARGET_IPHASE4539 + bool "Support IPHASE4539" + +config TARGET_MUAS3001 + bool "Support muas3001" + +config TARGET_PM826 + bool "Support PM826" + +config TARGET_PM828 + bool "Support PM828" + +config TARGET_PPMC8260 + bool "Support ppmc8260" + +config TARGET_SACSNG + bool "Support sacsng" + +config TARGET_MPC8266ADS + bool "Support MPC8266ADS" + +config TARGET_VOVPN_GW + bool "Support VoVPN-GW" + +config TARGET_IDS8247 + bool "Support IDS8247" + +config TARGET_KM82XX + bool "Support km82xx" + +config TARGET_TQM8260 + bool "Support TQM8260" + +config TARGET_TQM8272 + bool "Support TQM8272" + +endchoice + +source "board/atc/Kconfig" +source "board/cogent/Kconfig" +source "board/cpu86/Kconfig" +source "board/cpu87/Kconfig" +source "board/ep8260/Kconfig" +source "board/ep82xxm/Kconfig" +source "board/freescale/mpc8266ads/Kconfig" +source "board/funkwerk/vovpn-gw/Kconfig" +source "board/gw8260/Kconfig" +source "board/hymod/Kconfig" +source "board/ids/ids8247/Kconfig" +source "board/iphase4539/Kconfig" +source "board/keymile/km82xx/Kconfig" +source "board/muas3001/Kconfig" +source "board/pm826/Kconfig" +source "board/pm828/Kconfig" +source "board/ppmc8260/Kconfig" +source "board/sacsng/Kconfig" +source "board/tqc/tqm8260/Kconfig" +source "board/tqc/tqm8272/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc8260/config.mk b/arch/powerpc/cpu/mpc8260/config.mk index 59f152d..6a1b6e3 100644 --- a/arch/powerpc/cpu/mpc8260/config.mk +++ b/arch/powerpc/cpu/mpc8260/config.mk @@ -5,5 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -DCONFIG_MPC8260 -DCONFIG_CPM2 \ +PLATFORM_CPPFLAGS += -DCONFIG_CPM2 \ -mstring -mcpu=603e -mmultiple diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig new file mode 100644 index 0000000..5fd3393 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -0,0 +1,100 @@ +menu "mpc83xx CPU" + depends on MPC83xx + +config SYS_CPU + string + default "mpc83xx" + +choice + prompt "Target select" + +config TARGET_MPC8308_P1M + bool "Support mpc8308_p1m" + +config TARGET_SBC8349 + bool "Support sbc8349" + +config TARGET_VE8313 + bool "Support ve8313" + +config TARGET_VME8349 + bool "Support vme8349" + +config TARGET_MPC8308RDB + bool "Support MPC8308RDB" + +config TARGET_MPC8313ERDB + bool "Support MPC8313ERDB" + +config TARGET_MPC8315ERDB + bool "Support MPC8315ERDB" + +config TARGET_MPC8323ERDB + bool "Support MPC8323ERDB" + +config TARGET_MPC832XEMDS + bool "Support MPC832XEMDS" + +config TARGET_MPC8349EMDS + bool "Support MPC8349EMDS" + +config TARGET_MPC8349ITX + bool "Support MPC8349ITX" + +config TARGET_MPC8360EMDS + bool "Support MPC8360EMDS" + +config TARGET_MPC8360ERDK + bool "Support MPC8360ERDK" + +config TARGET_MPC837XEMDS + bool "Support MPC837XEMDS" + +config TARGET_MPC837XERDB + bool "Support MPC837XERDB" + +config TARGET_IDS8313 + bool "Support ids8313" + +config TARGET_KM8360 + bool "Support km8360" + +config TARGET_SUVD3 + bool "Support suvd3" + +config TARGET_TUXX1 + bool "Support tuxx1" + +config TARGET_MERGERBOX + bool "Support MERGERBOX" + +config TARGET_MVBLM7 + bool "Support MVBLM7" + +config TARGET_TQM834X + bool "Support TQM834x" + +endchoice + +source "board/esd/vme8349/Kconfig" +source "board/freescale/mpc8308rdb/Kconfig" +source "board/freescale/mpc8313erdb/Kconfig" +source "board/freescale/mpc8315erdb/Kconfig" +source "board/freescale/mpc8323erdb/Kconfig" +source "board/freescale/mpc832xemds/Kconfig" +source "board/freescale/mpc8349emds/Kconfig" +source "board/freescale/mpc8349itx/Kconfig" +source "board/freescale/mpc8360emds/Kconfig" +source "board/freescale/mpc8360erdk/Kconfig" +source "board/freescale/mpc837xemds/Kconfig" +source "board/freescale/mpc837xerdb/Kconfig" +source "board/ids/ids8313/Kconfig" +source "board/keymile/km83xx/Kconfig" +source "board/matrix_vision/mergerbox/Kconfig" +source "board/matrix_vision/mvblm7/Kconfig" +source "board/mpc8308_p1m/Kconfig" +source "board/sbc8349/Kconfig" +source "board/tqc/tqm834x/Kconfig" +source "board/ve8313/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc83xx/config.mk b/arch/powerpc/cpu/mpc83xx/config.mk index dfce4d5..0c08350 100644 --- a/arch/powerpc/cpu/mpc83xx/config.mk +++ b/arch/powerpc/cpu/mpc83xx/config.mk @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -DCONFIG_MPC83xx -DCONFIG_E300 -msoft-float +PLATFORM_CPPFLAGS += -DCONFIG_E300 -msoft-float diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig new file mode 100644 index 0000000..0f70380 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -0,0 +1,190 @@ +menu "mpc85xx CPU" + depends on MPC85xx + +config SYS_CPU + string + default "mpc85xx" + +choice + prompt "Target select" + +config TARGET_SBC8548 + bool "Support sbc8548" + +config TARGET_SOCRATES + bool "Support socrates" + +config TARGET_HWW1U1A + bool "Support HWW1U1A" + +config TARGET_B4860QDS + bool "Support B4860QDS" + +config TARGET_BSC9131RDB + bool "Support BSC9131RDB" + +config TARGET_BSC9132QDS + bool "Support BSC9132QDS" + +config TARGET_C29XPCIE + bool "Support C29XPCIE" + +config TARGET_P3041DS + bool "Support P3041DS" + +config TARGET_P4080DS + bool "Support P4080DS" + +config TARGET_P5020DS + bool "Support P5020DS" + +config TARGET_P5040DS + bool "Support P5040DS" + +config TARGET_MPC8536DS + bool "Support MPC8536DS" + +config TARGET_MPC8540ADS + bool "Support MPC8540ADS" + +config TARGET_MPC8541CDS + bool "Support MPC8541CDS" + +config TARGET_MPC8544DS + bool "Support MPC8544DS" + +config TARGET_MPC8548CDS + bool "Support MPC8548CDS" + +config TARGET_MPC8555CDS + bool "Support MPC8555CDS" + +config TARGET_MPC8560ADS + bool "Support MPC8560ADS" + +config TARGET_MPC8568MDS + bool "Support MPC8568MDS" + +config TARGET_MPC8569MDS + bool "Support MPC8569MDS" + +config TARGET_MPC8572DS + bool "Support MPC8572DS" + +config TARGET_P1010RDB + bool "Support P1010RDB" + +config TARGET_P1022DS + bool "Support P1022DS" + +config TARGET_P1023RDB + bool "Support P1023RDB" + +config TARGET_P1_P2_RDB + bool "Support P1_P2_RDB" + +config TARGET_P1_P2_RDB_PC + bool "Support p1_p2_rdb_pc" + +config TARGET_P1_TWR + bool "Support p1_twr" + +config TARGET_P2020COME + bool "Support P2020COME" + +config TARGET_P2020DS + bool "Support P2020DS" + +config TARGET_P2041RDB + bool "Support P2041RDB" + +config TARGET_QEMU_PPCE500 + bool "Support qemu-ppce500" + +config TARGET_T1040QDS + bool "Support T1040QDS" + +config TARGET_T104XRDB + bool "Support T104xRDB" + +config TARGET_T208XQDS + bool "Support T208xQDS" + +config TARGET_T208XRDB + bool "Support T208xRDB" + +config TARGET_T4240EMU + bool "Support T4240EMU" + +config TARGET_T4240QDS + bool "Support T4240QDS" + +config TARGET_T4240RDB + bool "Support T4240RDB" + +config TARGET_CONTROLCENTERD + bool "Support controlcenterd" + +config TARGET_KMP204X + bool "Support kmp204x" + +config TARGET_STXGP3 + bool "Support stxgp3" + +config TARGET_STXSSA + bool "Support stxssa" + +config TARGET_XPEDITE520X + bool "Support xpedite520x" + +config TARGET_XPEDITE537X + bool "Support xpedite537x" + +config TARGET_XPEDITE550X + bool "Support xpedite550x" + +endchoice + +source "board/exmeritus/hww1u1a/Kconfig" +source "board/freescale/b4860qds/Kconfig" +source "board/freescale/bsc9131rdb/Kconfig" +source "board/freescale/bsc9132qds/Kconfig" +source "board/freescale/c29xpcie/Kconfig" +source "board/freescale/corenet_ds/Kconfig" +source "board/freescale/mpc8536ds/Kconfig" +source "board/freescale/mpc8540ads/Kconfig" +source "board/freescale/mpc8541cds/Kconfig" +source "board/freescale/mpc8544ds/Kconfig" +source "board/freescale/mpc8548cds/Kconfig" +source "board/freescale/mpc8555cds/Kconfig" +source "board/freescale/mpc8560ads/Kconfig" +source "board/freescale/mpc8568mds/Kconfig" +source "board/freescale/mpc8569mds/Kconfig" +source "board/freescale/mpc8572ds/Kconfig" +source "board/freescale/p1010rdb/Kconfig" +source "board/freescale/p1022ds/Kconfig" +source "board/freescale/p1023rdb/Kconfig" +source "board/freescale/p1_p2_rdb/Kconfig" +source "board/freescale/p1_p2_rdb_pc/Kconfig" +source "board/freescale/p1_twr/Kconfig" +source "board/freescale/p2020come/Kconfig" +source "board/freescale/p2020ds/Kconfig" +source "board/freescale/p2041rdb/Kconfig" +source "board/freescale/qemu-ppce500/Kconfig" +source "board/freescale/t1040qds/Kconfig" +source "board/freescale/t104xrdb/Kconfig" +source "board/freescale/t208xqds/Kconfig" +source "board/freescale/t208xrdb/Kconfig" +source "board/freescale/t4qds/Kconfig" +source "board/freescale/t4rdb/Kconfig" +source "board/gdsys/p1022/Kconfig" +source "board/keymile/kmp204x/Kconfig" +source "board/sbc8548/Kconfig" +source "board/socrates/Kconfig" +source "board/stx/stxgp3/Kconfig" +source "board/stx/stxssa/Kconfig" +source "board/xes/xpedite520x/Kconfig" +source "board/xes/xpedite537x/Kconfig" +source "board/xes/xpedite550x/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc85xx/config.mk b/arch/powerpc/cpu/mpc85xx/config.mk index 1470f95..72c964c 100644 --- a/arch/powerpc/cpu/mpc85xx/config.mk +++ b/arch/powerpc/cpu/mpc85xx/config.mk @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -Wa,-me500 -msoft-float -mno-string +PLATFORM_CPPFLAGS += -Wa,-me500 -msoft-float -mno-string # -mspe=yes is needed to have -mno-spe accepted by a buggy GCC; # see "[PATCH,rs6000] make -mno-spe work as expected" on diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig new file mode 100644 index 0000000..f0ff441 --- /dev/null +++ b/arch/powerpc/cpu/mpc86xx/Kconfig @@ -0,0 +1,30 @@ +menu "mpc86xx CPU" + depends on MPC86xx + +config SYS_CPU + string + default "mpc86xx" + +choice + prompt "Target select" + +config TARGET_SBC8641D + bool "Support sbc8641d" + +config TARGET_MPC8610HPCD + bool "Support MPC8610HPCD" + +config TARGET_MPC8641HPCN + bool "Support MPC8641HPCN" + +config TARGET_XPEDITE517X + bool "Support xpedite517x" + +endchoice + +source "board/freescale/mpc8610hpcd/Kconfig" +source "board/freescale/mpc8641hpcn/Kconfig" +source "board/sbc8641d/Kconfig" +source "board/xes/xpedite517x/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc86xx/config.mk b/arch/powerpc/cpu/mpc86xx/config.mk index 4c7235f..69a0b96 100644 --- a/arch/powerpc/cpu/mpc86xx/config.mk +++ b/arch/powerpc/cpu/mpc86xx/config.mk @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -mstring -maltivec -mabi=altivec -msoft-float +PLATFORM_CPPFLAGS += -mstring -maltivec -mabi=altivec -msoft-float diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig new file mode 100644 index 0000000..35608a6 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -0,0 +1,160 @@ +menu "mpc8xx CPU" + depends on 8xx + +config SYS_CPU + string + default "mpc8xx" + +choice + prompt "Target select" + +config TARGET_COGENT_MPC8XX + bool "Support cogent_mpc8xx" + +config TARGET_ESTEEM192E + bool "Support ESTEEM192E" + +config TARGET_FLAGADM + bool "Support FLAGADM" + +config TARGET_GEN860T + bool "Support GEN860T" + +config TARGET_HERMES + bool "Support hermes" + +config TARGET_ICU862 + bool "Support ICU862" + +config TARGET_IP860 + bool "Support IP860" + +config TARGET_IVML24 + bool "Support IVML24" + +config TARGET_IVMS8 + bool "Support IVMS8" + +config TARGET_LWMON + bool "Support lwmon" + +config TARGET_NETVIA + bool "Support NETVIA" + +config TARGET_R360MPI + bool "Support R360MPI" + +config TARGET_RRVISION + bool "Support RRvision" + +config TARGET_SXNI855T + bool "Support SXNI855T" + +config TARGET_SPD823TS + bool "Support SPD823TS" + +config TARGET_SVM_SC8XX + bool "Support svm_sc8xx" + +config TARGET_MHPC + bool "Support MHPC" + +config TARGET_TOP860 + bool "Support TOP860" + +config TARGET_KUP4K + bool "Support KUP4K" + +config TARGET_KUP4X + bool "Support KUP4X" + +config TARGET_ELPT860 + bool "Support ELPT860" + +config TARGET_UC100 + bool "Support uc100" + +config TARGET_STXXTC + bool "Support stxxtc" + +config TARGET_FPS850L + bool "Support FPS850L" + +config TARGET_FPS860L + bool "Support FPS860L" + +config TARGET_NSCU + bool "Support NSCU" + +config TARGET_SM850 + bool "Support SM850" + +config TARGET_TK885D + bool "Support TK885D" + +config TARGET_TQM823L + bool "Support TQM823L" + +config TARGET_TQM823M + bool "Support TQM823M" + +config TARGET_TQM850L + bool "Support TQM850L" + +config TARGET_TQM850M + bool "Support TQM850M" + +config TARGET_TQM855L + bool "Support TQM855L" + +config TARGET_TQM855M + bool "Support TQM855M" + +config TARGET_TQM860L + bool "Support TQM860L" + +config TARGET_TQM860M + bool "Support TQM860M" + +config TARGET_TQM862L + bool "Support TQM862L" + +config TARGET_TQM862M + bool "Support TQM862M" + +config TARGET_TQM866M + bool "Support TQM866M" + +config TARGET_TQM885D + bool "Support TQM885D" + +config TARGET_VIRTLAB2 + bool "Support virtlab2" + +endchoice + +source "board/LEOX/elpt860/Kconfig" +source "board/RRvision/Kconfig" +source "board/cogent/Kconfig" +source "board/eltec/mhpc/Kconfig" +source "board/emk/top860/Kconfig" +source "board/esteem192e/Kconfig" +source "board/flagadm/Kconfig" +source "board/gen860t/Kconfig" +source "board/hermes/Kconfig" +source "board/icu862/Kconfig" +source "board/ip860/Kconfig" +source "board/ivm/Kconfig" +source "board/kup/kup4k/Kconfig" +source "board/kup/kup4x/Kconfig" +source "board/lwmon/Kconfig" +source "board/manroland/uc100/Kconfig" +source "board/netvia/Kconfig" +source "board/r360mpi/Kconfig" +source "board/sixnet/Kconfig" +source "board/spd8xx/Kconfig" +source "board/stx/stxxtc/Kconfig" +source "board/svm_sc8xx/Kconfig" +source "board/tqc/tqm8xx/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/mpc8xx/config.mk b/arch/powerpc/cpu/mpc8xx/config.mk index ee2c883..485e43d 100644 --- a/arch/powerpc/cpu/mpc8xx/config.mk +++ b/arch/powerpc/cpu/mpc8xx/config.mk @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -DCONFIG_8xx -mstring -mcpu=860 -msoft-float +PLATFORM_CPPFLAGS += -mstring -mcpu=860 -msoft-float diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c index 2fd5b11..9590bfd 100644 --- a/arch/powerpc/cpu/mpc8xx/video.c +++ b/arch/powerpc/cpu/mpc8xx/video.c @@ -948,7 +948,7 @@ static inline void console_newline (void) } } -void video_putc (const char c) +void video_putc(struct stdio_dev *dev, const char c) { if (!video_enable) { serial_putc (c); @@ -985,7 +985,7 @@ void video_putc (const char c) } } -void video_puts (const char *s) +void video_puts(struct stdio_dev *dev, const char *s) { int count = strlen (s); @@ -994,7 +994,7 @@ void video_puts (const char *s) serial_putc (*s++); else while (count--) - video_putc (*s++); + video_putc(dev, *s++); } /************************************************************************/ diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig new file mode 100644 index 0000000..2d15dd1 --- /dev/null +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -0,0 +1,322 @@ +menu "ppc4xx CPU" + depends on 4xx + +config SYS_CPU + string + default "ppc4xx" + +choice + prompt "Target select" + +config TARGET_CSB272 + bool "Support csb272" + +config TARGET_CSB472 + bool "Support csb472" + +config TARGET_G2000 + bool "Support G2000" + +config TARGET_JSE + bool "Support JSE" + +config TARGET_KORAT + bool "Support korat" + +config TARGET_LWMON5 + bool "Support lwmon5" + +config TARGET_PCS440EP + bool "Support pcs440ep" + +config TARGET_SBC405 + bool "Support sbc405" + +config TARGET_SC3 + bool "Support sc3" + +config TARGET_T3CORP + bool "Support t3corp" + +config TARGET_W7OLMC + bool "Support W7OLMC" + +config TARGET_W7OLMG + bool "Support W7OLMG" + +config TARGET_ZEUS + bool "Support zeus" + +config TARGET_ACADIA + bool "Support acadia" + +config TARGET_BAMBOO + bool "Support bamboo" + +config TARGET_BLUESTONE + bool "Support bluestone" + +config TARGET_BUBINGA + bool "Support bubinga" + +config TARGET_CANYONLANDS + bool "Support canyonlands" + +config TARGET_EBONY + bool "Support ebony" + +config TARGET_KATMAI + bool "Support katmai" + +config TARGET_KILAUEA + bool "Support kilauea" + +config TARGET_LUAN + bool "Support luan" + +config TARGET_MAKALU + bool "Support makalu" + +config TARGET_OCOTEA + bool "Support ocotea" + +config TARGET_REDWOOD + bool "Support redwood" + +config TARGET_SEQUOIA + bool "Support sequoia" + +config TARGET_TAIHU + bool "Support taihu" + +config TARGET_TAISHAN + bool "Support taishan" + +config TARGET_WALNUT + bool "Support walnut" + +config TARGET_YOSEMITE + bool "Support yosemite" + +config TARGET_YUCCA + bool "Support yucca" + +config TARGET_FX12MM + bool "Support fx12mm" + +config TARGET_V5FX30TEVAL + bool "Support v5fx30teval" + +config TARGET_CRAYL1 + bool "Support CRAYL1" + +config TARGET_CATCENTER + bool "Support CATcenter" + +config TARGET_PPCHAMELEONEVB + bool "Support PPChameleonEVB" + +config TARGET_APC405 + bool "Support APC405" + +config TARGET_AR405 + bool "Support AR405" + +config TARGET_ASH405 + bool "Support ASH405" + +config TARGET_CMS700 + bool "Support CMS700" + +config TARGET_CPCI2DP + bool "Support CPCI2DP" + +config TARGET_CPCI405 + bool "Support CPCI405" + +config TARGET_CPCI4052 + bool "Support CPCI4052" + +config TARGET_CPCI405AB + bool "Support CPCI405AB" + +config TARGET_CPCI405DT + bool "Support CPCI405DT" + +config TARGET_CPCIISER4 + bool "Support CPCIISER4" + +config TARGET_DP405 + bool "Support DP405" + +config TARGET_DU405 + bool "Support DU405" + +config TARGET_DU440 + bool "Support DU440" + +config TARGET_HH405 + bool "Support HH405" + +config TARGET_HUB405 + bool "Support HUB405" + +config TARGET_OCRTC + bool "Support OCRTC" + +config TARGET_PCI405 + bool "Support PCI405" + +config TARGET_PLU405 + bool "Support PLU405" + +config TARGET_PMC405 + bool "Support PMC405" + +config TARGET_PMC405DE + bool "Support PMC405DE" + +config TARGET_PMC440 + bool "Support PMC440" + +config TARGET_VOH405 + bool "Support VOH405" + +config TARGET_VOM405 + bool "Support VOM405" + +config TARGET_WUH405 + bool "Support WUH405" + +config TARGET_DLVISION_10G + bool "Support dlvision-10g" + +config TARGET_IO + bool "Support io" + +config TARGET_IOCON + bool "Support iocon" + +config TARGET_NEO + bool "Support neo" + +config TARGET_IO64 + bool "Support io64" + +config TARGET_DLVISION + bool "Support dlvision" + +config TARGET_GDPPC440ETX + bool "Support gdppc440etx" + +config TARGET_INTIP + bool "Support intip" + +config TARGET_ICON + bool "Support icon" + +config TARGET_MIP405 + bool "Support MIP405" + +config TARGET_PIP405 + bool "Support PIP405" + +config TARGET_ALPR + bool "Support alpr" + +config TARGET_P3P440 + bool "Support p3p440" + +config TARGET_KAREF + bool "Support KAREF" + +config TARGET_METROBOX + bool "Support METROBOX" + +config TARGET_XPEDITE1000 + bool "Support xpedite1000" + +config TARGET_ML507 + bool "Support ml507" + +config TARGET_XILINX_PPC405_GENERIC + bool "Support xilinx-ppc405-generic" + +config TARGET_XILINX_PPC440_GENERIC + bool "Support xilinx-ppc440-generic" + +endchoice + +source "board/amcc/acadia/Kconfig" +source "board/amcc/bamboo/Kconfig" +source "board/amcc/bluestone/Kconfig" +source "board/amcc/bubinga/Kconfig" +source "board/amcc/canyonlands/Kconfig" +source "board/amcc/ebony/Kconfig" +source "board/amcc/katmai/Kconfig" +source "board/amcc/kilauea/Kconfig" +source "board/amcc/luan/Kconfig" +source "board/amcc/makalu/Kconfig" +source "board/amcc/ocotea/Kconfig" +source "board/amcc/redwood/Kconfig" +source "board/amcc/sequoia/Kconfig" +source "board/amcc/taihu/Kconfig" +source "board/amcc/taishan/Kconfig" +source "board/amcc/walnut/Kconfig" +source "board/amcc/yosemite/Kconfig" +source "board/amcc/yucca/Kconfig" +source "board/avnet/fx12mm/Kconfig" +source "board/avnet/v5fx30teval/Kconfig" +source "board/cray/L1/Kconfig" +source "board/csb272/Kconfig" +source "board/csb472/Kconfig" +source "board/dave/PPChameleonEVB/Kconfig" +source "board/esd/apc405/Kconfig" +source "board/esd/ar405/Kconfig" +source "board/esd/ash405/Kconfig" +source "board/esd/cms700/Kconfig" +source "board/esd/cpci2dp/Kconfig" +source "board/esd/cpci405/Kconfig" +source "board/esd/cpciiser4/Kconfig" +source "board/esd/dp405/Kconfig" +source "board/esd/du405/Kconfig" +source "board/esd/du440/Kconfig" +source "board/esd/hh405/Kconfig" +source "board/esd/hub405/Kconfig" +source "board/esd/ocrtc/Kconfig" +source "board/esd/pci405/Kconfig" +source "board/esd/plu405/Kconfig" +source "board/esd/pmc405/Kconfig" +source "board/esd/pmc405de/Kconfig" +source "board/esd/pmc440/Kconfig" +source "board/esd/voh405/Kconfig" +source "board/esd/vom405/Kconfig" +source "board/esd/wuh405/Kconfig" +source "board/g2000/Kconfig" +source "board/gdsys/405ep/Kconfig" +source "board/gdsys/405ex/Kconfig" +source "board/gdsys/dlvision/Kconfig" +source "board/gdsys/gdppc440etx/Kconfig" +source "board/gdsys/intip/Kconfig" +source "board/jse/Kconfig" +source "board/korat/Kconfig" +source "board/lwmon5/Kconfig" +source "board/mosaixtech/icon/Kconfig" +source "board/mpl/mip405/Kconfig" +source "board/mpl/pip405/Kconfig" +source "board/pcs440ep/Kconfig" +source "board/prodrive/alpr/Kconfig" +source "board/prodrive/p3p440/Kconfig" +source "board/sandburst/karef/Kconfig" +source "board/sandburst/metrobox/Kconfig" +source "board/sbc405/Kconfig" +source "board/sc3/Kconfig" +source "board/t3corp/Kconfig" +source "board/w7o/Kconfig" +source "board/xes/xpedite1000/Kconfig" +source "board/xilinx/ml507/Kconfig" +source "board/xilinx/ppc405-generic/Kconfig" +source "board/xilinx/ppc440-generic/Kconfig" +source "board/zeus/Kconfig" + +endmenu diff --git a/arch/powerpc/cpu/ppc4xx/config.mk b/arch/powerpc/cpu/ppc4xx/config.mk index 102f069..f87c9dc 100644 --- a/arch/powerpc/cpu/ppc4xx/config.mk +++ b/arch/powerpc/cpu/ppc4xx/config.mk @@ -5,10 +5,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -DCONFIG_4xx -mstring -msoft-float +PLATFORM_CPPFLAGS += -mstring -msoft-float -cfg=$(shell grep configs $(objtree)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -is440:=$(shell grep CONFIG_440 $(srctree)/include/$(cfg)) +cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h +is440:=$(shell grep CONFIG_440 $(cfg)) ifneq (,$(findstring CONFIG_440,$(is440))) PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440 diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index d465dcd..0b27d29 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -12,9 +12,7 @@ #include <asm/ppc4xx-gpio.h> #include <asm/ppc4xx.h> -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) DECLARE_GLOBAL_DATA_PTR; -#endif #ifndef CONFIG_SYS_PLL_RECONFIG #define CONFIG_SYS_PLL_RECONFIG 0 @@ -451,6 +449,8 @@ cpu_init_f (void) mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP); #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ + + gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); } /* diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig new file mode 100644 index 0000000..c393550 --- /dev/null +++ b/arch/sandbox/Kconfig @@ -0,0 +1,16 @@ +menu "Sandbox architecture" + depends on SANDBOX + +config SYS_ARCH + string + default "sandbox" + +config SYS_BOARD + string + default "sandbox" + +config SYS_CONFIG_NAME + string + default "sandbox" + +endmenu diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index c3f889f..e38a44b 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -1,7 +1,7 @@ # Copyright (c) 2011 The Chromium OS Authors. # SPDX-License-Identifier: GPL-2.0+ -PLATFORM_CPPFLAGS += -DCONFIG_SANDBOX -D__SANDBOX__ -U_FORTIFY_SOURCE +PLATFORM_CPPFLAGS += -D__SANDBOX__ -U_FORTIFY_SOURCE PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM -DCONFIG_SYS_GENERIC_BOARD PLATFORM_LIBS += -lrt diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 3f4005b..1aa397c 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <dm/root.h> #include <os.h> #include <asm/state.h> @@ -14,6 +15,9 @@ void reset_cpu(ulong ignored) if (state_uninit()) os_exit(2); + if (dm_uninit()) + os_exit(2); + /* This is considered normal termination for now */ os_exit(0); } diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index aad3b8b..b3d7051 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -6,6 +6,7 @@ #include <common.h> #include <os.h> #include <asm/getopt.h> +#include <asm/io.h> #include <asm/sections.h> #include <asm/state.h> @@ -218,6 +219,7 @@ SANDBOX_CMDLINE_OPT_SHORT(terminal, 't', 1, int main(int argc, char *argv[]) { struct sandbox_state *state; + gd_t data; int ret; ret = state_init(); @@ -236,6 +238,12 @@ int main(int argc, char *argv[]) if (state->ram_buf_rm && state->ram_buf_fname) os_unlink(state->ram_buf_fname); + memset(&data, '\0', sizeof(data)); + gd = &data; +#ifdef CONFIG_SYS_MALLOC_F_LEN + gd->malloc_base = CONFIG_MALLOC_F_ADDR; +#endif + /* Do pre- and post-relocation init */ board_init_f(0); diff --git a/arch/sandbox/include/asm/config.h b/arch/sandbox/include/asm/config.h index 6c1bff9..ec7729e 100644 --- a/arch/sandbox/include/asm/config.h +++ b/arch/sandbox/include/asm/config.h @@ -7,7 +7,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_GENERIC_GLOBAL_DATA #define CONFIG_SANDBOX_ARCH /* Used by drivers/spi/sandbox_spi.c and arch/sandbox/include/asm/state.h */ diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig new file mode 100644 index 0000000..e6ded16 --- /dev/null +++ b/arch/sh/Kconfig @@ -0,0 +1,98 @@ +menu "SuperH architecture" + depends on SH + +config SYS_ARCH + string + default "sh" + +choice + prompt "Target select" + +config TARGET_RSK7203 + bool "Support rsk7203" + +config TARGET_RSK7264 + bool "Support rsk7264" + +config TARGET_RSK7269 + bool "Support rsk7269" + +config TARGET_MPR2 + bool "Support mpr2" + +config TARGET_MS7720SE + bool "Support ms7720se" + +config TARGET_SHMIN + bool "Support shmin" + +config TARGET_ESPT + bool "Support espt" + +config TARGET_MS7722SE + bool "Support ms7722se" + +config TARGET_MS7750SE + bool "Support ms7750se" + +config TARGET_AP_SH4A_4A + bool "Support ap_sh4a_4a" + +config TARGET_AP325RXA + bool "Support ap325rxa" + +config TARGET_ECOVEC + bool "Support ecovec" + +config TARGET_MIGOR + bool "Support MigoR" + +config TARGET_R0P7734 + bool "Support r0p7734" + +config TARGET_R2DPLUS + bool "Support r2dplus" + +config TARGET_R7780MP + bool "Support r7780mp" + +config TARGET_SH7752EVB + bool "Support sh7752evb" + +config TARGET_SH7753EVB + bool "Support sh7753evb" + +config TARGET_SH7757LCR + bool "Support sh7757lcr" + +config TARGET_SH7763RDP + bool "Support sh7763rdp" + +config TARGET_SH7785LCR + bool "Support sh7785lcr" + +endchoice + +source "board/alphaproject/ap_sh4a_4a/Kconfig" +source "board/espt/Kconfig" +source "board/mpr2/Kconfig" +source "board/ms7720se/Kconfig" +source "board/ms7722se/Kconfig" +source "board/ms7750se/Kconfig" +source "board/renesas/MigoR/Kconfig" +source "board/renesas/ap325rxa/Kconfig" +source "board/renesas/ecovec/Kconfig" +source "board/renesas/r0p7734/Kconfig" +source "board/renesas/r2dplus/Kconfig" +source "board/renesas/r7780mp/Kconfig" +source "board/renesas/rsk7203/Kconfig" +source "board/renesas/rsk7264/Kconfig" +source "board/renesas/rsk7269/Kconfig" +source "board/renesas/sh7752evb/Kconfig" +source "board/renesas/sh7753evb/Kconfig" +source "board/renesas/sh7757lcr/Kconfig" +source "board/renesas/sh7763rdp/Kconfig" +source "board/renesas/sh7785lcr/Kconfig" +source "board/shmin/Kconfig" + +endmenu diff --git a/arch/sh/cpu/sh2/u-boot.lds b/arch/sh/cpu/sh2/u-boot.lds deleted file mode 100644 index 254d9f2..0000000 --- a/arch/sh/cpu/sh2/u-boot.lds +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2008 Nobuhiro Iwamatsu - * Copyright (C) 2008 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - * entry and reloct_dst will be provided via ldflags - */ - . = .; - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - KEEP(arch/sh/cpu/sh2/start.o (.text)) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - PROVIDE (reloc_dst_end = .); - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (__bss_end = .); -} diff --git a/arch/sh/cpu/sh4/u-boot.lds b/arch/sh/cpu/sh4/u-boot.lds deleted file mode 100644 index 57544ce..0000000 --- a/arch/sh/cpu/sh4/u-boot.lds +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2007 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * Copyright (C) 2008-2009 - * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - * entry and reloct_dst will be provided via ldflags - */ - . = .; - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - KEEP(arch/sh/cpu/sh4/start.o (.text)) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss (NOLOAD) : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (__bss_end = .); -} diff --git a/arch/sh/cpu/sh3/u-boot.lds b/arch/sh/cpu/u-boot.lds index 26de086..30c7a9d 100644 --- a/arch/sh/cpu/sh3/u-boot.lds +++ b/arch/sh/cpu/u-boot.lds @@ -1,10 +1,10 @@ /* * Copyright (C) 2007 - * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * Copyright (C) 2007 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * + * Copyright (C) 2008-2009 + * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * * Copyright (C) 2008 * Mark Jonas <mark.jonas@de.bosch.com> * @@ -28,7 +28,7 @@ SECTIONS .text : { - KEEP(arch/sh/cpu/sh3/start.o (.text)) + KEEP(*/start.o (.text)) . = ALIGN(8192); common/env_embedded.o (.ppcenv) . = ALIGN(8192); diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig new file mode 100644 index 0000000..fc92910 --- /dev/null +++ b/arch/sparc/Kconfig @@ -0,0 +1,34 @@ +menu "SPARC architecture" + depends on SPARC + +config SYS_ARCH + string + default "sparc" + +choice + prompt "Target select" + +config TARGET_GRSIM_LEON2 + bool "Support grsim_leon2" + +config TARGET_GR_CPCI_AX2000 + bool "Support gr_cpci_ax2000" + +config TARGET_GR_EP2S60 + bool "Support gr_ep2s60" + +config TARGET_GR_XC3S_1500 + bool "Support gr_xc3s_1500" + +config TARGET_GRSIM + bool "Support grsim" + +endchoice + +source "board/gaisler/gr_cpci_ax2000/Kconfig" +source "board/gaisler/gr_ep2s60/Kconfig" +source "board/gaisler/gr_xc3s_1500/Kconfig" +source "board/gaisler/grsim/Kconfig" +source "board/gaisler/grsim_leon2/Kconfig" + +endmenu diff --git a/arch/sparc/config.mk b/arch/sparc/config.mk index be59f58..196d28a 100644 --- a/arch/sparc/config.mk +++ b/arch/sparc/config.mk @@ -14,4 +14,4 @@ gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) \ -T $(srctree)/examples/standalone/sparc.lds -PLATFORM_CPPFLAGS += -DCONFIG_SPARC -D__sparc__ +PLATFORM_CPPFLAGS += -D__sparc__ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig new file mode 100644 index 0000000..8fc619a --- /dev/null +++ b/arch/x86/Kconfig @@ -0,0 +1,18 @@ +menu "x86 architecture" + depends on X86 + +config SYS_ARCH + string + default "x86" + +choice + prompt "Target select" + +config TARGET_COREBOOT + bool "Support coreboot" + +endchoice + +source "board/chromebook-x86/coreboot/Kconfig" + +endmenu diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk index 4b2c873..f7b01d3 100644 --- a/arch/x86/cpu/config.mk +++ b/arch/x86/cpu/config.mk @@ -7,7 +7,7 @@ CROSS_COMPILE ?= i386-linux- -PLATFORM_CPPFLAGS += -DCONFIG_X86 -D__I386__ -Werror +PLATFORM_CPPFLAGS += -D__I386__ -Werror # DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! LDPPFLAGS += -DRESET_SEG_START=0xffff0000 diff --git a/arch/x86/lib/video.c b/arch/x86/lib/video.c index dfd2a84..975949d 100644 --- a/arch/x86/lib/video.c +++ b/arch/x86/lib/video.c @@ -104,7 +104,7 @@ static void __video_putc(const char c, int *x, int *y) } } -static void video_putc(const char c) +static void video_putc(struct stdio_dev *dev, const char c) { int x, y, pos; @@ -123,7 +123,7 @@ static void video_putc(const char c) outb_p(0xff & (pos >> 1), vidport+1); } -static void video_puts(const char *s) +static void video_puts(struct stdio_dev *dev, const char *s) { int x, y, pos; char c; @@ -178,8 +178,6 @@ int video_init(void) vga_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM; vga_dev.putc = video_putc; /* 'putc' function */ vga_dev.puts = video_puts; /* 'puts' function */ - vga_dev.tstc = NULL; /* 'tstc' function */ - vga_dev.getc = NULL; /* 'getc' function */ if (stdio_register(&vga_dev) == 0) return 1; @@ -191,8 +189,6 @@ int video_init(void) strcpy(kbd_dev.name, "kbd"); kbd_dev.ext = 0; kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - kbd_dev.putc = NULL; /* 'putc' function */ - kbd_dev.puts = NULL; /* 'puts' function */ kbd_dev.tstc = i8042_tstc; /* 'tstc' function */ kbd_dev.getc = i8042_getc; /* 'getc' function */ |