diff options
Diffstat (limited to 'arch')
192 files changed, 7449 insertions, 11115 deletions
diff --git a/arch/arm/config.mk b/arch/arm/config.mk index bdabcf4..fd3e5fb 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -103,3 +103,6 @@ ALL-y += checkarmreloc # such usage by requiring word relocations. PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations) endif + +# limit ourselves to the sections we want in the .bin. +OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rel.dyn diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile index fd0da53..b2d30b1 100644 --- a/arch/arm/cpu/Makefile +++ b/arch/arm/cpu/Makefile @@ -1,2 +1,3 @@ +obj-$(CONFIG_AT91FAMILY) += at91-common/ obj-$(CONFIG_TEGRA) += $(SOC)-common/ obj-$(CONFIG_TEGRA) += tegra-common/ diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 9294611..72c69b9 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -49,33 +49,68 @@ int get_num_cpus(void) * Timing tables for each SOC for all four oscillator options. */ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { - /* T20: 1 GHz */ - /* n, m, p, cpcon */ - {{ 1000, 13, 0, 12}, /* OSC 13M */ - { 625, 12, 0, 8}, /* OSC 19.2M */ - { 1000, 12, 0, 12}, /* OSC 12M */ - { 1000, 26, 0, 12}, /* OSC 26M */ + /* + * T20: 1 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { + { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ + { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ + { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ }, - - /* T25: 1.2 GHz */ - {{ 923, 10, 0, 12}, - { 750, 12, 0, 8}, - { 600, 6, 0, 12}, - { 600, 13, 0, 12}, + /* + * T25: 1.2 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { + { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ + { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ + { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ }, - - /* T30: 1.4 GHz */ - {{ 862, 8, 0, 8}, - { 583, 8, 0, 4}, - { 700, 6, 0, 8}, - { 700, 13, 0, 8}, + /* + * T30: 1.4 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { + { .n = 862, .m = 8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ + { .n = 583, .m = 8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */ + { .n = 700, .m = 6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ + { .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ }, - - /* T114: 1.4 GHz */ - {{ 862, 8, 0, 8}, - { 583, 8, 0, 4}, - { 696, 12, 0, 8}, - { 700, 13, 0, 8}, + /* + * T114: 700 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 23:20 4 + * PLLX_BASE n 15: 8 8 + * PLLX_BASE m 7: 0 8 + */ + { + { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ + { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ + { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ + { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ }, }; @@ -100,6 +135,7 @@ void adjust_pllp_out_freqs(void) int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, u32 divp, u32 cpcon) { + int chip = tegra_get_chip(); u32 reg; /* If PLLX is already enabled, just return */ @@ -116,7 +152,10 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, writel(reg, &pll->pll_base); /* Set cpcon to PLLX_MISC */ - reg = (cpcon << PLL_CPCON_SHIFT); + if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30) + reg = (cpcon << PLL_CPCON_SHIFT); + else + reg = 0; /* Set dccon to PLLX_MISC if freq > 600MHz */ if (divn > 600) diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/cpu/arm926ejs/at91/led.c index 5dd9048..46ed055 100644 --- a/arch/arm/cpu/arm926ejs/at91/led.c +++ b/arch/arm/cpu/arm926ejs/at91/led.c @@ -7,43 +7,41 @@ */ #include <common.h> -#include <asm/io.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_pio.h> +#include <asm/gpio.h> #include <asm/arch/gpio.h> #ifdef CONFIG_RED_LED void red_led_on(void) { - at91_set_gpio_value(CONFIG_RED_LED, 1); + gpio_set_value(CONFIG_RED_LED, 1); } void red_led_off(void) { - at91_set_gpio_value(CONFIG_RED_LED, 0); + gpio_set_value(CONFIG_RED_LED, 0); } #endif #ifdef CONFIG_GREEN_LED void green_led_on(void) { - at91_set_gpio_value(CONFIG_GREEN_LED, 0); + gpio_set_value(CONFIG_GREEN_LED, 0); } void green_led_off(void) { - at91_set_gpio_value(CONFIG_GREEN_LED, 1); + gpio_set_value(CONFIG_GREEN_LED, 1); } #endif #ifdef CONFIG_YELLOW_LED void yellow_led_on(void) { - at91_set_gpio_value(CONFIG_YELLOW_LED, 0); + gpio_set_value(CONFIG_YELLOW_LED, 0); } void yellow_led_off(void) { - at91_set_gpio_value(CONFIG_YELLOW_LED, 1); + gpio_set_value(CONFIG_YELLOW_LED, 1); } #endif diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds index 40bcc31..80fb9bd 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -51,11 +51,13 @@ SECTIONS _end = .; - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds index 4927736..76b499d 100644 --- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -51,11 +51,13 @@ SECTIONS _end = .; - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index d3347b3..0467d00 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,7 +12,7 @@ obj-y += cache_v7.o obj-y += cpu.o obj-y += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index 966fcab..5566310 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -19,4 +19,3 @@ obj-y += ddr.o obj-y += emif4.o obj-y += board.o obj-y += mux.o -obj-$(CONFIG_NAND_OMAP_GPMC) += elm.o diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 803aa9c..c7dad66 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -241,3 +241,11 @@ void s_init(void) sdram_init(); #endif } + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif /* !CONFIG_SYS_DCACHE_OFF */ diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 8e5f3c6..0672798 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -101,9 +101,15 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs, static void setup_dplls(void) { const struct dpll_params *params; - do_setup_dpll(&dpll_core_regs, &dpll_core); - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu); - do_setup_dpll(&dpll_per_regs, &dpll_per); + + params = get_dpll_core_params(); + do_setup_dpll(&dpll_core_regs, params); + + params = get_dpll_mpu_params(); + do_setup_dpll(&dpll_mpu_regs, params); + + params = get_dpll_per_params(); + do_setup_dpll(&dpll_per_regs, params); writel(0x300, &cmwkup->clkdcoldodpllper); params = get_dpll_ddr_params(); diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index fabe259..92142c8 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -62,6 +62,21 @@ const struct dpll_params dpll_core = { const struct dpll_params dpll_per = { 960, OSC-1, 5, -1, -1, -1, -1}; +const struct dpll_params *get_dpll_mpu_params(void) +{ + return &dpll_mpu; +} + +const struct dpll_params *get_dpll_core_params(void) +{ + return &dpll_core; +} + +const struct dpll_params *get_dpll_per_params(void) +{ + return &dpll_per; +} + void setup_clocks_for_console(void) { clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index c4890f2..97c00b4 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -18,6 +18,7 @@ struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; +struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; const struct dpll_regs dpll_mpu_regs = { .cm_clkmode_dpll = CM_WKUP + 0x560, @@ -47,15 +48,9 @@ const struct dpll_regs dpll_ddr_regs = { .cm_idlest_dpll = CM_WKUP + 0x5A4, .cm_clksel_dpll = CM_WKUP + 0x5AC, .cm_div_m2_dpll = CM_WKUP + 0x5B0, + .cm_div_m4_dpll = CM_WKUP + 0x5B8, }; -const struct dpll_params dpll_mpu = { - -1, -1, -1, -1, -1, -1, -1}; -const struct dpll_params dpll_core = { - -1, -1, -1, -1, -1, -1, -1}; -const struct dpll_params dpll_per = { - -1, -1, -1, -1, -1, -1, -1}; - void setup_clocks_for_console(void) { /* Do not add any spl_debug prints in this function */ @@ -107,4 +102,7 @@ void enable_basic_clocks(void) }; do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); + + /* Select the Master osc clk as Timer2 clock source */ + writel(0x1, &cmdpll->clktimer2clk); } diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index fa697c7..d05e666 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -36,6 +36,73 @@ static struct ddr_data_regs *ddr_data_reg[2] = { static struct ddr_cmdtctrl *ioctrl_reg = { (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR}; +static inline u32 get_mr(int nr, u32 cs, u32 mr_addr) +{ + u32 mr; + + mr_addr |= cs << EMIF_REG_CS_SHIFT; + writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); + + mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data); + debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr); + if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && + ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && + ((mr & 0xff000000) >> 24) == (mr & 0xff)) + return mr & 0xff; + else + return mr; +} + +static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val) +{ + mr_addr |= cs << EMIF_REG_CS_SHIFT; + writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); + writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data); +} + +static void configure_mr(int nr, u32 cs) +{ + u32 mr_addr; + + while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) + ; + set_mr(nr, cs, LPDDR2_MR10, 0x56); + + set_mr(nr, cs, LPDDR2_MR1, 0x43); + set_mr(nr, cs, LPDDR2_MR2, 0x2); + + mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; + set_mr(nr, cs, mr_addr, 0x2); +} + +/* + * Configure EMIF4D5 registers and MR registers + */ +void config_sdram_emif4d5(const struct emif_regs *regs, int nr) +{ + writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl); + writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw); + writel(0x1, &emif_reg[nr]->emif_iodft_tlgc); + writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); + + writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config); + writel(regs->emif_rd_wr_lvl_rmp_win, + &emif_reg[nr]->emif_rd_wr_lvl_rmp_win); + writel(regs->emif_rd_wr_lvl_rmp_ctl, + &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); + writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl); + writel(regs->emif_rd_wr_exec_thresh, + &emif_reg[nr]->emif_rd_wr_exec_thresh); + + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); + + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) { + configure_mr(nr, 0); + configure_mr(nr, 1); + } +} + /** * Configure SDRAM */ @@ -72,15 +139,67 @@ void set_sdram_timings(const struct emif_regs *regs, int nr) writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw); } +void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) +{ +} + +/* + * Configure EXT PHY registers + */ +static void ext_phy_settings(const struct emif_regs *regs, int nr) +{ + u32 *ext_phy_ctrl_base = 0; + u32 *emif_ext_phy_ctrl_base = 0; + const u32 *ext_phy_ctrl_const_regs; + u32 i = 0; + u32 size; + + ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1); + emif_ext_phy_ctrl_base = + (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); + + /* Configure external phy control timing registers */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { + writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); + } + + /* + * external phy 6-24 registers do not change with + * ddr frequency + */ + emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size); + + if (!size) + return; + + for (i = 0; i < size; i++) { + writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); + } +} + /** * Configure DDR PHY */ void config_ddr_phy(const struct emif_regs *regs, int nr) { + /* + * disable initialization and refreshes for now until we + * finish programming EMIF regs. + */ + setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl, + EMIF_REG_INITREF_DIS_MASK); + writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1); writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw); + + if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) + ext_phy_settings(regs, nr); } /** @@ -88,16 +207,16 @@ void config_ddr_phy(const struct emif_regs *regs, int nr) */ void config_cmd_ctrl(const struct cmd_control *cmd, int nr) { + if (!cmd) + return; + writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio); - writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff); writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout); writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio); - writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff); writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout); writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio); - writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff); writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout); } @@ -108,6 +227,9 @@ void config_ddr_data(const struct ddr_data *data, int nr) { int i; + if (!data) + return; + for (i = 0; i < DDR_DATA_REGS_NR; i++) { writel(data->datardsratio0, &(ddr_data_reg[nr]+i)->dt0rdsratio0); @@ -121,18 +243,23 @@ void config_ddr_data(const struct ddr_data *data, int nr) &(ddr_data_reg[nr]+i)->dt0fwsratio0); writel(data->datawrsratio0, &(ddr_data_reg[nr]+i)->dt0wrsratio0); - writel(data->datauserank0delay, - &(ddr_data_reg[nr]+i)->dt0rdelays0); - writel(data->datadldiff0, - &(ddr_data_reg[nr]+i)->dt0dldiff0); } } -void config_io_ctrl(unsigned long val) +void config_io_ctrl(const struct ctrl_ioregs *ioregs) { - writel(val, &ioctrl_reg->cm0ioctl); - writel(val, &ioctrl_reg->cm1ioctl); - writel(val, &ioctrl_reg->cm2ioctl); - writel(val, &ioctrl_reg->dt0ioctl); - writel(val, &ioctrl_reg->dt1ioctl); + if (!ioregs) + return; + + writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl); + writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl); + writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl); + writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl); + writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl); +#ifdef CONFIG_AM43XX + writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl); + writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl); + writel(ioregs->emif_sdram_config_ext, + &ioctrl_reg->emif_sdram_config_ext); +#endif } diff --git a/arch/arm/cpu/armv7/am33xx/elm.c b/arch/arm/cpu/armv7/am33xx/elm.c deleted file mode 100644 index 8f1d6af..0000000 --- a/arch/arm/cpu/armv7/am33xx/elm.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com> - * Mansoor Ahamed <mansoor.ahamed@ti.com> - * - * BCH Error Location Module (ELM) support. - * - * NOTE: - * 1. Supports only continuous mode. Dont see need for page mode in uboot - * 2. Supports only syndrome polynomial 0. i.e. poly local variable is - * always set to ELM_DEFAULT_POLY. Dont see need for other polynomial - * sets in uboot - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/errno.h> -#include <asm/arch/cpu.h> -#include <asm/omap_gpmc.h> -#include <asm/arch/elm.h> - -#define ELM_DEFAULT_POLY (0) - -struct elm *elm_cfg; - -/** - * elm_load_syndromes - Load BCH syndromes based on nibble selection - * @syndrome: BCH syndrome - * @nibbles: - * @poly: Syndrome Polynomial set to use - * - * Load BCH syndromes based on nibble selection - */ -static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) -{ - u32 *ptr; - u32 val; - - /* reg 0 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[0]; - val = syndrome[0] | (syndrome[1] << 8) | (syndrome[2] << 16) | - (syndrome[3] << 24); - writel(val, ptr); - /* reg 1 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[1]; - val = syndrome[4] | (syndrome[5] << 8) | (syndrome[6] << 16) | - (syndrome[7] << 24); - writel(val, ptr); - - /* BCH 8-bit with 26 nibbles (4*8=32) */ - if (nibbles > 13) { - /* reg 2 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2]; - val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) | - (syndrome[11] << 24); - writel(val, ptr); - /* reg 3 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[3]; - val = syndrome[12] | (syndrome[13] << 8) | - (syndrome[14] << 16) | (syndrome[15] << 24); - writel(val, ptr); - } - - /* BCH 16-bit with 52 nibbles (7*8=56) */ - if (nibbles > 26) { - /* reg 4 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4]; - val = syndrome[16] | (syndrome[17] << 8) | - (syndrome[18] << 16) | (syndrome[19] << 24); - writel(val, ptr); - - /* reg 5 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[5]; - val = syndrome[20] | (syndrome[21] << 8) | - (syndrome[22] << 16) | (syndrome[23] << 24); - writel(val, ptr); - - /* reg 6 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]; - val = syndrome[24] | (syndrome[25] << 8) | - (syndrome[26] << 16) | (syndrome[27] << 24); - writel(val, ptr); - } -} - -/** - * elm_check_errors - Check for BCH errors and return error locations - * @syndrome: BCH syndrome - * @nibbles: - * @error_count: Returns number of errrors in the syndrome - * @error_locations: Returns error locations (in decimal) in this array - * - * Check the provided syndrome for BCH errors and return error count - * and locations in the array passed. Returns -1 if error is not correctable, - * else returns 0 - */ -int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, - u32 *error_locations) -{ - u8 poly = ELM_DEFAULT_POLY; - s8 i; - u32 location_status; - - elm_load_syndromes(syndrome, nibbles, poly); - - /* start processing */ - writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]) - | ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID), - &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]); - - /* wait for processing to complete */ - while ((readl(&elm_cfg->irqstatus) & (0x1 << poly)) != 0x1) - ; - /* clear status */ - writel((readl(&elm_cfg->irqstatus) | (0x1 << poly)), - &elm_cfg->irqstatus); - - /* check if correctable */ - location_status = readl(&elm_cfg->error_location[poly].location_status); - if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK)) - return -1; - - /* get error count */ - *error_count = readl(&elm_cfg->error_location[poly].location_status) & - ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK; - - for (i = 0; i < *error_count; i++) { - error_locations[i] = - readl(&elm_cfg->error_location[poly].error_location_x[i]); - } - - return 0; -} - - -/** - * elm_config - Configure ELM module - * @level: 4 / 8 / 16 bit BCH - * - * Configure ELM module based on BCH level. - * Set mode as continuous mode. - * Currently we are using only syndrome 0 and syndromes 1 to 6 are not used. - * Also, the mode is set only for syndrome 0 - */ -int elm_config(enum bch_level level) -{ - u32 val; - u8 poly = ELM_DEFAULT_POLY; - u32 buffer_size = 0x7FF; - - /* config size and level */ - val = (u32)(level) & ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK; - val |= ((buffer_size << ELM_LOCATION_CONFIG_ECC_SIZE_POS) & - ELM_LOCATION_CONFIG_ECC_SIZE_MASK); - writel(val, &elm_cfg->location_config); - - /* config continous mode */ - /* enable interrupt generation for syndrome polynomial set */ - writel((readl(&elm_cfg->irqenable) | (0x1 << poly)), - &elm_cfg->irqenable); - /* set continuous mode for the syndrome polynomial set */ - writel((readl(&elm_cfg->page_ctrl) & ~(0x1 << poly)), - &elm_cfg->page_ctrl); - - return 0; -} - -/** - * elm_reset - Do a soft reset of ELM - * - * Perform a soft reset of ELM and return after reset is done. - */ -void elm_reset(void) -{ - /* initiate reset */ - writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET), - &elm_cfg->sysconfig); - - /* wait for reset complete and normal operation */ - while ((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) != - ELM_SYSSTATUS_RESETDONE) - ; -} - -/** - * elm_init - Initialize ELM module - * - * Initialize ELM support. Currently it does only base address init - * and ELM reset. - */ -void elm_init(void) -{ - elm_cfg = (struct elm *)ELM_BASE; - elm_reset(); -} diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 59ad25c..d28fceb 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -48,6 +48,11 @@ static struct vtp_reg *vtpreg[2] = { #ifdef CONFIG_AM33XX static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; #endif +#ifdef CONFIG_AM43XX +static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; +static struct cm_device_inst *cm_device = + (struct cm_device_inst *)CM_DEVICE_INST; +#endif #ifdef CONFIG_TI81XX void config_dmm(const struct dmm_lisa_map_regs *regs) @@ -87,7 +92,7 @@ void __weak ddr_pll_config(unsigned int ddrpll_m) { } -void config_ddr(unsigned int pll, unsigned int ioctrl, +void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr) { @@ -99,7 +104,18 @@ void config_ddr(unsigned int pll, unsigned int ioctrl, config_ddr_data(data, nr); #ifdef CONFIG_AM33XX - config_io_ctrl(ioctrl); + config_io_ctrl(ioregs); + + /* Set CKE to be controlled by EMIF/DDR PHY */ + writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); +#endif +#ifdef CONFIG_AM43XX + writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl); + while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0) + ; + writel(0x0, &ddrctrl->ddrioctrl); + + config_io_ctrl(ioregs); /* Set CKE to be controlled by EMIF/DDR PHY */ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); @@ -108,6 +124,9 @@ void config_ddr(unsigned int pll, unsigned int ioctrl, /* Program EMIF instance */ config_ddr_phy(regs, nr); set_sdram_timings(regs, nr); - config_sdram(regs, nr); + if (get_emif_rev(EMIF1_BASE) == EMIF_4D5) + config_sdram_emif4d5(regs, nr); + else + config_sdram(regs, nr); } #endif diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c index b6eb466..56c9e7d 100644 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -22,17 +22,6 @@ struct gpmc *gpmc_cfg; -#if defined(CONFIG_CMD_NAND) -static const u32 gpmc_m_nand[GPMC_MAX_REG] = { - M_NAND_GPMC_CONFIG1, - M_NAND_GPMC_CONFIG2, - M_NAND_GPMC_CONFIG3, - M_NAND_GPMC_CONFIG4, - M_NAND_GPMC_CONFIG5, - M_NAND_GPMC_CONFIG6, 0 -}; -#endif - void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size) @@ -61,11 +50,34 @@ void gpmc_init(void) { /* putting a blanket check on GPMC based on ZeBu for now */ gpmc_cfg = (struct gpmc *)GPMC_BASE; - -#ifdef CONFIG_CMD_NAND - const u32 *gpmc_config = NULL; - u32 base = 0; +#if defined(CONFIG_NOR) +/* configure GPMC for NOR */ + const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, + STNOR_GPMC_CONFIG2, + STNOR_GPMC_CONFIG3, + STNOR_GPMC_CONFIG4, + STNOR_GPMC_CONFIG5, + STNOR_GPMC_CONFIG6, + STNOR_GPMC_CONFIG7 + }; + u32 size = GPMC_SIZE_16M; + u32 base = CONFIG_SYS_FLASH_BASE; +#elif defined(CONFIG_NAND) +/* configure GPMC for NAND */ + const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, + 0 + }; + u32 size = GPMC_SIZE_256M; + u32 base = CONFIG_SYS_NAND_BASE; +#else + const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 }; u32 size = 0; + u32 base = 0; #endif /* global settings */ writel(0x00000008, &gpmc_cfg->sysconfig); @@ -81,12 +93,6 @@ void gpmc_init(void) */ writel(0, &gpmc_cfg->cs[0].config7); sdelay(1000); - -#ifdef CONFIG_CMD_NAND - gpmc_config = gpmc_m_nand; - - base = PISMO1_NAND_BASE; - size = PISMO1_NAND_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); -#endif + /* enable chip-select specific configurations */ + enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); } diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/cpu/armv7/at91/sama5d3_devices.c index 51f0a6d..78ecfc8 100644 --- a/arch/arm/cpu/armv7/at91/sama5d3_devices.c +++ b/arch/arm/cpu/armv7/at91/sama5d3_devices.c @@ -15,7 +15,7 @@ unsigned int has_emac() { - return cpu_is_sama5d31() || cpu_is_sama5d35(); + return cpu_is_sama5d31() || cpu_is_sama5d35() || cpu_is_sama5d36(); } unsigned int has_gmac() @@ -42,6 +42,8 @@ char *get_cpu_name() return "SAMA5D34"; case ARCH_EXID_SAMA5D35: return "SAMA5D35"; + case ARCH_EXID_SAMA5D36: + return "SAMA5D36"; default: return "Unknown CPU type"; } @@ -82,7 +84,7 @@ void at91_seriald_hw_init(void) at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */ /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_SYS); + at91_periph_clk_enable(ATMEL_ID_DBGU); } #if defined(CONFIG_ATMEL_SPI) diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c index 3808aed..e3ebfe0 100644 --- a/arch/arm/cpu/armv7/at91/timer.c +++ b/arch/arm/cpu/armv7/at91/timer.c @@ -60,7 +60,7 @@ int timer_init(void) at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; /* Enable PITC Clock */ - at91_periph_clk_enable(ATMEL_ID_SYS); + at91_periph_clk_enable(ATMEL_ID_PIT); /* Enable PITC */ writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 36fedd6..84a5047 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -1410,7 +1410,8 @@ void set_mmc_clk(int dev_index, unsigned int div) else { if (proid_is_exynos4412()) exynos4x12_set_mmc_clk(dev_index, div); - exynos4_set_mmc_clk(dev_index, div); + else + exynos4_set_mmc_clk(dev_index, div); } } diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 8002bce..74cc700 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -462,7 +462,7 @@ static int exynos4_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC3: case PERIPH_ID_SDMMC4: - printf("SDMMC device %d not implemented\n", peripheral); + debug("SDMMC device %d not implemented\n", peripheral); return -1; default: debug("%s: invalid peripheral %d", __func__, peripheral); diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c index 3651c00..ade45fd 100644 --- a/arch/arm/cpu/armv7/exynos/spl_boot.c +++ b/arch/arm/cpu/armv7/exynos/spl_boot.c @@ -10,8 +10,11 @@ #include <asm/arch/clock.h> #include <asm/arch/clk.h> #include <asm/arch/dmc.h> +#include <asm/arch/periph.h> +#include <asm/arch/pinmux.h> #include <asm/arch/power.h> #include <asm/arch/spl.h> +#include <asm/arch/spi.h> #include "common_setup.h" #include "clock_init.h" @@ -59,6 +62,121 @@ static int config_branch_prediction(int set_cr_z) } #endif +#ifdef CONFIG_SPI_BOOTING +static void spi_rx_tx(struct exynos_spi *regs, int todo, + void *dinp, void const *doutp, int i) +{ + uint *rxp = (uint *)(dinp + (i * (32 * 1024))); + int rx_lvl, tx_lvl; + uint out_bytes, in_bytes; + + out_bytes = todo; + in_bytes = todo; + setbits_le32(®s->ch_cfg, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_CH_RST); + writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt); + + while (in_bytes) { + uint32_t spi_sts; + int temp; + + spi_sts = readl(®s->spi_sts); + rx_lvl = ((spi_sts >> 15) & 0x7f); + tx_lvl = ((spi_sts >> 6) & 0x7f); + while (tx_lvl < 32 && out_bytes) { + temp = 0xffffffff; + writel(temp, ®s->tx_data); + out_bytes -= 4; + tx_lvl += 4; + } + while (rx_lvl >= 4 && in_bytes) { + temp = readl(®s->rx_data); + if (rxp) + *rxp++ = temp; + in_bytes -= 4; + rx_lvl -= 4; + } + } +} + +/* + * Copy uboot from spi flash to RAM + * + * @parma uboot_size size of u-boot to copy + * @param uboot_addr address in u-boot to copy + */ +static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr) +{ + int upto, todo; + int i, timeout = 100; + struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE; + + set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ + /* set the spi1 GPIO */ + exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); + + /* set pktcnt and enable it */ + writel(4 | SPI_PACKET_CNT_EN, ®s->pkt_cnt); + /* set FB_CLK_SEL */ + writel(SPI_FB_DELAY_180, ®s->fb_clk); + /* set CH_WIDTH and BUS_WIDTH as word */ + setbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | + SPI_MODE_BUS_WIDTH_WORD); + clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ + + /* clear rx and tx channel if set priveously */ + clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + + setbits_le32(®s->swap_cfg, SPI_RX_SWAP_EN | + SPI_RX_BYTE_SWAP | + SPI_RX_HWORD_SWAP); + + /* do a soft reset */ + setbits_le32(®s->ch_cfg, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_CH_RST); + + /* now set rx and tx channel ON */ + setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); + clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ + + /* Send read instruction (0x3h) followed by a 24 bit addr */ + writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, ®s->tx_data); + + /* waiting for TX done */ + while (!(readl(®s->spi_sts) & SPI_ST_TX_DONE)) { + if (!timeout) { + debug("SPI TIMEOUT\n"); + break; + } + timeout--; + } + + for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) { + todo = min(uboot_size - upto, (1 << 15)); + spi_rx_tx(regs, todo, (void *)(uboot_addr), + (void *)(SPI_FLASH_UBOOT_POS), i); + } + + setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ + + /* + * Let put controller mode to BYTE as + * SPI driver does not support WORD mode yet + */ + clrbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | + SPI_MODE_BUS_WIDTH_WORD); + writel(0, ®s->swap_cfg); + + /* + * Flush spi tx, rx fifos and reset the SPI controller + * and clear rx/tx channel + */ + clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); +} +#endif + /* * Copy U-boot from mmc to RAM: * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains @@ -70,6 +188,9 @@ void copy_uboot_to_ram(void) u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL; u32 offset = 0, size = 0; +#ifdef CONFIG_SPI_BOOTING + struct spl_machine_param *param = spl_get_machine_params(); +#endif #ifdef CONFIG_SUPPORT_EMMC_BOOT u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst); void (*end_bootop_from_emmc)(void); @@ -91,9 +212,8 @@ void copy_uboot_to_ram(void) switch (bootmode) { #ifdef CONFIG_SPI_BOOTING case BOOT_MODE_SERIAL: - offset = SPI_FLASH_UBOOT_POS; - size = CONFIG_BL2_SIZE; - copy_bl2 = get_irom_func(SPI_INDEX); + /* Customised function to copy u-boot from SF */ + exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE); break; #endif case BOOT_MODE_MMC: diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 24b4c18..6367e09 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -14,6 +14,7 @@ .arch_extension sec .arch_extension virt + .align 5 /* the vector table for secure state and HYP mode */ _monitor_vectors: .word 0 /* reset */ @@ -32,7 +33,6 @@ _monitor_vectors: * to non-secure state. * We use only r0 and r1 here, due to constraints in the caller. */ - .align 5 _secure_monitor: mrc p15, 0, r1, c1, c1, 0 @ read SCR bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 4d3a165..59f5352 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -17,6 +17,11 @@ obj-y += vc.o obj-y += abb.o endif +ifneq ($(CONFIG_OMAP54XX),) +obj-y += pipe3-phy.o +obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o +endif + ifeq ($(CONFIG_OMAP34XX),) obj-y += boot-common.o obj-y += lowlevel_init.o diff --git a/arch/arm/cpu/armv7/omap-common/abb.c b/arch/arm/cpu/armv7/omap-common/abb.c index a46783f..423aeb9 100644 --- a/arch/arm/cpu/armv7/omap-common/abb.c +++ b/arch/arm/cpu/armv7/omap-common/abb.c @@ -11,6 +11,7 @@ #include <common.h> #include <asm/omap_common.h> +#include <asm/arch/clock.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index bb77b5c..dfa3760 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -779,7 +779,8 @@ void gpi2c_init(void) static int gpi2c = 1; if (gpi2c) { - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, + CONFIG_SYS_OMAP24_I2C_SLAVE); gpi2c = 0; } } diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index b0e1caa..cd6289b 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -50,20 +50,6 @@ inline u32 emif_num(u32 base) return 0; } -/* - * Get SDRAM type connected to EMIF. - * Assuming similar SDRAM parts are connected to both EMIF's - * which is typically the case. So it is sufficient to get - * SDRAM type from EMIF1. - */ -u32 emif_sdram_type() -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; - - return (readl(&emif->emif_sdram_config) & - EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; -} - static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) { u32 mr; @@ -206,7 +192,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) } } -static void ddr3_leveling(u32 base, const struct emif_regs *regs) +static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; @@ -217,47 +203,86 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs) /* * Set invert_clkout (if activated)--DDR_PHYCTRL_1 - * Invert clock adds an additional half cycle delay on the command - * interface. The additional half cycle, is usually meant to enable - * leveling in the situation that DQS is later than CK on the board.It - * also helps provide some additional margin for leveling. + * Invert clock adds an additional half cycle delay on the + * command interface. The additional half cycle, is usually + * meant to enable leveling in the situation that DQS is later + * than CK on the board.It also helps provide some additional + * margin for leveling. */ - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + writel(regs->emif_ddr_phy_ctlr_1, + &emif->emif_ddr_phy_ctrl_1); + + writel(regs->emif_ddr_phy_ctlr_1, + &emif->emif_ddr_phy_ctrl_1_shdw); __udelay(130); writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT) - & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); + & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); /* Launch Full leveling */ writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); /* Wait till full leveling is complete */ readl(&emif->emif_rd_wr_lvl_ctl); - __udelay(130); + __udelay(130); /* Read data eye leveling no of samples */ config_data_eye_leveling_samples(base); - /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */ - writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl); + /* + * Launch 8 incremental WR_LVL- to compensate for + * PHY limitation. + */ + writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, + &emif->emif_rd_wr_lvl_ctl); + __udelay(130); /* Launch Incremental leveling */ writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl); - __udelay(130); + __udelay(130); } -static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs) +static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + u32 fifo_reg; + + fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1); + writel(fifo_reg | 0x00000100, + &emif->emif_ddr_fifo_misaligned_clear_1); + + fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2); + writel(fifo_reg | 0x00000100, + &emif->emif_ddr_fifo_misaligned_clear_2); + + /* Launch Full leveling */ + writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); + + /* Wait till full leveling is complete */ + readl(&emif->emif_rd_wr_lvl_ctl); + __udelay(130); + + /* Read data eye leveling no of samples */ config_data_eye_leveling_samples(base); - writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); - writel(regs->sdram_config, &emif->emif_sdram_config); + /* + * Disable leveling. This is because if leveling is kept + * enabled, then PHY triggers a false leveling during + * EMIF-idle scenario which results in wrong delay + * values getting updated. After this the EMIF becomes + * unaccessible. So disable it after the first time + */ + writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl); +} + +static void ddr3_leveling(u32 base, const struct emif_regs *regs) +{ + if (is_omap54xx()) + omap5_ddr3_leveling(base, regs); + else + dra7_ddr3_leveling(base, regs); } static void ddr3_init(u32 base, const struct emif_regs *regs) @@ -270,9 +295,6 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) * defined, contents of mode Registers must be fully initialized. * H/W takes care of this initialization */ - writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); - writel(regs->sdram_config_init, &emif->emif_sdram_config); - writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); /* Update timing registers */ @@ -283,15 +305,24 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); - do_ext_phy_settings(base, regs); + /* + * The same sequence should work on OMAP5432 as well. But strange that + * it is not working + */ + if (omap_revision() == DRA752_ES1_0) { + do_ext_phy_settings(base, regs); + writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); + writel(regs->sdram_config_init, &emif->emif_sdram_config); + } else { + writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); + writel(regs->sdram_config_init, &emif->emif_sdram_config); + do_ext_phy_settings(base, regs); + } /* enable leveling */ writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); - if (omap_revision() == DRA752_ES1_0) - ddr3_sw_leveling(base, regs); - else - ddr3_leveling(base, regs); + ddr3_leveling(base, regs); } #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS @@ -1079,10 +1110,7 @@ static void do_sdram_init(u32 base) if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) { set_lpmode_selfrefresh(base); emif_reset_phy(base); - if (omap_revision() == DRA752_ES1_0) - ddr3_sw_leveling(base, regs); - else - ddr3_leveling(base, regs); + ddr3_leveling(base, regs); } /* Write to the shadow registers */ @@ -1244,6 +1272,42 @@ void dmm_init(u32 base) } +static void do_bug0039_workaround(u32 base) +{ + u32 val, i, clkctrl; + struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base; + const struct read_write_regs *bug_00339_regs; + u32 iterations; + u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0]; + u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1; + + if (is_dra7xx()) + phy_status_base++; + + bug_00339_regs = get_bug_regs(&iterations); + + /* Put EMIF in to idle */ + clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl); + __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl); + + /* Copy the phy status registers in to phy ctrl shadow registers */ + for (i = 0; i < iterations; i++) { + val = __raw_readl(phy_status_base + + bug_00339_regs[i].read_reg - 1); + + __raw_writel(val, phy_ctrl_base + + ((bug_00339_regs[i].write_reg - 1) << 1)); + + __raw_writel(val, phy_ctrl_base + + (bug_00339_regs[i].write_reg << 1) - 1); + } + + /* Disable leveling */ + writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl); + + __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl); +} + /* * SDRAM initialization: * SDRAM initialization has two parts: @@ -1319,5 +1383,11 @@ void sdram_init(void) debug("get_ram_size() successful"); } + if (sdram_type == EMIF_SDRAM_TYPE_DDR3 && + (!in_sdram && !warm_reset())) { + do_bug0039_workaround(EMIF1_BASE); + do_bug0039_workaround(EMIF2_BASE); + } + debug("<<sdram_init()\n"); } diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c new file mode 100644 index 0000000..b71d769 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c @@ -0,0 +1,231 @@ +/* + * TI PIPE3 PHY + * + * (C) Copyright 2013 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <sata.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <asm/errno.h> +#include "pipe3-phy.h" + +/* PLLCTRL Registers */ +#define PLL_STATUS 0x00000004 +#define PLL_GO 0x00000008 +#define PLL_CONFIGURATION1 0x0000000C +#define PLL_CONFIGURATION2 0x00000010 +#define PLL_CONFIGURATION3 0x00000014 +#define PLL_CONFIGURATION4 0x00000020 + +#define PLL_REGM_MASK 0x001FFE00 +#define PLL_REGM_SHIFT 9 +#define PLL_REGM_F_MASK 0x0003FFFF +#define PLL_REGM_F_SHIFT 0 +#define PLL_REGN_MASK 0x000001FE +#define PLL_REGN_SHIFT 1 +#define PLL_SELFREQDCO_MASK 0x0000000E +#define PLL_SELFREQDCO_SHIFT 1 +#define PLL_SD_MASK 0x0003FC00 +#define PLL_SD_SHIFT 10 +#define SET_PLL_GO 0x1 +#define PLL_TICOPWDN BIT(16) +#define PLL_LDOPWDN BIT(15) +#define PLL_LOCK 0x2 +#define PLL_IDLE 0x1 + +/* PHY POWER CONTROL Register */ +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE + +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000 +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16 + +#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3 +#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0 + + +#define PLL_IDLE_TIME 100 /* in milliseconds */ +#define PLL_LOCK_TIME 100 /* in milliseconds */ + +static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset) +{ + return __raw_readl(addr + offset); +} + +static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset, + u32 data) +{ + __raw_writel(data, addr + offset); +} + +static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3 + *pipe3) +{ + u32 rate; + struct pipe3_dpll_map *dpll_map = pipe3->dpll_map; + + rate = get_sys_clk_freq(); + + for (; dpll_map->rate; dpll_map++) { + if (rate == dpll_map->rate) + return &dpll_map->params; + } + + printf("%s: No DPLL configuration for %u Hz SYS CLK\n", + __func__, rate); + return NULL; +} + + +static int omap_pipe3_wait_lock(struct omap_pipe3 *phy) +{ + u32 val; + int timeout = PLL_LOCK_TIME; + + do { + mdelay(1); + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); + if (val & PLL_LOCK) + break; + } while (--timeout); + + if (!(val & PLL_LOCK)) { + printf("%s: DPLL failed to lock\n", __func__); + return -EBUSY; + } + + return 0; +} + +static int omap_pipe3_dpll_program(struct omap_pipe3 *phy) +{ + u32 val; + struct pipe3_dpll_params *dpll_params; + + dpll_params = omap_pipe3_get_dpll_params(phy); + if (!dpll_params) { + printf("%s: Invalid DPLL parameters\n", __func__); + return -EINVAL; + } + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); + val &= ~PLL_REGN_MASK; + val |= dpll_params->n << PLL_REGN_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); + val &= ~PLL_SELFREQDCO_MASK; + val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); + val &= ~PLL_REGM_MASK; + val |= dpll_params->m << PLL_REGM_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); + val &= ~PLL_REGM_F_MASK; + val |= dpll_params->mf << PLL_REGM_F_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); + val &= ~PLL_SD_MASK; + val |= dpll_params->sd << PLL_SD_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); + + omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); + + return omap_pipe3_wait_lock(phy); +} + +static void omap_control_phy_power(struct omap_pipe3 *phy, int on) +{ + u32 val, rate; + + val = readl(phy->power_reg); + + rate = get_sys_clk_freq(); + rate = rate/1000000; + + if (on) { + val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK); + val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON << + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; + val |= rate << + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; + } else { + val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; + val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF << + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; + } + + writel(val, phy->power_reg); +} + +int phy_pipe3_power_on(struct omap_pipe3 *phy) +{ + int ret; + u32 val; + + /* Program the DPLL only if not locked */ + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); + if (!(val & PLL_LOCK)) { + ret = omap_pipe3_dpll_program(phy); + if (ret) + return ret; + } else { + /* else just bring it out of IDLE mode */ + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); + if (val & PLL_IDLE) { + val &= ~PLL_IDLE; + omap_pipe3_writel(phy->pll_ctrl_base, + PLL_CONFIGURATION2, val); + ret = omap_pipe3_wait_lock(phy); + if (ret) + return ret; + } + } + + /* Power up the PHY */ + omap_control_phy_power(phy, 1); + + return 0; +} + +int phy_pipe3_power_off(struct omap_pipe3 *phy) +{ + u32 val; + int timeout = PLL_IDLE_TIME; + + /* Power down the PHY */ + omap_control_phy_power(phy, 0); + + /* Put DPLL in IDLE mode */ + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); + val |= PLL_IDLE; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); + + /* wait for LDO and Oscillator to power down */ + do { + mdelay(1); + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); + if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) + break; + } while (--timeout); + + if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { + printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n", + __func__, val); + return -EBUSY; + } + + return 0; +} + diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.h b/arch/arm/cpu/armv7/omap-common/pipe3-phy.h new file mode 100644 index 0000000..441f49a --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/pipe3-phy.h @@ -0,0 +1,36 @@ +/* + * TI PIPE3 PHY + * + * (C) Copyright 2013 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OMAP_PIPE3_PHY_H +#define __OMAP_PIPE3_PHY_H + +struct pipe3_dpll_params { + u16 m; + u8 n; + u8 freq:3; + u8 sd; + u32 mf; +}; + +struct pipe3_dpll_map { + unsigned long rate; + struct pipe3_dpll_params params; +}; + +struct omap_pipe3 { + void __iomem *pll_ctrl_base; + void __iomem *power_reg; + struct pipe3_dpll_map *dpll_map; +}; + + +int phy_pipe3_power_on(struct omap_pipe3 *phy); +int phy_pipe3_power_off(struct omap_pipe3 *pipe3); + +#endif /* __OMAP_PIPE3_PHY_H */ diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c new file mode 100644 index 0000000..f5468c4 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/sata.c @@ -0,0 +1,75 @@ +/* + * TI SATA platform driver + * + * (C) Copyright 2013 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <ahci.h> +#include <scsi.h> +#include <asm/arch/clock.h> +#include <asm/arch/sata.h> +#include <asm/io.h> +#include "pipe3-phy.h" + +static struct pipe3_dpll_map dpll_map_sata[] = { + {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */ + {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */ + {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ + {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */ + {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */ + {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */ + { }, /* Terminator */ +}; + +struct omap_pipe3 sata_phy = { + .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE, + /* .power_reg is updated at runtime */ + .dpll_map = dpll_map_sata, +}; + +int omap_sata_init(void) +{ + int ret; + u32 val; + + u32 const clk_domains_sata[] = { + 0 + }; + + u32 const clk_modules_hw_auto_sata[] = { + (*prcm)->cm_l3init_ocp2scp3_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_sata[] = { + (*prcm)->cm_l3init_sata_clkctrl, + 0 + }; + + do_enable_clocks(clk_domains_sata, + clk_modules_hw_auto_sata, + clk_modules_explicit_en_sata, + 0); + + /* Enable optional functional clock for SATA */ + setbits_le32((*prcm)->cm_l3init_sata_clkctrl, + SATA_CLKCTRL_OPTFCLKEN_MASK); + + sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata; + + /* Power up the PHY */ + phy_pipe3_power_on(&sata_phy); + + /* Enable SATA module, No Idle, No Standby */ + val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO; + writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG); + + ret = ahci_init(DWC_AHSATA_BASE); + scsi_scan(1); + + return ret; +} diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds index 5e93b34..02aa129 100644 --- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds @@ -33,6 +33,11 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*_i2c_*))); + } >.sram + + . = ALIGN(4); __image_copy_end = .; _end = .; diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 7d1f8d9..2922816 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -98,7 +98,7 @@ void spl_board_init(void) gpmc_init(); #endif #ifdef CONFIG_SPL_I2C_SUPPORT - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif } #endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 9f989ff..1bc27bd 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -708,7 +708,7 @@ void per_clocks_enable(void) sr32(&prcm_base->iclken_per, 17, 1, 1); #endif -#ifdef CONFIG_DRIVER_OMAP34XX_I2C +#ifdef CONFIG_SYS_I2C_OMAP34XX /* Turn on all 3 I2C clocks */ sr32(&prcm_base->fclken1_core, 15, 3, 0x7); sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */ @@ -730,8 +730,6 @@ void per_clocks_enable(void) sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON); sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON); } - sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON); - sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON); sdelay(1000); } diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 6a225c8..1b2f439 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -288,17 +288,21 @@ struct vcores_data omap4460_volts = { .mm.pmic = &twl6030, }; +/* + * Take closest integer part of the mV value corresponding to a TWL6032 SMPS + * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7. + */ struct vcores_data omap4470_volts = { - .mpu.value = 1200, + .mpu.value = 1202, .mpu.addr = SMPS_REG_ADDR_SMPS1, .mpu.pmic = &twl6030, .core.value = 1126, - .core.addr = SMPS_REG_ADDR_SMPS1, + .core.addr = SMPS_REG_ADDR_SMPS2, .core.pmic = &twl6030, - .mm.value = 1137, - .mm.addr = SMPS_REG_ADDR_SMPS1, + .mm.value = 1139, + .mm.addr = SMPS_REG_ADDR_SMPS5, .mm.pmic = &twl6030, }; diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index e4c8316..6903696 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -32,7 +32,7 @@ #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -static const struct emif_regs emif_regs_elpida_200_mhz_2cs = { +const struct emif_regs emif_regs_elpida_200_mhz_2cs = { .sdram_config_init = 0x80000eb9, .sdram_config = 0x80001ab9, .ref_ctrl = 0x0000030c, @@ -46,7 +46,7 @@ static const struct emif_regs emif_regs_elpida_200_mhz_2cs = { .emif_ddr_phy_ctlr_1 = 0x049ff808 }; -static const struct emif_regs emif_regs_elpida_380_mhz_1cs = { +const struct emif_regs emif_regs_elpida_380_mhz_1cs = { .sdram_config_init = 0x80000eb1, .sdram_config = 0x80001ab1, .ref_ctrl = 0x000005cd, @@ -321,3 +321,8 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) { *regs = &mr_regs; } + +__weak const struct read_write_regs *get_bug_regs(u32 *iterations) +{ + return 0; +} diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index a1b249e..5268a1f 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -39,17 +39,6 @@ static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; -/* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */ -static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = { - {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - /* OPP NOM FREQUENCY for ES1.0 */ static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -83,6 +72,7 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; +/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */ static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ @@ -169,13 +159,13 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { }; static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { - {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ + {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */ {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */ - {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ - {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ - {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ + {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */ + {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ }; static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { @@ -272,7 +262,7 @@ struct dplls omap5_dplls_es1 = { }; struct dplls omap5_dplls_es2 = { - .mpu = mpu_dpll_params_1100mhz, + .mpu = mpu_dpll_params_1ghz, .core = core_dpll_params_2128mhz_ddr532_es2, .per = per_dpll_params_768mhz_es2, .iva = iva_dpll_params_2330mhz, @@ -600,6 +590,7 @@ const struct ctrl_ioregs ioregs_omap5432_es1 = { .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE, .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE, .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, + .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, }; const struct ctrl_ioregs ioregs_omap5432_es2 = { @@ -610,16 +601,18 @@ const struct ctrl_ioregs ioregs_omap5432_es2 = { .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2, .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2, .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, + .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, }; const struct ctrl_ioregs ioregs_dra7xx_es1 = { .ctrl_ddrch = 0x40404040, .ctrl_lpddr2ch = 0x40404040, .ctrl_ddr3ch = 0x80808080, - .ctrl_ddrio_0 = 0xbae8c631, - .ctrl_ddrio_1 = 0xb46318d8, + .ctrl_ddrio_0 = 0xA2084210, + .ctrl_ddrio_1 = 0x84210840, .ctrl_ddrio_2 = 0x84210000, - .ctrl_emif_sdram_config_ext = 0xb2c00000, + .ctrl_emif_sdram_config_ext = 0x0001C1A7, + .ctrl_emif_sdram_config_ext_final = 0x000101A7, .ctrl_ddr_ctrl_ext_0 = 0xA2000000, }; diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 1065891..5386ae0 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -168,12 +168,6 @@ void do_io_settings(void) io_settings_lpddr2(); else io_settings_ddr3(); - - /* Efuse settings */ - writel(EFUSE_1, (*ctrl)->control_efuse_1); - writel(EFUSE_2, (*ctrl)->control_efuse_2); - writel(EFUSE_3, (*ctrl)->control_efuse_3); - writel(EFUSE_4, (*ctrl)->control_efuse_4); } static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = { @@ -297,13 +291,17 @@ void srcomp_enable(void) void config_data_eye_leveling_samples(u32 emif_base) { + const struct ctrl_ioregs *ioregs; + + get_ioregs(&ioregs); + /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/ if (emif_base == EMIF1_BASE) - writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, - (*ctrl)->control_emif1_sdram_config_ext); + writel(ioregs->ctrl_emif_sdram_config_ext_final, + (*ctrl)->control_emif1_sdram_config_ext); else if (emif_base == EMIF2_BASE) - writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, - (*ctrl)->control_emif2_sdram_config_ext); + writel(ioregs->ctrl_emif_sdram_config_ext_final, + (*ctrl)->control_emif2_sdram_config_ext); } void init_omap_revision(void) diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 304ac1c..77c428b 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -203,8 +203,10 @@ struct prcm_regs const omap5_es1_prcm = { .cm_l3init_hsusbotg_clkctrl = 0x4a009360, .cm_l3init_hsusbtll_clkctrl = 0x4a009368, .cm_l3init_p1500_clkctrl = 0x4a009378, + .cm_l3init_sata_clkctrl = 0x4a009388, .cm_l3init_fsusb_clkctrl = 0x4a0093d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, + .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, /* cm2.l4per */ .cm_l4per_clkstctrl = 0x4a009400, @@ -296,6 +298,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { .control_status = 0x4A002134, .control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4, .control_phy_power_usb = 0x4A002370, + .control_phy_power_sata = 0x4A002374, .control_padconf_core_base = 0x4A002800, .control_paconf_global = 0x4A002DA0, .control_paconf_mode = 0x4A002DA4, @@ -373,6 +376,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_status = 0x4A002134, + .control_phy_power_sata = 0x4A002374, .control_core_mac_id_0_lo = 0x4A002514, .control_core_mac_id_0_hi = 0x4A002518, .control_core_mac_id_1_lo = 0x4A00251C, @@ -698,6 +702,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_l3init_hsusbotg_clkctrl = 0x4a009660, .cm_l3init_hsusbtll_clkctrl = 0x4a009668, .cm_l3init_p1500_clkctrl = 0x4a009678, + .cm_l3init_sata_clkctrl = 0x4a009688, .cm_l3init_fsusb_clkctrl = 0x4a0096d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8, @@ -891,9 +896,11 @@ struct prcm_regs const dra7xx_prcm = { .cm_l3init_hsusbhost_clkctrl = 0x4a009340, .cm_l3init_hsusbotg_clkctrl = 0x4a009348, .cm_l3init_hsusbtll_clkctrl = 0x4a009350, + .cm_l3init_sata_clkctrl = 0x4a009388, .cm_gmac_clkstctrl = 0x4a0093c0, .cm_gmac_gmac_clkctrl = 0x4a0093d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, + .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, /* cm2.l4per */ .cm_l4per_clkstctrl = 0x4a009700, diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index e65c116..2e18706 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -148,13 +148,13 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0E20400A, - .emif_ddr_phy_ctlr_1 = 0x0E24400A, - .emif_ddr_ext_phy_ctrl_1 = 0x04040100, - .emif_ddr_ext_phy_ctrl_2 = 0x009E009E, - .emif_ddr_ext_phy_ctrl_3 = 0x009E009E, - .emif_ddr_ext_phy_ctrl_4 = 0x009E009E, - .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, + .emif_ddr_phy_ctlr_1_init = 0x0024400A, + .emif_ddr_phy_ctlr_1 = 0x0024400A, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00B000B0, + .emif_ddr_ext_phy_ctrl_3 = 0x00B000B0, + .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, + .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, .emif_rd_wr_lvl_rmp_win = 0x00000000, .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, @@ -172,13 +172,13 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0020400A, - .emif_ddr_phy_ctlr_1 = 0x0E24400A, - .emif_ddr_ext_phy_ctrl_1 = 0x04040100, - .emif_ddr_ext_phy_ctrl_2 = 0x009D009D, - .emif_ddr_ext_phy_ctrl_3 = 0x009D009D, - .emif_ddr_ext_phy_ctrl_4 = 0x009D009D, - .emif_ddr_ext_phy_ctrl_5 = 0x009D009D, + .emif_ddr_phy_ctlr_1_init = 0x0024400A, + .emif_ddr_phy_ctlr_1 = 0x0024400A, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00B000B0, + .emif_ddr_ext_phy_ctrl_3 = 0x00B000B0, + .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, + .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, .emif_rd_wr_lvl_rmp_win = 0x00000000, .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, @@ -306,7 +306,7 @@ void emif_get_device_details(u32 emif_nr, #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ -const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { +const u32 ext_phy_ctrl_const_base[] = { 0x01004010, 0x00001004, 0x04010040, @@ -329,7 +329,7 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x0 }; -const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { +const u32 ddr3_ext_phy_ctrl_const_base_es1[] = { 0x01004010, 0x00001004, 0x04010040, @@ -352,7 +352,7 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x0 }; -const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { +const u32 ddr3_ext_phy_ctrl_const_base_es2[] = { 0x50D4350D, 0x00000D43, 0x04010040, @@ -376,51 +376,61 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { }; const u32 -dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = { - 0x009E009E, - 0x002E002E, - 0x002E002E, - 0x002E002E, - 0x002E002E, - 0x002E002E, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x0, - 0x600020, +dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { + 0x00B000B0, + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040, + 0x00800080, + 0x00800080, + 0x00800080, + 0x00800080, + 0x00800080, + 0x00600060, + 0x00600060, + 0x00600060, + 0x00600060, + 0x00600060, + 0x00800080, + 0x00800080, 0x40010080, - 0x8102040 + 0x08102040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 }; const u32 -dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = { - 0x009D009D, - 0x002D002D, - 0x002D002D, - 0x002D002D, - 0x002D002D, - 0x002D002D, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, +dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { + 0x00BB00BB, + 0x00440044, + 0x00440044, + 0x00440044, + 0x00440044, + 0x00440044, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x00600060, + 0x00600060, + 0x00600060, + 0x00600060, + 0x00600060, 0x0, - 0x600020, + 0x00600020, 0x40010080, - 0x8102040 + 0x08102040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 }; const struct lpddr2_mr_regs mr_regs = { @@ -431,27 +441,38 @@ const struct lpddr2_mr_regs mr_regs = { .mr16 = MR16_REF_FULL_ARRAY }; -static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs) +static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, + const u32 **regs, + u32 *size) { switch (omap_revision()) { case OMAP5430_ES1_0: case OMAP5430_ES2_0: *regs = ext_phy_ctrl_const_base; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base); break; case OMAP5432_ES1_0: *regs = ddr3_ext_phy_ctrl_const_base_es1; + *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1); break; case OMAP5432_ES2_0: *regs = ddr3_ext_phy_ctrl_const_base_es2; + *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2); break; case DRA752_ES1_0: - if (emif_nr == 1) + if (emif_nr == 1) { *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1; - else + *size = + ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1); + } else { *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2; + *size = + ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2); + } break; default: *regs = ddr3_ext_phy_ctrl_const_base_es2; + *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2); } } @@ -468,6 +489,7 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) u32 emif_nr; const u32 *ext_phy_ctrl_const_regs; u32 i = 0; + u32 size; emif_nr = (base == EMIF1_BASE) ? 1 : 2; @@ -487,8 +509,10 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) * external phy 6-24 registers do not change with * ddr frequency */ - emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs); - for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { + emif_get_ext_phy_ctrl_const_regs(emif_nr, + &ext_phy_ctrl_const_regs, &size); + + for (i = 0; i < size; i++) { writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); /* Update shadow registers */ @@ -545,6 +569,74 @@ static const struct lpddr2_device_timings dev_4G_S4_timings = { .min_tck = &min_tck, }; +/* + * List of status registers to be controlled back to control registers + * after initial leveling + * readreg, writereg + */ +const struct read_write_regs omap5_bug_00339_regs[] = { + { 8, 5 }, + { 9, 6 }, + { 10, 7 }, + { 14, 8 }, + { 15, 9 }, + { 16, 10 }, + { 11, 2 }, + { 12, 3 }, + { 13, 4 }, + { 17, 11 }, + { 18, 12 }, + { 19, 13 }, +}; + +const struct read_write_regs dra_bug_00339_regs[] = { + { 7, 7 }, + { 8, 8 }, + { 9, 9 }, + { 10, 10 }, + { 11, 11 }, + { 12, 2 }, + { 13, 3 }, + { 14, 4 }, + { 15, 5 }, + { 16, 6 }, + { 17, 12 }, + { 18, 13 }, + { 19, 14 }, + { 20, 15 }, + { 21, 16 }, + { 22, 17 }, + { 23, 18 }, + { 24, 19 }, + { 25, 20 }, + { 26, 21} +}; + +const struct read_write_regs *get_bug_regs(u32 *iterations) +{ + const struct read_write_regs *bug_00339_regs_ptr = NULL; + + switch (omap_revision()) { + case OMAP5430_ES1_0: + case OMAP5430_ES2_0: + case OMAP5432_ES1_0: + case OMAP5432_ES2_0: + bug_00339_regs_ptr = omap5_bug_00339_regs; + *iterations = sizeof(omap5_bug_00339_regs)/ + sizeof(omap5_bug_00339_regs[0]); + break; + case DRA752_ES1_0: + bug_00339_regs_ptr = dra_bug_00339_regs; + *iterations = sizeof(dra_bug_00339_regs)/ + sizeof(dra_bug_00339_regs[0]); + break; + default: + printf("\n Error: UnKnown SOC"); + } + + return bug_00339_regs_ptr; +} + void emif_get_device_timings_sdp(u32 emif_nr, const struct lpddr2_device_timings **cs0_device_timings, const struct lpddr2_device_timings **cs1_device_timings) diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile index 8f4cf3a..2221999 100644 --- a/arch/arm/cpu/armv7/rmobile/Makefile +++ b/arch/arm/cpu/armv7/rmobile/Makefile @@ -5,20 +5,13 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y = lowlevel_init.o -obj-y += cpu_info.o +obj-y = cpu_info.o obj-y += emac.o obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o obj-$(CONFIG_GLOBAL_TIMER) += timer.o -obj-$(CONFIG_R8A7740) += cpu_info-r8a7740.o -obj-$(CONFIG_R8A7740) += pfc-r8a7740.o -obj-$(CONFIG_SH73A0) += cpu_info-sh73a0.o -obj-$(CONFIG_SH73A0) += pfc-sh73a0.o -obj-$(CONFIG_TMU_TIMER) += sh_timer.o - -SRCS += $(obj)sh_timer.c -# from arch/sh/lib/ directory -$(obj)sh_timer.c: - @rm -f $(obj)sh_timer.c - ln -s $(SRCTREE)/arch/sh/lib/time.c $(obj)sh_timer.c +obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o +obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o +obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o +obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o +obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o diff --git a/arch/arm/cpu/armv7/rmobile/config.mk b/arch/arm/cpu/armv7/rmobile/config.mk deleted file mode 100644 index 3a36ab6..0000000 --- a/arch/arm/cpu/armv7/rmobile/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# Make ARMv5 to allow more compilers to work, even though its v7a. -PLATFORM_CPPFLAGS += -march=armv5 diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c new file mode 100644 index 0000000..7232e23 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c @@ -0,0 +1,22 @@ +/* + * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c + * This file is r8a7790 processor support. + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ +#include <common.h> +#include <asm/io.h> + +#define PRR 0xFF000044 + +u32 rmobile_get_cpu_type(void) +{ + return (readl(PRR) & 0x00007F00) >> 8; +} + +u32 rmobile_get_cpu_rev_integer(void) +{ + return (readl(PRR) & 0x000000F0) >> 4; +} diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c new file mode 100644 index 0000000..2de58ed --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c @@ -0,0 +1,29 @@ +/* + * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ +#include <common.h> +#include <asm/io.h> + +#define PRR 0xFF000044 + +u32 rmobile_get_cpu_type(void) +{ + u32 product; + + product = readl(PRR); + + return (u32)((product & 0x00007F00) >> 8); +} + +u32 rmobile_get_cpu_rev_integer(void) +{ + u32 product; + + product = readl(PRR); + + return (u32)((product & 0x000000F0) >> 4); +} diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c index 07a33fb..83d5282 100644 --- a/arch/arm/cpu/armv7/rmobile/cpu_info.c +++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c @@ -58,6 +58,16 @@ int print_cpuinfo(void) rmobile_get_cpu_rev_fraction()); break; + case 0x45: + printf("CPU: Renesas Electronics R8A7790 rev %d\n", + rmobile_get_cpu_rev_integer()); + break; + + case 0x47: + printf("CPU: Renesas Electronics R8A7791 rev %d\n", + rmobile_get_cpu_rev_integer()); + break; + default: printf("CPU: Renesas Electronics CPU rev %d.%d\n", rmobile_get_cpu_rev_integer(), diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S new file mode 100644 index 0000000..e07cc80 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S @@ -0,0 +1,60 @@ +/* + * arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S + * This file is lager low level initialize. + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <config.h> +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + mrc p15, 0, r4, c0, c0, 5 /* mpidr */ + orr r4, r4, r4, lsr #6 + and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */ + + b do_lowlevel_init + + .pool + +/* + * CPU ID #1-#3 come here + */ + .align 4 +do_cpu_waiting: + ldr r1, =0xe6180000 /* sysc */ +1: ldr r0, [r1, #0x20] /* sbar */ + tst r0, r0 + beq 1b + bx r0 + +/* + * Only CPU ID #0 comes here + */ + .align 4 +do_lowlevel_init: + /* surpress wfe if ca15 */ + tst r4, #4 + mrceq p15, 0, r0, c1, c0, 1 /* actlr */ + orreq r0, r0, #(1<<7) + mcreq p15, 0, r0, c1, c0, 1 + /* and set l2 latency */ + mrceq p15, 1, r0, c9, c0, 2 /* l2ctlr */ + orreq r0, r0, #0x00000800 + orreq r0, r0, #0x00000003 + mcreq p15, 1, r0, c9, c0, 2 + + ldr r3, =(CONFIG_SYS_INIT_SP_ADDR) + sub sp, r3, #4 + str lr, [sp] + + /* initialize system */ + bl s_init + + ldr lr, [sp] + mov pc, lr + nop +ENDPROC(lowlevel_init) + .ltorg diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c new file mode 100644 index 0000000..1259062 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c @@ -0,0 +1,829 @@ +/* + * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c + * This file is r8a7790 processor support - PFC hardware block. + * + * Copy from linux-kernel:drivers/pinctrl/sh-pfc/pfc-r8a7790.c + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Magnus Damm + * Copyright (C) 2012 Renesas Solutions Corp. + * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <sh_pfc.h> +#include <asm/gpio.h> +#include "pfc-r8a7790.h" + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + GP_ALL(IN), + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12, + FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27, + FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12, + FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26, + FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9, + FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22, + FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8, + FN_IP3_14_12, FN_IP3_17_15, + + /* GPSR1 */ + FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26, + FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9, + FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21, + FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6, + FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18, + FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0, + FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11, + + /* GPSR2 */ + FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, + FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14, + FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22, + FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7, + FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23, + FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6, + FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13, + + /* GPSR3 */ + FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4, + FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18, + FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26, + FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11, + FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26, + FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9, + FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18, + + /* GPSR4 */ + FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30, + FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8, + FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20, + FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0, + FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13, + FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26, + FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9, + FN_IP14_15_12, FN_IP14_18_16, + + /* GPSR5 */ + FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28, + FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12, + FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20, + FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0, + FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7, + FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0, + FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22, + + /* IPSR0 - IPSR5 */ + /* IPSR6 */ + FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, + FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, + FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, + FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, + FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, + FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, + FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, + FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, + FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, + FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER, + FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, + FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0, + FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, + FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, + FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, + FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, + FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, + FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, + FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, + FN_STP_IVCXO27_1_B, FN_HRX0_F, + + /* IPSR7 */ + FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, + FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, + FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, + FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, + FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC, + FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0, + FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, + FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, + FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, + FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, + FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, + FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C, + FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, + FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN, + FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, + FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, + FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, + FN_MII_RXD2, + + /* IPSR8 - IPSR16 */ + + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIF1_4, + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + FN_SEL_SCIFB1_4, + FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6, + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3, + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + FN_SEL_SOF1_0, FN_SEL_SOF1_1, + FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, + FN_SEL_SSI6_0, FN_SEL_SSI6_1, + FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, + FN_SEL_VI3_0, FN_SEL_VI3_1, + FN_SEL_VI2_0, FN_SEL_VI2_1, + FN_SEL_VI1_0, FN_SEL_VI1_1, + FN_SEL_VI0_0, FN_SEL_VI0_1, + FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, + FN_SEL_LBS_0, FN_SEL_LBS_1, + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + FN_SEL_SOF3_0, FN_SEL_SOF3_1, + FN_SEL_SOF0_0, FN_SEL_SOF0_1, + + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, + FN_SEL_CAN1_0, FN_SEL_CAN1_1, + FN_SEL_ADI_0, FN_SEL_ADI_1, + FN_SEL_SSP_0, FN_SEL_SSP_1, + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, + FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, + FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, + FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, + FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, + FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, + + FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, + FN_SEL_IIC0_0, FN_SEL_IIC0_1, + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + FN_SEL_IIC2_4, + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, + FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, + FN_SEL_I2C2_4, + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, + + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, + VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, + DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, + SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, + INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, + DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, + MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, + SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, + ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK, + TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK, + SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK, + STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, + SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK, + STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, + SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, + RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK, + TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, + RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK, + STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, + ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK, + STP_IVCXO27_1_B_MARK, HRX0_F_MARK, + + ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK, + SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, + RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK, + ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK, + HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK, + SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK, + STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, + ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK, + TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, + SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, + GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, + STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK, + PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, + PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK, + AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, + ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK, + VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, + MII_RXD2_MARK, + + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_IPSR_DATA(IP6_2_0, DACK0), + PINMUX_IPSR_DATA(IP6_2_0, IRQ0), + PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), + PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP6_8_6, DACK1), + PINMUX_IPSR_DATA(IP6_8_6, IRQ1), + PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N), + PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), + PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP6_13_11, DACK2), + PINMUX_IPSR_DATA(IP6_13_11, IRQ2), + PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), + PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4), + PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), + PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4), + PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), + PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), + PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), + PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), + PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5), + + PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), + PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), + PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), + PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), + PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2), + PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), + PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), + PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_18_16, PWM0), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_21_19, PWM1), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N), + PINMUX_IPSR_DATA(IP7_24_22, PWM2), + PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0), + PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), + PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N), + PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN), + PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC), + PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C), + PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), + PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), + PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), + PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), + PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), + PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), + PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2), + +}; + +static struct pinmux_gpio pinmux_gpios[] = { + PINMUX_GPIO_GP_ALL(), + + /*IPSR0 - IPSR5*/ + /*IPSR6*/ + GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N), + GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B), + GPIO_FN(SSI_WS78_C), GPIO_FN(DREQ1_N), GPIO_FN(VI1_CLKENB), + GPIO_FN(VI1_CLKENB_B), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SSI_SCK78_B), + GPIO_FN(DACK1), GPIO_FN(IRQ1), GPIO_FN(INTC_IRQ1_N), GPIO_FN(SSI_WS6_B), + GPIO_FN(SSI_SDATA8_C), GPIO_FN(DREQ2_N), GPIO_FN(HSCK1_B), + GPIO_FN(HCTS0_N_B), GPIO_FN(MSIOF0_TXD_B), GPIO_FN(DACK2), + GPIO_FN(IRQ2), GPIO_FN(INTC_IRQ2_N), GPIO_FN(SSI_SDATA6_B), + GPIO_FN(HRTS0_N_B), GPIO_FN(MSIOF0_RXD_B), GPIO_FN(ETH_CRS_DV), + GPIO_FN(RMII_CRS_DV), GPIO_FN(STP_ISCLK_0_B), GPIO_FN(TS_SDEN0_D), + GPIO_FN(GLO_Q0_C), GPIO_FN(SCL2_E), GPIO_FN(SCL2_CIS_E), + GPIO_FN(ETH_RX_ER), GPIO_FN(RMII_RX_ER), GPIO_FN(STP_ISD_0_B), + GPIO_FN(TS_SPSYNC0_D), GPIO_FN(GLO_Q1_C), GPIO_FN(SDA2_E), + GPIO_FN(SDA2_CIS_E), GPIO_FN(ETH_RXD0), GPIO_FN(RMII_RXD0), + GPIO_FN(STP_ISEN_0_B), GPIO_FN(TS_SDAT0_D), GPIO_FN(GLO_I0_C), + GPIO_FN(SCIFB1_SCK_G), GPIO_FN(SCK1_E), GPIO_FN(ETH_RXD1), + GPIO_FN(RMII_RXD1), GPIO_FN(HRX0_E), GPIO_FN(STP_ISSYNC_0_B), + GPIO_FN(TS_SCK0_D), GPIO_FN(GLO_I1_C), GPIO_FN(SCIFB1_RXD_G), + GPIO_FN(RX1_E), GPIO_FN(ETH_LINK), GPIO_FN(RMII_LINK), GPIO_FN(HTX0_E), + GPIO_FN(STP_IVCXO27_0_B), GPIO_FN(SCIFB1_TXD_G), GPIO_FN(TX1_E), + GPIO_FN(ETH_REF_CLK), GPIO_FN(RMII_REF_CLK), GPIO_FN(HCTS0_N_E), + GPIO_FN(STP_IVCXO27_1_B), GPIO_FN(HRX0_F), + + /*IPSR7*/ + GPIO_FN(ETH_MDIO), GPIO_FN(RMII_MDIO), GPIO_FN(HRTS0_N_E), + GPIO_FN(SIM0_D_C), GPIO_FN(HCTS0_N_F), GPIO_FN(ETH_TXD1), + GPIO_FN(RMII_TXD1), GPIO_FN(HTX0_F), GPIO_FN(BPFCLK_G), + GPIO_FN(RDS_CLK_F), GPIO_FN(ETH_TX_EN), GPIO_FN(RMII_TX_EN), + GPIO_FN(SIM0_CLK_C), GPIO_FN(HRTS0_N_F), GPIO_FN(ETH_MAGIC), + GPIO_FN(RMII_MAGIC), GPIO_FN(SIM0_RST_C), GPIO_FN(ETH_TXD0), + GPIO_FN(RMII_TXD0), GPIO_FN(STP_ISCLK_1_B), GPIO_FN(TS_SDEN1_C), + GPIO_FN(GLO_SCLK_C), GPIO_FN(ETH_MDC), GPIO_FN(RMII_MDC), + GPIO_FN(STP_ISD_1_B), GPIO_FN(TS_SPSYNC1_C), GPIO_FN(GLO_SDATA_C), + GPIO_FN(PWM0), GPIO_FN(SCIFA2_SCK_C), GPIO_FN(STP_ISEN_1_B), + GPIO_FN(TS_SDAT1_C), GPIO_FN(GLO_SS_C), GPIO_FN(PWM1), + GPIO_FN(SCIFA2_TXD_C), GPIO_FN(STP_ISSYNC_1_B), GPIO_FN(TS_SCK1_C), + GPIO_FN(GLO_RFON_C), GPIO_FN(PCMOE_N), GPIO_FN(PWM2), GPIO_FN(PWMFSW0), + GPIO_FN(SCIFA2_RXD_C), GPIO_FN(PCMWE_N), GPIO_FN(IECLK_C), + GPIO_FN(DU1_DOTCLKIN), GPIO_FN(AUDIO_CLKC), GPIO_FN(AUDIO_CLKOUT_C), + GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1), + GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N), + GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2), + /*IPSR8 - IPSR16*/ +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP3_17_15, + GP_0_30_FN, FN_IP3_14_12, + GP_0_29_FN, FN_IP3_11_8, + GP_0_28_FN, FN_IP3_7_4, + GP_0_27_FN, FN_IP3_3_0, + GP_0_26_FN, FN_IP2_28_26, + GP_0_25_FN, FN_IP2_25_22, + GP_0_24_FN, FN_IP2_21_18, + GP_0_23_FN, FN_IP2_17_15, + GP_0_22_FN, FN_IP2_14_12, + GP_0_21_FN, FN_IP2_11_9, + GP_0_20_FN, FN_IP2_8_6, + GP_0_19_FN, FN_IP2_5_3, + GP_0_18_FN, FN_IP2_2_0, + GP_0_17_FN, FN_IP1_29_28, + GP_0_16_FN, FN_IP1_27_26, + GP_0_15_FN, FN_IP1_25_22, + GP_0_14_FN, FN_IP1_21_18, + GP_0_13_FN, FN_IP1_17_15, + GP_0_12_FN, FN_IP1_14_12, + GP_0_11_FN, FN_IP1_11_8, + GP_0_10_FN, FN_IP1_7_4, + GP_0_9_FN, FN_IP1_3_0, + GP_0_8_FN, FN_IP0_30_27, + GP_0_7_FN, FN_IP0_26_23, + GP_0_6_FN, FN_IP0_22_20, + GP_0_5_FN, FN_IP0_19_16, + GP_0_4_FN, FN_IP0_15_12, + GP_0_3_FN, FN_IP0_11_9, + GP_0_2_FN, FN_IP0_8_6, + GP_0_1_FN, FN_IP0_5_3, + GP_0_0_FN, FN_IP0_2_0 } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + GP_1_29_FN, FN_IP6_13_11, + GP_1_28_FN, FN_IP6_10_9, + GP_1_27_FN, FN_IP6_8_6, + GP_1_26_FN, FN_IP6_5_3, + GP_1_25_FN, FN_IP6_2_0, + GP_1_24_FN, FN_IP5_29_27, + GP_1_23_FN, FN_IP5_26_24, + GP_1_22_FN, FN_IP5_23_21, + GP_1_21_FN, FN_IP5_20_18, + GP_1_20_FN, FN_IP5_17_15, + GP_1_19_FN, FN_IP5_14_13, + GP_1_18_FN, FN_IP5_12_10, + GP_1_17_FN, FN_IP5_9_6, + GP_1_16_FN, FN_IP5_5_3, + GP_1_15_FN, FN_IP5_2_0, + GP_1_14_FN, FN_IP4_29_27, + GP_1_13_FN, FN_IP4_26_24, + GP_1_12_FN, FN_IP4_23_21, + GP_1_11_FN, FN_IP4_20_18, + GP_1_10_FN, FN_IP4_17_15, + GP_1_9_FN, FN_IP4_14_12, + GP_1_8_FN, FN_IP4_11_9, + GP_1_7_FN, FN_IP4_8_6, + GP_1_6_FN, FN_IP4_5_3, + GP_1_5_FN, FN_IP4_2_0, + GP_1_4_FN, FN_IP3_31_29, + GP_1_3_FN, FN_IP3_28_26, + GP_1_2_FN, FN_IP3_25_23, + GP_1_1_FN, FN_IP3_22_20, + GP_1_0_FN, FN_IP3_19_18, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + 0, 0, + 0, 0, + GP_2_29_FN, FN_IP7_15_13, + GP_2_28_FN, FN_IP7_12_10, + GP_2_27_FN, FN_IP7_9_8, + GP_2_26_FN, FN_IP7_7_6, + GP_2_25_FN, FN_IP7_5_3, + GP_2_24_FN, FN_IP7_2_0, + GP_2_23_FN, FN_IP6_31_29, + GP_2_22_FN, FN_IP6_28_26, + GP_2_21_FN, FN_IP6_25_23, + GP_2_20_FN, FN_IP6_22_20, + GP_2_19_FN, FN_IP6_19_17, + GP_2_18_FN, FN_IP6_16_14, + GP_2_17_FN, FN_VI1_DATA7_VI1_B7, + GP_2_16_FN, FN_IP8_27, + GP_2_15_FN, FN_IP8_26, + GP_2_14_FN, FN_IP8_25_24, + GP_2_13_FN, FN_IP8_23_22, + GP_2_12_FN, FN_IP8_21_20, + GP_2_11_FN, FN_IP8_19_18, + GP_2_10_FN, FN_IP8_17_16, + GP_2_9_FN, FN_IP8_15_14, + GP_2_8_FN, FN_IP8_13_12, + GP_2_7_FN, FN_IP8_11_10, + GP_2_6_FN, FN_IP8_9_8, + GP_2_5_FN, FN_IP8_7_6, + GP_2_4_FN, FN_IP8_5_4, + GP_2_3_FN, FN_IP8_3_2, + GP_2_2_FN, FN_IP8_1_0, + GP_2_1_FN, FN_IP7_30_29, + GP_2_0_FN, FN_IP7_28_27 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP11_21_18, + GP_3_30_FN, FN_IP11_17_15, + GP_3_29_FN, FN_IP11_14_13, + GP_3_28_FN, FN_IP11_12_11, + GP_3_27_FN, FN_IP11_10_9, + GP_3_26_FN, FN_IP11_8_7, + GP_3_25_FN, FN_IP11_6_5, + GP_3_24_FN, FN_IP11_4, + GP_3_23_FN, FN_IP11_3_0, + GP_3_22_FN, FN_IP10_29_26, + GP_3_21_FN, FN_IP10_25_23, + GP_3_20_FN, FN_IP10_22_19, + GP_3_19_FN, FN_IP10_18_15, + GP_3_18_FN, FN_IP10_14_11, + GP_3_17_FN, FN_IP10_10_7, + GP_3_16_FN, FN_IP10_6_4, + GP_3_15_FN, FN_IP10_3_0, + GP_3_14_FN, FN_IP9_31_28, + GP_3_13_FN, FN_IP9_27_26, + GP_3_12_FN, FN_IP9_25_24, + GP_3_11_FN, FN_IP9_23_22, + GP_3_10_FN, FN_IP9_21_20, + GP_3_9_FN, FN_IP9_19_18, + GP_3_8_FN, FN_IP9_17_16, + GP_3_7_FN, FN_IP9_15_12, + GP_3_6_FN, FN_IP9_11_8, + GP_3_5_FN, FN_IP9_7_6, + GP_3_4_FN, FN_IP9_5_4, + GP_3_3_FN, FN_IP9_3_2, + GP_3_2_FN, FN_IP9_1_0, + GP_3_1_FN, FN_IP8_30_29, + GP_3_0_FN, FN_IP8_28 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP14_18_16, + GP_4_30_FN, FN_IP14_15_12, + GP_4_29_FN, FN_IP14_11_9, + GP_4_28_FN, FN_IP14_8_6, + GP_4_27_FN, FN_IP14_5_3, + GP_4_26_FN, FN_IP14_2_0, + GP_4_25_FN, FN_IP13_30_29, + GP_4_24_FN, FN_IP13_28_26, + GP_4_23_FN, FN_IP13_25_23, + GP_4_22_FN, FN_IP13_22_19, + GP_4_21_FN, FN_IP13_18_16, + GP_4_20_FN, FN_IP13_15_13, + GP_4_19_FN, FN_IP13_12_10, + GP_4_18_FN, FN_IP13_9_7, + GP_4_17_FN, FN_IP13_6_3, + GP_4_16_FN, FN_IP13_2_0, + GP_4_15_FN, FN_IP12_30_28, + GP_4_14_FN, FN_IP12_27_25, + GP_4_13_FN, FN_IP12_24_23, + GP_4_12_FN, FN_IP12_22_20, + GP_4_11_FN, FN_IP12_19_17, + GP_4_10_FN, FN_IP12_16_14, + GP_4_9_FN, FN_IP12_13_11, + GP_4_8_FN, FN_IP12_10_8, + GP_4_7_FN, FN_IP12_7_6, + GP_4_6_FN, FN_IP12_5_4, + GP_4_5_FN, FN_IP12_3_2, + GP_4_4_FN, FN_IP12_1_0, + GP_4_3_FN, FN_IP11_31_30, + GP_4_2_FN, FN_IP11_29_27, + GP_4_1_FN, FN_IP11_26_24, + GP_4_0_FN, FN_IP11_23_22 } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + GP_5_31_FN, FN_IP7_24_22, + GP_5_30_FN, FN_IP7_21_19, + GP_5_29_FN, FN_IP7_18_16, + GP_5_28_FN, FN_DU_DOTCLKIN2, + GP_5_27_FN, FN_IP7_26_25, + GP_5_26_FN, FN_DU_DOTCLKIN0, + GP_5_25_FN, FN_AVS2, + GP_5_24_FN, FN_AVS1, + GP_5_23_FN, FN_USB2_OVC, + GP_5_22_FN, FN_USB2_PWEN, + GP_5_21_FN, FN_IP16_7, + GP_5_20_FN, FN_IP16_6, + GP_5_19_FN, FN_USB0_OVC_VBUS, + GP_5_18_FN, FN_USB0_PWEN, + GP_5_17_FN, FN_IP16_5_3, + GP_5_16_FN, FN_IP16_2_0, + GP_5_15_FN, FN_IP15_29_28, + GP_5_14_FN, FN_IP15_27_26, + GP_5_13_FN, FN_IP15_25_23, + GP_5_12_FN, FN_IP15_22_20, + GP_5_11_FN, FN_IP15_19_18, + GP_5_10_FN, FN_IP15_17_16, + GP_5_9_FN, FN_IP15_15_14, + GP_5_8_FN, FN_IP15_13_12, + GP_5_7_FN, FN_IP15_11_9, + GP_5_6_FN, FN_IP15_8_6, + GP_5_5_FN, FN_IP15_5_3, + GP_5_4_FN, FN_IP15_2_0, + GP_5_3_FN, FN_IP14_30_28, + GP_5_2_FN, FN_IP14_27_25, + GP_5_1_FN, FN_IP14_24_22, + GP_5_0_FN, FN_IP14_21_19 } + }, + + /*IPSR0 - IPSR5*/ + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, + 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { + /* IP6_31_29 [3] */ + FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, + FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, + /* IP6_28_26 [3] */ + FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, + FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, + /* IP6_25_23 [3] */ + FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, + FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, + /* IP6_22_20 [3] */ + FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, + FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, + /* IP6_19_17 [3] */ + FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B, + FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0, + /* IP6_16_14 [3] */ + FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, + FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, + FN_SCL2_CIS_E, 0, + /* IP6_13_11 [3] */ + FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, + /* IP6_10_9 [2] */ + FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, + /* IP6_8_6 [3] */ + FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, + FN_SSI_SDATA8_C, 0, 0, 0, + /* IP6_5_3 [3] */ + FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, + FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, + /* IP6_2_0 [3] */ + FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, + FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, + 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { + /* IP7_31 [1] */ + 0, 0, + /* IP7_30_29 [2] */ + FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, + FN_MII_RXD2, + /* IP7_28_27 [2] */ + FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, + /* IP7_26_25 [2] */ + FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, + /* IP7_24_22 [3] */ + FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C, + 0, 0, 0, + /* IP7_21_19 [3] */ + FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, + FN_GLO_RFON_C, FN_PCMOE_N, 0, 0, + /* IP7_18_16 [3] */ + FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, + FN_GLO_SS_C, 0, 0, 0, + /* IP7_15_13 [3] */ + FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, + FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, + /* IP7_12_10 [3] */ + FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, + FN_GLO_SCLK_C, 0, 0, 0, + /* IP7_9_8 [2] */ + FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0, + /* IP7_7_6 [2] */ + FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F, + /* IP7_5_3 [3] */ + FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, + 0, 0, 0, + /* IP7_2_0 [3] */ + FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, + FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } + }, + /*IPSR8 - IPSR16*/ + { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, + { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { + 0, 0, + 0, 0, + GP_1_29_IN, GP_1_29_OUT, + GP_1_28_IN, GP_1_28_OUT, + GP_1_27_IN, GP_1_27_OUT, + GP_1_26_IN, GP_1_26_OUT, + GP_1_25_IN, GP_1_25_OUT, + GP_1_24_IN, GP_1_24_OUT, + GP_1_23_IN, GP_1_23_OUT, + GP_1_22_IN, GP_1_22_OUT, + GP_1_21_IN, GP_1_21_OUT, + GP_1_20_IN, GP_1_20_OUT, + GP_1_19_IN, GP_1_19_OUT, + GP_1_18_IN, GP_1_18_OUT, + GP_1_17_IN, GP_1_17_OUT, + GP_1_16_IN, GP_1_16_OUT, + GP_1_15_IN, GP_1_15_OUT, + GP_1_14_IN, GP_1_14_OUT, + GP_1_13_IN, GP_1_13_OUT, + GP_1_12_IN, GP_1_12_OUT, + GP_1_11_IN, GP_1_11_OUT, + GP_1_10_IN, GP_1_10_OUT, + GP_1_9_IN, GP_1_9_OUT, + GP_1_8_IN, GP_1_8_OUT, + GP_1_7_IN, GP_1_7_OUT, + GP_1_6_IN, GP_1_6_OUT, + GP_1_5_IN, GP_1_5_OUT, + GP_1_4_IN, GP_1_4_OUT, + GP_1_3_IN, GP_1_3_OUT, + GP_1_2_IN, GP_1_2_OUT, + GP_1_1_IN, GP_1_1_OUT, + GP_1_0_IN, GP_1_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { + 0, 0, + 0, 0, + GP_2_29_IN, GP_2_29_OUT, + GP_2_28_IN, GP_2_28_OUT, + GP_2_27_IN, GP_2_27_OUT, + GP_2_26_IN, GP_2_26_OUT, + GP_2_25_IN, GP_2_25_OUT, + GP_2_24_IN, GP_2_24_OUT, + GP_2_23_IN, GP_2_23_OUT, + GP_2_22_IN, GP_2_22_OUT, + GP_2_21_IN, GP_2_21_OUT, + GP_2_20_IN, GP_2_20_OUT, + GP_2_19_IN, GP_2_19_OUT, + GP_2_18_IN, GP_2_18_OUT, + GP_2_17_IN, GP_2_17_OUT, + GP_2_16_IN, GP_2_16_OUT, + GP_2_15_IN, GP_2_15_OUT, + GP_2_14_IN, GP_2_14_OUT, + GP_2_13_IN, GP_2_13_OUT, + GP_2_12_IN, GP_2_12_OUT, + GP_2_11_IN, GP_2_11_OUT, + GP_2_10_IN, GP_2_10_OUT, + GP_2_9_IN, GP_2_9_OUT, + GP_2_8_IN, GP_2_8_OUT, + GP_2_7_IN, GP_2_7_OUT, + GP_2_6_IN, GP_2_6_OUT, + GP_2_5_IN, GP_2_5_OUT, + GP_2_4_IN, GP_2_4_OUT, + GP_2_3_IN, GP_2_3_OUT, + GP_2_2_IN, GP_2_2_OUT, + GP_2_1_IN, GP_2_1_OUT, + GP_2_0_IN, GP_2_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } }, + { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } }, + { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } }, + { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { + 0, 0, GP_1_29_DATA, GP_1_28_DATA, + GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA, + GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, + GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, + GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, + GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, + GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, + GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } + }, + { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { + 0, 0, GP_2_29_DATA, GP_2_28_DATA, + GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA, + GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA, + GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA, + GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA, + GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA, + GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA, + GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA } + }, + { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } }, + { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } }, + { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } }, + { }, +}; + +static struct pinmux_info r8a7790_pinmux_info = { + .name = "r8a7790_pfc", + + .unlock_reg = 0xe6060000, /* PMMR */ + + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_FN_MII_RXD2 /* GPIO_FN_TCLK1_B */, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void r8a7790_pinmux_init(void) +{ + register_pinmux(&r8a7790_pinmux_info); +} diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h new file mode 100644 index 0000000..a13317b --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h @@ -0,0 +1,92 @@ +/* + * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __PFC_R8A7790_H__ +#define __PFC_R8A7790_H__ + +#include <sh_pfc.h> +#include <asm/gpio.h> + +#define CPU_32_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + +#define CPU_32_PORT2(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx) + +#if defined(CONFIG_R8A7790) +#define CPU_32_PORT1(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx) \ +/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */ +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT(fn, pfx##_0_, sfx), \ + CPU_32_PORT1(fn, pfx##_1_, sfx), \ + CPU_32_PORT2(fn, pfx##_2_, sfx), \ + CPU_32_PORT(fn, pfx##_3_, sfx), \ + CPU_32_PORT(fn, pfx##_4_, sfx), \ + CPU_32_PORT(fn, pfx##_5_, sfx) + +#elif defined(CONFIG_R8A7791) +#define CPU_32_PORT1(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ + PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx) + +/* + * GP_0_0_DATA -> GP_7_25_DATA + * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31] + * GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31]) + */ +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT(fn, pfx##_0_, sfx), \ + CPU_32_PORT1(fn, pfx##_1_, sfx), \ + CPU_32_PORT(fn, pfx##_2_, sfx), \ + CPU_32_PORT(fn, pfx##_3_, sfx), \ + CPU_32_PORT(fn, pfx##_4_, sfx), \ + CPU_32_PORT(fn, pfx##_5_, sfx), \ + CPU_32_PORT(fn, pfx##_6_, sfx), \ + CPU_32_PORT1(fn, pfx##_7_, sfx) +#else +#error "NO support" +#endif + +#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ + GP##pfx##_IN, GP##pfx##_OUT) + +#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT +#define _GP_INDT(pfx, sfx) GP##pfx##_DATA + +#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) + +#define PORT_10_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ + PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ + PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ + PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +#define CPU_32_PORT_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ + PORT_10_REV(fn, pfx, sfx) + +#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) + +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ + FN_##ipsr, FN_##fn) + +#endif /* __PFC_R8A7790_H__ */ diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c new file mode 100644 index 0000000..f49f990 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c @@ -0,0 +1,1117 @@ +/* + * arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <sh_pfc.h> +#include <asm/gpio.h> +#include "pfc-r8a7790.h" + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + GP_ALL(IN), + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5, + FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11, + FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19, + FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29, + FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8, + FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20, + + /* GPSR1 */ + FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3, + FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16, + FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25, + FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N, + FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18, + FN_IP3_21_20, + + /* GPSR2 */ + FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, + FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19, + FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26, + FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9, + FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22, + FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0, + FN_IP6_5_3, FN_IP6_7_6, + + /* GPSR3 */ + FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13, + FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24, + FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9, + FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24, + FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7, + FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16, + FN_IP9_18_17, + + /* GPSR4 */ + FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25, + FN_VI0_DATA0_VI0_B0, FN_VI0_DATA0_VI0_B1, FN_VI0_DATA0_VI0_B2, + FN_IP9_28_27, FN_VI0_DATA0_VI0_B4, FN_VI0_DATA0_VI0_B5, + FN_VI0_DATA0_VI0_B6, FN_VI0_DATA0_VI0_B7, FN_IP9_31_29, FN_IP10_2_0, + FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15, + FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25, + FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6, + FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4, + + /* GPSR5 */ + FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19, + FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24, + FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30, + FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10, + FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20, + FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3, + FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22, + + /* GPSR6 */ + FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14, + FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23, + FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0, + FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7, + FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17, + FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29, + + /* GPSR7 */ + FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24, + FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8, + FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, + FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27, + FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12, + FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, + + /* IPSR0 - IPSR10 */ + + /* IPSR11 */ + FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, + FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, + FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, + FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, + FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B, + FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B, + FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, + FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, + FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5, + FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7, + FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO, + FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC, + FN_VI1_DATA7, FN_AVB_MDC, + FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, + FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, + + /* IPSR12 */ + FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, + FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, + FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, + FN_SCL2_D, FN_MSIOF1_RXD_E, + FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E, + FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, + FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, + FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, + FN_CAN1_TX_C, FN_MSIOF1_TXD_E, + FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, + FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, + FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, + FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, + FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, + FN_ADIDATA_B, FN_MSIOF0_SYNC_C, + FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, + FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, + + /* IPSR13 */ + /* MOD_SEL */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + FN_SEL_QSP_0, FN_SEL_QSP_1, + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3, + FN_SEL_HSCIF1_4, + FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, + + /* MOD_SEL2 */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + FN_SEL_SCIF0_4, + FN_SEL_SCIF_0, FN_SEL_SCIF_1, + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CAN0_4, FN_SEL_CAN0_5, + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, + FN_SEL_ADG_0, FN_SEL_ADG_1, + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4, + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, + FN_SEL_SIM_0, FN_SEL_SIM_1, + FN_SEL_SSI8_0, FN_SEL_SSI8_1, + + /* MOD_SEL3 */ + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, + FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, + FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, + FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, + FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + FN_SEL_MMC_0, FN_SEL_MMC_1, + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, + FN_SEL_IIC1_4, + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, + + /* MOD_SEL4 */ + FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, + FN_SEL_SOF1_4, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, + FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, + FN_SEL_RAD_0, FN_SEL_RAD_1, + FN_SEL_RCN_0, FN_SEL_RCN_1, + FN_SEL_RSP_0, FN_SEL_RSP_1, + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, + FN_SEL_SCIF2_4, + FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3, + FN_SEL_SOF2_4, + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + FN_SEL_SSI0_0, FN_SEL_SSI0_1, + FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + EX_CS0_N_MARK, RD_N_MARK, + + AUDIO_CLKA_MARK, + + VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA0_VI0_B1_MARK, + VI0_DATA0_VI0_B2_MARK, VI0_DATA0_VI0_B4_MARK, VI0_DATA0_VI0_B5_MARK, + VI0_DATA0_VI0_B6_MARK, VI0_DATA0_VI0_B7_MARK, + + USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, + + /* IPSR0 IPSR10 */ + /* IPSR11 */ + VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK, + VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK, + VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK, + SDA4_B_MARK, _MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK, + VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK, + TX4_B_MARK, SCIFA4_TXD_B_MARK, + VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK, + RX4_B_MARK, SCIFA4_RXD_B_MARK, + VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK, + VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK, + VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK, + VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK, + VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK, + VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK, + VI1_DATA7_MARK, AVB_MDC_MARK, + ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK, + ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK, + + /* IPSR12 */ + ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK, + ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK, + ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK, + SCL2_D_MARK, MSIOF1_RXD_E_MARK, + ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK, + SDA2_D_MARK, MSIOF1_SCK_E_MARK, + ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK, + CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK, + ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK, + CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK, + ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK, + ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK, + ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK, + ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK, + STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK, + ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK, + STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK, + ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK, + + /* IPSR13 */ + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + /* OTHER IPSR0 - IPSR10 */ + /* IPSR11 */ + PINMUX_IPSR_DATA(IP11_2_0, VI0_R5), + PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3), + PINMUX_IPSR_DATA(IP11_5_3, VI0_R6), + PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1), + PINMUX_IPSR_DATA(IP11_8_6, VI0_R7), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2), + PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3), + PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_19, AVB_RXD4), + PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_20, AVB_RXD5), + PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_21, AVB_RXD6), + PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_22, AVB_RXD7), + PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_24, AVB_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV), + PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_27, AVB_MDC), + PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO), + PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2), + PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV), + PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK), + PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2), + + /* IPSR12 */ + PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER), + PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS), + PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0), + PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0), + PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0), + PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT), + PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0), + PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0), + PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1), + PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK), + PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK), + PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1), + PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN), + PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3), + PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC), + PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4), + PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0), + PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5), + PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC), + PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6), + PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), + + /* IPSR13 - IPSR16 */ +}; + +static struct pinmux_gpio pinmux_gpios[] = { + PINMUX_GPIO_GP_ALL(), + + /* OTHER, IPSR0 - IPSR10 */ + /* IPSR11 */ + GPIO_FN(VI0_R5), GPIO_FN(VI2_DATA6), GPIO_FN(GLO_SDATA_B), + GPIO_FN(RX0_C), GPIO_FN(SDA1_D), + GPIO_FN(VI0_R6), GPIO_FN(VI2_DATA7), + GPIO_FN(GLO_SS_B), GPIO_FN(TX1_C), GPIO_FN(SCL4_B), + GPIO_FN(VI0_R7), GPIO_FN(GLO_RFON_B), + GPIO_FN(RX1_C), GPIO_FN(CAN0_RX_E), + GPIO_FN(SDA4_B), GPIO_FN(HRX1_D), GPIO_FN(SCIFB0_RXD_D), + GPIO_FN(VI1_HSYNC_N), GPIO_FN(AVB_RXD0), GPIO_FN(TS_SDATA0_B), + GPIO_FN(TX4_B), GPIO_FN(SCIFA4_TXD_B), + GPIO_FN(VI1_VSYNC_N), GPIO_FN(AVB_RXD1), GPIO_FN(TS_SCK0_B), + GPIO_FN(RX4_B), GPIO_FN(SCIFA4_RXD_B), + GPIO_FN(VI1_CLKENB), GPIO_FN(AVB_RXD2), GPIO_FN(TS_SDEN0_B), + GPIO_FN(VI1_FIELD), GPIO_FN(AVB_RXD3), GPIO_FN(TS_SPSYNC0_B), + GPIO_FN(VI1_CLK), GPIO_FN(AVB_RXD4), + GPIO_FN(VI1_DATA0), GPIO_FN(AVB_RXD5), + GPIO_FN(VI1_DATA1), GPIO_FN(AVB_RXD6), + GPIO_FN(VI1_DATA2), GPIO_FN(AVB_RXD7), + GPIO_FN(VI1_DATA3), GPIO_FN(AVB_RX_ER), + GPIO_FN(VI1_DATA4), GPIO_FN(AVB_MDIO), + GPIO_FN(VI1_DATA5), GPIO_FN(AVB_RX_DV), + GPIO_FN(VI1_DATA6), GPIO_FN(AVB_MAGIC), + GPIO_FN(VI1_DATA7), GPIO_FN(AVB_MDC), + GPIO_FN(ETH_MDIO), GPIO_FN(AVB_RX_CLK), GPIO_FN(SCL2_C), + GPIO_FN(ETH_CRS_DV), GPIO_FN(AVB_LINK), GPIO_FN(SDA2_C), + + /* IPSR12 */ + GPIO_FN(ETH_RX_ER), GPIO_FN(AVB_CRS), GPIO_FN(SCL3), GPIO_FN(SCL7), + GPIO_FN(ETH_RXD0), GPIO_FN(AVB_PHY_INT), GPIO_FN(SDA3), GPIO_FN(SDA7), + GPIO_FN(ETH_RXD1), GPIO_FN(AVB_GTXREFCLK), GPIO_FN(CAN0_TX_C), + GPIO_FN(SCL2_D), GPIO_FN(MSIOF1_RXD_E), + GPIO_FN(ETH_LINK), GPIO_FN(AVB_TXD0), GPIO_FN(CAN0_RX_C), + GPIO_FN(SDA2_D), GPIO_FN(MSIOF1_SCK_E), + GPIO_FN(ETH_REFCLK), GPIO_FN(AVB_TXD1), GPIO_FN(SCIFA3_RXD_B), + GPIO_FN(CAN1_RX_C), GPIO_FN(MSIOF1_SYNC_E), + GPIO_FN(ETH_TXD1), GPIO_FN(AVB_TXD2), GPIO_FN(SCIFA3_TXD_B), + GPIO_FN(CAN1_TX_C), GPIO_FN(MSIOF1_TXD_E), + GPIO_FN(ETH_TX_EN), GPIO_FN(AVB_TXD3), + GPIO_FN(TCLK1_B), GPIO_FN(CAN_CLK_B), + GPIO_FN(ETH_MAGIC), GPIO_FN(AVB_TXD4), GPIO_FN(IETX_C), + GPIO_FN(ETH_TXD0), GPIO_FN(AVB_TXD5), GPIO_FN(IECLK_C), + GPIO_FN(ETH_MDC), GPIO_FN(AVB_TXD6), GPIO_FN(IERX_C), + GPIO_FN(STP_IVCXO27_0), GPIO_FN(AVB_TXD7), GPIO_FN(SCIFB2_TXD_D), + GPIO_FN(ADIDATA_B), GPIO_FN(MSIOF0_SYNC_C), + GPIO_FN(STP_ISCLK_0), GPIO_FN(AVB_TX_EN), GPIO_FN(SCIFB2_RXD_D), + GPIO_FN(ADICS_SAMP_B), GPIO_FN(MSIOF0_SCK_C), + + /* IPSR13 - IPSR16 */ +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP1_22_20, + GP_0_30_FN, FN_IP1_19_17, + GP_0_29_FN, FN_IP1_16_14, + GP_0_28_FN, FN_IP1_13_11, + GP_0_27_FN, FN_IP1_10_8, + GP_0_26_FN, FN_IP1_7_6, + GP_0_25_FN, FN_IP1_5_4, + GP_0_24_FN, FN_IP1_3_2, + GP_0_23_FN, FN_IP1_1_0, + GP_0_22_FN, FN_IP0_30_29, + GP_0_21_FN, FN_IP0_28_27, + GP_0_20_FN, FN_IP0_26_25, + GP_0_19_FN, FN_IP0_24_23, + GP_0_18_FN, FN_IP0_22_21, + GP_0_17_FN, FN_IP0_20_19, + GP_0_16_FN, FN_IP0_18_16, + GP_0_15_FN, FN_IP0_15, + GP_0_14_FN, FN_IP0_14, + GP_0_13_FN, FN_IP0_13, + GP_0_12_FN, FN_IP0_12, + GP_0_11_FN, FN_IP0_11, + GP_0_10_FN, FN_IP0_10, + GP_0_9_FN, FN_IP0_9, + GP_0_8_FN, FN_IP0_8, + GP_0_7_FN, FN_IP0_7, + GP_0_6_FN, FN_IP0_6, + GP_0_5_FN, FN_IP0_5, + GP_0_4_FN, FN_IP0_4, + GP_0_3_FN, FN_IP0_3, + GP_0_2_FN, FN_IP0_2, + GP_0_1_FN, FN_IP0_1, + GP_0_0_FN, FN_IP0_0, } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_FN, FN_IP3_21_20, + GP_1_24_FN, FN_IP3_19_18, + GP_1_23_FN, FN_IP3_17_16, + GP_1_22_FN, FN_IP3_15_14, + GP_1_21_FN, FN_IP3_13_12, + GP_1_20_FN, FN_IP3_11_9, + GP_1_19_FN, FN_RD_N, + GP_1_18_FN, FN_IP3_8_6, + GP_1_17_FN, FN_IP3_5_3, + GP_1_16_FN, FN_IP3_2_0, + GP_1_15_FN, FN_IP2_29_27, + GP_1_14_FN, FN_IP2_26_25, + GP_1_13_FN, FN_IP2_24_23, + GP_1_12_FN, FN_EX_CS0_N, + GP_1_11_FN, FN_IP2_22_21, + GP_1_10_FN, FN_IP2_20_19, + GP_1_9_FN, FN_IP2_18_16, + GP_1_8_FN, FN_IP2_15_13, + GP_1_7_FN, FN_IP2_12_10, + GP_1_6_FN, FN_IP2_9_7, + GP_1_5_FN, FN_IP2_6_5, + GP_1_4_FN, FN_IP2_4_3, + GP_1_3_FN, FN_IP2_2_0, + GP_1_2_FN, FN_IP1_31_29, + GP_1_1_FN, FN_IP1_28_26, + GP_1_0_FN, FN_IP1_25_23, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + GP_2_31_FN, FN_IP6_7_6, + GP_2_30_FN, FN_IP6_5_3, + GP_2_29_FN, FN_IP6_2_0, + GP_2_28_FN, FN_AUDIO_CLKA, + GP_2_27_FN, FN_IP5_31_29, + GP_2_26_FN, FN_IP5_28_26, + GP_2_25_FN, FN_IP5_25_24, + GP_2_24_FN, FN_IP5_23_22, + GP_2_23_FN, FN_IP5_21_20, + GP_2_22_FN, FN_IP5_19_17, + GP_2_21_FN, FN_IP5_16_15, + GP_2_20_FN, FN_IP5_14_12, + GP_2_19_FN, FN_IP5_11_9, + GP_2_18_FN, FN_IP5_8_6, + GP_2_17_FN, FN_IP5_5_3, + GP_2_16_FN, FN_IP5_2_0, + GP_2_15_FN, FN_IP4_30_28, + GP_2_14_FN, FN_IP4_27_26, + GP_2_13_FN, FN_IP4_25_24, + GP_2_12_FN, FN_IP4_23_22, + GP_2_11_FN, FN_IP4_21, + GP_2_10_FN, FN_IP4_20, + GP_2_9_FN, FN_IP4_19, + GP_2_8_FN, FN_IP4_18_16, + GP_2_7_FN, FN_IP4_15_13, + GP_2_6_FN, FN_IP4_12_10, + GP_2_5_FN, FN_IP4_9_8, + GP_2_4_FN, FN_IP4_7_5, + GP_2_3_FN, FN_IP4_4_2, + GP_2_2_FN, FN_IP4_1_0, + GP_2_1_FN, FN_IP3_30_28, + GP_2_0_FN, FN_IP3_27_25 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP9_18_17, + GP_3_30_FN, FN_IP9_16, + GP_3_29_FN, FN_IP9_15_13, + GP_3_28_FN, FN_IP9_12, + GP_3_27_FN, FN_IP9_11, + GP_3_26_FN, FN_IP9_10_8, + GP_3_25_FN, FN_IP9_7, + GP_3_24_FN, FN_IP9_6, + GP_3_23_FN, FN_IP9_5_3, + GP_3_22_FN, FN_IP9_2_0, + GP_3_21_FN, FN_IP8_30_28, + GP_3_20_FN, FN_IP8_27_26, + GP_3_19_FN, FN_IP8_25_24, + GP_3_18_FN, FN_IP8_23_21, + GP_3_17_FN, FN_IP8_20_18, + GP_3_16_FN, FN_IP8_17_15, + GP_3_15_FN, FN_IP8_14_12, + GP_3_14_FN, FN_IP8_11_9, + GP_3_13_FN, FN_IP8_8_6, + GP_3_12_FN, FN_IP8_5_3, + GP_3_11_FN, FN_IP8_2_0, + GP_3_10_FN, FN_IP7_29_27, + GP_3_9_FN, FN_IP7_26_24, + GP_3_8_FN, FN_IP7_23_21, + GP_3_7_FN, FN_IP7_20_19, + GP_3_6_FN, FN_IP7_18_17, + GP_3_5_FN, FN_IP7_16_15, + GP_3_4_FN, FN_IP7_14_13, + GP_3_3_FN, FN_IP7_12_11, + GP_3_2_FN, FN_IP7_10_9, + GP_3_1_FN, FN_IP7_8_6, + GP_3_0_FN, FN_IP7_5_3 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP15_5_4, + GP_4_30_FN, FN_IP15_3_2, + GP_4_29_FN, FN_IP15_1_0, + GP_4_28_FN, FN_IP11_8_6, + GP_4_27_FN, FN_IP11_5_3, + GP_4_26_FN, FN_IP11_2_0, + GP_4_25_FN, FN_IP10_31_29, + GP_4_24_FN, FN_IP10_28_27, + GP_4_23_FN, FN_IP10_26_25, + GP_4_22_FN, FN_IP10_24_22, + GP_4_21_FN, FN_IP10_21_19, + GP_4_20_FN, FN_IP10_18_17, + GP_4_19_FN, FN_IP10_16_15, + GP_4_18_FN, FN_IP10_14_12, + GP_4_17_FN, FN_IP10_11_9, + GP_4_16_FN, FN_IP10_8_6, + GP_4_15_FN, FN_IP10_5_3, + GP_4_14_FN, FN_IP10_2_0, + GP_4_13_FN, FN_IP9_31_29, + GP_4_12_FN, FN_VI0_DATA0_VI0_B7, + GP_4_11_FN, FN_VI0_DATA0_VI0_B6, + GP_4_10_FN, FN_VI0_DATA0_VI0_B5, + GP_4_9_FN, FN_VI0_DATA0_VI0_B4, + GP_4_8_FN, FN_IP9_28_27, + GP_4_7_FN, FN_VI0_DATA0_VI0_B2, + GP_4_6_FN, FN_VI0_DATA0_VI0_B1, + GP_4_5_FN, FN_VI0_DATA0_VI0_B0, + GP_4_4_FN, FN_IP9_26_25, + GP_4_3_FN, FN_IP9_24_23, + GP_4_2_FN, FN_IP9_22_21, + GP_4_1_FN, FN_IP9_20_19, + GP_4_0_FN, FN_VI0_CLK } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + GP_5_31_FN, FN_IP3_24_22, + GP_5_30_FN, FN_IP13_9_7, + GP_5_29_FN, FN_IP13_6_5, + GP_5_28_FN, FN_IP13_4_3, + GP_5_27_FN, FN_IP13_2_0, + GP_5_26_FN, FN_IP12_29_27, + GP_5_25_FN, FN_IP12_26_24, + GP_5_24_FN, FN_IP12_23_22, + GP_5_23_FN, FN_IP12_21_20, + GP_5_22_FN, FN_IP12_19_18, + GP_5_21_FN, FN_IP12_17_16, + GP_5_20_FN, FN_IP12_15_13, + GP_5_19_FN, FN_IP12_12_10, + GP_5_18_FN, FN_IP12_9_7, + GP_5_17_FN, FN_IP12_6_4, + GP_5_16_FN, FN_IP12_3_2, + GP_5_15_FN, FN_IP12_1_0, + GP_5_14_FN, FN_IP11_31_30, + GP_5_13_FN, FN_IP11_29_28, + GP_5_12_FN, FN_IP11_27, + GP_5_11_FN, FN_IP11_26, + GP_5_10_FN, FN_IP11_25, + GP_5_9_FN, FN_IP11_24, + GP_5_8_FN, FN_IP11_23, + GP_5_7_FN, FN_IP11_22, + GP_5_6_FN, FN_IP11_21, + GP_5_5_FN, FN_IP11_20, + GP_5_4_FN, FN_IP11_19, + GP_5_3_FN, FN_IP11_18_17, + GP_5_2_FN, FN_IP11_16_15, + GP_5_1_FN, FN_IP11_14_12, + GP_5_0_FN, FN_IP11_11_9 } + }, + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + 0, 0, + 0, 0, + GP_6_29_FN, FN_IP14_31_29, + GP_6_28_FN, FN_IP14_28_26, + GP_6_27_FN, FN_IP14_25_23, + GP_6_26_FN, FN_IP14_22_20, + GP_6_25_FN, FN_IP14_19_17, + GP_6_24_FN, FN_IP14_16_14, + GP_6_23_FN, FN_IP14_13_11, + GP_6_22_FN, FN_IP14_10_8, + GP_6_21_FN, FN_IP14_7, + GP_6_20_FN, FN_IP14_6, + GP_6_19_FN, FN_IP14_5, + GP_6_18_FN, FN_IP14_4, + GP_6_17_FN, FN_IP14_3, + GP_6_16_FN, FN_IP14_2, + GP_6_15_FN, FN_IP14_1_0, + GP_6_14_FN, FN_IP13_30_28, + GP_6_13_FN, FN_IP13_27, + GP_6_12_FN, FN_IP13_26, + GP_6_11_FN, FN_IP13_25, + GP_6_10_FN, FN_IP13_24_23, + GP_6_9_FN, FN_IP13_22, + 0, 0, + GP_6_7_FN, FN_IP13_21_19, + GP_6_6_FN, FN_IP13_18_16, + GP_6_5_FN, FN_IP13_15, + GP_6_4_FN, FN_IP13_14, + GP_6_3_FN, FN_IP13_13, + GP_6_2_FN, FN_IP13_12, + GP_6_1_FN, FN_IP13_11, + GP_6_0_FN, FN_IP13_10 } + }, + { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_25_FN, FN_USB1_PWEN, + GP_7_24_FN, FN_USB0_OVC, + GP_7_23_FN, FN_USB0_PWEN, + GP_7_22_FN, FN_IP15_14_12, + GP_7_21_FN, FN_IP15_11_9, + GP_7_20_FN, FN_IP15_8_6, + GP_7_19_FN, FN_IP7_2_0, + GP_7_18_FN, FN_IP6_29_27, + GP_7_17_FN, FN_IP6_26_24, + GP_7_16_FN, FN_IP6_23_21, + GP_7_15_FN, FN_IP6_20_19, + GP_7_14_FN, FN_IP6_18_16, + GP_7_13_FN, FN_IP6_15_14, + GP_7_12_FN, FN_IP6_13_12, + GP_7_11_FN, FN_IP6_11_10, + GP_7_10_FN, FN_IP6_9_8, + GP_7_9_FN, FN_IP16_11_10, + GP_7_8_FN, FN_IP16_9_8, + GP_7_7_FN, FN_IP16_7_6, + GP_7_6_FN, FN_IP16_5_3, + GP_7_5_FN, FN_IP16_2_0, + GP_7_4_FN, FN_IP15_29_27, + GP_7_3_FN, FN_IP15_26_24, + GP_7_2_FN, FN_IP15_23_21, + GP_7_1_FN, FN_IP15_20_18, + GP_7_0_FN, FN_IP15_17_15 } + }, + /* IPSR0 - IPSR10 */ + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, + 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, + 3, 3, 3, 3, 3) { + /* IP11_31_30 [2] */ + FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0, + /* IP11_29_28 [2] */ + FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0, + /* IP11_27 [1] */ + FN_VI1_DATA7, FN_AVB_MDC, + /* IP11_26 [1] */ + FN_VI1_DATA6, FN_AVB_MAGIC, + /* IP11_25 [1] */ + FN_VI1_DATA5, FN_AVB_RX_DV, + /* IP11_24 [1] */ + FN_VI1_DATA4, FN_AVB_MDIO, + /* IP11_23 [1] */ + FN_VI1_DATA3, FN_AVB_RX_ER, + /* IP11_22 [1] */ + FN_VI1_DATA2, FN_AVB_RXD7, + /* IP11_21 [1] */ + FN_VI1_DATA1, FN_AVB_RXD6, + /* IP11_20 [1] */ + FN_VI1_DATA0, FN_AVB_RXD5, + /* IP11_19 [1] */ + FN_VI1_CLK, FN_AVB_RXD4, + /* IP11_18_17 [2] */ + FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0, + /* IP11_16_15 [2] */ + FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0, + /* IP11_14_12 [3] */ + FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, + FN_RX4_B, FN_SCIFA4_RXD_B, + 0, 0, 0, + /* IP11_11_9 [3] */ + FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, + FN_TX4_B, FN_SCIFA4_TXD_B, + 0, 0, 0, + /* IP11_8_6 [3] */ + FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, + FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0, + /* IP11_5_3 [3] */ + FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, + 0, 0, 0, + /* IP11_2_0 [3] */ + FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, + 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) { + /* IP12_31_30 [2] */ + 0, 0, 0, 0, + /* IP12_29_27 [3] */ + FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, + FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, + 0, 0, 0, + /* IP12_26_24 [3] */ + FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, + FN_ADIDATA_B, FN_MSIOF0_SYNC_C, + 0, 0, 0, + /* IP12_23_22 [2] */ + FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0, + /* IP12_21_20 [2] */ + FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0, + /* IP12_19_18 [2] */ + FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0, + /* IP12_17_16 [2] */ + FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, + /* IP12_15_13 [3] */ + FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, + FN_CAN1_TX_C, FN_MSIOF1_TXD_E, + 0, 0, 0, + /* IP12_12_10 [3] */ + FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, + FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, + 0, 0, 0, + /* IP12_9_7 [3] */ + FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, + FN_SDA2_D, FN_MSIOF1_SCK_E, + 0, 0, 0, + /* IP12_6_4 [3] */ + FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, + FN_SCL2_D, FN_MSIOF1_RXD_E, + 0, 0, 0, + /* IP12_3_2 [2] */ + FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, + /* IP12_1_0 [2] */ + FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, } + }, + + /* IPSR13 - IPSR16 */ + + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, + 1, 2, 2, 2, 3, 2, 1, 1, 1, 1, + 3, 2, 2, 2, 1, 2, 2, 2) { + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIF1 [2] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + /* SEL_SCIFB [2] */ + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, + /* SEL_SCIFB2 [2] */ + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, + FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, + /* SEL_SCIFB1 [3] */ + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, + FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + 0, 0, 0, 0, + /* SEL_SCIFA1 [2] */ + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, + /* SEL_SSI9 [1] */ + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + /* SEL_SCFA [1] */ + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + /* SEL_QSP [1] */ + FN_SEL_QSP_0, FN_SEL_QSP_1, + /* SEL_SSI7 [1] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + /* SEL_HSCIF1 [3] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, + FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4, + 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_VI1 [2] */ + FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_TMU [1] */ + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + /* SEL_LBS [2] */ + FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, + /* SEL_TSIF0 [2] */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + /* SEL_SOF0 [2] */ + FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, + 3, 1, 1, 3, 2, 1, 1, 2, 2, + 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) { + /* SEL_SCIF0 [3] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, + FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, + 0, 0, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIF [1] */ + FN_SEL_SCIF_0, FN_SEL_SCIF_1, + /* SEL_CAN0 [3] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CAN0_4, FN_SEL_CAN0_5, + 0, 0, + /* SEL_CAN1 [2] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIFA2 [1] */ + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + /* SEL_SCIF4 [2] */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_ADG [1] */ + FN_SEL_ADG_0, FN_SEL_ADG_1, + /* SEL_FM [3] */ + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, + FN_SEL_FM_3, FN_SEL_FM_4, + 0, 0, 0, + /* SEL_SCIFA5 [2] */ + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_GPS [2] */ + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, + /* SEL_SCIFA4 [2] */ + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0, + /* SEL_SCIFA3 [2] */ + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0, + /* SEL_SIM [1] */ + FN_SEL_SIM_0, FN_SEL_SIM_1, + /* RESEVED [1] */ + 0, 0, + /* SEL_SSI8 [1] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, + 2, 2, 2, 2, 2, 2, 2, 2, + 1, 1, 2, 2, 3, 2, 2, 2, 1) { + /* SEL_HSCIF2 [2] */ + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, + FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, + /* SEL_CANCLK [2] */ + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, + /* SEL_IIC8 [2] */ + FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0, + /* SEL_IIC7 [2] */ + FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0, + /* SEL_IIC4 [2] */ + FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0, + /* SEL_IIC3 [2] */ + FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, + /* SEL_SCIF3 [2] */ + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, + /* SEL_IEB [2] */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + /* SEL_MMC [1] */ + FN_SEL_MMC_0, FN_SEL_MMC_1, + /* SEL_SCIF5 [1] */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_IIC2 [2] */ + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + /* SEL_IIC1 [3] */ + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, + FN_SEL_IIC1_4, + 0, 0, 0, + /* SEL_IIC0 [2] */ + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [1] */ + 0, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, + 3, 2, 2, 1, 1, 1, 1, 3, 2, + 2, 3, 1, 1, 1, 2, 2, 2, 2) { + /* SEL_SOF1 [3] */ + FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, + FN_SEL_SOF1_4, + 0, 0, 0, + /* SEL_HSCIF0 [2] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0, + /* SEL_DIS [2] */ + FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_RAD [1] */ + FN_SEL_RAD_0, FN_SEL_RAD_1, + /* SEL_RCN [1] */ + FN_SEL_RCN_0, FN_SEL_RCN_1, + /* SEL_RSP [1] */ + FN_SEL_RSP_0, FN_SEL_RSP_1, + /* SEL_SCIF2 [3] */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, + FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, + 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_SOF2 [3] */ + FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, + FN_SEL_SOF2_3, FN_SEL_SOF2_4, + 0, 0, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_SSI1 [1] */ + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + /* SEL_SSI0 [1] */ + FN_SEL_SSI0_0, FN_SEL_SSI0_1, + /* SEL_SSP [2] */ + FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, + { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_IN, GP_1_25_OUT, + GP_1_24_IN, GP_1_24_OUT, + GP_1_23_IN, GP_1_23_OUT, + GP_1_22_IN, GP_1_22_OUT, + GP_1_21_IN, GP_1_21_OUT, + GP_1_20_IN, GP_1_20_OUT, + GP_1_19_IN, GP_1_19_OUT, + GP_1_18_IN, GP_1_18_OUT, + GP_1_17_IN, GP_1_17_OUT, + GP_1_16_IN, GP_1_16_OUT, + GP_1_15_IN, GP_1_15_OUT, + GP_1_14_IN, GP_1_14_OUT, + GP_1_13_IN, GP_1_13_OUT, + GP_1_12_IN, GP_1_12_OUT, + GP_1_11_IN, GP_1_11_OUT, + GP_1_10_IN, GP_1_10_OUT, + GP_1_9_IN, GP_1_9_OUT, + GP_1_8_IN, GP_1_8_OUT, + GP_1_7_IN, GP_1_7_OUT, + GP_1_6_IN, GP_1_6_OUT, + GP_1_5_IN, GP_1_5_OUT, + GP_1_4_IN, GP_1_4_OUT, + GP_1_3_IN, GP_1_3_OUT, + GP_1_2_IN, GP_1_2_OUT, + GP_1_1_IN, GP_1_1_OUT, + GP_1_0_IN, GP_1_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } }, + { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } }, + { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } }, + { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } }, + { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } }, + { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_25_IN, GP_7_25_OUT, + GP_7_24_IN, GP_7_24_OUT, + GP_7_23_IN, GP_7_23_OUT, + GP_7_22_IN, GP_7_22_OUT, + GP_7_21_IN, GP_7_21_OUT, + GP_7_20_IN, GP_7_20_OUT, + GP_7_19_IN, GP_7_19_OUT, + GP_7_18_IN, GP_7_18_OUT, + GP_7_17_IN, GP_7_17_OUT, + GP_7_16_IN, GP_7_16_OUT, + GP_7_15_IN, GP_7_15_OUT, + GP_7_14_IN, GP_7_14_OUT, + GP_7_13_IN, GP_7_13_OUT, + GP_7_12_IN, GP_7_12_OUT, + GP_7_11_IN, GP_7_11_OUT, + GP_7_10_IN, GP_7_10_OUT, + GP_7_9_IN, GP_7_9_OUT, + GP_7_8_IN, GP_7_8_OUT, + GP_7_7_IN, GP_7_7_OUT, + GP_7_6_IN, GP_7_6_OUT, + GP_7_5_IN, GP_7_5_OUT, + GP_7_4_IN, GP_7_4_OUT, + GP_7_3_IN, GP_7_3_OUT, + GP_7_2_IN, GP_7_2_OUT, + GP_7_1_IN, GP_7_1_OUT, + GP_7_0_IN, GP_7_0_OUT, } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } }, + { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { + 0, 0, 0, 0, + 0, 0, GP_1_25_DATA, GP_1_24_DATA, + GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, + GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, + GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, + GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, + GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, + GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } + }, + { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } }, + { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } }, + { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } }, + { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } }, + { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } }, + { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) { + 0, 0, 0, 0, + 0, 0, GP_7_25_DATA, GP_7_24_DATA, + GP_7_23_DATA, GP_7_22_DATA, GP_7_21_DATA, GP_7_20_DATA, + GP_7_19_DATA, GP_7_18_DATA, GP_7_17_DATA, GP_7_16_DATA, + GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA, + GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA, + GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA, + GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA } + }, + { }, +}; + +static struct pinmux_info r8a7791_pinmux_info = { + .name = "r8a7791_pfc", + + .unlock_reg = 0xe6060000, /* PMMR */ + + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_FN_MSIOF0_SCK_C /* GPIO_FN_CAN1_RX_B */, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void r8a7791_pinmux_init(void) +{ + register_pinmux(&r8a7791_pinmux_info); +} diff --git a/arch/arm/cpu/armv7/rmobile/timer.c b/arch/arm/cpu/armv7/rmobile/timer.c index 72e0c12..04700e7 100644 --- a/arch/arm/cpu/armv7/rmobile/timer.c +++ b/arch/arm/cpu/armv7/rmobile/timer.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <div64.h> #include <asm/io.h> #include <asm/arch-armv7/globaltimer.h> #include <asm/arch/rmobile.h> @@ -38,13 +39,16 @@ static u64 get_time_us(void) u64 timer = get_cpu_global_timer(); timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1)); - timer /= (u64)CLK2MHZ(CONFIG_SYS_CPU_CLK); + do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK)); return timer; } static ulong get_time_ms(void) { - return (ulong)(get_time_us() / 1000); + u64 us = get_time_us(); + + do_div(us, 1000); + return us; } int timer_init(void) diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index dac2bbd..3e84a0c 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -9,4 +9,4 @@ obj-y := lowlevel_init.o obj-y += misc.o timer.o reset_manager.o system_manager.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/arch/arm/cpu/armv7/socfpga/freeze_controller.c new file mode 100644 index 0000000..b8c9bce --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c @@ -0,0 +1,215 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/freeze_controller.h> +#include <asm/arch/timer.h> +#include <asm/errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_freeze_controller *freeze_controller_base = + (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS); + +/* + * Default state from cold reset is FREEZE_ALL; the global + * flag is set to TRUE to indicate the IO banks are frozen + */ +static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM] + = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN, + FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN}; + +/* Freeze HPS IOs */ +void sys_mgr_frzctrl_freeze_req(void) +{ + u32 ioctrl_reg_offset; + u32 reg_value; + u32 reg_cfg_mask; + u32 channel_id; + + /* select software FSM */ + writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); + + /* Freeze channel 0 to 2 */ + for (channel_id = 0; channel_id <= 2; channel_id++) { + ioctrl_reg_offset = (u32)( + &freeze_controller_base->vioctrl + + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + + /* + * Assert active low enrnsl, plniotri + * and niotri signals + */ + reg_cfg_mask = + SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK + | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK; + clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * Assert active low bhniotri signal and de-assert + * active high csrdone + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK; + clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* Set global flag to indicate channel is frozen */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN; + } + + /* Freeze channel 3 */ + /* + * Assert active low enrnsl, plniotri and + * niotri signals + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK + | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK; + clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); + + /* + * assert active low bhniotri & nfrzdrv signals, + * de-assert active high csrdone and assert + * active high frzreg and nfrzdrv signals + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK; + reg_value + = (reg_value & ~reg_cfg_mask) + | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK + | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* + * assert active high reinit signal and de-assert + * active high pllbiasen signals + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_value + = (reg_value & + ~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK) + | SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* Set global flag to indicate channel is frozen */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN; +} + +/* Unfreeze/Thaw HPS IOs */ +void sys_mgr_frzctrl_thaw_req(void) +{ + u32 ioctrl_reg_offset; + u32 reg_cfg_mask; + u32 reg_value; + u32 channel_id; + + /* select software FSM */ + writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); + + /* Thaw channel 0 to 2 */ + for (channel_id = 0; channel_id <= 2; channel_id++) { + ioctrl_reg_offset + = (u32)(&freeze_controller_base->vioctrl + + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + + /* + * Assert active low bhniotri signal and + * de-assert active high csrdone + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK; + setbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * de-assert active low plniotri and niotri signals + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK; + setbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * de-assert active low enrnsl signal + */ + setbits_le32(ioctrl_reg_offset, + SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK); + + /* Set global flag to indicate channel is thawed */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED; + } + + /* Thaw channel 3 */ + /* de-assert active high reinit signal */ + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK); + + /* + * Note: Delay for 40ns at min + * assert active high pllbiasen signals + */ + setbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK); + + /* + * Delay 1000 intosc. intosc is based on eosc1 + * Use worst case which is fatest eosc1=50MHz, delay required + * is 1/50MHz * 1000 = 20us + */ + udelay(20); + + /* + * de-assert active low bhniotri signals, + * assert active high csrdone and nfrzdrv signal + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_value = (reg_value + | SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK) + & ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* + * Delay 33 intosc + * Use worst case which is fatest eosc1=50MHz, delay required + * is 1/50MHz * 33 = 660ns ~= 1us + */ + udelay(1); + + /* de-assert active low plniotri and niotri signals */ + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK; + + setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); + + /* + * Note: Delay for 40ns at min + * de-assert active high frzreg signal + */ + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK); + + /* + * Note: Delay for 40ns at min + * de-assert active low enrnsl signal + */ + setbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK); + + /* Set global flag to indicate channel is thawed */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED; +} diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 74bceab..36a00c3 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -13,6 +13,7 @@ #include <asm/arch/reset_manager.h> #include <spl.h> #include <asm/arch/system_manager.h> +#include <asm/arch/freeze_controller.h> DECLARE_GLOBAL_DATA_PTR; @@ -27,6 +28,10 @@ u32 spl_boot_device(void) void spl_board_init(void) { #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET + debug("Freezing all I/O banks\n"); + /* freeze all IO banks */ + sys_mgr_frzctrl_freeze_req(); + /* configure the pin muxing through system manager */ sysmgr_pinmux_init(); #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ @@ -34,6 +39,10 @@ void spl_board_init(void) /* de-assert reset for peripherals and bridges based on handoff */ reset_deassert_peripherals_handoff(); + debug("Unfreezing/Thaw all I/O banks\n"); + /* unfreeze / thaw all IO banks */ + sys_mgr_frzctrl_thaw_req(); + /* enable console uart printing */ preloader_console_init(); } diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 2bb3843..9af340e 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -16,23 +16,24 @@ void lowlevel_init(void) int arch_cpu_init(void) { zynq_slcr_unlock(); - /* remap DDR to zero, FILTERSTART */ - writel(0, &scu_base->filter_start); /* Device config APB, unlock the PCAP */ writel(0x757BDF0D, &devcfg_base->unlock); writel(0xFFFFFFFF, &devcfg_base->rom_shadow); +#if (CONFIG_SYS_SDRAM_BASE == 0) + /* remap DDR to zero, FILTERSTART */ + writel(0, &scu_base->filter_start); + /* OCM_CFG, Mask out the ROM, map ram into upper addresses */ writel(0x1F, &slcr_base->ocm_cfg); /* FPGA_RST_CTRL, clear resets on AXI fabric ports */ writel(0x0, &slcr_base->fpga_rst_ctrl); - /* TZ_DDR_RAM, Set DDR trust zone non-secure */ - writel(0xFFFFFFFF, &slcr_base->trust_zone); /* Set urgent bits with register */ writel(0x0, &slcr_base->ddr_urgent_sel); /* Urgent write, ports S2/S3 */ writel(0xC, &slcr_base->ddr_urgent); +#endif zynq_slcr_lock(); diff --git a/arch/arm/cpu/at91-common/Makefile b/arch/arm/cpu/at91-common/Makefile new file mode 100644 index 0000000..5b97838 --- /dev/null +++ b/arch/arm/cpu/at91-common/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2000-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2013 Atmel Corporation +# Bo Shen <voice.shen@atmel.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o +obj-$(CONFIG_SPL_BUILD) += mpddrc.o spl.o diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/cpu/at91-common/mpddrc.c new file mode 100644 index 0000000..8136396 --- /dev/null +++ b/arch/arm/cpu/at91-common/mpddrc.c @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2013 Atmel Corporation + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/atmel_mpddrc.h> + +static inline void atmel_mpddr_op(int mode, u32 ram_address) +{ + struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + + writel(mode, &mpddr->mr); + writel(0, ram_address); +} + +int ddr2_init(const unsigned int ram_address, + const struct atmel_mpddr *mpddr_value) +{ + struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + u32 ba_off, cr; + + /* Compute bank offset according to NC in configuration register */ + ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9; + if (!(mpddr_value->cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)) + ba_off += ((mpddr->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11; + + ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2; + + /* Program the memory device type into the memory device register */ + writel(mpddr_value->md, &mpddr->md); + + /* Program the configuration register */ + writel(mpddr_value->cr, &mpddr->cr); + + /* Program the timing register */ + writel(mpddr_value->tpr0, &mpddr->tpr0); + writel(mpddr_value->tpr1, &mpddr->tpr1); + writel(mpddr_value->tpr2, &mpddr->tpr2); + + /* Issue a NOP command */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* A 200 us is provided to precede any signal toggle */ + udelay(200); + + /* Issue a NOP command */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* Issue an all banks precharge command */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); + + /* Issue an extended mode register set(EMRS2) to choose operation */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x2 << ba_off)); + + /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x3 << ba_off)); + + /* + * Issue an extended mode register set(EMRS1) to enable DLL and + * program D.I.C (output driver impedance control) + */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x1 << ba_off)); + + /* Enable DLL reset */ + cr = readl(&mpddr->cr); + writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr); + + /* A mode register set(MRS) cycle is issued to reset DLL */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); + + /* Issue an all banks precharge command */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); + + /* Two auto-refresh (CBR) cycles are provided */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); + + /* Disable DLL reset */ + cr = readl(&mpddr->cr); + writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr); + + /* A mode register set (MRS) cycle is issued to disable DLL reset */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); + + /* Set OCD calibration in default state */ + cr = readl(&mpddr->cr); + writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr); + + /* + * An extended mode register set (EMRS1) cycle is issued + * to OCD default value + */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x1 << ba_off)); + + /* OCD calibration mode exit */ + cr = readl(&mpddr->cr); + writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr); + + /* + * An extended mode register set (EMRS1) cycle is issued + * to enable OCD exit + */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x1 << ba_off)); + + /* A nornal mode command is provided */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address); + + /* Perform a write access to any DDR2-SDRAM address */ + writel(0, ram_address); + + /* Write the refresh rate */ + writel(mpddr_value->rtr, &mpddr->rtr); + + return 0; +} diff --git a/arch/arm/cpu/at91-common/phy.c b/arch/arm/cpu/at91-common/phy.c new file mode 100644 index 0000000..3b6c60c --- /dev/null +++ b/arch/arm/cpu/at91-common/phy.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + * + * (C) Copyright 2012 + * Markus Hubig <mhubig@imko.de> + * IMKO GmbH <www.imko.de> + * + * Copyright (C) 2013 DENX Software Engineering, hs@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/sizes.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <watchdog.h> + +void at91_phy_reset(void) +{ + unsigned long erstl; + unsigned long start = get_timer(0); + unsigned long const timeout = 1000; /* 1000ms */ + at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC; + + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; + + /* + * Need to reset PHY -> 500ms reset + * Reset PHY by pulling the NRST line for 500ms to low. To do so + * disable user reset for low level on NRST pin and poll the NRST + * level in reset status register. + */ + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); + + /* Wait for end of hardware reset */ + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) { + /* avoid shutdown by watchdog */ + WATCHDOG_RESET(); + mdelay(10); + + /* timeout for not getting stuck in an endless loop */ + if (get_timer(start) >= timeout) { + puts("*** ERROR: Timeout waiting for PHY reset!\n"); + break; + } + }; + + /* Restore NRST value */ + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); +} diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c new file mode 100644 index 0000000..37c0cc4 --- /dev/null +++ b/arch/arm/cpu/at91-common/spl.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2013 Atmel Corporation + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_wdt.h> +#include <asm/arch/clk.h> +#include <spl.h> + +static void at91_disable_wdt(void) +{ + struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT; + + writel(AT91_WDT_MR_WDDIS, &wdt->mr); +} + +void at91_plla_init(u32 pllar) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(pllar, &pmc->pllar); + while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) + ; +} + +void at91_mck_init(u32 mckr) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = readl(&pmc->mckr); + tmp &= ~(AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_2); + tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_2); + writel(tmp, &pmc->mckr); + + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; +} + + +u32 spl_boot_device(void) +{ +#ifdef CONFIG_SYS_USE_MMC + return BOOT_DEVICE_MMC1; +#endif + return BOOT_DEVICE_NONE; +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { +#ifdef CONFIG_SYS_USE_MMC + case BOOT_DEVICE_MMC1: + return MMCSD_MODE_FAT; + break; +#endif + case BOOT_DEVICE_NONE: + default: + hang(); + } +} + +void s_init(void) +{ + /* disable watchdog */ + at91_disable_wdt(); + + /* PMC configuration */ + at91_pmc_init(); + + at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + + timer_init(); + + board_early_init_f(); + + preloader_console_init(); + + mem_init(); +} diff --git a/arch/arm/cpu/at91-common/u-boot-spl.lds b/arch/arm/cpu/at91-common/u-boot-spl.lds new file mode 100644 index 0000000..038335d --- /dev/null +++ b/arch/arm/cpu/at91-common/u-boot-spl.lds @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Aneesh V <aneesh@ti.com> + * + * (C) 2013 Atmel Corporation + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + arch/arm/cpu/armv7/start.o (.text*) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } >.sdram +} diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds index c8d2e12..676ae2c 100644 --- a/arch/arm/cpu/ixp/u-boot.lds +++ b/arch/arm/cpu/ixp/u-boot.lds @@ -79,10 +79,13 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c index c9a7d45..7e861e2 100644 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -279,6 +279,7 @@ void reset_cpu(ulong ignored) tmp = readl(OSCR); tmp += 0x1000; writel(tmp, OSMR3); + writel(MDREFR_SLFRSH, MDREFR); for (;;) ; diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index 6fb11cb..60d71a6 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -71,6 +71,7 @@ int tegra_get_chip_sku(void) switch (sku_id) { case SKU_ID_T33: case SKU_ID_T30: + case SKU_ID_TM30MQS_P_A3: return TEGRA_SOC_T30; } break; diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index 36cc54a..4880d0f 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -51,12 +51,15 @@ SECTIONS __bss_end = .; } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } #if defined(CONFIG_SPL_MAX_SIZE) diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 23bf030..9463a33 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -91,12 +91,14 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } - /DISCARD/ : { *(.ARM.exidx*) } - /DISCARD/ : { *(.gnu.linkonce.armexidx.*) } + .dynsym _end : { *(.dynsym) } + .hash : { *(.hash) } + .got.plt : { *(.got.plt) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 519249e..7637457 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -98,13 +98,12 @@ extern const struct dpll_regs dpll_mpu_regs; extern const struct dpll_regs dpll_core_regs; extern const struct dpll_regs dpll_per_regs; extern const struct dpll_regs dpll_ddr_regs; -extern const struct dpll_params dpll_mpu; -extern const struct dpll_params dpll_core; -extern const struct dpll_params dpll_per; -extern const struct dpll_params dpll_ddr; extern struct cm_wkuppll *const cmwkup; +const struct dpll_params *get_dpll_mpu_params(void); +const struct dpll_params *get_dpll_core_params(void); +const struct dpll_params *get_dpll_per_params(void); const struct dpll_params *get_dpll_ddr_params(void); void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); void prcm_init(void); diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 02ed595..4c9352a 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -28,6 +28,9 @@ #define UART_CLK_RUNNING_MASK 0x1 #define UART_SMART_IDLE_EN (0x1 << 0x3) +#define CM_DLL_CTRL_NO_OVERRIDE 0x0 +#define CM_DLL_READYST 0x4 + extern void enable_dmm_clocks(void); extern const struct dpll_params dpll_core_opp100; extern struct dpll_params dpll_mpu_opp100; diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 05752ce..9febfa2 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -237,6 +237,14 @@ struct cm_perpll { unsigned int cpswclkstctrl; /* offset 0x144 */ unsigned int lcdcclkstctrl; /* offset 0x148 */ }; + +/* Encapsulating Display pll registers */ +struct cm_dpll { + unsigned int resv1[2]; + unsigned int clktimer2clk; /* offset 0x08 */ + unsigned int resv2[10]; + unsigned int clklcdcpixelclk; /* offset 0x34 */ +}; #else /* Encapsulating core pll registers */ struct cm_wkuppll { @@ -392,15 +400,17 @@ struct cm_perpll { unsigned int resv40[7]; unsigned int cpgmac0clkctrl; /* offset 0xB20 */ }; -#endif /* CONFIG_AM43XX */ -/* Encapsulating Display pll registers */ +struct cm_device_inst { + unsigned int cm_clkout1_ctrl; + unsigned int cm_dll_ctrl; +}; + struct cm_dpll { - unsigned int resv1[2]; - unsigned int clktimer2clk; /* offset 0x08 */ - unsigned int resv2[10]; - unsigned int clklcdcpixelclk; /* offset 0x34 */ + unsigned int resv1; + unsigned int clktimer2clk; /* offset 0x04 */ }; +#endif /* CONFIG_AM43XX */ /* Control Module RTC registers */ struct cm_rtc { @@ -475,6 +485,8 @@ struct ctrl_stat { unsigned int statusreg; /* ofset 0x40 */ unsigned int resv2[51]; unsigned int secure_emif_sdram_config; /* offset 0x0110 */ + unsigned int resv3[319]; + unsigned int dev_attr; }; /* AM33XX GPIO registers */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index fe48b5f..c1777df 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -18,8 +18,11 @@ #define VTP_CTRL_READY (0x1 << 5) #define VTP_CTRL_ENABLE (0x1 << 6) #define VTP_CTRL_START_EN (0x1) -#define PHY_DLL_LOCK_DIFF 0x0 +#ifdef CONFIG_AM43XX +#define DDR_CKE_CTRL_NORMAL 0x3 +#else #define DDR_CKE_CTRL_NORMAL 0x1 +#endif #define PHY_EN_DYN_PWRDN (0x1 << 20) /* Micron MT47H128M16RT-25E */ @@ -29,7 +32,6 @@ #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a -#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0 #define MT47H128M16RT25E_RATIO 0x80 #define MT47H128M16RT25E_INVERT_CLKOUT 0x00 #define MT47H128M16RT25E_RD_DQS 0x12 @@ -38,7 +40,6 @@ #define MT47H128M16RT25E_PHY_GATELVL 0x00 #define MT47H128M16RT25E_PHY_WR_DATA 0x40 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80 -#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B /* Micron MT41J128M16JT-125 */ @@ -49,7 +50,6 @@ #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2 #define MT41J128MJT125_EMIF_SDREF 0x0000093B #define MT41J128MJT125_ZQ_CFG 0x50074BE4 -#define MT41J128MJT125_DLL_LOCK_DIFF 0x1 #define MT41J128MJT125_RATIO 0x40 #define MT41J128MJT125_INVERT_CLKOUT 0x1 #define MT41J128MJT125_RD_DQS 0x3B @@ -58,6 +58,12 @@ #define MT41J128MJT125_PHY_FIFO_WE 0x100 #define MT41J128MJT125_IOCTRL_VALUE 0x18B +/* Micron MT41J64M16JT-125 */ +#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32 + +/* Micron MT41J256M16JT-125 */ +#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32 + /* Micron MT41J256M8HX-15E */ #define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06 #define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B @@ -66,7 +72,6 @@ #define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32 #define MT41J256M8HX15E_EMIF_SDREF 0x0000093B #define MT41J256M8HX15E_ZQ_CFG 0x50074BE4 -#define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1 #define MT41J256M8HX15E_RATIO 0x40 #define MT41J256M8HX15E_INVERT_CLKOUT 0x1 #define MT41J256M8HX15E_RD_DQS 0x3B @@ -83,7 +88,6 @@ #define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 #define MT41K256M16HA125E_EMIF_SDREF 0xC30 #define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 -#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1 #define MT41K256M16HA125E_RATIO 0x80 #define MT41K256M16HA125E_INVERT_CLKOUT 0x0 #define MT41K256M16HA125E_RD_DQS 0x38 @@ -100,7 +104,6 @@ #define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2 #define MT41J512M8RH125_EMIF_SDREF 0x0000093B #define MT41J512M8RH125_ZQ_CFG 0x50074BE4 -#define MT41J512M8RH125_DLL_LOCK_DIFF 0x1 #define MT41J512M8RH125_RATIO 0x80 #define MT41J512M8RH125_INVERT_CLKOUT 0x0 #define MT41J512M8RH125_RD_DQS 0x3B @@ -117,7 +120,6 @@ #define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2 #define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30 #define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4 -#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1 #define K4B2G1646EBIH9_RATIO 0x80 #define K4B2G1646EBIH9_INVERT_CLKOUT 0x0 #define K4B2G1646EBIH9_RD_DQS 0x35 @@ -126,6 +128,22 @@ #define K4B2G1646EBIH9_PHY_WR_DATA 0x76 #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B +#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294 +#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 +#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 + +#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84 +#define DDR3_DATA0_IOCTRL_VALUE 0x84 +#define DDR3_DATA1_IOCTRL_VALUE 0x84 +#define DDR3_DATA2_IOCTRL_VALUE 0x84 +#define DDR3_DATA3_IOCTRL_VALUE 0x84 + /** * Configure DMM */ @@ -135,6 +153,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs); * Configure SDRAM */ void config_sdram(const struct emif_regs *regs, int nr); +void config_sdram_emif4d5(const struct emif_regs *regs, int nr); /** * Set SDRAM timings @@ -149,18 +168,15 @@ void config_ddr_phy(const struct emif_regs *regs, int nr); struct ddr_cmd_regs { unsigned int resv0[7]; unsigned int cm0csratio; /* offset 0x01C */ - unsigned int resv1[2]; - unsigned int cm0dldiff; /* offset 0x028 */ + unsigned int resv1[3]; unsigned int cm0iclkout; /* offset 0x02C */ unsigned int resv2[8]; unsigned int cm1csratio; /* offset 0x050 */ - unsigned int resv3[2]; - unsigned int cm1dldiff; /* offset 0x05C */ + unsigned int resv3[3]; unsigned int cm1iclkout; /* offset 0x060 */ unsigned int resv4[8]; unsigned int cm2csratio; /* offset 0x084 */ - unsigned int resv5[2]; - unsigned int cm2dldiff; /* offset 0x090 */ + unsigned int resv5[3]; unsigned int cm2iclkout; /* offset 0x094 */ unsigned int resv6[3]; }; @@ -197,24 +213,21 @@ struct ddr_regs { unsigned int cm0configclk; /* offset 0x010 */ unsigned int resv1[2]; unsigned int cm0csratio; /* offset 0x01C */ - unsigned int resv2[2]; - unsigned int cm0dldiff; /* offset 0x028 */ + unsigned int resv2[3]; unsigned int cm0iclkout; /* offset 0x02C */ unsigned int resv3[4]; unsigned int cm1config; /* offset 0x040 */ unsigned int cm1configclk; /* offset 0x044 */ unsigned int resv4[2]; unsigned int cm1csratio; /* offset 0x050 */ - unsigned int resv5[2]; - unsigned int cm1dldiff; /* offset 0x05C */ + unsigned int resv5[3]; unsigned int cm1iclkout; /* offset 0x060 */ unsigned int resv6[4]; unsigned int cm2config; /* offset 0x074 */ unsigned int cm2configclk; /* offset 0x078 */ unsigned int resv7[2]; unsigned int cm2csratio; /* offset 0x084 */ - unsigned int resv8[2]; - unsigned int cm2dldiff; /* offset 0x090 */ + unsigned int resv8[3]; unsigned int cm2iclkout; /* offset 0x094 */ unsigned int resv9[12]; unsigned int dt0rdsratio0; /* offset 0x0C8 */ @@ -243,17 +256,14 @@ struct cmd_control { unsigned long cmd0csratio; unsigned long cmd0csforce; unsigned long cmd0csdelay; - unsigned long cmd0dldiff; unsigned long cmd0iclkout; unsigned long cmd1csratio; unsigned long cmd1csforce; unsigned long cmd1csdelay; - unsigned long cmd1dldiff; unsigned long cmd1iclkout; unsigned long cmd2csratio; unsigned long cmd2csforce; unsigned long cmd2csdelay; - unsigned long cmd2dldiff; unsigned long cmd2iclkout; }; @@ -267,8 +277,6 @@ struct ddr_data { unsigned long datagiratio0; unsigned long datafwsratio0; unsigned long datawrsratio0; - unsigned long datauserank0delay; - unsigned long datadldiff0; }; /** @@ -291,12 +299,27 @@ struct ddr_cmdtctrl { unsigned int resv2[12]; unsigned int dt0ioctl; unsigned int dt1ioctl; + unsigned int dt2ioctrl; + unsigned int dt3ioctrl; + unsigned int resv3[4]; + unsigned int emif_sdram_config_ext; +}; + +struct ctrl_ioregs { + unsigned int cm0ioctl; + unsigned int cm1ioctl; + unsigned int cm2ioctl; + unsigned int dt0ioctl; + unsigned int dt1ioctl; + unsigned int dt2ioctrl; + unsigned int dt3ioctrl; + unsigned int emif_sdram_config_ext; }; /** * Configure DDR io control registers */ -void config_io_ctrl(unsigned long val); +void config_io_ctrl(const struct ctrl_ioregs *ioregs); struct ddr_ctrl { unsigned int ddrioctrl; @@ -304,8 +327,9 @@ struct ddr_ctrl { unsigned int ddrckectrl; }; -void config_ddr(unsigned int pll, unsigned int ioctrl, +void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr); +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size); #endif /* _DDR_DEFS_H */ diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h index 13a047f..a1ffd49 100644 --- a/arch/arm/include/asm/arch-am33xx/gpio.h +++ b/arch/arm/include/asm/arch-am33xx/gpio.h @@ -13,4 +13,16 @@ #define AM33XX_GPIO2_BASE 0x481AC000 #define AM33XX_GPIO3_BASE 0x481AE000 +#define GPIO_22 22 + +/* GPIO CTRL register */ +#define GPIO_CTRL_DISABLEMODULE_SHIFT 0 +#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0) +#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK + +/* GPIO OUTPUT ENABLE register */ +#define GPIO_OE_ENABLE(x) (1 << x) + +/* GPIO SETDATAOUT register */ +#define GPIO_SETDATAOUT(x) (1 << x) #endif /* _GPIO_AM33xx_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index ee5fce0..dd950e5 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -48,13 +48,6 @@ #define EMIF4_0_CFG_BASE 0x4C000000 #define EMIF4_1_CFG_BASE 0x4D000000 -/* PLL related registers */ -#define CM_DPLL 0x44E00500 -#define CM_DEVICE 0x44E00700 -#define CM_RTC 0x44E00800 -#define CM_CEFUSE 0x44E00A00 -#define PRM_DEVICE 0x44E00F00 - /* DDR Base address */ #define DDR_CTRL_ADDR 0x44E10E04 #define DDR_CONTROL_BASE_ADDR 0x44E11404 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index e4231c8..c67a080 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -30,6 +30,8 @@ #define PRCM_BASE 0x44E00000 #define CM_PER 0x44E00000 #define CM_WKUP 0x44E00400 +#define CM_DPLL 0x44E00500 +#define CM_RTC 0x44E00800 #define PRM_RSTCTRL (PRCM_BASE + 0x0F00) #define PRM_RSTST (PRM_RSTCTRL + 8) diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 3b665e6..15399dc 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -30,6 +30,8 @@ #define PRCM_BASE 0x44DF0000 #define CM_WKUP 0x44DF2800 #define CM_PER 0x44DF8800 +#define CM_DPLL 0x44DF4200 +#define CM_RTC 0x44DF8500 #define PRM_RSTCTRL (PRCM_BASE + 0x4000) #define PRM_RSTST (PRM_RSTCTRL + 4) @@ -54,11 +56,25 @@ /* USB Clock Control */ #define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260) #define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268) -#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 2) +#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1) #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) #define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) -#define USBPHYOCPSCP_MODULE_EN (1 << 2) +#define USBPHYOCPSCP_MODULE_EN (1 << 1) +#define CM_DEVICE_INST 0x44df4100 + +/* Control status register */ +#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) +#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 +#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) +#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 +#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) +#define CTRL_SYSBOOT_15_14_SHIFT 22 + +#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 +#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 + +#define NUM_CRYSTAL_FREQ 0x4 #endif /* __AM43XX_HARDWARE_AM43XX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h b/arch/arm/include/asm/arch-am33xx/i2c.h index 8bfa53f..8642c8f 100644 --- a/arch/arm/include/asm/arch-am33xx/i2c.h +++ b/arch/arm/include/asm/arch-am33xx/i2c.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _I2C_H_ -#define _I2C_H_ +#ifndef _I2C_AM33XX_H_ +#define _I2C_AM33XX_H_ #define I2C_BASE1 0x44E0B000 #define I2C_BASE2 0x4802A000 @@ -62,4 +62,4 @@ struct i2c { #define I2C_IP_CLK 48000000 #define I2C_INTERNAL_SAMPLING_CLK 12000000 -#endif /* _I2C_H_ */ +#endif /* _I2C_AM33XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h index 983ea28..e7e8c58 100644 --- a/arch/arm/include/asm/arch-am33xx/mem.h +++ b/arch/arm/include/asm/arch-am33xx/mem.h @@ -68,9 +68,4 @@ #define PISMO2_NAND_CS0 7 #define PISMO2_NAND_CS1 8 -/* make it readable for the gpmc_init */ -#define PISMO1_NOR_BASE FLASH_BASE -#define PISMO1_NAND_BASE CONFIG_SYS_NAND_BASE -#define PISMO1_NAND_SIZE GPMC_SIZE_256M - #endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h index 0206912..98fc2b5 100644 --- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h @@ -137,6 +137,51 @@ struct pad_signals { int mcasp0_fsr; int mcasp0_axr1; int mcasp0_ahclkx; + int xdma_event_intr0; + int xdma_event_intr1; + int nresetin_out; + int porz; + int nnmi; + int osc0_in; + int osc0_out; + int rsvd1; + int tms; + int tdi; + int tdo; + int tck; + int ntrst; + int emu0; + int emu1; + int osc1_in; + int osc1_out; + int pmic_power_en; + int rtc_porz; + int rsvd2; + int ext_wakeup; + int enz_kaldo_1p8v; + int usb0_dm; + int usb0_dp; + int usb0_ce; + int usb0_id; + int usb0_vbus; + int usb0_drvvbus; + int usb1_dm; + int usb1_dp; + int usb1_ce; + int usb1_id; + int usb1_vbus; + int usb1_drvvbus; + int ddr_resetn; + int ddr_csn0; + int ddr_cke; + int ddr_ck; + int ddr_nck; + int ddr_casn; + int ddr_rasn; + int ddr_wen; + int ddr_ba0; + int ddr_ba1; + int ddr_ba2; }; #endif /* _MUX_AM43XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 2250721..7a7d91b 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -26,6 +26,8 @@ #elif defined(CONFIG_AM43XX) #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40340000 -#define SRAM_SCRATCH_SPACE_ADDR 0x4033C000 +#define SRAM_SCRATCH_SPACE_ADDR 0x40337C00 +#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR +#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC #endif #endif diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 95de9aa..5cd1e95 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -13,11 +13,18 @@ #define BOOT_DEVICE_MMC1 6 #define BOOT_DEVICE_MMC2 5 #define BOOT_DEVICE_UART 0x43 -#define BOOT_DEVICE_MMC2_2 0xFF +#elif defined(CONFIG_AM43XX) +#define BOOT_DEVICE_NOR 1 +#define BOOT_DEVICE_NAND 5 +#define BOOT_DEVICE_MMC1 7 +#define BOOT_DEVICE_MMC2 8 +#define BOOT_DEVICE_SPI 10 +#define BOOT_DEVICE_UART 65 +#define BOOT_DEVICE_CPGMAC 71 #else #define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 -#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) +#if defined(CONFIG_AM33XX) #define BOOT_DEVICE_MMC1 8 #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ #elif defined(CONFIG_TI814X) @@ -28,8 +35,8 @@ #define BOOT_DEVICE_UART 65 #define BOOT_DEVICE_USBETH 68 #define BOOT_DEVICE_CPGMAC 70 -#define BOOT_DEVICE_MMC2_2 0xFF #endif +#define BOOT_DEVICE_MMC2_2 0xFF #if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h index abcb97d..59e2f43 100644 --- a/arch/arm/include/asm/arch-at91/at91_common.h +++ b/arch/arm/include/asm/arch-at91/at91_common.h @@ -22,5 +22,10 @@ void at91_spi1_hw_init(unsigned long cs_mask); void at91_udp_hw_init(void); void at91_uhp_hw_init(void); void at91_lcd_hw_init(void); +void at91_plla_init(u32 pllar); +void at91_mck_init(u32 mckr); +void at91_pmc_init(void); +void mem_init(void); +void at91_phy_reset(void); #endif /* AT91_COMMON_H */ diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h index 676f024..50464ff 100644 --- a/arch/arm/include/asm/arch-at91/at91_pio.h +++ b/arch/arm/include/asm/arch-at91/at91_pio.h @@ -151,37 +151,4 @@ int at91_get_pio_value(unsigned port, unsigned pin); #define AT91_PIO_PORTD 0x3 #define AT91_PIO_PORTE 0x4 -#ifdef CONFIG_AT91_LEGACY - -#define PIO_PER 0x00 /* Enable Register */ -#define PIO_PDR 0x04 /* Disable Register */ -#define PIO_PSR 0x08 /* Status Register */ -#define PIO_OER 0x10 /* Output Enable Register */ -#define PIO_ODR 0x14 /* Output Disable Register */ -#define PIO_OSR 0x18 /* Output Status Register */ -#define PIO_IFER 0x20 /* Glitch Input Filter Enable */ -#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ -#define PIO_IFSR 0x28 /* Glitch Input Filter Status */ -#define PIO_SODR 0x30 /* Set Output Data Register */ -#define PIO_CODR 0x34 /* Clear Output Data Register */ -#define PIO_ODSR 0x38 /* Output Data Status Register */ -#define PIO_PDSR 0x3c /* Pin Data Status Register */ -#define PIO_IER 0x40 /* Interrupt Enable Register */ -#define PIO_IDR 0x44 /* Interrupt Disable Register */ -#define PIO_IMR 0x48 /* Interrupt Mask Register */ -#define PIO_ISR 0x4c /* Interrupt Status Register */ -#define PIO_MDER 0x50 /* Multi-driver Enable Register */ -#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ -#define PIO_MDSR 0x58 /* Multi-driver Status Register */ -#define PIO_PUDR 0x60 /* Pull-up Disable Register */ -#define PIO_PUER 0x64 /* Pull-up Enable Register */ -#define PIO_PUSR 0x68 /* Pull-up Status Register */ -#define PIO_ASR 0x70 /* Peripheral A Select Register */ -#define PIO_BSR 0x74 /* Peripheral B Select Register */ -#define PIO_ABSR 0x78 /* AB Status Register */ -#define PIO_OWER 0xa0 /* Output Write Enable Register */ -#define PIO_OWDR 0xa4 /* Output Write Disable Register */ -#define PIO_OWSR 0xa8 /* Output Write Status Register */ -#endif - #endif diff --git a/arch/arm/include/asm/arch-at91/at91_pit.h b/arch/arm/include/asm/arch-at91/at91_pit.h index d314b06..56724f1 100644 --- a/arch/arm/include/asm/arch-at91/at91_pit.h +++ b/arch/arm/include/asm/arch-at91/at91_pit.h @@ -25,20 +25,4 @@ typedef struct at91_pit { #define AT91_PIT_MR_PIV_MASK(x) (x & 0x000fffff) #define AT91_PIT_MR_PIV(x) (x & AT91_PIT_MR_PIV_MASK) -#ifdef CONFIG_AT91_LEGACY - -#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ -#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ -#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ -#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ - -#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ -#define AT91_PIT_PITS (1 << 0) /* Timer Status */ - -#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ -#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ -#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ -#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ - -#endif /* CONFIG_AT91_LEGACY */ #endif diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h index 7b36f74..4535608 100644 --- a/arch/arm/include/asm/arch-at91/at91_pmc.h +++ b/arch/arm/include/asm/arch-at91/at91_pmc.h @@ -14,13 +14,15 @@ #ifndef AT91_PMC_H #define AT91_PMC_H +#ifdef __ASSEMBLY__ + #define AT91_ASM_PMC_MOR (ATMEL_BASE_PMC + 0x20) #define AT91_ASM_PMC_PLLAR (ATMEL_BASE_PMC + 0x28) #define AT91_ASM_PMC_PLLBR (ATMEL_BASE_PMC + 0x2c) #define AT91_ASM_PMC_MCKR (ATMEL_BASE_PMC + 0x30) #define AT91_ASM_PMC_SR (ATMEL_BASE_PMC + 0x68) -#ifndef __ASSEMBLY__ +#else #include <asm/types.h> @@ -73,7 +75,11 @@ typedef struct at91_pmc { #define AT91_PMC_PLLXR_DIV(x) (x & 0xFF) #define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8) #define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14) +#ifdef CONFIG_SAMA5D3 +#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18) +#else #define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16) +#endif #define AT91_PMC_PLLAR_29 0x20000000 #define AT91_PMC_PLLBR_USBDIV_1 0x00000000 #define AT91_PMC_PLLBR_USBDIV_2 0x10000000 @@ -124,8 +130,8 @@ typedef struct at91_pmc { #define AT91_PMC_MCKR_MDIV_MASK 0x00000300 #endif -#define AT91_PMC_MCKR_PLLADIV_1 0x00001000 -#define AT91_PMC_MCKR_PLLADIV_2 0x00002000 +#define AT91_PMC_MCKR_PLLADIV_1 0x00000000 +#define AT91_PMC_MCKR_PLLADIV_2 0x00001000 #define AT91_PMC_IXR_MOSCS 0x00000001 #define AT91_PMC_IXR_LOCKA 0x00000002 @@ -137,13 +143,6 @@ typedef struct at91_pmc { #define AT91_PMC_IXR_PCKRDY2 0x00000400 #define AT91_PMC_IXR_PCKRDY3 0x00000800 -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ -#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ - -#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ -#endif - #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ @@ -159,34 +158,18 @@ typedef struct at91_pmc { #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ -#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ -#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ - -#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ -#endif - #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ -#endif #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ -#endif + #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ -#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ -#endif + #define AT91_PMC_DIV (0xff << 0) /* Divider */ #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ @@ -198,9 +181,6 @@ typedef struct at91_pmc { #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ #define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ -#endif #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ #define AT91_PMC_CSS_SLOW (0 << 0) #define AT91_PMC_CSS_MAIN (1 << 0) @@ -228,9 +208,6 @@ typedef struct at91_pmc { #define AT91_PMC_PDIV_1 (0 << 12) #define AT91_PMC_PDIV_2 (1 << 12) -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register */ -#endif #define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */ #define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */ #define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */ @@ -238,13 +215,6 @@ typedef struct at91_pmc { #define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */ #define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ - -#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ -#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ -#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ -#endif #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ @@ -255,13 +225,6 @@ typedef struct at91_pmc { #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ -#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ -#endif #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ -#ifdef CONFIG_AT91_LEGACY -#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ -#endif /* CONFIG_AT91_LEGACY */ #endif diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h b/arch/arm/include/asm/arch-at91/at91_spi.h index f44cf67..b18665b 100644 --- a/arch/arm/include/asm/arch-at91/at91_spi.h +++ b/arch/arm/include/asm/arch-at91/at91_spi.h @@ -118,6 +118,6 @@ typedef struct at91_spi { #define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */ -#endif /* CONFIG_AT91_LEGACY */ +#endif /* CONFIG_ATMEL_LEGACY */ #endif diff --git a/arch/arm/include/asm/arch-at91/at91_wdt.h b/arch/arm/include/asm/arch-at91/at91_wdt.h index f0f4ed1..0644bbf 100644 --- a/arch/arm/include/asm/arch-at91/at91_wdt.h +++ b/arch/arm/include/asm/arch-at91/at91_wdt.h @@ -40,25 +40,4 @@ typedef struct at91_wdt { #define AT91_WDT_MR_WDDBGHLT 0x10000000 #define AT91_WDT_MR_WDIDLEHLT 0x20000000 -#ifdef CONFIG_AT91_LEGACY - -#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ -#define AT91_WDT_WDRSTT (1 << 0) /* Restart */ -#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ - -#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ -#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ -#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ -#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ -#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ -#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ -#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ -#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ -#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ - -#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ -#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ -#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ - -#endif /* CONFIG_AT91_LEGACY */ #endif diff --git a/arch/arm/include/asm/arch-at91/at91cap9.h b/arch/arm/include/asm/arch-at91/at91cap9.h index 7ac5bc1..63870bc 100644 --- a/arch/arm/include/asm/arch-at91/at91cap9.h +++ b/arch/arm/include/asm/arch-at91/at91cap9.h @@ -55,75 +55,6 @@ #define AT91_RSTC_BASE 0xfffffd00 #define AT91_PIT_BASE 0xfffffd30 -#ifdef CONFIG_AT91_LEGACY - -/* - * User Peripheral physical base addresses. - */ -#define AT91CAP9_BASE_UDPHS 0xfff78000 -#define AT91CAP9_BASE_TCB0 0xfff7c000 -#define AT91CAP9_BASE_TC0 0xfff7c000 -#define AT91CAP9_BASE_TC1 0xfff7c040 -#define AT91CAP9_BASE_TC2 0xfff7c080 -#define AT91CAP9_BASE_MCI0 0xfff80000 -#define AT91CAP9_BASE_MCI1 0xfff84000 -#define AT91CAP9_BASE_TWI 0xfff88000 -#define AT91CAP9_BASE_US0 0xfff8c000 -#define AT91CAP9_BASE_US1 0xfff90000 -#define AT91CAP9_BASE_US2 0xfff94000 -#define AT91CAP9_BASE_SSC0 0xfff98000 -#define AT91CAP9_BASE_SSC1 0xfff9c000 -#define AT91CAP9_BASE_AC97C 0xfffa0000 -#define AT91CAP9_BASE_SPI0 0xfffa4000 -#define AT91CAP9_BASE_SPI1 0xfffa8000 -#define AT91CAP9_BASE_CAN 0xfffac000 -#define AT91CAP9_BASE_PWMC 0xfffb8000 -#define AT91CAP9_BASE_EMAC 0xfffbc000 -#define AT91CAP9_BASE_ADC 0xfffc0000 -#define AT91CAP9_BASE_ISI 0xfffc4000 -#define AT91_BASE_SYS 0xffffe200 - -/* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) -#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) -#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS) -#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS) -#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) -#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) -#define AT91_GPBR_REVB (0xfffffd50 - AT91_BASE_SYS) -#define AT91_GPBR_REVC (0xfffffd60 - AT91_BASE_SYS) - -#define AT91_USART0 AT91CAP9_BASE_US0 -#define AT91_USART1 AT91CAP9_BASE_US1 -#define AT91_USART2 AT91CAP9_BASE_US2 - -/* - * SCKCR flags - */ -#define AT91CAP9_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */ -#define AT91CAP9_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */ -#define AT91CAP9_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */ -#define AT91CAP9_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */ -#define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3) -#define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3) - -#endif /* CONFIG_AT91_LEGACY */ /* * Internal Memory. */ diff --git a/arch/arm/include/asm/arch-at91/at91sam9_smc.h b/arch/arm/include/asm/arch-at91/at91sam9_smc.h index ec5d797..d29e98e 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9_smc.h +++ b/arch/arm/include/asm/arch-at91/at91sam9_smc.h @@ -73,64 +73,4 @@ typedef struct at91_smc { #define AT91_SMC_MODE_PS_16 0x20000000 #define AT91_SMC_MODE_PS_32 0x30000000 -#ifdef CONFIG_AT91_LEGACY - -#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ -#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ -#define AT91_SMC_NWESETUP_(x) ((x) << 0) -#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ -#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) -#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ -#define AT91_SMC_NRDSETUP_(x) ((x) << 16) -#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ -#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) - -#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ -#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ -#define AT91_SMC_NWEPULSE_(x) ((x) << 0) -#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ -#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) -#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ -#define AT91_SMC_NRDPULSE_(x) ((x) << 16) -#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ -#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) - -#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ -#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ -#define AT91_SMC_NWECYCLE_(x) ((x) << 0) -#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ -#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) - -#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ -#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ -#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ -#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ -#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) -#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) -#define AT91_SMC_EXNWMODE_READY (3 << 4) -#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ -#define AT91_SMC_BAT_SELECT (0 << 8) -#define AT91_SMC_BAT_WRITE (1 << 8) -#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ -#define AT91_SMC_DBW_8 (0 << 12) -#define AT91_SMC_DBW_16 (1 << 12) -#define AT91_SMC_DBW_32 (2 << 12) -#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ -#define AT91_SMC_TDF_(x) ((x) << 16) -#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ -#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ -#define AT91_SMC_PS (3 << 28) /* Page Size */ -#define AT91_SMC_PS_4 (0 << 28) -#define AT91_SMC_PS_8 (1 << 28) -#define AT91_SMC_PS_16 (2 << 28) -#define AT91_SMC_PS_32 (3 << 28) - -#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ -#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ -#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ -#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ -#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ -#endif - -#endif #endif diff --git a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h new file mode 100644 index 0000000..5741f6e --- /dev/null +++ b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2013 Atmel Corporation + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ATMEL_MPDDRC_H__ +#define __ATMEL_MPDDRC_H__ + +/* + * Only define the needed register in mpddr + * If other register needed, will add them later + */ +struct atmel_mpddr { + u32 mr; + u32 rtr; + u32 cr; + u32 tpr0; + u32 tpr1; + u32 tpr2; + u32 reserved[2]; + u32 md; +}; + +int ddr2_init(const unsigned int ram_address, + const struct atmel_mpddr *mpddr); + +/* Bit field in mode register */ +#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0 +#define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1 +#define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD 0x2 +#define ATMEL_MPDDRC_MR_MODE_LMR_CMD 0x3 +#define ATMEL_MPDDRC_MR_MODE_RFSH_CMD 0x4 +#define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5 +#define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6 +#define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7 + +/* Bit field in configuration register */ +#define ATMEL_MPDDRC_CR_NC_MASK 0x3 +#define ATMEL_MPDDRC_CR_NC_COL_9 0x0 +#define ATMEL_MPDDRC_CR_NC_COL_10 0x1 +#define ATMEL_MPDDRC_CR_NC_COL_11 0x2 +#define ATMEL_MPDDRC_CR_NC_COL_12 0x3 +#define ATMEL_MPDDRC_CR_NR_MASK (0x3 << 2) +#define ATMEL_MPDDRC_CR_NR_ROW_11 (0x0 << 2) +#define ATMEL_MPDDRC_CR_NR_ROW_12 (0x1 << 2) +#define ATMEL_MPDDRC_CR_NR_ROW_13 (0x2 << 2) +#define ATMEL_MPDDRC_CR_NR_ROW_14 (0x3 << 2) +#define ATMEL_MPDDRC_CR_CAS_MASK (0x7 << 4) +#define ATMEL_MPDDRC_CR_CAS_DDR_CAS2 (0x2 << 4) +#define ATMEL_MPDDRC_CR_CAS_DDR_CAS3 (0x3 << 4) +#define ATMEL_MPDDRC_CR_CAS_DDR_CAS4 (0x4 << 4) +#define ATMEL_MPDDRC_CR_CAS_DDR_CAS5 (0x5 << 4) +#define ATMEL_MPDDRC_CR_CAS_DDR_CAS6 (0x6 << 4) +#define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED (0x1 << 7) +#define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8) +#define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9) +#define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12) +#define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17) +#define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20) +#define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21) +#define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED (0x1 << 22) +#define ATMEL_MPDDRC_CR_UNAL_SUPPORTED (0x1 << 23) + +/* Bit field in timing parameter 0 register */ +#define ATMEL_MPDDRC_TPR0_TRAS_OFFSET 0 +#define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf +#define ATMEL_MPDDRC_TPR0_TRCD_OFFSET 4 +#define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf +#define ATMEL_MPDDRC_TPR0_TWR_OFFSET 8 +#define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf +#define ATMEL_MPDDRC_TPR0_TRC_OFFSET 12 +#define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf +#define ATMEL_MPDDRC_TPR0_TRP_OFFSET 16 +#define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf +#define ATMEL_MPDDRC_TPR0_TRRD_OFFSET 20 +#define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf +#define ATMEL_MPDDRC_TPR0_TWTR_OFFSET 24 +#define ATMEL_MPDDRC_TPR0_TWTR_MASK 0x7 +#define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET 27 +#define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK 0x1 +#define ATMEL_MPDDRC_TPR0_TMRD_OFFSET 28 +#define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf + +/* Bit field in timing parameter 1 register */ +#define ATMEL_MPDDRC_TPR1_TRFC_OFFSET 0 +#define ATMEL_MPDDRC_TPR1_TRFC_MASK 0x7f +#define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET 8 +#define ATMEL_MPDDRC_TPR1_TXSNR_MASK 0xff +#define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET 16 +#define ATMEL_MPDDRC_TPR1_TXSRD_MASK 0xff +#define ATMEL_MPDDRC_TPR1_TXP_OFFSET 24 +#define ATMEL_MPDDRC_TPR1_TXP_MASK 0xf + +/* Bit field in timing parameter 2 register */ +#define ATMEL_MPDDRC_TPR2_TXARD_OFFSET 0 +#define ATMEL_MPDDRC_TPR2_TXARD_MASK 0xf +#define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET 4 +#define ATMEL_MPDDRC_TPR2_TXARDS_MASK 0xf +#define ATMEL_MPDDRC_TPR2_TRPA_OFFSET 8 +#define ATMEL_MPDDRC_TPR2_TRPA_MASK 0xf +#define ATMEL_MPDDRC_TPR2_TRTP_OFFSET 12 +#define ATMEL_MPDDRC_TPR2_TRTP_MASK 0x7 +#define ATMEL_MPDDRC_TPR2_TFAW_OFFSET 16 +#define ATMEL_MPDDRC_TPR2_TFAW_MASK 0xf + +/* Bit field in Memory Device Register */ +#define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3 +#define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6 +#define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4) +#define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4) +#define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4) + +#endif diff --git a/arch/arm/include/asm/arch-at91/gpio.h b/arch/arm/include/asm/arch-at91/gpio.h index 0700427..ff6142b 100644 --- a/arch/arm/include/asm/arch-at91/gpio.h +++ b/arch/arm/include/asm/arch-at91/gpio.h @@ -16,7 +16,7 @@ #ifdef CONFIG_ATMEL_LEGACY -#define PIN_BASE 32 +#define PIN_BASE 0 #define MAX_GPIO_BANKS 5 @@ -231,4 +231,26 @@ static inline unsigned pin_to_mask(unsigned pin) #define at91_set_gpio_value(x, y) at91_set_pio_value(x, y) #define at91_get_gpio_value(x) at91_get_pio_value(x) #endif -#endif + +#define GPIO_PIOA_BASE (0) +#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) +#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) +#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32) +#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32) +#define GPIO_PIN_PA(x) (GPIO_PIOA_BASE + (x)) +#define GPIO_PIN_PB(x) (GPIO_PIOB_BASE + (x)) +#define GPIO_PIN_PC(x) (GPIO_PIOC_BASE + (x)) +#define GPIO_PIN_PD(x) (GPIO_PIOD_BASE + (x)) +#define GPIO_PIN_PE(x) (GPIO_PIOE_BASE + (x)) + +static inline unsigned at91_gpio_to_port(unsigned gpio) +{ + return gpio / 32; +} + +static inline unsigned at91_gpio_to_pin(unsigned gpio) +{ + return gpio % 32; +} + +#endif /* __ASM_ARCH_AT91_GPIO_H */ diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h b/arch/arm/include/asm/arch-at91/sama5d3.h index 123a627..6d936f4 100644 --- a/arch/arm/include/asm/arch-at91/sama5d3.h +++ b/arch/arm/include/asm/arch-at91/sama5d3.h @@ -79,6 +79,7 @@ #define ARCH_EXID_SAMA5D33 0x00414300 #define ARCH_EXID_SAMA5D34 0x00414301 #define ARCH_EXID_SAMA5D35 0x00584300 +#define ARCH_EXID_SAMA5D36 0x00004301 #define cpu_is_sama5d3() (get_chip_id() == ARCH_ID_SAMA5D3) #define cpu_is_sama5d31() (cpu_is_sama5d3() && \ @@ -89,6 +90,8 @@ (get_extension_chip_id() == ARCH_EXID_SAMA5D34)) #define cpu_is_sama5d35() (cpu_is_sama5d3() && \ (get_extension_chip_id() == ARCH_EXID_SAMA5D35)) +#define cpu_is_sama5d36() (cpu_is_sama5d3() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D36)) /* * User Peripherals physical base addresses. diff --git a/arch/arm/include/asm/arch-at91/spl.h b/arch/arm/include/asm/arch-at91/spl.h new file mode 100644 index 0000000..68c5349 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/spl.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2013 Atmel Corporation + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +enum { + BOOT_DEVICE_NONE, +#ifdef CONFIG_SYS_USE_MMC + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_MMC2_2, +#endif +}; + +#endif diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h index 24abe57..6b806ec 100644 --- a/arch/arm/include/asm/arch-bcm2835/mbox.h +++ b/arch/arm/include/asm/arch-bcm2835/mbox.h @@ -350,6 +350,7 @@ struct bcm2835_mbox_tag_overscan { u32 top; u32 bottom; u32 left; + u32 right; } resp; } body; }; diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 7aaf4bf..27b1844 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -478,8 +478,9 @@ struct davinci_syscfg_regs { dv_reg rsvd[13]; dv_reg kick0; dv_reg kick1; - dv_reg rsvd1[53]; + dv_reg rsvd1[52]; dv_reg mstpri[3]; + dv_reg rsvd2; dv_reg pinmux[20]; dv_reg suspsrc; dv_reg chipsig; diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index d1c5d4f..09d739d 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -6,10 +6,6 @@ */ #define DWMCI_CLKSEL 0x09C -#define DWMCI_SHIFT_0 0x0 -#define DWMCI_SHIFT_1 0x1 -#define DWMCI_SHIFT_2 0x2 -#define DWMCI_SHIFT_3 0x3 #define DWMCI_SET_SAMPLE_CLK(x) (x) #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24) diff --git a/arch/arm/include/asm/arch-exynos/mmc.h b/arch/arm/include/asm/arch-exynos/mmc.h index 98312d1..98d6530 100644 --- a/arch/arm/include/asm/arch-exynos/mmc.h +++ b/arch/arm/include/asm/arch-exynos/mmc.h @@ -55,7 +55,7 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width); -static inline unsigned int s5p_mmc_init(int index, int bus_width) +static inline int s5p_mmc_init(int index, int bus_width) { unsigned int base = samsung_get_base_mmc() + (S5P_MMC_DEV_OFFSET * index); diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index 8db18c5..2bfee18 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -16,7 +16,7 @@ struct exynos4_power { unsigned int gnss_rtc_out_ctrl; unsigned char res2[0x1ec]; unsigned int system_power_down_ctrl; - unsigned char res3[0x1]; + unsigned int res3; unsigned int system_power_down_option; unsigned char res4[0x1f4]; unsigned int swreset; diff --git a/arch/arm/include/asm/arch-exynos/spi.h b/arch/arm/include/asm/arch-exynos/spi.h index 147c1a7..0ba931b 100644 --- a/arch/arm/include/asm/arch-exynos/spi.h +++ b/arch/arm/include/asm/arch-exynos/spi.h @@ -30,6 +30,7 @@ struct exynos_spi { #define EXYNOS_SPI_MAX_FREQ 50000000 #define SPI_TIMEOUT_MS 10 +#define SF_READ_DATA_CMD 0x3 /* SPI_CHCFG */ #define SPI_CH_HS_EN (1 << 6) diff --git a/arch/arm/include/asm/arch-omap3/clock.h b/arch/arm/include/asm/arch-omap3/clock.h index be669c1..1912cc9 100644 --- a/arch/arm/include/asm/arch-omap3/clock.h +++ b/arch/arm/include/asm/arch-omap3/clock.h @@ -27,8 +27,6 @@ #define ICK_DSS_ON 0x00000001 #define FCK_CAM_ON 0x00000001 #define ICK_CAM_ON 0x00000001 -#define FCK_PER_ON 0x0003ffff -#define ICK_PER_ON 0x0003ffff /* Used to index into DPLL parameter tables */ typedef struct { diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h index ae0babf..8bf6b48 100644 --- a/arch/arm/include/asm/arch-omap3/dss.h +++ b/arch/arm/include/asm/arch-omap3/dss.h @@ -178,10 +178,11 @@ struct venc_regs { #define LCD_INTERFACE_24_BIT 3 /* Polarity */ -#define DSS_IVS (1 << 12) -#define DSS_IHS (1 << 13) -#define DSS_IPC (1 << 14) -#define DSS_IEO (1 << 15) +#define DSS_IVS (1 << 12) +#define DSS_IHS (1 << 13) +#define DSS_IPC (1 << 14) +#define DSS_IEO (1 << 15) +#define DSS_ONOFF (1 << 17) /* GFX format */ #define GFXFORMAT_BITMAP1 (0x0 << 1) diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index 7fb549a..65a5995 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -55,6 +55,7 @@ struct control_prog_io { #define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000) #define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000) #define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000) +#define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000) /* General Purpose Timers */ #define OMAP34XX_GPT1 0x48318000 diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index e35f51c..f66da0d 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -116,7 +116,7 @@ struct s32ktimer { */ #define NON_SECURE_SRAM_START 0x40304000 #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ -#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START +#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000 /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4030D000 diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 39c5316..ce8217f 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -16,6 +16,10 @@ DECLARE_GLOBAL_DATA_PTR; +extern const struct emif_regs emif_regs_elpida_200_mhz_2cs; +extern const struct emif_regs emif_regs_elpida_380_mhz_1cs; +extern const struct emif_regs emif_regs_elpida_400_mhz_1cs; +extern const struct emif_regs emif_regs_elpida_400_mhz_2cs; struct omap_sysinfo { char *board_string; }; diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 8869b50..2dfe4ef 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -137,6 +137,9 @@ #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) +/* CM_L3INIT_SATA_CLKCTRL */ +#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + /* CM_WKUP_GPTIMER1_CLKCTRL */ #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 3c2306f..590235b 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -64,6 +64,9 @@ /* QSPI */ #define QSPI_BASE 0x4B300000 +/* SATA */ +#define DWC_AHSATA_BASE 0x4A140000 + /* * Hardware Register Details */ @@ -239,6 +242,7 @@ struct ctrl_ioregs { u32 ctrl_ddrio_1; u32 ctrl_ddrio_2; u32 ctrl_emif_sdram_config_ext; + u32 ctrl_emif_sdram_config_ext_final; u32 ctrl_ddr_ctrl_ext_0; }; diff --git a/arch/arm/include/asm/arch-omap5/sata.h b/arch/arm/include/asm/arch-omap5/sata.h new file mode 100644 index 0000000..2ca8947 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/sata.h @@ -0,0 +1,48 @@ +/* + * SATA Wrapper Register map + * + * (C) Copyright 2013 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TI_SATA_H +#define _TI_SATA_H + +/* SATA Wrapper module */ +#define TI_SATA_WRAPPER_BASE (OMAP54XX_L4_CORE_BASE + 0x141100) +/* SATA PHY Module */ +#define TI_SATA_PLLCTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x96800) + +/* SATA Wrapper register offsets */ +#define TI_SATA_SYSCONFIG 0x00 +#define TI_SATA_CDRLOCK 0x04 + +/* Register Set */ +#define TI_SATA_SYSCONFIG_OVERRIDE0 (1 << 16) +#define TI_SATA_SYSCONFIG_STANDBY_MASK (0x3 << 4) +#define TI_SATA_SYSCONFIG_IDLE_MASK (0x3 << 2) + +/* Standby modes */ +#define TI_SATA_STANDBY_FORCE 0x0 +#define TI_SATA_STANDBY_NO (0x1 << 4) +#define TI_SATA_STANDBY_SMART_WAKE (0x3 << 4) +#define TI_SATA_STANDBY_SMART (0x2 << 4) + +/* Idle modes */ +#define TI_SATA_IDLE_FORCE 0x0 +#define TI_SATA_IDLE_NO (0x1 << 2) +#define TI_SATA_IDLE_SMART_WAKE (0x3 << 2) +#define TI_SATA_IDLE_SMART (0x2 << 2) + +#ifdef CONFIG_SCSI_AHCI_PLAT +int omap_sata_init(void); +#else +static inline int omap_sata_init(void) +{ + return 0; +} +#endif /* CONFIG_SCSI_AHCI_PLAT */ + +#endif /* _TI_SATA_H */ diff --git a/arch/arm/include/asm/arch-rmobile/gpio.h b/arch/arm/include/asm/arch-rmobile/gpio.h index 6b5e4ed..560e9f4 100644 --- a/arch/arm/include/asm/arch-rmobile/gpio.h +++ b/arch/arm/include/asm/arch-rmobile/gpio.h @@ -7,6 +7,12 @@ void sh73a0_pinmux_init(void); #elif defined(CONFIG_R8A7740) #include "r8a7740-gpio.h" void r8a7740_pinmux_init(void); +#elif defined(CONFIG_R8A7790) +#include "r8a7790-gpio.h" +void r8a7790_pinmux_init(void); +#elif defined(CONFIG_R8A7791) +#include "r8a7791-gpio.h" +void r8a7791_pinmux_init(void); #endif #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h new file mode 100644 index 0000000..444e361 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h @@ -0,0 +1,387 @@ +#ifndef __ASM_R8A7790_H__ +#define __ASM_R8A7790_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU + */ +enum { + GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, + GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, + GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, + GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, + GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, + GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, + GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, + GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, + + GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, + GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, + GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, + GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, + GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, + GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, + GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, + GPIO_GP_1_28, GPIO_GP_1_29, + + GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, + GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, + GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, + GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, + GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, + GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, + GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, + GPIO_GP_2_28, GPIO_GP_2_29, + + GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, + GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, + GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, + GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, + GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, + GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, + GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, + GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, + + GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, + GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, + GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, + GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, + GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, + GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, + GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, + GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, + + GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, + GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, + GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, + GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, + GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, + GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, + GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, + GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31, + + GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC_VBUS, + GPIO_FN_USB2_PWEN, GPIO_FN_USB2_OVC, GPIO_FN_AVS1, GPIO_FN_AVS2, + GPIO_FN_DU_DOTCLKIN0, GPIO_FN_DU_DOTCLKIN2, + + /* IPSR0 */ + GPIO_FN_D1, GPIO_FN_MSIOF3_SYNC_B, GPIO_FN_VI3_DATA1, GPIO_FN_VI0_G5, + GPIO_FN_VI0_G5_B, GPIO_FN_D2, GPIO_FN_MSIOF3_RXD_B, GPIO_FN_VI3_DATA2, + GPIO_FN_VI0_G6, GPIO_FN_VI0_G6_B, GPIO_FN_D3, GPIO_FN_MSIOF3_TXD_B, + GPIO_FN_VI3_DATA3, GPIO_FN_VI0_G7, GPIO_FN_VI0_G7_B, GPIO_FN_D4, + GPIO_FN_SCIFB1_RXD_F, GPIO_FN_SCIFB0_RXD_C, GPIO_FN_VI3_DATA4, + GPIO_FN_VI0_R0, GPIO_FN_VI0_R0_B, GPIO_FN_RX0_B, GPIO_FN_D5, + GPIO_FN_SCIFB1_TXD_F, GPIO_FN_SCIFB0_TXD_C, GPIO_FN_VI3_DATA5, + GPIO_FN_VI0_R1, GPIO_FN_VI0_R1_B, GPIO_FN_TX0_B, GPIO_FN_D6, + GPIO_FN_SCL2_C, GPIO_FN_VI3_DATA6, GPIO_FN_VI0_R2, GPIO_FN_VI0_R2_B, + GPIO_FN_SCL2_CIS_C, GPIO_FN_D7, GPIO_FN_AD_DI_B, GPIO_FN_SDA2_C, + GPIO_FN_VI3_DATA7, GPIO_FN_VI0_R3, GPIO_FN_VI0_R3_B, GPIO_FN_SDA2_CIS_C, + GPIO_FN_D8, GPIO_FN_SCIFA1_SCK_C, GPIO_FN_AVB_TXD0, GPIO_FN_MII_TXD0, + GPIO_FN_VI0_G0, GPIO_FN_VI0_G0_B, GPIO_FN_VI2_DATA0_VI2_B0, + + /* IPSR1 */ + GPIO_FN_D9, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_AVB_TXD1, GPIO_FN_MII_TXD1, + GPIO_FN_VI0_G1, GPIO_FN_VI0_G1_B, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_D10, + GPIO_FN_SCIFA1_TXD_C, GPIO_FN_AVB_TXD2, GPIO_FN_MII_TXD2, + GPIO_FN_VI0_G2, GPIO_FN_VI0_G2_B, GPIO_FN_VI2_DATA2_VI2_B2, GPIO_FN_D11, + GPIO_FN_SCIFA1_CTS_N_C, GPIO_FN_AVB_TXD3, GPIO_FN_MII_TXD3, + GPIO_FN_VI0_G3, GPIO_FN_VI0_G3_B, GPIO_FN_VI2_DATA3_VI2_B3, + GPIO_FN_D12, GPIO_FN_SCIFA1_RTS_N_C, GPIO_FN_AVB_TXD4, + GPIO_FN_VI0_HSYNC_N, GPIO_FN_VI0_HSYNC_N_B, GPIO_FN_VI2_DATA4_VI2_B4, + GPIO_FN_D13, GPIO_FN_AVB_TXD5, GPIO_FN_VI0_VSYNC_N, + GPIO_FN_VI0_VSYNC_N_B, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_D14, + GPIO_FN_SCIFB1_RXD_C, GPIO_FN_AVB_TXD6, GPIO_FN_RX1_B, + GPIO_FN_VI0_CLKENB, GPIO_FN_VI0_CLKENB_B, GPIO_FN_VI2_DATA6_VI2_B6, + GPIO_FN_D15, GPIO_FN_SCIFB1_TXD_C, GPIO_FN_AVB_TXD7, GPIO_FN_TX1_B, + GPIO_FN_VI0_FIELD, GPIO_FN_VI0_FIELD_B, GPIO_FN_VI2_DATA7_VI2_B7, + GPIO_FN_A0, GPIO_FN_PWM3, GPIO_FN_A1, GPIO_FN_PWM4, + + /* IPSR2 */ + GPIO_FN_A2, GPIO_FN_PWM5, GPIO_FN_MSIOF1_SS1_B, GPIO_FN_A3, + GPIO_FN_PWM6, GPIO_FN_MSIOF1_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF1_TXD_B, + GPIO_FN_TPU0TO0, GPIO_FN_A5, GPIO_FN_SCIFA1_TXD_B, GPIO_FN_TPU0TO1, + GPIO_FN_A6, GPIO_FN_SCIFA1_RTS_N_B, GPIO_FN_TPU0TO2, GPIO_FN_A7, + GPIO_FN_SCIFA1_SCK_B, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_TPU0TO3, + GPIO_FN_A8, GPIO_FN_SCIFA1_RXD_B, GPIO_FN_SSI_SCK5_B, GPIO_FN_VI0_R4, + GPIO_FN_VI0_R4_B, GPIO_FN_SCIFB2_RXD_C, GPIO_FN_VI2_DATA0_VI2_B0_B, + GPIO_FN_A9, GPIO_FN_SCIFA1_CTS_N_B, GPIO_FN_SSI_WS5_B, GPIO_FN_VI0_R5, + GPIO_FN_VI0_R5_B, GPIO_FN_SCIFB2_TXD_C, GPIO_FN_VI2_DATA1_VI2_B1_B, + GPIO_FN_A10, GPIO_FN_SSI_SDATA5_B, GPIO_FN_MSIOF2_SYNC, GPIO_FN_VI0_R6, + GPIO_FN_VI0_R6_B, GPIO_FN_VI2_DATA2_VI2_B2_B, + + /* IPSR3 */ + GPIO_FN_A11, GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_MSIOF2_SCK, GPIO_FN_VI1_R0, + GPIO_FN_VI1_R0_B, GPIO_FN_VI2_G0, GPIO_FN_VI2_DATA3_VI2_B3_B, + GPIO_FN_A12, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_MSIOF2_TXD, GPIO_FN_VI1_R1, + GPIO_FN_VI1_R1_B, GPIO_FN_VI2_G1, GPIO_FN_VI2_DATA4_VI2_B4_B, + GPIO_FN_A13, GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_EX_WAIT2, + GPIO_FN_MSIOF2_RXD, GPIO_FN_VI1_R2, GPIO_FN_VI1_R2_B, GPIO_FN_VI2_G2, + GPIO_FN_VI2_DATA5_VI2_B5_B, GPIO_FN_A14, GPIO_FN_SCIFB2_TXD_B, + GPIO_FN_ATACS11_N, GPIO_FN_MSIOF2_SS1, GPIO_FN_A15, + GPIO_FN_SCIFB2_SCK_B, GPIO_FN_ATARD1_N, GPIO_FN_MSIOF2_SS2, GPIO_FN_A16, + GPIO_FN_ATAWR1_N, GPIO_FN_A17, GPIO_FN_AD_DO_B, GPIO_FN_ATADIR1_N, + GPIO_FN_A18, GPIO_FN_AD_CLK_B, GPIO_FN_ATAG1_N, GPIO_FN_A19, + GPIO_FN_AD_NCS_N_B, GPIO_FN_ATACS01_N, GPIO_FN_EX_WAIT0_B, GPIO_FN_A20, + GPIO_FN_SPCLK, GPIO_FN_VI1_R3, GPIO_FN_VI1_R3_B, GPIO_FN_VI2_G4, + + /* IPSR4 */ + GPIO_FN_A21, GPIO_FN_MOSI_IO0, GPIO_FN_VI1_R4, GPIO_FN_VI1_R4_B, + GPIO_FN_VI2_G5, GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_VI1_R5, + GPIO_FN_VI1_R5_B, GPIO_FN_VI2_G6, GPIO_FN_A23, GPIO_FN_IO2, + GPIO_FN_VI1_G7, GPIO_FN_VI1_G7_B, GPIO_FN_VI2_G7, GPIO_FN_A24, + GPIO_FN_IO3, GPIO_FN_VI1_R7, GPIO_FN_VI1_R7_B, GPIO_FN_VI2_CLKENB, + GPIO_FN_VI2_CLKENB_B, GPIO_FN_A25, GPIO_FN_SSL, GPIO_FN_VI1_G6, + GPIO_FN_VI1_G6_B, GPIO_FN_VI2_FIELD, GPIO_FN_VI2_FIELD_B, GPIO_FN_CS0_N, + GPIO_FN_VI1_R6, GPIO_FN_VI1_R6_B, GPIO_FN_VI2_G3, GPIO_FN_MSIOF0_SS2_B, + GPIO_FN_CS1_N_A26, GPIO_FN_SPEEDIN, GPIO_FN_VI0_R7, GPIO_FN_VI0_R7_B, + GPIO_FN_VI2_CLK, GPIO_FN_VI2_CLK_B, GPIO_FN_EX_CS0_N, GPIO_FN_HRX1_B, + GPIO_FN_VI1_G5, GPIO_FN_VI1_G5_B, GPIO_FN_VI2_R0, GPIO_FN_HTX0_B, + GPIO_FN_MSIOF0_SS1_B, GPIO_FN_EX_CS1_N, GPIO_FN_GPS_CLK, + GPIO_FN_HCTS1_N_B, GPIO_FN_VI1_FIELD, GPIO_FN_VI1_FIELD_B, + GPIO_FN_VI2_R1, GPIO_FN_EX_CS2_N, GPIO_FN_GPS_SIGN, GPIO_FN_HRTS1_N_B, + GPIO_FN_VI3_CLKENB, GPIO_FN_VI1_G0, GPIO_FN_VI1_G0_B, GPIO_FN_VI2_R2, + + /* IPSR5 */ + GPIO_FN_EX_CS3_N, GPIO_FN_GPS_MAG, GPIO_FN_VI3_FIELD, GPIO_FN_VI1_G1, + GPIO_FN_VI1_G1_B, GPIO_FN_VI2_R3, GPIO_FN_EX_CS4_N, + GPIO_FN_MSIOF1_SCK_B, GPIO_FN_VI3_HSYNC_N, + GPIO_FN_VI2_HSYNC_N, GPIO_FN_SCL1, GPIO_FN_VI2_HSYNC_N_B, + GPIO_FN_INTC_EN0_N, GPIO_FN_SCL1_CIS, GPIO_FN_EX_CS5_N, GPIO_FN_CAN0_RX, + GPIO_FN_MSIOF1_RXD_B, GPIO_FN_VI3_VSYNC_N, GPIO_FN_VI1_G2, + GPIO_FN_VI1_G2_B, GPIO_FN_VI2_R4, GPIO_FN_SDA1, GPIO_FN_INTC_EN1_N, + GPIO_FN_SDA1_CIS, GPIO_FN_BS_N, GPIO_FN_IETX, GPIO_FN_HTX1_B, + GPIO_FN_CAN1_TX, GPIO_FN_DRACK0, GPIO_FN_IETX_C, GPIO_FN_RD_N, + GPIO_FN_CAN0_TX, GPIO_FN_SCIFA0_SCK_B, GPIO_FN_RD_WR_N, GPIO_FN_VI1_G3, + GPIO_FN_VI1_G3_B, GPIO_FN_VI2_R5, GPIO_FN_SCIFA0_RXD_B, + GPIO_FN_INTC_IRQ4_N, GPIO_FN_WE0_N, GPIO_FN_IECLK, GPIO_FN_CAN_CLK, + GPIO_FN_VI2_VSYNC_N, GPIO_FN_SCIFA0_TXD_B, GPIO_FN_VI2_VSYNC_N_B, + GPIO_FN_WE1_N, GPIO_FN_IERX, GPIO_FN_CAN1_RX, GPIO_FN_VI1_G4, + GPIO_FN_VI1_G4_B, GPIO_FN_VI2_R6, GPIO_FN_SCIFA0_CTS_N_B, + GPIO_FN_IERX_C, GPIO_FN_EX_WAIT0, GPIO_FN_IRQ3, GPIO_FN_INTC_IRQ3_N, + GPIO_FN_VI3_CLK, GPIO_FN_SCIFA0_RTS_N_B, GPIO_FN_HRX0_B, + GPIO_FN_MSIOF0_SCK_B, GPIO_FN_DREQ0_N, GPIO_FN_VI1_HSYNC_N, + GPIO_FN_VI1_HSYNC_N_B, GPIO_FN_VI2_R7, GPIO_FN_SSI_SCK78_C, + GPIO_FN_SSI_WS78_B, + + /* IPSR6 */ + GPIO_FN_DACK0, GPIO_FN_IRQ0, GPIO_FN_INTC_IRQ0_N, GPIO_FN_SSI_SCK6_B, + GPIO_FN_VI1_VSYNC_N, GPIO_FN_VI1_VSYNC_N_B, GPIO_FN_SSI_WS78_C, + GPIO_FN_DREQ1_N, GPIO_FN_VI1_CLKENB, GPIO_FN_VI1_CLKENB_B, + GPIO_FN_SSI_SDATA7_C, GPIO_FN_SSI_SCK78_B, GPIO_FN_DACK1, GPIO_FN_IRQ1, + GPIO_FN_INTC_IRQ1_N, GPIO_FN_SSI_WS6_B, GPIO_FN_SSI_SDATA8_C, + GPIO_FN_DREQ2_N, GPIO_FN_HSCK1_B, GPIO_FN_HCTS0_N_B, + GPIO_FN_MSIOF0_TXD_B, GPIO_FN_DACK2, GPIO_FN_IRQ2, GPIO_FN_INTC_IRQ2_N, + GPIO_FN_SSI_SDATA6_B, GPIO_FN_HRTS0_N_B, GPIO_FN_MSIOF0_RXD_B, + GPIO_FN_ETH_CRS_DV, GPIO_FN_RMII_CRS_DV, GPIO_FN_STP_ISCLK_0_B, + GPIO_FN_TS_SDEN0_D, GPIO_FN_GLO_Q0_C, GPIO_FN_SCL2_E, + GPIO_FN_SCL2_CIS_E, GPIO_FN_ETH_RX_ER, GPIO_FN_RMII_RX_ER, + GPIO_FN_STP_ISD_0_B, GPIO_FN_TS_SPSYNC0_D, GPIO_FN_GLO_Q1_C, + GPIO_FN_SDA2_E, GPIO_FN_SDA2_CIS_E, GPIO_FN_ETH_RXD0, GPIO_FN_RMII_RXD0, + GPIO_FN_STP_ISEN_0_B, GPIO_FN_TS_SDAT0_D, GPIO_FN_GLO_I0_C, + GPIO_FN_SCIFB1_SCK_G, GPIO_FN_SCK1_E, GPIO_FN_ETH_RXD1, + GPIO_FN_RMII_RXD1, GPIO_FN_HRX0_E, GPIO_FN_STP_ISSYNC_0_B, + GPIO_FN_TS_SCK0_D, GPIO_FN_GLO_I1_C, GPIO_FN_SCIFB1_RXD_G, + GPIO_FN_RX1_E, GPIO_FN_ETH_LINK, GPIO_FN_RMII_LINK, GPIO_FN_HTX0_E, + GPIO_FN_STP_IVCXO27_0_B, GPIO_FN_SCIFB1_TXD_G, GPIO_FN_TX1_E, + GPIO_FN_ETH_REF_CLK, GPIO_FN_RMII_REF_CLK, GPIO_FN_HCTS0_N_E, + GPIO_FN_STP_IVCXO27_1_B, GPIO_FN_HRX0_F, + + /* IPSR7 */ + GPIO_FN_ETH_MDIO, GPIO_FN_RMII_MDIO, GPIO_FN_HRTS0_N_E, + GPIO_FN_SIM0_D_C, GPIO_FN_HCTS0_N_F, GPIO_FN_ETH_TXD1, + GPIO_FN_RMII_TXD1, GPIO_FN_HTX0_F, GPIO_FN_BPFCLK_G, GPIO_FN_RDS_CLK_F, + GPIO_FN_ETH_TX_EN, GPIO_FN_RMII_TX_EN, GPIO_FN_SIM0_CLK_C, + GPIO_FN_HRTS0_N_F, GPIO_FN_ETH_MAGIC, GPIO_FN_RMII_MAGIC, + GPIO_FN_SIM0_RST_C, GPIO_FN_ETH_TXD0, GPIO_FN_RMII_TXD0, + GPIO_FN_STP_ISCLK_1_B, GPIO_FN_TS_SDEN1_C, GPIO_FN_GLO_SCLK_C, + GPIO_FN_ETH_MDC, GPIO_FN_RMII_MDC, GPIO_FN_STP_ISD_1_B, + GPIO_FN_TS_SPSYNC1_C, GPIO_FN_GLO_SDATA_C, GPIO_FN_PWM0, + GPIO_FN_SCIFA2_SCK_C, GPIO_FN_STP_ISEN_1_B, GPIO_FN_TS_SDAT1_C, + GPIO_FN_GLO_SS_C, GPIO_FN_PWM1, GPIO_FN_SCIFA2_TXD_C, + GPIO_FN_STP_ISSYNC_1_B, GPIO_FN_TS_SCK1_C, GPIO_FN_GLO_RFON_C, + GPIO_FN_PCMOE_N, GPIO_FN_PWM2, GPIO_FN_PWMFSW0, GPIO_FN_SCIFA2_RXD_C, + GPIO_FN_PCMWE_N, GPIO_FN_IECLK_C, GPIO_FN_DU1_DOTCLKIN, + GPIO_FN_AUDIO_CLKC, GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_VI0_CLK, + GPIO_FN_ATACS00_N, GPIO_FN_AVB_RXD1, GPIO_FN_MII_RXD1, + GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_ATACS10_N, GPIO_FN_AVB_RXD2, + GPIO_FN_MII_RXD2, + + /* IPSR8 */ + GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_ATARD0_N, GPIO_FN_AVB_RXD3, + GPIO_FN_MII_RXD3, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_ATAWR0_N, + GPIO_FN_AVB_RXD4, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ATADIR0_N, + GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ATAG0_N, + GPIO_FN_AVB_RXD6, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_EX_WAIT1, + GPIO_FN_AVB_RXD7, GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RX_ER, + GPIO_FN_MII_RX_ER, GPIO_FN_VI0_DATA7_VI0_B7, GPIO_FN_AVB_RX_CLK, + GPIO_FN_MII_RX_CLK, GPIO_FN_VI1_CLK, GPIO_FN_AVB_RX_DV, + GPIO_FN_MII_RX_DV, GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SCIFA1_SCK_D, + GPIO_FN_AVB_CRS, GPIO_FN_MII_CRS, GPIO_FN_VI1_DATA1_VI1_B1, + GPIO_FN_SCIFA1_RXD_D, GPIO_FN_AVB_MDC, GPIO_FN_MII_MDC, + GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SCIFA1_TXD_D, GPIO_FN_AVB_MDIO, + GPIO_FN_MII_MDIO, GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SCIFA1_CTS_N_D, + GPIO_FN_AVB_GTX_CLK, GPIO_FN_VI1_DATA4_VI1_B4, GPIO_FN_SCIFA1_RTS_N_D, + GPIO_FN_AVB_MAGIC, GPIO_FN_MII_MAGIC, GPIO_FN_VI1_DATA5_VI1_B5, + GPIO_FN_AVB_PHY_INT, GPIO_FN_VI1_DATA6_VI1_B6, GPIO_FN_AVB_GTXREFCLK, + GPIO_FN_SD0_CLK, GPIO_FN_VI1_DATA0_VI1_B0_B, GPIO_FN_SD0_CMD, + GPIO_FN_SCIFB1_SCK_B, GPIO_FN_VI1_DATA1_VI1_B1_B, + + /* IPSR9 */ + GPIO_FN_SD0_DAT0, GPIO_FN_SCIFB1_RXD_B, GPIO_FN_VI1_DATA2_VI1_B2_B, + GPIO_FN_SD0_DAT1, GPIO_FN_SCIFB1_TXD_B, GPIO_FN_VI1_DATA3_VI1_B3_B, + GPIO_FN_SD0_DAT2, GPIO_FN_SCIFB1_CTS_N_B, GPIO_FN_VI1_DATA4_VI1_B4_B, + GPIO_FN_SD0_DAT3, GPIO_FN_SCIFB1_RTS_N_B, GPIO_FN_VI1_DATA5_VI1_B5_B, + GPIO_FN_SD0_CD, GPIO_FN_MMC0_D6, GPIO_FN_TS_SDEN0_B, GPIO_FN_USB0_EXTP, + GPIO_FN_GLO_SCLK, GPIO_FN_VI1_DATA6_VI1_B6_B, GPIO_FN_SCL1_B, + GPIO_FN_SCL1_CIS_B, GPIO_FN_VI2_DATA6_VI2_B6_B, GPIO_FN_SD0_WP, + GPIO_FN_MMC0_D7, GPIO_FN_TS_SPSYNC0_B, GPIO_FN_USB0_IDIN, + GPIO_FN_GLO_SDATA, GPIO_FN_VI1_DATA7_VI1_B7_B, GPIO_FN_SDA1_B, + GPIO_FN_SDA1_CIS_B, GPIO_FN_VI2_DATA7_VI2_B7_B, GPIO_FN_SD1_CLK, + GPIO_FN_AVB_TX_EN, GPIO_FN_MII_TX_EN, GPIO_FN_SD1_CMD, + GPIO_FN_AVB_TX_ER, GPIO_FN_MII_TX_ER, GPIO_FN_SCIFB0_SCK_B, + GPIO_FN_SD1_DAT0, GPIO_FN_AVB_TX_CLK, GPIO_FN_MII_TX_CLK, + GPIO_FN_SCIFB0_RXD_B, GPIO_FN_SD1_DAT1, GPIO_FN_AVB_LINK, + GPIO_FN_MII_LINK, GPIO_FN_SCIFB0_TXD_B, GPIO_FN_SD1_DAT2, + GPIO_FN_AVB_COL, GPIO_FN_MII_COL, GPIO_FN_SCIFB0_CTS_N_B, + GPIO_FN_SD1_DAT3, GPIO_FN_AVB_RXD0, GPIO_FN_MII_RXD0, + GPIO_FN_SCIFB0_RTS_N_B, GPIO_FN_SD1_CD, GPIO_FN_MMC1_D6, + GPIO_FN_TS_SDEN1, GPIO_FN_USB1_EXTP, GPIO_FN_GLO_SS, GPIO_FN_VI0_CLK_B, + GPIO_FN_SCL2_D, GPIO_FN_SCL2_CIS_D, GPIO_FN_SIM0_CLK_B, + GPIO_FN_VI3_CLK_B, + + /* IPSR10 */ + GPIO_FN_SD1_WP, GPIO_FN_MMC1_D7, GPIO_FN_TS_SPSYNC1, GPIO_FN_USB1_IDIN, + GPIO_FN_GLO_RFON, GPIO_FN_VI1_CLK_B, GPIO_FN_SDA2_D, GPIO_FN_SDA2_CIS_D, + GPIO_FN_SIM0_D_B, GPIO_FN_SD2_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_SIM0_CLK, + GPIO_FN_VI0_DATA0_VI0_B0_B, GPIO_FN_TS_SDEN0_C, GPIO_FN_GLO_SCLK_B, + GPIO_FN_VI3_DATA0_B, GPIO_FN_SD2_CMD, GPIO_FN_MMC0_CMD, GPIO_FN_SIM0_D, + GPIO_FN_VI0_DATA1_VI0_B1_B, GPIO_FN_SCIFB1_SCK_E, GPIO_FN_SCK1_D, + GPIO_FN_TS_SPSYNC0_C, GPIO_FN_GLO_SDATA_B, GPIO_FN_VI3_DATA1_B, + GPIO_FN_SD2_DAT0, GPIO_FN_MMC0_D0, GPIO_FN_FMCLK_B, + GPIO_FN_VI0_DATA2_VI0_B2_B, GPIO_FN_SCIFB1_RXD_E, GPIO_FN_RX1_D, + GPIO_FN_TS_SDAT0_C, GPIO_FN_GLO_SS_B, GPIO_FN_VI3_DATA2_B, + GPIO_FN_SD2_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FMIN_B, GPIO_FN_RDS_DATA, + GPIO_FN_VI0_DATA3_VI0_B3_B, GPIO_FN_SCIFB1_TXD_E, GPIO_FN_TX1_D, + GPIO_FN_TS_SCK0_C, GPIO_FN_GLO_RFON_B, GPIO_FN_VI3_DATA3_B, + GPIO_FN_SD2_DAT2, GPIO_FN_MMC0_D2, GPIO_FN_BPFCLK_B, GPIO_FN_RDS_CLK, + GPIO_FN_VI0_DATA4_VI0_B4_B, GPIO_FN_HRX0_D, GPIO_FN_TS_SDEN1_B, + GPIO_FN_GLO_Q0_B, GPIO_FN_VI3_DATA4_B, GPIO_FN_SD2_DAT3, + GPIO_FN_MMC0_D3, GPIO_FN_SIM0_RST, GPIO_FN_VI0_DATA5_VI0_B5_B, + GPIO_FN_HTX0_D, GPIO_FN_TS_SPSYNC1_B, GPIO_FN_GLO_Q1_B, + GPIO_FN_VI3_DATA5_B, GPIO_FN_SD2_CD, GPIO_FN_MMC0_D4, + GPIO_FN_TS_SDAT0_B, GPIO_FN_USB2_EXTP, GPIO_FN_GLO_I0, + GPIO_FN_VI0_DATA6_VI0_B6_B, GPIO_FN_HCTS0_N_D, GPIO_FN_TS_SDAT1_B, + GPIO_FN_GLO_I0_B, GPIO_FN_VI3_DATA6_B, + + /* IPSR11 */ + GPIO_FN_SD2_WP, GPIO_FN_MMC0_D5, GPIO_FN_TS_SCK0_B, GPIO_FN_USB2_IDIN, + GPIO_FN_GLO_I1, GPIO_FN_VI0_DATA7_VI0_B7_B, GPIO_FN_HRTS0_N_D, + GPIO_FN_TS_SCK1_B, GPIO_FN_GLO_I1_B, GPIO_FN_VI3_DATA7_B, + GPIO_FN_SD3_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_SD3_CMD, GPIO_FN_MMC1_CMD, + GPIO_FN_MTS_N, GPIO_FN_SD3_DAT0, GPIO_FN_MMC1_D0, GPIO_FN_STM_N, + GPIO_FN_SD3_DAT1, GPIO_FN_MMC1_D1, GPIO_FN_MDATA, GPIO_FN_SD3_DAT2, + GPIO_FN_MMC1_D2, GPIO_FN_SDATA, GPIO_FN_SD3_DAT3, GPIO_FN_MMC1_D3, + GPIO_FN_SCKZ, GPIO_FN_SD3_CD, GPIO_FN_MMC1_D4, GPIO_FN_TS_SDAT1, + GPIO_FN_VSP, GPIO_FN_GLO_Q0, GPIO_FN_SIM0_RST_B, GPIO_FN_SD3_WP, + GPIO_FN_MMC1_D5, GPIO_FN_TS_SCK1, GPIO_FN_GLO_Q1, GPIO_FN_FMIN_C, + GPIO_FN_RDS_DATA_B, GPIO_FN_FMIN_E, GPIO_FN_RDS_DATA_D, GPIO_FN_FMIN_F, + GPIO_FN_RDS_DATA_E, GPIO_FN_MLB_CLK, GPIO_FN_SCL2_B, GPIO_FN_SCL2_CIS_B, + GPIO_FN_MLB_SIG, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_RX1_C, GPIO_FN_SDA2_B, + GPIO_FN_SDA2_CIS_B, GPIO_FN_MLB_DAT, GPIO_FN_SPV_EVEN, + GPIO_FN_SCIFB1_TXD_D, GPIO_FN_TX1_C, GPIO_FN_BPFCLK_C, + GPIO_FN_RDS_CLK_B, GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_CLK_B, + GPIO_FN_MOUT0, + + /* IPSR12 */ + GPIO_FN_SSI_WS0129, GPIO_FN_CAN0_TX_B, GPIO_FN_MOUT1, + GPIO_FN_SSI_SDATA0, GPIO_FN_CAN0_RX_B, GPIO_FN_MOUT2, + GPIO_FN_SSI_SDATA1, GPIO_FN_CAN1_TX_B, GPIO_FN_MOUT5, + GPIO_FN_SSI_SDATA2, GPIO_FN_CAN1_RX_B, GPIO_FN_SSI_SCK1, GPIO_FN_MOUT6, + GPIO_FN_SSI_SCK34, GPIO_FN_STP_OPWM_0, GPIO_FN_SCIFB0_SCK, + GPIO_FN_MSIOF1_SCK, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_SSI_WS34, + GPIO_FN_STP_IVCXO27_0, GPIO_FN_SCIFB0_RXD, GPIO_FN_MSIOF1_SYNC, + GPIO_FN_CAN_STEP0, GPIO_FN_SSI_SDATA3, GPIO_FN_STP_ISCLK_0, + GPIO_FN_SCIFB0_TXD, GPIO_FN_MSIOF1_SS1, GPIO_FN_CAN_TXCLK, + GPIO_FN_SSI_SCK4, GPIO_FN_STP_ISD_0, GPIO_FN_SCIFB0_CTS_N, + GPIO_FN_MSIOF1_SS2, GPIO_FN_SSI_SCK5_C, GPIO_FN_CAN_DEBUGOUT0, + GPIO_FN_SSI_WS4, GPIO_FN_STP_ISEN_0, GPIO_FN_SCIFB0_RTS_N, + GPIO_FN_MSIOF1_TXD, GPIO_FN_SSI_WS5_C, GPIO_FN_CAN_DEBUGOUT1, + GPIO_FN_SSI_SDATA4, GPIO_FN_STP_ISSYNC_0, GPIO_FN_MSIOF1_RXD, + GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_SSI_SCK5, GPIO_FN_SCIFB1_SCK, + GPIO_FN_IERX_B, GPIO_FN_DU2_EXHSYNC_DU2_HSYNC, GPIO_FN_QSTH_QHS, + GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_SSI_WS5, GPIO_FN_SCIFB1_RXD, + GPIO_FN_IECLK_B, GPIO_FN_DU2_EXVSYNC_DU2_VSYNC, GPIO_FN_QSTB_QHE, + GPIO_FN_CAN_DEBUGOUT4, + + /* IPSR13 */ + GPIO_FN_SSI_SDATA5, GPIO_FN_SCIFB1_TXD, GPIO_FN_IETX_B, GPIO_FN_DU2_DR2, + GPIO_FN_LCDOUT2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK6, + GPIO_FN_SCIFB1_CTS_N, GPIO_FN_BPFCLK_D, GPIO_FN_RDS_CLK_C, + GPIO_FN_DU2_DR3, GPIO_FN_LCDOUT3, GPIO_FN_CAN_DEBUGOUT6, + GPIO_FN_BPFCLK_F, GPIO_FN_RDS_CLK_E, GPIO_FN_SSI_WS6, + GPIO_FN_SCIFB1_RTS_N, GPIO_FN_CAN0_TX_D, GPIO_FN_DU2_DR4, + GPIO_FN_LCDOUT4, GPIO_FN_CAN_DEBUGOUT7, GPIO_FN_SSI_SDATA6, + GPIO_FN_FMIN_D, GPIO_FN_RDS_DATA_C, GPIO_FN_DU2_DR5, GPIO_FN_LCDOUT5, + GPIO_FN_CAN_DEBUGOUT8, GPIO_FN_SSI_SCK78, GPIO_FN_STP_IVCXO27_1, + GPIO_FN_SCK1, GPIO_FN_SCIFA1_SCK, GPIO_FN_DU2_DR6, GPIO_FN_LCDOUT6, + GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_WS78, GPIO_FN_STP_ISCLK_1, + GPIO_FN_SCIFB2_SCK, GPIO_FN_SCIFA2_CTS_N, GPIO_FN_DU2_DR7, + GPIO_FN_LCDOUT7, GPIO_FN_CAN_DEBUGOUT10, GPIO_FN_SSI_SDATA7, + GPIO_FN_STP_ISD_1, GPIO_FN_SCIFB2_RXD, GPIO_FN_SCIFA2_RTS_N, + GPIO_FN_TCLK2, GPIO_FN_QSTVA_QVS, GPIO_FN_CAN_DEBUGOUT11, + GPIO_FN_BPFCLK_E, GPIO_FN_RDS_CLK_D, GPIO_FN_SSI_SDATA7_B, + GPIO_FN_FMIN_G, GPIO_FN_RDS_DATA_F, GPIO_FN_SSI_SDATA8, + GPIO_FN_STP_ISEN_1, GPIO_FN_SCIFB2_TXD, GPIO_FN_CAN0_TX_C, + GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SDATA8_B, GPIO_FN_SSI_SDATA9, + GPIO_FN_STP_ISSYNC_1, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_SSI_WS1, + GPIO_FN_SSI_SDATA5_C, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_AUDIO_CLKA, + GPIO_FN_SCIFB2_RTS_N, GPIO_FN_CAN_DEBUGOUT14, + + /* IPSR14 */ + GPIO_FN_AUDIO_CLKB, GPIO_FN_SCIF_CLK, GPIO_FN_CAN0_RX_D, + GPIO_FN_DVC_MUTE, GPIO_FN_CAN0_RX_C, GPIO_FN_CAN_DEBUGOUT15, + GPIO_FN_REMOCON, GPIO_FN_SCIFA0_SCK, GPIO_FN_HSCK1, GPIO_FN_SCK0, + GPIO_FN_MSIOF3_SS2, GPIO_FN_DU2_DG2, GPIO_FN_LCDOUT10, GPIO_FN_SDA1_C, + GPIO_FN_SDA1_CIS_C, GPIO_FN_SCIFA0_RXD, GPIO_FN_HRX1, GPIO_FN_RX0, + GPIO_FN_DU2_DR0, GPIO_FN_LCDOUT0, GPIO_FN_SCIFA0_TXD, GPIO_FN_HTX1, + GPIO_FN_TX0, GPIO_FN_DU2_DR1, GPIO_FN_LCDOUT1, GPIO_FN_SCIFA0_CTS_N, + GPIO_FN_HCTS1_N, GPIO_FN_CTS0_N, GPIO_FN_MSIOF3_SYNC, GPIO_FN_DU2_DG3, + GPIO_FN_LCDOUT11, GPIO_FN_PWM0_B, GPIO_FN_SCL1_C, GPIO_FN_SCL1_CIS_C, + GPIO_FN_SCIFA0_RTS_N, GPIO_FN_HRTS1_N, GPIO_FN_RTS0_N_TANS, + GPIO_FN_MSIOF3_SS1, GPIO_FN_DU2_DG0, GPIO_FN_LCDOUT8, GPIO_FN_PWM1_B, + GPIO_FN_SCIFA1_RXD, GPIO_FN_AD_DI, GPIO_FN_RX1, + GPIO_FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, + GPIO_FN_SCIFA1_TXD, GPIO_FN_AD_DO, GPIO_FN_TX1, GPIO_FN_DU2_DG1, + GPIO_FN_LCDOUT9, GPIO_FN_SCIFA1_CTS_N, GPIO_FN_AD_CLK, + GPIO_FN_CTS1_N, GPIO_FN_MSIOF3_RXD, GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_QCLK, + GPIO_FN_SCIFA1_RTS_N, GPIO_FN_AD_NCS_N, GPIO_FN_RTS1_N_TANS, + GPIO_FN_MSIOF3_TXD, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_QSTVB_QVE, + GPIO_FN_HRTS0_N_C, + + /* IPSR15 */ + GPIO_FN_SCIFA2_SCK, GPIO_FN_FMCLK, GPIO_FN_MSIOF3_SCK, GPIO_FN_DU2_DG7, + GPIO_FN_LCDOUT15, GPIO_FN_SCIF_CLK_B, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN, + GPIO_FN_DU2_DB0, GPIO_FN_LCDOUT16, GPIO_FN_SCL2, GPIO_FN_SCL2_CIS, + GPIO_FN_SCIFA2_TXD, GPIO_FN_BPFCLK, GPIO_FN_DU2_DB1, GPIO_FN_LCDOUT17, + GPIO_FN_SDA2, GPIO_FN_SDA2_CIS, GPIO_FN_HSCK0, GPIO_FN_TS_SDEN0, + GPIO_FN_DU2_DG4, GPIO_FN_LCDOUT12, GPIO_FN_HCTS0_N_C, GPIO_FN_HRX0, + GPIO_FN_DU2_DB2, GPIO_FN_LCDOUT18, GPIO_FN_HTX0, GPIO_FN_DU2_DB3, + GPIO_FN_LCDOUT19, GPIO_FN_HCTS0_N, GPIO_FN_SSI_SCK9, GPIO_FN_DU2_DB4, + GPIO_FN_LCDOUT20, GPIO_FN_HRTS0_N, GPIO_FN_SSI_WS9, GPIO_FN_DU2_DB5, + GPIO_FN_LCDOUT21, GPIO_FN_MSIOF0_SCK, GPIO_FN_TS_SDAT0, GPIO_FN_ADICLK, + GPIO_FN_DU2_DB6, GPIO_FN_LCDOUT22, GPIO_FN_MSIOF0_SYNC, GPIO_FN_TS_SCK0, + GPIO_FN_SSI_SCK2, GPIO_FN_ADIDATA, GPIO_FN_DU2_DB7, GPIO_FN_LCDOUT23, + GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF0_SS1, GPIO_FN_ADICHS0, + GPIO_FN_DU2_DG5, GPIO_FN_LCDOUT13, GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICHS1, + GPIO_FN_DU2_DG6, GPIO_FN_LCDOUT14, + + /* IPSR16 */ + GPIO_FN_MSIOF0_SS2, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_ADICHS2, + GPIO_FN_DU2_DISP, GPIO_FN_QPOLA, GPIO_FN_HTX0_C, GPIO_FN_SCIFA2_TXD_B, + GPIO_FN_MSIOF0_RXD, GPIO_FN_TS_SPSYNC0, GPIO_FN_SSI_WS2, + GPIO_FN_ADICS_SAMP, GPIO_FN_DU2_CDE, GPIO_FN_QPOLB, GPIO_FN_HRX0_C, + GPIO_FN_USB1_PWEN, GPIO_FN_AUDIO_CLKOUT_D, GPIO_FN_USB1_OVC, + GPIO_FN_TCLK1_B, +}; + +#endif /* __ASM_R8A7790_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h new file mode 100644 index 0000000..42d65d3 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h @@ -0,0 +1,614 @@ +/* + * arch/arm/include/asm/arch-rmobile/r8a7790.h + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ARCH_R8A7790_H +#define __ASM_ARCH_R8A7790_H + +/* + * R8A7790 I/O Addresses + */ +#define RWDT_BASE 0xE6020000 +#define SWDT_BASE 0xE6030000 +#define LBSC_BASE 0xFEC00200 +#define DBSC3_0_BASE 0xE6790000 +#define DBSC3_1_BASE 0xE67A0000 +#define TMU_BASE 0xE61E0000 +#define GPIO5_BASE 0xE6055000 + +#define S3C_BASE 0xE6784000 +#define S3C_INT_BASE 0xE6784A00 +#define S3C_MEDIA_BASE 0xE6784B00 + +#define S3C_QOS_DCACHE_BASE 0xE6784BDC +#define S3C_QOS_CCI0_BASE 0xE6784C00 +#define S3C_QOS_CCI1_BASE 0xE6784C24 +#define S3C_QOS_MXI_BASE 0xE6784C48 +#define S3C_QOS_AXI_BASE 0xE6784C6C + +#define DBSC3_0_QOS_R0_BASE 0xE6791000 +#define DBSC3_0_QOS_R1_BASE 0xE6791100 +#define DBSC3_0_QOS_R2_BASE 0xE6791200 +#define DBSC3_0_QOS_R3_BASE 0xE6791300 +#define DBSC3_0_QOS_R4_BASE 0xE6791400 +#define DBSC3_0_QOS_R5_BASE 0xE6791500 +#define DBSC3_0_QOS_R6_BASE 0xE6791600 +#define DBSC3_0_QOS_R7_BASE 0xE6791700 +#define DBSC3_0_QOS_R8_BASE 0xE6791800 +#define DBSC3_0_QOS_R9_BASE 0xE6791900 +#define DBSC3_0_QOS_R10_BASE 0xE6791A00 +#define DBSC3_0_QOS_R11_BASE 0xE6791B00 +#define DBSC3_0_QOS_R12_BASE 0xE6791C00 +#define DBSC3_0_QOS_R13_BASE 0xE6791D00 +#define DBSC3_0_QOS_R14_BASE 0xE6791E00 +#define DBSC3_0_QOS_R15_BASE 0xE6791F00 +#define DBSC3_0_QOS_W0_BASE 0xE6792000 +#define DBSC3_0_QOS_W1_BASE 0xE6792100 +#define DBSC3_0_QOS_W2_BASE 0xE6792200 +#define DBSC3_0_QOS_W3_BASE 0xE6792300 +#define DBSC3_0_QOS_W4_BASE 0xE6792400 +#define DBSC3_0_QOS_W5_BASE 0xE6792500 +#define DBSC3_0_QOS_W6_BASE 0xE6792600 +#define DBSC3_0_QOS_W7_BASE 0xE6792700 +#define DBSC3_0_QOS_W8_BASE 0xE6792800 +#define DBSC3_0_QOS_W9_BASE 0xE6792900 +#define DBSC3_0_QOS_W10_BASE 0xE6792A00 +#define DBSC3_0_QOS_W11_BASE 0xE6792B00 +#define DBSC3_0_QOS_W12_BASE 0xE6792C00 +#define DBSC3_0_QOS_W13_BASE 0xE6792D00 +#define DBSC3_0_QOS_W14_BASE 0xE6792E00 +#define DBSC3_0_QOS_W15_BASE 0xE6792F00 + +#define DBSC3_0_DBADJ2 0xE67900C8 + +#define CCI_400_MAXOT_1 0xF0091110 +#define CCI_400_MAXOT_2 0xF0092110 +#define CCI_400_QOSCNTL_1 0xF009110C +#define CCI_400_QOSCNTL_2 0xF009210C + +#define MXI_BASE 0xFE960000 +#define MXI_QOS_BASE 0xFE960300 + +#define SYS_AXI_SYX64TO128_BASE 0xFF800300 +#define SYS_AXI_AVB_BASE 0xFF800340 +#define SYS_AXI_G2D_BASE 0xFF800540 +#define SYS_AXI_IMP0_BASE 0xFF800580 +#define SYS_AXI_IMP1_BASE 0xFF8005C0 +#define SYS_AXI_IMUX0_BASE 0xFF800600 +#define SYS_AXI_IMUX1_BASE 0xFF800640 +#define SYS_AXI_IMUX2_BASE 0xFF800680 +#define SYS_AXI_LBS_BASE 0xFF8006C0 +#define SYS_AXI_MMUDS_BASE 0xFF800700 +#define SYS_AXI_MMUM_BASE 0xFF800740 +#define SYS_AXI_MMUR_BASE 0xFF800780 +#define SYS_AXI_MMUS0_BASE 0xFF8007C0 +#define SYS_AXI_MMUS1_BASE 0xFF800800 +#define SYS_AXI_MTSB0_BASE 0xFF800880 +#define SYS_AXI_MTSB1_BASE 0xFF8008C0 +#define SYS_AXI_PCI_BASE 0xFF800900 +#define SYS_AXI_RTX_BASE 0xFF800940 +#define SYS_AXI_SDS0_BASE 0xFF800A80 +#define SYS_AXI_SDS1_BASE 0xFF800AC0 +#define SYS_AXI_USB20_BASE 0xFF800C00 +#define SYS_AXI_USB21_BASE 0xFF800C40 +#define SYS_AXI_USB22_BASE 0xFF800C80 +#define SYS_AXI_USB30_BASE 0xFF800CC0 + +#define RT_AXI_SHX_BASE 0xFF810100 +#define RT_AXI_RDS_BASE 0xFF8101C0 +#define RT_AXI_RTX64TO128_BASE 0xFF810200 +#define RT_AXI_STPRO_BASE 0xFF810240 + +#define MP_AXI_ADSP_BASE 0xFF820100 +#define MP_AXI_ASDS0_BASE 0xFF8201C0 +#define MP_AXI_ASDS1_BASE 0xFF820200 +#define MP_AXI_MLP_BASE 0xFF820240 +#define MP_AXI_MMUMP_BASE 0xFF820280 +#define MP_AXI_SPU_BASE 0xFF8202C0 +#define MP_AXI_SPUC_BASE 0xFF820300 + +#define SYS_AXI256_AXI128TO256_BASE 0xFF860100 +#define SYS_AXI256_SYX_BASE 0xFF860140 +#define SYS_AXI256_MPX_BASE 0xFF860180 +#define SYS_AXI256_MXI_BASE 0xFF8601C0 + +#define CCI_AXI_MMUS0_BASE 0xFF880100 +#define CCI_AXI_SYX2_BASE 0xFF880140 +#define CCI_AXI_MMUR_BASE 0xFF880180 +#define CCI_AXI_MMUDS_BASE 0xFF8801C0 +#define CCI_AXI_MMUM_BASE 0xFF880200 +#define CCI_AXI_MXI_BASE 0xFF880240 +#define CCI_AXI_MMUS1_BASE 0xFF880280 +#define CCI_AXI_MMUMP_BASE 0xFF8802C0 + +#define MEDIA_AXI_JPR_BASE 0xFE964100 +#define MEDIA_AXI_JPW_BASE 0xFE966100 +#define MEDIA_AXI_GCU0R_BASE 0xFE964140 +#define MEDIA_AXI_GCU0W_BASE 0xFE966140 +#define MEDIA_AXI_GCU1R_BASE 0xFE964180 +#define MEDIA_AXI_GCU1W_BASE 0xFE966180 +#define MEDIA_AXI_TDMR_BASE 0xFE964500 +#define MEDIA_AXI_TDMW_BASE 0xFE966500 +#define MEDIA_AXI_VSP0CR_BASE 0xFE964540 +#define MEDIA_AXI_VSP0CW_BASE 0xFE966540 +#define MEDIA_AXI_VSP1CR_BASE 0xFE964580 +#define MEDIA_AXI_VSP1CW_BASE 0xFE966580 +#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0 +#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0 +#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600 +#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600 +#define MEDIA_AXI_VIN0W_BASE 0xFE966900 +#define MEDIA_AXI_VSP0R_BASE 0xFE964D00 +#define MEDIA_AXI_VSP0W_BASE 0xFE966D00 +#define MEDIA_AXI_FDP0R_BASE 0xFE964D40 +#define MEDIA_AXI_FDP0W_BASE 0xFE966D40 +#define MEDIA_AXI_IMSR_BASE 0xFE964D80 +#define MEDIA_AXI_IMSW_BASE 0xFE966D80 +#define MEDIA_AXI_VSP1R_BASE 0xFE965100 +#define MEDIA_AXI_VSP1W_BASE 0xFE967100 +#define MEDIA_AXI_FDP1R_BASE 0xFE965140 +#define MEDIA_AXI_FDP1W_BASE 0xFE967140 +#define MEDIA_AXI_IMRR_BASE 0xFE965180 +#define MEDIA_AXI_IMRW_BASE 0xFE967180 +#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0 +#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0 +#define MEDIA_AXI_VSPD0R_BASE 0xFE965500 +#define MEDIA_AXI_VSPD0W_BASE 0xFE967500 +#define MEDIA_AXI_VSPD1R_BASE 0xFE965540 +#define MEDIA_AXI_VSPD1W_BASE 0xFE967540 +#define MEDIA_AXI_DU0R_BASE 0xFE965580 +#define MEDIA_AXI_DU0W_BASE 0xFE967580 +#define MEDIA_AXI_DU1R_BASE 0xFE9655C0 +#define MEDIA_AXI_DU1W_BASE 0xFE9675C0 +#define MEDIA_AXI_VCP0CR_BASE 0xFE965900 +#define MEDIA_AXI_VCP0CW_BASE 0xFE967900 +#define MEDIA_AXI_VCP0VR_BASE 0xFE965940 +#define MEDIA_AXI_VCP0VW_BASE 0xFE967940 +#define MEDIA_AXI_VPC0R_BASE 0xFE965980 +#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00 +#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00 +#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40 +#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40 +#define MEDIA_AXI_VPC1R_BASE 0xFE965D80 + +#define SYS_AXI_AVBDMSCR 0xFF802000 +#define SYS_AXI_SYX2DMSCR 0xFF802004 +#define SYS_AXI_CC50DMSCR 0xFF802008 +#define SYS_AXI_CC51DMSCR 0xFF80200C +#define SYS_AXI_CCIDMSCR 0xFF802010 +#define SYS_AXI_CSDMSCR 0xFF802014 +#define SYS_AXI_DDMDMSCR 0xFF802018 +#define SYS_AXI_ETHDMSCR 0xFF80201C +#define SYS_AXI_G2DDMSCR 0xFF802020 +#define SYS_AXI_IMP0DMSCR 0xFF802024 +#define SYS_AXI_IMP1DMSCR 0xFF802028 +#define SYS_AXI_LBSDMSCR 0xFF80202C +#define SYS_AXI_MMUDSDMSCR 0xFF802030 +#define SYS_AXI_MMUMXDMSCR 0xFF802034 +#define SYS_AXI_MMURDDMSCR 0xFF802038 +#define SYS_AXI_MMUS0DMSCR 0xFF80203C +#define SYS_AXI_MMUS1DMSCR 0xFF802040 +#define SYS_AXI_MPXDMSCR 0xFF802044 +#define SYS_AXI_MTSB0DMSCR 0xFF802048 +#define SYS_AXI_MTSB1DMSCR 0xFF80204C +#define SYS_AXI_PCIDMSCR 0xFF802050 +#define SYS_AXI_RTXDMSCR 0xFF802054 +#define SYS_AXI_SAT0DMSCR 0xFF802058 +#define SYS_AXI_SAT1DMSCR 0xFF80205C +#define SYS_AXI_SDM0DMSCR 0xFF802060 +#define SYS_AXI_SDM1DMSCR 0xFF802064 +#define SYS_AXI_SDS0DMSCR 0xFF802068 +#define SYS_AXI_SDS1DMSCR 0xFF80206C +#define SYS_AXI_ETRABDMSCR 0xFF802070 +#define SYS_AXI_ETRKFDMSCR 0xFF802074 +#define SYS_AXI_UDM0DMSCR 0xFF802078 +#define SYS_AXI_UDM1DMSCR 0xFF80207C +#define SYS_AXI_USB20DMSCR 0xFF802080 +#define SYS_AXI_USB21DMSCR 0xFF802084 +#define SYS_AXI_USB22DMSCR 0xFF802088 +#define SYS_AXI_USB30DMSCR 0xFF80208C +#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100 +#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104 +#define SYS_AXI_AVBSLVDMSCR 0xFF802108 +#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C +#define SYS_AXI_ETHSLVDMSCR 0xFF802110 +#define SYS_AXI_GICSLVDMSCR 0xFF802114 +#define SYS_AXI_IMPSLVDMSCR 0xFF802118 +#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C +#define SYS_AXI_IMX1SLVDMSCR 0xFF802120 +#define SYS_AXI_IMX2SLVDMSCR 0xFF802124 +#define SYS_AXI_LBSSLVDMSCR 0xFF802128 +#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C +#define SYS_AXI_MMC1SLVDMSCR 0xFF802130 +#define SYS_AXI_MPXSLVDMSCR 0xFF802134 +#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138 +#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C +#define SYS_AXI_MXTSLVDMSCR 0xFF802140 +#define SYS_AXI_PCISLVDMSCR 0xFF802144 +#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148 +#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C +#define SYS_AXI_RTXSLVDMSCR 0xFF802150 +#define SYS_AXI_SAT0SLVDMSCR 0xFF802168 +#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C +#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170 +#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174 +#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178 +#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C +#define SYS_AXI_SGXSLVDMSCR 0xFF802180 +#define SYS_AXI_STBSLVDMSCR 0xFF802188 +#define SYS_AXI_STMSLVDMSCR 0xFF80218C +#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194 +#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198 +#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C +#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0 +#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4 +#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8 +#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC + +#define RT_AXI_CBMDMSCR 0xFF812000 +#define RT_AXI_DBDMSCR 0xFF812004 +#define RT_AXI_RDMDMSCR 0xFF812008 +#define RT_AXI_RDSDMSCR 0xFF81200C +#define RT_AXI_STRDMSCR 0xFF812010 +#define RT_AXI_SY2RTDMSCR 0xFF812014 +#define RT_AXI_CBSSLVDMSCR 0xFF812100 +#define RT_AXI_DBSSLVDMSCR 0xFF812104 +#define RT_AXI_RTAP1SLVDMSCR 0xFF812108 +#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C +#define RT_AXI_RTAP3SLVDMSCR 0xFF812110 +#define RT_AXI_RT2SYSLVDMSCR 0xFF812114 +#define RT_AXI_A128TO64SLVDMSCR 0xFF812118 +#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C +#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120 +#define RT_AXI_UTLBRSLVDMSCR 0xFF812128 + +#define MP_AXI_ADSPDMSCR 0xFF822000 +#define MP_AXI_ASDM0DMSCR 0xFF822004 +#define MP_AXI_ASDM1DMSCR 0xFF822008 +#define MP_AXI_ASDS0DMSCR 0xFF82200C +#define MP_AXI_ASDS1DMSCR 0xFF822010 +#define MP_AXI_MLPDMSCR 0xFF822014 +#define MP_AXI_MMUMPDMSCR 0xFF822018 +#define MP_AXI_SPUDMSCR 0xFF82201C +#define MP_AXI_SPUCDMSCR 0xFF822020 +#define MP_AXI_SY2MPDMSCR 0xFF822024 +#define MP_AXI_ADSPSLVDMSCR 0xFF822100 +#define MP_AXI_MLMSLVDMSCR 0xFF822104 +#define MP_AXI_MPAP4SLVDMSCR 0xFF822108 +#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C +#define MP_AXI_MPAP6SLVDMSCR 0xFF822110 +#define MP_AXI_MPAP7SLVDMSCR 0xFF822114 +#define MP_AXI_MP2SYSLVDMSCR 0xFF822118 +#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C +#define MP_AXI_MPXAPSLVDMSCR 0xFF822124 +#define MP_AXI_SPUSLVDMSCR 0xFF822128 +#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C + +#define ADM_AXI_ASDM0DMSCR 0xFF842000 +#define ADM_AXI_ASDM1DMSCR 0xFF842004 +#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104 +#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108 +#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C + +#define DM_AXI_RDMDMSCR 0xFF852000 +#define DM_AXI_SDM0DMSCR 0xFF852004 +#define DM_AXI_SDM1DMSCR 0xFF852008 +#define DM_AXI_MMAP0SLVDMSCR 0xFF852100 +#define DM_AXI_MMAP1SLVDMSCR 0xFF852104 +#define DM_AXI_QSPAPSLVDMSCR 0xFF852108 +#define DM_AXI_RAP4SLVDMSCR 0xFF85210C +#define DM_AXI_RAP5SLVDMSCR 0xFF852110 +#define DM_AXI_SAP4SLVDMSCR 0xFF852114 +#define DM_AXI_SAP5SLVDMSCR 0xFF852118 +#define DM_AXI_SAP6SLVDMSCR 0xFF85211C +#define DM_AXI_SAP65SLVDMSCR 0xFF852120 +#define DM_AXI_SDAP0SLVDMSCR 0xFF852124 +#define DM_AXI_SDAP1SLVDMSCR 0xFF852128 +#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C +#define DM_AXI_SDAP3SLVDMSCR 0xFF852130 + +#define SYS_AXI256_SYXDMSCR 0xFF862000 +#define SYS_AXI256_MPXDMSCR 0xFF862004 +#define SYS_AXI256_MXIDMSCR 0xFF862008 +#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100 +#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104 +#define SYS_AXI256_SYXSLVDMSCR 0xFF862108 +#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C +#define SYS_AXI256_S3CSLVDMSCR 0xFF862110 + +#define MXT_SYXDMSCR 0xFF872000 +#define MXT_CMM0SLVDMSCR 0xFF872100 +#define MXT_CMM1SLVDMSCR 0xFF872104 +#define MXT_CMM2SLVDMSCR 0xFF872108 +#define MXT_FDPSLVDMSCR 0xFF87210C +#define MXT_IMRSLVDMSCR 0xFF872110 +#define MXT_VINSLVDMSCR 0xFF872114 +#define MXT_VPC0SLVDMSCR 0xFF872118 +#define MXT_VPC1SLVDMSCR 0xFF87211C +#define MXT_VSP0SLVDMSCR 0xFF872120 +#define MXT_VSP1SLVDMSCR 0xFF872124 +#define MXT_VSPD0SLVDMSCR 0xFF872128 +#define MXT_VSPD1SLVDMSCR 0xFF87212C +#define MXT_MAP1SLVDMSCR 0xFF872130 +#define MXT_MAP2SLVDMSCR 0xFF872134 + +#define CCI_AXI_MMUS0DMSCR 0xFF882000 +#define CCI_AXI_SYX2DMSCR 0xFF882004 +#define CCI_AXI_MMURDMSCR 0xFF882008 +#define CCI_AXI_MMUDSDMSCR 0xFF88200C +#define CCI_AXI_MMUMDMSCR 0xFF882010 +#define CCI_AXI_MXIDMSCR 0xFF882014 +#define CCI_AXI_MMUS1DMSCR 0xFF882018 +#define CCI_AXI_MMUMPDMSCR 0xFF88201C +#define CCI_AXI_DVMDMSCR 0xFF882020 +#define CCI_AXI_CCISLVDMSCR 0xFF882100 + +#define CCI_AXI_IPMMUIDVMCR 0xFF880400 +#define CCI_AXI_IPMMURDVMCR 0xFF880404 +#define CCI_AXI_IPMMUS0DVMCR 0xFF880408 +#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C +#define CCI_AXI_IPMMUMPDVMCR 0xFF880410 +#define CCI_AXI_IPMMUDSDVMCR 0xFF880414 +#define CCI_AXI_AX2ADDRMASK 0xFF88041C + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +/* RWDT */ +struct r8a7790_rwdt { + u32 rwtcnt; /* 0x00 */ + u32 rwtcsra; /* 0x04 */ + u16 rwtcsrb; /* 0x08 */ +}; + +/* SWDT */ +struct r8a7790_swdt { + u32 swtcnt; /* 0x00 */ + u32 swtcsra; /* 0x04 */ + u16 swtcsrb; /* 0x08 */ +}; + +/* LBSC */ +struct r8a7790_lbsc { + u32 cs0ctrl; + u32 cs1ctrl; + u32 ecs0ctrl; + u32 ecs1ctrl; + u32 ecs2ctrl; + u32 ecs3ctrl; + u32 ecs4ctrl; + u32 ecs5ctrl; + u32 dummy0[4]; /* 0x20 .. 0x2C */ + u32 cswcr0; + u32 cswcr1; + u32 ecswcr0; + u32 ecswcr1; + u32 ecswcr2; + u32 ecswcr3; + u32 ecswcr4; + u32 ecswcr5; + u32 exdmawcr0; + u32 exdmawcr1; + u32 exdmawcr2; + u32 dummy1[9]; /* 0x5C .. 0x7C */ + u32 cspwcr0; + u32 cspwcr1; + u32 ecspwcr0; + u32 ecspwcr1; + u32 ecspwcr2; + u32 ecspwcr3; + u32 ecspwcr4; + u32 ecspwcr5; + u32 exwtsync; + u32 dummy2[3]; /* 0xA4 .. 0xAC */ + u32 cs0bstctl; + u32 cs0btph; + u32 dummy3[2]; /* 0xB8 .. 0xBC */ + u32 cs1gdst; + u32 ecs0gdst; + u32 ecs1gdst; + u32 ecs2gdst; + u32 ecs3gdst; + u32 ecs4gdst; + u32 ecs5gdst; + u32 dummy4[5]; /* 0xDC .. 0xEC */ + u32 exdmaset0; + u32 exdmaset1; + u32 exdmaset2; + u32 dummy5[5]; /* 0xFC .. 0x10C */ + u32 exdmcr0; + u32 exdmcr1; + u32 exdmcr2; + u32 dummy6[5]; /* 0x11C .. 0x12C */ + u32 bcintsr; + u32 bcintcr; + u32 bcintmr; + u32 dummy7; /* 0x13C */ + u32 exbatlv; + u32 exwtsts; + u32 dummy8[14]; /* 0x148 .. 0x17C */ + u32 atacsctrl; + u32 dummy9[15]; /* 0x184 .. 0x1BC */ + u32 exbct; + u32 extct; +}; + +/* DBSC3 */ +struct r8a7790_dbsc3 { + u32 dummy0[3]; /* 0x00 .. 0x08 */ + u32 dbstate1; + u32 dbacen; + u32 dbrfen; + u32 dbcmd; + u32 dbwait; + u32 dbkind; + u32 dbconf0; + u32 dummy1[2]; /* 0x28 .. 0x2C */ + u32 dbphytype; + u32 dummy2[3]; /* 0x34 .. 0x3C */ + u32 dbtr0; + u32 dbtr1; + u32 dbtr2; + u32 dummy3; /* 0x4C */ + u32 dbtr3; + u32 dbtr4; + u32 dbtr5; + u32 dbtr6; + u32 dbtr7; + u32 dbtr8; + u32 dbtr9; + u32 dbtr10; + u32 dbtr11; + u32 dbtr12; + u32 dbtr13; + u32 dbtr14; + u32 dbtr15; + u32 dbtr16; + u32 dbtr17; + u32 dbtr18; + u32 dbtr19; + u32 dummy4[7]; /* 0x94 .. 0xAC */ + u32 dbbl; + u32 dummy5[3]; /* 0xB4 .. 0xBC */ + u32 dbadj0; + u32 dummy6; /* 0xC4 */ + u32 dbadj2; + u32 dummy7[5]; /* 0xCC .. 0xDC */ + u32 dbrfcnf0; + u32 dbrfcnf1; + u32 dbrfcnf2; + u32 dummy8[2]; /* 0xEC .. 0xF0 */ + u32 dbcalcnf; + u32 dbcaltr; + u32 dummy9; /* 0xFC */ + u32 dbrnk0; + u32 dummy10[31]; /* 0x104 .. 0x17C */ + u32 dbpdncnf; + u32 dummy11[47]; /* 0x184 ..0x23C */ + u32 dbdfistat; + u32 dbdficnt; + u32 dummy12[14]; /* 0x248 .. 0x27C */ + u32 dbpdlck; + u32 dummy13[3]; /* 0x284 .. 0x28C */ + u32 dbpdrga; + u32 dummy14[3]; /* 0x294 .. 0x29C */ + u32 dbpdrgd; + u32 dummy15[24]; /* 0x2A4 .. 0x300 */ + u32 dbbs0cnt1; + u32 dummy16[30]; /* 0x308 .. 0x37C */ + u32 dbwt0cnf0; + u32 dbwt0cnf1; + u32 dbwt0cnf2; + u32 dbwt0cnf3; + u32 dbwt0cnf4; +}; + +/* GPIO */ +struct r8a7790_gpio { + u32 iointsel; + u32 inoutsel; + u32 outdt; + u32 indt; + u32 intdt; + u32 intclr; + u32 intmsk; + u32 posneg; + u32 edglevel; + u32 filonoff; + u32 intmsks; + u32 mskclrs; + u32 outdtsel; + u32 outdth; + u32 outdtl; + u32 bothedge; +}; + +/* S3C(QoS) */ +struct r8a7790_s3c { + u32 s3cexcladdmsk; + u32 s3cexclidmsk; + u32 s3cadsplcr; + u32 s3cmaar; + u32 s3carcr11; + u32 s3crorr; + u32 s3cworr; + u32 s3carcr22; + u32 dummy1[2]; /* 0x20 .. 0x24 */ + u32 s3cmctr; + u32 dummy2; /* 0x2C */ + u32 cconf0; + u32 cconf1; + u32 cconf2; + u32 cconf3; +}; + +struct r8a7790_s3c_qos { + u32 s3cqos0; + u32 s3cqos1; + u32 s3cqos2; + u32 s3cqos3; + u32 s3cqos4; + u32 s3cqos5; + u32 s3cqos6; + u32 s3cqos7; + u32 s3cqos8; +}; + +/* DBSC(QoS) */ +struct r8a7790_dbsc3_qos { + u32 dblgcnt; + u32 dbtmval0; + u32 dbtmval1; + u32 dbtmval2; + u32 dbtmval3; + u32 dbrqctr; + u32 dbthres0; + u32 dbthres1; + u32 dbthres2; + u32 dummy0; /* 0x24 */ + u32 dblgqon; +}; + +/* MXI(QoS) */ +struct r8a7790_mxi { + u32 mxsaar0; + u32 mxsaar1; + u32 dummy0[7]; /* 0x08 .. 0x20 */ + u32 mxaxiracr; + u32 mxs3cracr; + u32 dummy1[2]; /* 0x2C .. 0x30 */ + u32 mxaxiwacr; + u32 mxs3cwacr; + u32 dummy2; /* 0x3C */ + u32 mxrtcr; + u32 mxwtcr; +}; + +struct r8a7790_mxi_qos { + u32 vspdu0; + u32 vspdu1; + u32 du0; + u32 du1; +}; + +/* AXI(QoS) */ +struct r8a7790_axi_qos { + u32 qosconf; + u32 qosctset0; + u32 qosctset1; + u32 qosctset2; + u32 qosctset3; + u32 qosreqctr; + u32 qosthres0; + u32 qosthres1; + u32 qosthres2; + u32 qosqon; +}; + +#endif + +#endif /* __ASM_ARCH_R8A7790_H */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h new file mode 100644 index 0000000..d3cf0c1 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h @@ -0,0 +1,438 @@ +#ifndef __ASM_R8A7791_H__ +#define __ASM_R8A7791_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU + */ +enum { + GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, + GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, + GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, + GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, + GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, + GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, + GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, + GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, + + GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, + GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, + GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, + GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, + GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, + GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, + GPIO_GP_1_24, GPIO_GP_1_25, + + GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, + GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, + GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, + GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, + GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, + GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, + GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, + GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31, + + GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, + GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, + GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, + GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, + GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, + GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, + GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, + GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, + + GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, + GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, + GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, + GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, + GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, + GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, + GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, + GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, + + GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, + GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, + GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, + GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, + GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, + GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, + GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, + GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31, + + GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, + GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, + GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11, + GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15, + GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19, + GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23, + GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27, + GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31, + + GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3, + GPIO_GP_7_4, GPIO_GP_7_5, GPIO_GP_7_6, GPIO_GP_7_7, + GPIO_GP_7_8, GPIO_GP_7_9, GPIO_GP_7_10, GPIO_GP_7_11, + GPIO_GP_7_12, GPIO_GP_7_13, GPIO_GP_7_14, GPIO_GP_7_15, + GPIO_GP_7_16, GPIO_GP_7_17, GPIO_GP_7_18, GPIO_GP_7_19, + GPIO_GP_7_20, GPIO_GP_7_21, GPIO_GP_7_22, GPIO_GP_7_23, + GPIO_GP_7_24, GPIO_GP_7_25, + + GPIO_FN_EX_CS0_N, GPIO_FN_RD_N, GPIO_FN_AUDIO_CLKA, + GPIO_FN_VI0_CLK, GPIO_FN_VI0_DATA0_VI0_B0, + GPIO_FN_VI0_DATA0_VI0_B1, GPIO_FN_VI0_DATA0_VI0_B2, + GPIO_FN_VI0_DATA0_VI0_B4, GPIO_FN_VI0_DATA0_VI0_B5, + GPIO_FN_VI0_DATA0_VI0_B6, GPIO_FN_VI0_DATA0_VI0_B7, + GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN, + + /* IPSR0 */ + GPIO_FN_D0, GPIO_FN_D1, GPIO_FN_D2, GPIO_FN_D3, GPIO_FN_D4, GPIO_FN_D5, + GPIO_FN_D6, GPIO_FN_D7, GPIO_FN_D8, GPIO_FN_D9, GPIO_FN_D10, + GPIO_FN_D11, GPIO_FN_D12, GPIO_FN_D13, GPIO_FN_D14, GPIO_FN_D15, + GPIO_FN_A0, GPIO_FN_ATAWR0_N_C, GPIO_FN_MSIOF0_SCK_B, + GPIO_FN_SCL0_C, GPIO_FN_PWM2_B, + GPIO_FN_A1, GPIO_FN_MSIOF0_SYNC_B, GPIO_FN_A2, GPIO_FN_MSIOF0_SS1_B, + GPIO_FN_A3, GPIO_FN_MSIOF0_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF0_TXD_B, + GPIO_FN_A5, GPIO_FN_MSIOF0_RXD_B, GPIO_FN_A6, GPIO_FN_MSIOF1_SCK, + + /* IPSR1 */ + GPIO_FN_A7, GPIO_FN_MSIOF1_SYNC, GPIO_FN_A8, + GPIO_FN_MSIOF1_SS1, GPIO_FN_SCL0, + GPIO_FN_A9, GPIO_FN_MSIOF1_SS2, GPIO_FN_SDA0, + GPIO_FN_A10, GPIO_FN_MSIOF1_TXD, GPIO_FN_MSIOF1_TXD_D, + GPIO_FN_A11, GPIO_FN_MSIOF1_RXD, GPIO_FN_SCL3_D, GPIO_FN_MSIOF1_RXD_D, + GPIO_FN_A12, GPIO_FN_FMCLK, GPIO_FN_SDA3_D, GPIO_FN_MSIOF1_SCK_D, + GPIO_FN_A13, GPIO_FN_ATAG0_N_C, GPIO_FN_BPFCLK, GPIO_FN_MSIOF1_SS1_D, + GPIO_FN_A14, GPIO_FN_ATADIR0_N_C, GPIO_FN_FMIN, + GPIO_FN_FMIN_C, GPIO_FN_MSIOF1_SYNC_D, + GPIO_FN_A15, GPIO_FN_BPFCLK_C, + GPIO_FN_A16, GPIO_FN_DREQ2_B, GPIO_FN_FMCLK_C, GPIO_FN_SCIFA1_SCK_B, + GPIO_FN_A17, GPIO_FN_DACK2_B, GPIO_FN_SDA0_C, + GPIO_FN_A18, GPIO_FN_DREQ1, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_SCIFB1_RXD_C, + + /* IPSR2 */ + GPIO_FN_A19, GPIO_FN_DACK1, GPIO_FN_SCIFA1_TXD_C, + GPIO_FN_SCIFB1_TXD_C, GPIO_FN_SCIFB1_SCK_B, + GPIO_FN_A20, GPIO_FN_SPCLK, + GPIO_FN_A21, GPIO_FN_ATAWR0_N_B, GPIO_FN_MOSI_IO0, + GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_FMCLK_B, + GPIO_FN_TX0, GPIO_FN_SCIFA0_TXD, + GPIO_FN_A23, GPIO_FN_IO2, GPIO_FN_BPFCLK_B, + GPIO_FN_RX0, GPIO_FN_SCIFA0_RXD, + GPIO_FN_A24, GPIO_FN_DREQ2, GPIO_FN_IO3, + GPIO_FN_TX1, GPIO_FN_SCIFA1_TXD, + GPIO_FN_A25, GPIO_FN_DACK2, GPIO_FN_SSL, GPIO_FN_DREQ1_C, + GPIO_FN_RX1, GPIO_FN_SCIFA1_RXD, + GPIO_FN_CS0_N, GPIO_FN_ATAG0_N_B, GPIO_FN_SCL1, + GPIO_FN_CS1_N_A26, GPIO_FN_ATADIR0_N_B, GPIO_FN_SDA1, + GPIO_FN_EX_CS1_N, GPIO_FN_MSIOF2_SCK, + GPIO_FN_EX_CS2_N, GPIO_FN_ATAWR0_N, GPIO_FN_MSIOF2_SYNC, + GPIO_FN_EX_CS3_N, GPIO_FN_ATADIR0_N, GPIO_FN_MSIOF2_TXD, + GPIO_FN_ATAG0_N, GPIO_FN_EX_WAIT1, + + /* IPSR3 */ + GPIO_FN_EX_CS4_N, GPIO_FN_ATARD0_N, + GPIO_FN_MSIOF2_RXD, GPIO_FN_EX_WAIT2, + GPIO_FN_EX_CS5_N, GPIO_FN_ATACS00_N, GPIO_FN_MSIOF2_SS1, + GPIO_FN_HRX1_B, GPIO_FN_SCIFB1_RXD_B, + GPIO_FN_PWM1, GPIO_FN_TPU_TO1, + GPIO_FN_BS_N, GPIO_FN_ATACS10_N, GPIO_FN_MSIOF2_SS2, + GPIO_FN_HTX1_B, GPIO_FN_SCIFB1_TXD_B, + GPIO_FN_PWM2, GPIO_FN_TPU_TO2, + GPIO_FN_RD_WR_N, GPIO_FN_HRX2_B, GPIO_FN_FMIN_B, + GPIO_FN_SCIFB0_RXD_B, GPIO_FN_DREQ1_D, + GPIO_FN_WE0_N, GPIO_FN_HCTS2_N_B, GPIO_FN_SCIFB0_TXD_B, + GPIO_FN_WE1_N, GPIO_FN_ATARD0_N_B, + GPIO_FN_HTX2_B, GPIO_FN_SCIFB0_RTS_N_B, + GPIO_FN_EX_WAIT0, GPIO_FN_HRTS2_N_B, GPIO_FN_SCIFB0_CTS_N_B, + GPIO_FN_DREQ0, GPIO_FN_PWM3, GPIO_FN_TPU_TO3, + GPIO_FN_DACK0, GPIO_FN_DRACK0, GPIO_FN_REMOCON, + GPIO_FN_SPEEDIN, GPIO_FN_HSCK0_C, GPIO_FN_HSCK2_C, + GPIO_FN_SCIFB0_SCK_B, GPIO_FN_SCIFB2_SCK_B, + GPIO_FN_DREQ2_C, GPIO_FN_HTX2_D, + GPIO_FN_SSI_SCK0129, GPIO_FN_HRX0_C, GPIO_FN_HRX2_C, + GPIO_FN_SCIFB0_RXD_C, GPIO_FN_SCIFB2_RXD_C, + GPIO_FN_SSI_WS0129, GPIO_FN_HTX0_C, GPIO_FN_HTX2_C, + GPIO_FN_SCIFB0_TXD_C, GPIO_FN_SCIFB2_TXD_C, + + /* IPSR4 */ + GPIO_FN_SSI_SDATA0, GPIO_FN_SCL0_B, + GPIO_FN_SCL7_B, GPIO_FN_MSIOF2_SCK_C, + GPIO_FN_SSI_SCK1, GPIO_FN_SDA0_B, GPIO_FN_SDA7_B, + GPIO_FN_MSIOF2_SYNC_C, GPIO_FN_GLO_I0_D, + GPIO_FN_SSI_WS1, GPIO_FN_SCL1_B, GPIO_FN_SCL8_B, + GPIO_FN_MSIOF2_TXD_C, GPIO_FN_GLO_I1_D, + GPIO_FN_SSI_SDATA1, GPIO_FN_SDA1_B, + GPIO_FN_SDA8_B, GPIO_FN_MSIOF2_RXD_C, + GPIO_FN_SSI_SCK2, GPIO_FN_SCL2, GPIO_FN_GPS_CLK_B, + GPIO_FN_GLO_Q0_D, GPIO_FN_HSCK1_E, + GPIO_FN_SSI_WS2, GPIO_FN_SDA2, GPIO_FN_GPS_SIGN_B, + GPIO_FN_RX2_E, GPIO_FN_GLO_Q1_D, GPIO_FN_HCTS1_N_E, + GPIO_FN_SSI_SDATA2, GPIO_FN_GPS_MAG_B, + GPIO_FN_TX2_E, GPIO_FN_HRTS1_N_E, + GPIO_FN_SSI_SCK34, GPIO_FN_SSI_WS34, GPIO_FN_SSI_SDATA3, + GPIO_FN_SSI_SCK4, GPIO_FN_GLO_SS_D, + GPIO_FN_SSI_WS4, GPIO_FN_GLO_RFON_D, + GPIO_FN_SSI_SDATA4, GPIO_FN_MSIOF2_SCK_D, + GPIO_FN_SSI_SCK5, GPIO_FN_MSIOF1_SCK_C, + GPIO_FN_TS_SDATA0, GPIO_FN_GLO_I0, + GPIO_FN_MSIOF2_SYNC_D, GPIO_FN_VI1_R2_B, + + /* IPSR5 */ + GPIO_FN_SSI_WS5, GPIO_FN_MSIOF1_SYNC_C, GPIO_FN_TS_SCK0, + GPIO_FN_GLO_I1, GPIO_FN_MSIOF2_TXD_D, GPIO_FN_VI1_R3_B, + GPIO_FN_SSI_SDATA5, GPIO_FN_MSIOF1_TXD_C, GPIO_FN_TS_SDEN0, + GPIO_FN_GLO_Q0, GPIO_FN_MSIOF2_SS1_D, GPIO_FN_VI1_R4_B, + GPIO_FN_SSI_SCK6, GPIO_FN_MSIOF1_RXD_C, GPIO_FN_TS_SPSYNC0, + GPIO_FN_GLO_Q1, GPIO_FN_MSIOF2_RXD_D, GPIO_FN_VI1_R5_B, + GPIO_FN_SSI_WS6, GPIO_FN_GLO_SCLK, + GPIO_FN_MSIOF2_SS2_D, GPIO_FN_VI1_R6_B, + GPIO_FN_SSI_SDATA6, GPIO_FN_STP_IVCXO27_0_B, + GPIO_FN_GLO_SDATA, GPIO_FN_VI1_R7_B, + GPIO_FN_SSI_SCK78, GPIO_FN_STP_ISCLK_0_B, GPIO_FN_GLO_SS, + GPIO_FN_SSI_WS78, GPIO_FN_TX0_D, GPIO_FN_STP_ISD_0_B, GPIO_FN_GLO_RFON, + GPIO_FN_SSI_SDATA7, GPIO_FN_RX0_D, GPIO_FN_STP_ISEN_0_B, + GPIO_FN_SSI_SDATA8, GPIO_FN_TX1_D, GPIO_FN_STP_ISSYNC_0_B, + GPIO_FN_SSI_SCK9, GPIO_FN_RX1_D, GPIO_FN_GLO_SCLK_D, + GPIO_FN_SSI_WS9, GPIO_FN_TX3_D, GPIO_FN_CAN0_TX_D, GPIO_FN_GLO_SDATA_D, + GPIO_FN_SSI_SDATA9, GPIO_FN_RX3_D, GPIO_FN_CAN0_RX_D, + + /* IPSR6 */ + GPIO_FN_AUDIO_CLKB, GPIO_FN_STP_OPWM_0_B, GPIO_FN_MSIOF1_SCK_B, + GPIO_FN_SCIF_CLK, GPIO_FN_BPFCLK_E, + GPIO_FN_AUDIO_CLKC, GPIO_FN_SCIFB0_SCK_C, GPIO_FN_MSIOF1_SYNC_B, + GPIO_FN_RX2, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN_E, + GPIO_FN_AUDIO_CLKOUT, GPIO_FN_MSIOF1_SS1_B, + GPIO_FN_TX2, GPIO_FN_SCIFA2_TXD, + GPIO_FN_IRQ0, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_INTC_IRQ0_N, + GPIO_FN_IRQ1, GPIO_FN_SCIFB1_SCK_C, GPIO_FN_INTC_IRQ1_N, + GPIO_FN_IRQ2, GPIO_FN_SCIFB1_TXD_D, GPIO_FN_INTC_IRQ2_N, + GPIO_FN_IRQ3, GPIO_FN_SCL4_C, + GPIO_FN_MSIOF2_TXD_E, GPIO_FN_INTC_IRQ3_N, + GPIO_FN_IRQ4, GPIO_FN_HRX1_C, GPIO_FN_SDA4_C, + GPIO_FN_MSIOF2_RXD_E, GPIO_FN_INTC_IRQ4_N, + GPIO_FN_IRQ5, GPIO_FN_HTX1_C, GPIO_FN_SCL1_E, GPIO_FN_MSIOF2_SCK_E, + GPIO_FN_IRQ6, GPIO_FN_HSCK1_C, GPIO_FN_MSIOF1_SS2_B, + GPIO_FN_SDA1_E, GPIO_FN_MSIOF2_SYNC_E, + GPIO_FN_IRQ7, GPIO_FN_HCTS1_N_C, GPIO_FN_MSIOF1_TXD_B, + GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D, + GPIO_FN_IRQ8, GPIO_FN_HRTS1_N_C, GPIO_FN_MSIOF1_RXD_B, + GPIO_FN_GPS_SIGN_C, GPIO_FN_GPS_SIGN_D, + + /* IPSR7 */ + GPIO_FN_IRQ9, GPIO_FN_DU1_DOTCLKIN_B, GPIO_FN_CAN_CLK_D, + GPIO_FN_GPS_MAG_C, GPIO_FN_SCIF_CLK_B, GPIO_FN_GPS_MAG_D, + GPIO_FN_DU1_DR0, GPIO_FN_LCDOUT0, GPIO_FN_VI1_DATA0_B, GPIO_FN_TX0_B, + GPIO_FN_SCIFA0_TXD_B, GPIO_FN_MSIOF2_SCK_B, + GPIO_FN_DU1_DR1, GPIO_FN_LCDOUT1, GPIO_FN_VI1_DATA1_B, GPIO_FN_RX0_B, + GPIO_FN_SCIFA0_RXD_B, GPIO_FN_MSIOF2_SYNC_B, + GPIO_FN_DU1_DR2, GPIO_FN_LCDOUT2, GPIO_FN_SSI_SCK0129_B, + GPIO_FN_DU1_DR3, GPIO_FN_LCDOUT3, GPIO_FN_SSI_WS0129_B, + GPIO_FN_DU1_DR4, GPIO_FN_LCDOUT4, GPIO_FN_SSI_SDATA0_B, + GPIO_FN_DU1_DR5, GPIO_FN_LCDOUT5, GPIO_FN_SSI_SCK1_B, + GPIO_FN_DU1_DR6, GPIO_FN_LCDOUT6, GPIO_FN_SSI_WS1_B, + GPIO_FN_DU1_DR7, GPIO_FN_LCDOUT7, GPIO_FN_SSI_SDATA1_B, + GPIO_FN_DU1_DG0, GPIO_FN_LCDOUT8, GPIO_FN_VI1_DATA2_B, GPIO_FN_TX1_B, + GPIO_FN_SCIFA1_TXD_B, GPIO_FN_MSIOF2_SS1_B, + GPIO_FN_DU1_DG1, GPIO_FN_LCDOUT9, GPIO_FN_VI1_DATA3_B, GPIO_FN_RX1_B, + GPIO_FN_SCIFA1_RXD_B, GPIO_FN_MSIOF2_SS2_B, + GPIO_FN_DU1_DG2, GPIO_FN_LCDOUT10, GPIO_FN_VI1_DATA4_B, + GPIO_FN_SCIF1_SCK_B, GPIO_FN_SCIFA1_SCK, GPIO_FN_SSI_SCK78_B, + + /* IPSR8 */ + GPIO_FN_DU1_DG3, GPIO_FN_LCDOUT11, + GPIO_FN_VI1_DATA5_B, GPIO_FN_SSI_WS78_B, + GPIO_FN_DU1_DG4, GPIO_FN_LCDOUT12, GPIO_FN_VI1_DATA6_B, + GPIO_FN_HRX0_B, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_SSI_SDATA7_B, + GPIO_FN_DU1_DG5, GPIO_FN_LCDOUT13, GPIO_FN_VI1_DATA7_B, + GPIO_FN_HCTS0_N_B, GPIO_FN_SCIFB2_TXD_B, GPIO_FN_SSI_SDATA8_B, + GPIO_FN_DU1_DG6, GPIO_FN_LCDOUT14, GPIO_FN_HRTS0_N_B, + GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_SSI_SCK9_B, + GPIO_FN_DU1_DG7, GPIO_FN_LCDOUT15, GPIO_FN_HTX0_B, + GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_SSI_WS9_B, + GPIO_FN_DU1_DB0, GPIO_FN_LCDOUT16, GPIO_FN_VI1_CLK_B, GPIO_FN_TX2_B, + GPIO_FN_SCIFA2_TXD_B, GPIO_FN_MSIOF2_TXD_B, + GPIO_FN_DU1_DB1, GPIO_FN_LCDOUT17, GPIO_FN_VI1_HSYNC_N_B, + GPIO_FN_RX2_B, GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF2_RXD_B, + GPIO_FN_DU1_DB2, GPIO_FN_LCDOUT18, GPIO_FN_VI1_VSYNC_N_B, + GPIO_FN_SCIF2_SCK_B, GPIO_FN_SCIFA2_SCK, GPIO_FN_SSI_SDATA9_B, + GPIO_FN_DU1_DB3, GPIO_FN_LCDOUT19, GPIO_FN_VI1_CLKENB_B, + GPIO_FN_DU1_DB4, GPIO_FN_LCDOUT20, + GPIO_FN_VI1_FIELD_B, GPIO_FN_CAN1_RX, + GPIO_FN_DU1_DB5, GPIO_FN_LCDOUT21, GPIO_FN_TX3, + GPIO_FN_SCIFA3_TXD, GPIO_FN_CAN1_TX, + + /* IPSR9 */ + GPIO_FN_DU1_DB6, GPIO_FN_LCDOUT22, GPIO_FN_SCL3_C, + GPIO_FN_RX3, GPIO_FN_SCIFA3_RXD, + GPIO_FN_DU1_DB7, GPIO_FN_LCDOUT23, GPIO_FN_SDA3_C, + GPIO_FN_SCIF3_SCK, GPIO_FN_SCIFA3_SCK, + GPIO_FN_DU1_DOTCLKIN, GPIO_FN_QSTVA_QVS, + GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_QCLK, + GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_QSTVB_QVE, GPIO_FN_CAN0_TX, + GPIO_FN_TX3_B, GPIO_FN_SCL2_B, GPIO_FN_PWM4, + GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_QSTH_QHS, + GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_QSTB_QHE, + GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, + GPIO_FN_CAN0_RX, GPIO_FN_RX3_B, GPIO_FN_SDA2_B, + GPIO_FN_DU1_DISP, GPIO_FN_QPOLA, + GPIO_FN_DU1_CDE, GPIO_FN_QPOLB, GPIO_FN_PWM4_B, + GPIO_FN_VI0_CLKENB, GPIO_FN_TX4, + GPIO_FN_SCIFA4_TXD, GPIO_FN_TS_SDATA0_D, + GPIO_FN_VI0_FIELD, GPIO_FN_RX4, GPIO_FN_SCIFA4_RXD, GPIO_FN_TS_SCK0_D, + GPIO_FN_VI0_HSYNC_N, GPIO_FN_TX5, + GPIO_FN_SCIFA5_TXD, GPIO_FN_TS_SDEN0_D, + GPIO_FN_VI0_VSYNC_N, GPIO_FN_RX5, + GPIO_FN_SCIFA5_RXD, GPIO_FN_TS_SPSYNC0_D, + GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_SCIF3_SCK_B, GPIO_FN_SCIFA3_SCK_B, + GPIO_FN_VI0_G0, GPIO_FN_SCL8, GPIO_FN_STP_IVCXO27_0_C, GPIO_FN_SCL4, + GPIO_FN_HCTS2_N, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_ATAWR1_N, + + /* IPSR10 */ + GPIO_FN_VI0_G1, GPIO_FN_SDA8, GPIO_FN_STP_ISCLK_0_C, GPIO_FN_SDA4, + GPIO_FN_HRTS2_N, GPIO_FN_SCIFB2_RTS_N, GPIO_FN_ATADIR1_N, + GPIO_FN_VI0_G2, GPIO_FN_VI2_HSYNC_N, GPIO_FN_STP_ISD_0_C, + GPIO_FN_SCL3_B, GPIO_FN_HSCK2, GPIO_FN_SCIFB2_SCK, GPIO_FN_ATARD1_N, + GPIO_FN_VI0_G3, GPIO_FN_VI2_VSYNC_N, GPIO_FN_STP_ISEN_0_C, + GPIO_FN_SDA3_B, GPIO_FN_HRX2, GPIO_FN_SCIFB2_RXD, GPIO_FN_ATACS01_N, + GPIO_FN_VI0_G4, GPIO_FN_VI2_CLKENB, GPIO_FN_STP_ISSYNC_0_C, + GPIO_FN_HTX2, GPIO_FN_SCIFB2_TXD, GPIO_FN_SCIFB0_SCK_D, + GPIO_FN_VI0_G5, GPIO_FN_VI2_FIELD, GPIO_FN_STP_OPWM_0_C, + GPIO_FN_FMCLK_D, GPIO_FN_CAN0_TX_E, + GPIO_FN_HTX1_D, GPIO_FN_SCIFB0_TXD_D, + GPIO_FN_VI0_G6, GPIO_FN_VI2_CLK, GPIO_FN_BPFCLK_D, + GPIO_FN_VI0_G7, GPIO_FN_VI2_DATA0, GPIO_FN_FMIN_D, + GPIO_FN_VI0_R0, GPIO_FN_VI2_DATA1, GPIO_FN_GLO_I0_B, + GPIO_FN_TS_SDATA0_C, GPIO_FN_ATACS11_N, + GPIO_FN_VI0_R1, GPIO_FN_VI2_DATA2, GPIO_FN_GLO_I1_B, + GPIO_FN_TS_SCK0_C, GPIO_FN_ATAG1_N, + GPIO_FN_VI0_R2, GPIO_FN_VI2_DATA3, + GPIO_FN_GLO_Q0_B, GPIO_FN_TS_SDEN0_C, + GPIO_FN_VI0_R3, GPIO_FN_VI2_DATA4, + GPIO_FN_GLO_Q1_B, GPIO_FN_TS_SPSYNC0_C, + GPIO_FN_VI0_R4, GPIO_FN_VI2_DATA5, GPIO_FN_GLO_SCLK_B, + GPIO_FN_TX0_C, GPIO_FN_SCL1_D, + + /* IPSR11 */ + GPIO_FN_VI0_R5, GPIO_FN_VI2_DATA6, GPIO_FN_GLO_SDATA_B, + GPIO_FN_RX0_C, GPIO_FN_SDA1_D, + GPIO_FN_VI0_R6, GPIO_FN_VI2_DATA7, GPIO_FN_GLO_SS_B, + GPIO_FN_TX1_C, GPIO_FN_SCL4_B, + GPIO_FN_VI0_R7, GPIO_FN_GLO_RFON_B, GPIO_FN_RX1_C, GPIO_FN_CAN0_RX_E, + GPIO_FN_SDA4_B, GPIO_FN_HRX1_D, GPIO_FN_SCIFB0_RXD_D, + GPIO_FN_VI1_HSYNC_N, GPIO_FN_AVB_RXD0, GPIO_FN_TS_SDATA0_B, + GPIO_FN_TX4_B, GPIO_FN_SCIFA4_TXD_B, + GPIO_FN_VI1_VSYNC_N, GPIO_FN_AVB_RXD1, GPIO_FN_TS_SCK0_B, + GPIO_FN_RX4_B, GPIO_FN_SCIFA4_RXD_B, + GPIO_FN_VI1_CLKENB, GPIO_FN_AVB_RXD2, GPIO_FN_TS_SDEN0_B, + GPIO_FN_VI1_FIELD, GPIO_FN_AVB_RXD3, GPIO_FN_TS_SPSYNC0_B, + GPIO_FN_VI1_CLK, GPIO_FN_AVB_RXD4, GPIO_FN_VI1_DATA0, GPIO_FN_AVB_RXD5, + GPIO_FN_VI1_DATA1, GPIO_FN_AVB_RXD6, + GPIO_FN_VI1_DATA2, GPIO_FN_AVB_RXD7, + GPIO_FN_VI1_DATA3, GPIO_FN_AVB_RX_ER, + GPIO_FN_VI1_DATA4, GPIO_FN_AVB_MDIO, + GPIO_FN_VI1_DATA5, GPIO_FN_AVB_RX_DV, + GPIO_FN_VI1_DATA6, GPIO_FN_AVB_MAGIC, + GPIO_FN_VI1_DATA7, GPIO_FN_AVB_MDC, + GPIO_FN_ETH_MDIO, GPIO_FN_AVB_RX_CLK, GPIO_FN_SCL2_C, + GPIO_FN_ETH_CRS_DV, GPIO_FN_AVB_LINK, GPIO_FN_SDA2_C, + + /* IPSR12 */ + GPIO_FN_ETH_RX_ER, GPIO_FN_AVB_CRS, GPIO_FN_SCL3, GPIO_FN_SCL7, + GPIO_FN_ETH_RXD0, GPIO_FN_AVB_PHY_INT, GPIO_FN_SDA3, GPIO_FN_SDA7, + GPIO_FN_ETH_RXD1, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN0_TX_C, + GPIO_FN_SCL2_D, GPIO_FN_MSIOF1_RXD_E, + GPIO_FN_ETH_LINK, GPIO_FN_AVB_TXD0, GPIO_FN_CAN0_RX_C, + GPIO_FN_SDA2_D, GPIO_FN_MSIOF1_SCK_E, + GPIO_FN_ETH_REFCLK, GPIO_FN_AVB_TXD1, GPIO_FN_SCIFA3_RXD_B, + GPIO_FN_CAN1_RX_C, GPIO_FN_MSIOF1_SYNC_E, + GPIO_FN_ETH_TXD1, GPIO_FN_AVB_TXD2, GPIO_FN_SCIFA3_TXD_B, + GPIO_FN_CAN1_TX_C, GPIO_FN_MSIOF1_TXD_E, + GPIO_FN_ETH_TX_EN, GPIO_FN_AVB_TXD3, + GPIO_FN_TCLK1_B, GPIO_FN_CAN_CLK_B, + GPIO_FN_ETH_MAGIC, GPIO_FN_AVB_TXD4, GPIO_FN_IETX_C, + GPIO_FN_ETH_TXD0, GPIO_FN_AVB_TXD5, GPIO_FN_IECLK_C, + GPIO_FN_ETH_MDC, GPIO_FN_AVB_TXD6, GPIO_FN_IERX_C, + GPIO_FN_STP_IVCXO27_0, GPIO_FN_AVB_TXD7, GPIO_FN_SCIFB2_TXD_D, + GPIO_FN_ADIDATA_B, GPIO_FN_MSIOF0_SYNC_C, + GPIO_FN_STP_ISCLK_0, GPIO_FN_AVB_TX_EN, GPIO_FN_SCIFB2_RXD_D, + GPIO_FN_ADICS_SAMP_B, GPIO_FN_MSIOF0_SCK_C, + + /* IPSR13 */ + GPIO_FN_STP_ISD_0, GPIO_FN_AVB_TX_ER, GPIO_FN_SCIFB2_SCK_C, + GPIO_FN_ADICLK_B, GPIO_FN_MSIOF0_SS1_C, + GPIO_FN_STP_ISEN_0, GPIO_FN_AVB_TX_CLK, + GPIO_FN_ADICHS0_B, GPIO_FN_MSIOF0_SS2_C, + GPIO_FN_STP_ISSYNC_0, GPIO_FN_AVB_COL, + GPIO_FN_ADICHS1_B, GPIO_FN_MSIOF0_RXD_C, + GPIO_FN_STP_OPWM_0, GPIO_FN_AVB_GTX_CLK, GPIO_FN_PWM0_B, + GPIO_FN_ADICHS2_B, GPIO_FN_MSIOF0_TXD_C, + GPIO_FN_SD0_CLK, GPIO_FN_SPCLK_B, GPIO_FN_SD0_CMD, GPIO_FN_MOSI_IO0_B, + GPIO_FN_SD0_DATA0, GPIO_FN_MISO_IO1_B, + GPIO_FN_SD0_DATA1, GPIO_FN_IO2_B, + GPIO_FN_SD0_DATA2, GPIO_FN_IO3_B, GPIO_FN_SD0_DATA3, GPIO_FN_SSL_B, + GPIO_FN_SD0_CD, GPIO_FN_MMC_D6_B, + GPIO_FN_SIM0_RST_B, GPIO_FN_CAN0_RX_F, + GPIO_FN_SCIFA5_TXD_B, GPIO_FN_TX3_C, + GPIO_FN_SD0_WP, GPIO_FN_MMC_D7_B, GPIO_FN_SIM0_D_B, GPIO_FN_CAN0_TX_F, + GPIO_FN_SCIFA5_RXD_B, GPIO_FN_RX3_C, + GPIO_FN_SD1_CMD, GPIO_FN_REMOCON_B, + GPIO_FN_SD1_DATA0, GPIO_FN_SPEEDIN_B, + GPIO_FN_SD1_DATA1, GPIO_FN_IETX_B, GPIO_FN_SD1_DATA2, GPIO_FN_IECLK_B, + GPIO_FN_SD1_DATA3, GPIO_FN_IERX_B, + GPIO_FN_SD1_CD, GPIO_FN_PWM0, GPIO_FN_TPU_TO0, GPIO_FN_SCL1_C, + + /* IPSR14 */ + GPIO_FN_SD1_WP, GPIO_FN_PWM1_B, GPIO_FN_SDA1_C, + GPIO_FN_SD2_CLK, GPIO_FN_MMC_CLK, GPIO_FN_SD2_CMD, GPIO_FN_MMC_CMD, + GPIO_FN_SD2_DATA0, GPIO_FN_MMC_D0, GPIO_FN_SD2_DATA1, GPIO_FN_MMC_D1, + GPIO_FN_SD2_DATA2, GPIO_FN_MMC_D2, GPIO_FN_SD2_DATA3, GPIO_FN_MMC_D3, + GPIO_FN_SD2_CD, GPIO_FN_MMC_D4, GPIO_FN_SCL8_C, + GPIO_FN_TX5_B, GPIO_FN_SCIFA5_TXD_C, + GPIO_FN_SD2_WP, GPIO_FN_MMC_D5, GPIO_FN_SDA8_C, + GPIO_FN_RX5_B, GPIO_FN_SCIFA5_RXD_C, + GPIO_FN_MSIOF0_SCK, GPIO_FN_RX2_C, GPIO_FN_ADIDATA, + GPIO_FN_VI1_CLK_C, GPIO_FN_VI1_G0_B, + GPIO_FN_MSIOF0_SYNC, GPIO_FN_TX2_C, GPIO_FN_ADICS_SAMP, + GPIO_FN_VI1_CLKENB_C, GPIO_FN_VI1_G1_B, + GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICLK, + GPIO_FN_VI1_FIELD_C, GPIO_FN_VI1_G2_B, + GPIO_FN_MSIOF0_RXD, GPIO_FN_ADICHS0, + GPIO_FN_VI1_DATA0_C, GPIO_FN_VI1_G3_B, + GPIO_FN_MSIOF0_SS1, GPIO_FN_MMC_D6, GPIO_FN_ADICHS1, GPIO_FN_TX0_E, + GPIO_FN_VI1_HSYNC_N_C, GPIO_FN_SCL7_C, GPIO_FN_VI1_G4_B, + GPIO_FN_MSIOF0_SS2, GPIO_FN_MMC_D7, GPIO_FN_ADICHS2, GPIO_FN_RX0_E, + GPIO_FN_VI1_VSYNC_N_C, GPIO_FN_SDA7_C, GPIO_FN_VI1_G5_B, + + /* IPSR15 */ + GPIO_FN_SIM0_RST, GPIO_FN_IETX, GPIO_FN_CAN1_TX_D, + GPIO_FN_SIM0_CLK, GPIO_FN_IECLK, GPIO_FN_CAN_CLK_C, + GPIO_FN_SIM0_D, GPIO_FN_IERX, GPIO_FN_CAN1_RX_D, + GPIO_FN_GPS_CLK, GPIO_FN_DU1_DOTCLKIN_C, GPIO_FN_AUDIO_CLKB_B, + GPIO_FN_PWM5_B, GPIO_FN_SCIFA3_TXD_C, + GPIO_FN_GPS_SIGN, GPIO_FN_TX4_C, GPIO_FN_SCIFA4_TXD_C, GPIO_FN_PWM5, + GPIO_FN_VI1_G6_B, GPIO_FN_SCIFA3_RXD_C, + GPIO_FN_GPS_MAG, GPIO_FN_RX4_C, GPIO_FN_SCIFA4_RXD_C, GPIO_FN_PWM6, + GPIO_FN_VI1_G7_B, GPIO_FN_SCIFA3_SCK_C, + GPIO_FN_HCTS0_N, GPIO_FN_SCIFB0_CTS_N, GPIO_FN_GLO_I0_C, + GPIO_FN_TCLK1, GPIO_FN_VI1_DATA1_C, + GPIO_FN_HRTS0_N, GPIO_FN_SCIFB0_RTS_N, + GPIO_FN_GLO_I1_C, GPIO_FN_VI1_DATA2_C, + GPIO_FN_HSCK0, GPIO_FN_SCIFB0_SCK, GPIO_FN_GLO_Q0_C, GPIO_FN_CAN_CLK, + GPIO_FN_TCLK2, GPIO_FN_VI1_DATA3_C, + GPIO_FN_HRX0, GPIO_FN_SCIFB0_RXD, GPIO_FN_GLO_Q1_C, + GPIO_FN_CAN0_RX_B, GPIO_FN_VI1_DATA4_C, + GPIO_FN_HTX0, GPIO_FN_SCIFB0_TXD, GPIO_FN_GLO_SCLK_C, + GPIO_FN_CAN0_TX_B, GPIO_FN_VI1_DATA5_C, + + /* IPSR16 */ + GPIO_FN_HRX1, GPIO_FN_SCIFB1_RXD, GPIO_FN_VI1_R0_B, + GPIO_FN_GLO_SDATA_C, GPIO_FN_VI1_DATA6_C, + GPIO_FN_HTX1, GPIO_FN_SCIFB1_TXD, GPIO_FN_VI1_R1_B, + GPIO_FN_GLO_SS_C, GPIO_FN_VI1_DATA7_C, + GPIO_FN_HSCK1, GPIO_FN_SCIFB1_SCK, GPIO_FN_MLB_CK, GPIO_FN_GLO_RFON_C, + GPIO_FN_HCTS1_N, GPIO_FN_SCIFB1_CTS_N, + GPIO_FN_MLB_SIG, GPIO_FN_CAN1_TX_B, + GPIO_FN_HRTS1_N, GPIO_FN_SCIFB1_RTS_N, + GPIO_FN_MLB_DAT, GPIO_FN_CAN1_RX_B, +}; + +#endif /* __ASM_R8A7791_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h new file mode 100644 index 0000000..2afda0a --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h @@ -0,0 +1,664 @@ +/* + * arch/arm/include/asm/arch-rmobile/r8a7791.h + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ARCH_R8A7791_H +#define __ASM_ARCH_R8A7791_H + +/* + * R8A7791 I/O Addresses + */ +#define RWDT_BASE 0xE6020000 +#define SWDT_BASE 0xE6030000 +#define LBSC_BASE 0xFEC00200 +#define DBSC3_0_BASE 0xE6790000 +#define DBSC3_1_BASE 0xE67A0000 +#define TMU_BASE 0xE61E0000 +#define GPIO5_BASE 0xE6055000 + +#define S3C_BASE 0xE6784000 +#define S3C_INT_BASE 0xE6784A00 +#define S3C_MEDIA_BASE 0xE6784B00 + +#define S3C_QOS_DCACHE_BASE 0xE6784BDC +#define S3C_QOS_CCI0_BASE 0xE6784C00 +#define S3C_QOS_CCI1_BASE 0xE6784C24 +#define S3C_QOS_MXI_BASE 0xE6784C48 +#define S3C_QOS_AXI_BASE 0xE6784C6C + +#define DBSC3_0_QOS_R0_BASE 0xE6791000 +#define DBSC3_0_QOS_R1_BASE 0xE6791100 +#define DBSC3_0_QOS_R2_BASE 0xE6791200 +#define DBSC3_0_QOS_R3_BASE 0xE6791300 +#define DBSC3_0_QOS_R4_BASE 0xE6791400 +#define DBSC3_0_QOS_R5_BASE 0xE6791500 +#define DBSC3_0_QOS_R6_BASE 0xE6791600 +#define DBSC3_0_QOS_R7_BASE 0xE6791700 +#define DBSC3_0_QOS_R8_BASE 0xE6791800 +#define DBSC3_0_QOS_R9_BASE 0xE6791900 +#define DBSC3_0_QOS_R10_BASE 0xE6791A00 +#define DBSC3_0_QOS_R11_BASE 0xE6791B00 +#define DBSC3_0_QOS_R12_BASE 0xE6791C00 +#define DBSC3_0_QOS_R13_BASE 0xE6791D00 +#define DBSC3_0_QOS_R14_BASE 0xE6791E00 +#define DBSC3_0_QOS_R15_BASE 0xE6791F00 +#define DBSC3_0_QOS_W0_BASE 0xE6792000 +#define DBSC3_0_QOS_W1_BASE 0xE6792100 +#define DBSC3_0_QOS_W2_BASE 0xE6792200 +#define DBSC3_0_QOS_W3_BASE 0xE6792300 +#define DBSC3_0_QOS_W4_BASE 0xE6792400 +#define DBSC3_0_QOS_W5_BASE 0xE6792500 +#define DBSC3_0_QOS_W6_BASE 0xE6792600 +#define DBSC3_0_QOS_W7_BASE 0xE6792700 +#define DBSC3_0_QOS_W8_BASE 0xE6792800 +#define DBSC3_0_QOS_W9_BASE 0xE6792900 +#define DBSC3_0_QOS_W10_BASE 0xE6792A00 +#define DBSC3_0_QOS_W11_BASE 0xE6792B00 +#define DBSC3_0_QOS_W12_BASE 0xE6792C00 +#define DBSC3_0_QOS_W13_BASE 0xE6792D00 +#define DBSC3_0_QOS_W14_BASE 0xE6792E00 +#define DBSC3_0_QOS_W15_BASE 0xE6792F00 + +#define DBSC3_1_QOS_R0_BASE 0xE67A1000 +#define DBSC3_1_QOS_R1_BASE 0xE67A1100 +#define DBSC3_1_QOS_R2_BASE 0xE67A1200 +#define DBSC3_1_QOS_R3_BASE 0xE67A1300 +#define DBSC3_1_QOS_R4_BASE 0xE67A1400 +#define DBSC3_1_QOS_R5_BASE 0xE67A1500 +#define DBSC3_1_QOS_R6_BASE 0xE67A1600 +#define DBSC3_1_QOS_R7_BASE 0xE67A1700 +#define DBSC3_1_QOS_R8_BASE 0xE67A1800 +#define DBSC3_1_QOS_R9_BASE 0xE67A1900 +#define DBSC3_1_QOS_R10_BASE 0xE67A1A00 +#define DBSC3_1_QOS_R11_BASE 0xE67A1B00 +#define DBSC3_1_QOS_R12_BASE 0xE67A1C00 +#define DBSC3_1_QOS_R13_BASE 0xE67A1D00 +#define DBSC3_1_QOS_R14_BASE 0xE67A1E00 +#define DBSC3_1_QOS_R15_BASE 0xE67A1F00 +#define DBSC3_1_QOS_W0_BASE 0xE67A2000 +#define DBSC3_1_QOS_W1_BASE 0xE67A2100 +#define DBSC3_1_QOS_W2_BASE 0xE67A2200 +#define DBSC3_1_QOS_W3_BASE 0xE67A2300 +#define DBSC3_1_QOS_W4_BASE 0xE67A2400 +#define DBSC3_1_QOS_W5_BASE 0xE67A2500 +#define DBSC3_1_QOS_W6_BASE 0xE67A2600 +#define DBSC3_1_QOS_W7_BASE 0xE67A2700 +#define DBSC3_1_QOS_W8_BASE 0xE67A2800 +#define DBSC3_1_QOS_W9_BASE 0xE67A2900 +#define DBSC3_1_QOS_W10_BASE 0xE67A2A00 +#define DBSC3_1_QOS_W11_BASE 0xE67A2B00 +#define DBSC3_1_QOS_W12_BASE 0xE67A2C00 +#define DBSC3_1_QOS_W13_BASE 0xE67A2D00 +#define DBSC3_1_QOS_W14_BASE 0xE67A2E00 +#define DBSC3_1_QOS_W15_BASE 0xE67A2F00 + +#define DBSC3_0_DBADJ2 0xE67900C8 + +#define CCI_400_MAXOT_1 0xF0091110 +#define CCI_400_MAXOT_2 0xF0092110 +#define CCI_400_QOSCNTL_1 0xF009110C +#define CCI_400_QOSCNTL_2 0xF009210C + +#define MXI_BASE 0xFE960000 +#define MXI_QOS_BASE 0xFE960300 + +#define SYS_AXI_SYX64TO128_BASE 0xFF800300 +#define SYS_AXI_AVB_BASE 0xFF800340 +#define SYS_AXI_G2D_BASE 0xFF800540 +#define SYS_AXI_IMP0_BASE 0xFF800580 +#define SYS_AXI_IMP1_BASE 0xFF8005C0 +#define SYS_AXI_IMUX0_BASE 0xFF800600 +#define SYS_AXI_IMUX1_BASE 0xFF800640 +#define SYS_AXI_IMUX2_BASE 0xFF800680 +#define SYS_AXI_LBS_BASE 0xFF8006C0 +#define SYS_AXI_MMUDS_BASE 0xFF800700 +#define SYS_AXI_MMUM_BASE 0xFF800740 +#define SYS_AXI_MMUR_BASE 0xFF800780 +#define SYS_AXI_MMUS0_BASE 0xFF8007C0 +#define SYS_AXI_MMUS1_BASE 0xFF800800 +#define SYS_AXI_MTSB0_BASE 0xFF800880 +#define SYS_AXI_MTSB1_BASE 0xFF8008C0 +#define SYS_AXI_PCI_BASE 0xFF800900 +#define SYS_AXI_RTX_BASE 0xFF800940 +#define SYS_AXI_SDS0_BASE 0xFF800A80 +#define SYS_AXI_SDS1_BASE 0xFF800AC0 +#define SYS_AXI_USB20_BASE 0xFF800C00 +#define SYS_AXI_USB21_BASE 0xFF800C40 +#define SYS_AXI_USB22_BASE 0xFF800C80 +#define SYS_AXI_USB30_BASE 0xFF800CC0 +#define SYS_AXI_AX2M_BASE 0xFF800380 +#define SYS_AXI_CC50_BASE 0xFF8003C0 +#define SYS_AXI_CCI_BASE 0xFF800440 +#define SYS_AXI_CS_BASE 0xFF800480 +#define SYS_AXI_DDM_BASE 0xFF8004C0 +#define SYS_AXI_ETH_BASE 0xFF800500 +#define SYS_AXI_MPXM_BASE 0xFF800840 +#define SYS_AXI_SAT0_BASE 0xFF800980 +#define SYS_AXI_SAT1_BASE 0xFF8009C0 +#define SYS_AXI_SDM0_BASE 0xFF800A00 +#define SYS_AXI_SDM1_BASE 0xFF800A40 +#define SYS_AXI_TRAB_BASE 0xFF800B00 +#define SYS_AXI_UDM0_BASE 0xFF800B80 +#define SYS_AXI_UDM1_BASE 0xFF800BC0 + +#define RT_AXI_SHX_BASE 0xFF810100 +#define RT_AXI_DBG_BASE 0xFF810140 +#define RT_AXI_RDM_BASE 0xFF810180 +#define RT_AXI_RDS_BASE 0xFF8101C0 +#define RT_AXI_RTX64TO128_BASE 0xFF810200 +#define RT_AXI_STPRO_BASE 0xFF810240 +#define RT_AXI_SY2RT_BASE 0xFF810280 + +#define MP_AXI_ADSP_BASE 0xFF820100 +#define MP_AXI_ASDS0_BASE 0xFF8201C0 +#define MP_AXI_ASDS1_BASE 0xFF820200 +#define MP_AXI_MLP_BASE 0xFF820240 +#define MP_AXI_MMUMP_BASE 0xFF820280 +#define MP_AXI_SPU_BASE 0xFF8202C0 +#define MP_AXI_SPUC_BASE 0xFF820300 + +#define SYS_AXI256_AXI128TO256_BASE 0xFF860100 +#define SYS_AXI256_SYX_BASE 0xFF860140 +#define SYS_AXI256_MPX_BASE 0xFF860180 +#define SYS_AXI256_MXI_BASE 0xFF8601C0 + +#define CCI_AXI_MMUS0_BASE 0xFF880100 +#define CCI_AXI_SYX2_BASE 0xFF880140 +#define CCI_AXI_MMUR_BASE 0xFF880180 +#define CCI_AXI_MMUDS_BASE 0xFF8801C0 +#define CCI_AXI_MMUM_BASE 0xFF880200 +#define CCI_AXI_MXI_BASE 0xFF880240 +#define CCI_AXI_MMUS1_BASE 0xFF880280 +#define CCI_AXI_MMUMP_BASE 0xFF8802C0 + +#define MEDIA_AXI_MXR_BASE 0xFE960080 +#define MEDIA_AXI_MXW_BASE 0xFE9600C0 +#define MEDIA_AXI_JPR_BASE 0xFE964100 +#define MEDIA_AXI_JPW_BASE 0xFE966100 +#define MEDIA_AXI_GCU0R_BASE 0xFE964140 +#define MEDIA_AXI_GCU0W_BASE 0xFE966140 +#define MEDIA_AXI_GCU1R_BASE 0xFE964180 +#define MEDIA_AXI_GCU1W_BASE 0xFE966180 +#define MEDIA_AXI_TDMR_BASE 0xFE964500 +#define MEDIA_AXI_TDMW_BASE 0xFE966500 +#define MEDIA_AXI_VSP0CR_BASE 0xFE964540 +#define MEDIA_AXI_VSP0CW_BASE 0xFE966540 +#define MEDIA_AXI_VSP1CR_BASE 0xFE964580 +#define MEDIA_AXI_VSP1CW_BASE 0xFE966580 +#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0 +#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0 +#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600 +#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600 +#define MEDIA_AXI_VIN0W_BASE 0xFE966900 +#define MEDIA_AXI_VSP0R_BASE 0xFE964D00 +#define MEDIA_AXI_VSP0W_BASE 0xFE966D00 +#define MEDIA_AXI_FDP0R_BASE 0xFE964D40 +#define MEDIA_AXI_FDP0W_BASE 0xFE966D40 +#define MEDIA_AXI_IMSR_BASE 0xFE964D80 +#define MEDIA_AXI_IMSW_BASE 0xFE966D80 +#define MEDIA_AXI_VSP1R_BASE 0xFE965100 +#define MEDIA_AXI_VSP1W_BASE 0xFE967100 +#define MEDIA_AXI_FDP1R_BASE 0xFE965140 +#define MEDIA_AXI_FDP1W_BASE 0xFE967140 +#define MEDIA_AXI_IMRR_BASE 0xFE965180 +#define MEDIA_AXI_IMRW_BASE 0xFE967180 +#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0 +#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0 +#define MEDIA_AXI_VSPD0R_BASE 0xFE965500 +#define MEDIA_AXI_VSPD0W_BASE 0xFE967500 +#define MEDIA_AXI_VSPD1R_BASE 0xFE965540 +#define MEDIA_AXI_VSPD1W_BASE 0xFE967540 +#define MEDIA_AXI_DU0R_BASE 0xFE965580 +#define MEDIA_AXI_DU0W_BASE 0xFE967580 +#define MEDIA_AXI_DU1R_BASE 0xFE9655C0 +#define MEDIA_AXI_DU1W_BASE 0xFE9675C0 +#define MEDIA_AXI_VCP0CR_BASE 0xFE965900 +#define MEDIA_AXI_VCP0CW_BASE 0xFE967900 +#define MEDIA_AXI_VCP0VR_BASE 0xFE965940 +#define MEDIA_AXI_VCP0VW_BASE 0xFE967940 +#define MEDIA_AXI_VPC0R_BASE 0xFE965980 +#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00 +#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00 +#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40 +#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40 +#define MEDIA_AXI_VPC1R_BASE 0xFE965D80 + +#define SYS_AXI_AVBDMSCR 0xFF802000 +#define SYS_AXI_SYX2DMSCR 0xFF802004 +#define SYS_AXI_CC50DMSCR 0xFF802008 +#define SYS_AXI_CC51DMSCR 0xFF80200C +#define SYS_AXI_CCIDMSCR 0xFF802010 +#define SYS_AXI_CSDMSCR 0xFF802014 +#define SYS_AXI_DDMDMSCR 0xFF802018 +#define SYS_AXI_ETHDMSCR 0xFF80201C +#define SYS_AXI_G2DDMSCR 0xFF802020 +#define SYS_AXI_IMP0DMSCR 0xFF802024 +#define SYS_AXI_IMP1DMSCR 0xFF802028 +#define SYS_AXI_LBSDMSCR 0xFF80202C +#define SYS_AXI_MMUDSDMSCR 0xFF802030 +#define SYS_AXI_MMUMXDMSCR 0xFF802034 +#define SYS_AXI_MMURDDMSCR 0xFF802038 +#define SYS_AXI_MMUS0DMSCR 0xFF80203C +#define SYS_AXI_MMUS1DMSCR 0xFF802040 +#define SYS_AXI_MPXDMSCR 0xFF802044 +#define SYS_AXI_MTSB0DMSCR 0xFF802048 +#define SYS_AXI_MTSB1DMSCR 0xFF80204C +#define SYS_AXI_PCIDMSCR 0xFF802050 +#define SYS_AXI_RTXDMSCR 0xFF802054 +#define SYS_AXI_SAT0DMSCR 0xFF802058 +#define SYS_AXI_SAT1DMSCR 0xFF80205C +#define SYS_AXI_SDM0DMSCR 0xFF802060 +#define SYS_AXI_SDM1DMSCR 0xFF802064 +#define SYS_AXI_SDS0DMSCR 0xFF802068 +#define SYS_AXI_SDS1DMSCR 0xFF80206C +#define SYS_AXI_ETRABDMSCR 0xFF802070 +#define SYS_AXI_ETRKFDMSCR 0xFF802074 +#define SYS_AXI_UDM0DMSCR 0xFF802078 +#define SYS_AXI_UDM1DMSCR 0xFF80207C +#define SYS_AXI_USB20DMSCR 0xFF802080 +#define SYS_AXI_USB21DMSCR 0xFF802084 +#define SYS_AXI_USB22DMSCR 0xFF802088 +#define SYS_AXI_USB30DMSCR 0xFF80208C +#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100 +#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104 +#define SYS_AXI_AVBSLVDMSCR 0xFF802108 +#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C +#define SYS_AXI_ETHSLVDMSCR 0xFF802110 +#define SYS_AXI_GICSLVDMSCR 0xFF802114 +#define SYS_AXI_IMPSLVDMSCR 0xFF802118 +#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C +#define SYS_AXI_IMX1SLVDMSCR 0xFF802120 +#define SYS_AXI_IMX2SLVDMSCR 0xFF802124 +#define SYS_AXI_LBSSLVDMSCR 0xFF802128 +#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C +#define SYS_AXI_MMC1SLVDMSCR 0xFF802130 +#define SYS_AXI_MPXSLVDMSCR 0xFF802134 +#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138 +#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C +#define SYS_AXI_MXTSLVDMSCR 0xFF802140 +#define SYS_AXI_PCISLVDMSCR 0xFF802144 +#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148 +#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C +#define SYS_AXI_RTXSLVDMSCR 0xFF802150 +#define SYS_AXI_SAT0SLVDMSCR 0xFF802168 +#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C +#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170 +#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174 +#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178 +#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C +#define SYS_AXI_SGXSLVDMSCR 0xFF802180 +#define SYS_AXI_STBSLVDMSCR 0xFF802188 +#define SYS_AXI_STMSLVDMSCR 0xFF80218C +#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194 +#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198 +#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C +#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0 +#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4 +#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8 +#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC + +#define RT_AXI_CBMDMSCR 0xFF812000 +#define RT_AXI_DBDMSCR 0xFF812004 +#define RT_AXI_RDMDMSCR 0xFF812008 +#define RT_AXI_RDSDMSCR 0xFF81200C +#define RT_AXI_STRDMSCR 0xFF812010 +#define RT_AXI_SY2RTDMSCR 0xFF812014 +#define RT_AXI_CBSSLVDMSCR 0xFF812100 +#define RT_AXI_DBSSLVDMSCR 0xFF812104 +#define RT_AXI_RTAP1SLVDMSCR 0xFF812108 +#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C +#define RT_AXI_RTAP3SLVDMSCR 0xFF812110 +#define RT_AXI_RT2SYSLVDMSCR 0xFF812114 +#define RT_AXI_A128TO64SLVDMSCR 0xFF812118 +#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C +#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120 +#define RT_AXI_UTLBRSLVDMSCR 0xFF812128 + +#define MP_AXI_ADSPDMSCR 0xFF822000 +#define MP_AXI_ASDM0DMSCR 0xFF822004 +#define MP_AXI_ASDM1DMSCR 0xFF822008 +#define MP_AXI_ASDS0DMSCR 0xFF82200C +#define MP_AXI_ASDS1DMSCR 0xFF822010 +#define MP_AXI_MLPDMSCR 0xFF822014 +#define MP_AXI_MMUMPDMSCR 0xFF822018 +#define MP_AXI_SPUDMSCR 0xFF82201C +#define MP_AXI_SPUCDMSCR 0xFF822020 +#define MP_AXI_SY2MPDMSCR 0xFF822024 +#define MP_AXI_ADSPSLVDMSCR 0xFF822100 +#define MP_AXI_MLMSLVDMSCR 0xFF822104 +#define MP_AXI_MPAP4SLVDMSCR 0xFF822108 +#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C +#define MP_AXI_MPAP6SLVDMSCR 0xFF822110 +#define MP_AXI_MPAP7SLVDMSCR 0xFF822114 +#define MP_AXI_MP2SYSLVDMSCR 0xFF822118 +#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C +#define MP_AXI_MPXAPSLVDMSCR 0xFF822124 +#define MP_AXI_SPUSLVDMSCR 0xFF822128 +#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C + +#define ADM_AXI_ASDM0DMSCR 0xFF842000 +#define ADM_AXI_ASDM1DMSCR 0xFF842004 +#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104 +#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108 +#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C + +#define DM_AXI_RDMDMSCR 0xFF852000 +#define DM_AXI_SDM0DMSCR 0xFF852004 +#define DM_AXI_SDM1DMSCR 0xFF852008 +#define DM_AXI_MMAP0SLVDMSCR 0xFF852100 +#define DM_AXI_MMAP1SLVDMSCR 0xFF852104 +#define DM_AXI_QSPAPSLVDMSCR 0xFF852108 +#define DM_AXI_RAP4SLVDMSCR 0xFF85210C +#define DM_AXI_RAP5SLVDMSCR 0xFF852110 +#define DM_AXI_SAP4SLVDMSCR 0xFF852114 +#define DM_AXI_SAP5SLVDMSCR 0xFF852118 +#define DM_AXI_SAP6SLVDMSCR 0xFF85211C +#define DM_AXI_SAP65SLVDMSCR 0xFF852120 +#define DM_AXI_SDAP0SLVDMSCR 0xFF852124 +#define DM_AXI_SDAP1SLVDMSCR 0xFF852128 +#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C +#define DM_AXI_SDAP3SLVDMSCR 0xFF852130 + +#define SYS_AXI256_SYXDMSCR 0xFF862000 +#define SYS_AXI256_MPXDMSCR 0xFF862004 +#define SYS_AXI256_MXIDMSCR 0xFF862008 +#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100 +#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104 +#define SYS_AXI256_SYXSLVDMSCR 0xFF862108 +#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C +#define SYS_AXI256_S3CSLVDMSCR 0xFF862110 + +#define MXT_SYXDMSCR 0xFF872000 +#define MXT_CMM0SLVDMSCR 0xFF872100 +#define MXT_CMM1SLVDMSCR 0xFF872104 +#define MXT_CMM2SLVDMSCR 0xFF872108 +#define MXT_FDPSLVDMSCR 0xFF87210C +#define MXT_IMRSLVDMSCR 0xFF872110 +#define MXT_VINSLVDMSCR 0xFF872114 +#define MXT_VPC0SLVDMSCR 0xFF872118 +#define MXT_VPC1SLVDMSCR 0xFF87211C +#define MXT_VSP0SLVDMSCR 0xFF872120 +#define MXT_VSP1SLVDMSCR 0xFF872124 +#define MXT_VSPD0SLVDMSCR 0xFF872128 +#define MXT_VSPD1SLVDMSCR 0xFF87212C +#define MXT_MAP1SLVDMSCR 0xFF872130 +#define MXT_MAP2SLVDMSCR 0xFF872134 + +#define CCI_AXI_MMUS0DMSCR 0xFF882000 +#define CCI_AXI_SYX2DMSCR 0xFF882004 +#define CCI_AXI_MMURDMSCR 0xFF882008 +#define CCI_AXI_MMUDSDMSCR 0xFF88200C +#define CCI_AXI_MMUMDMSCR 0xFF882010 +#define CCI_AXI_MXIDMSCR 0xFF882014 +#define CCI_AXI_MMUS1DMSCR 0xFF882018 +#define CCI_AXI_MMUMPDMSCR 0xFF88201C +#define CCI_AXI_DVMDMSCR 0xFF882020 +#define CCI_AXI_CCISLVDMSCR 0xFF882100 + +#define CCI_AXI_IPMMUIDVMCR 0xFF880400 +#define CCI_AXI_IPMMURDVMCR 0xFF880404 +#define CCI_AXI_IPMMUS0DVMCR 0xFF880408 +#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C +#define CCI_AXI_IPMMUMPDVMCR 0xFF880410 +#define CCI_AXI_IPMMUDSDVMCR 0xFF880414 +#define CCI_AXI_AX2ADDRMASK 0xFF88041C + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +/* RWDT */ +struct r8a7791_rwdt { + u32 rwtcnt; /* 0x00 */ + u32 rwtcsra; /* 0x04 */ + u16 rwtcsrb; /* 0x08 */ +}; + +/* SWDT */ +struct r8a7791_swdt { + u32 swtcnt; /* 0x00 */ + u32 swtcsra; /* 0x04 */ + u16 swtcsrb; /* 0x08 */ +}; + +/* LBSC */ +struct r8a7791_lbsc { + u32 cs0ctrl; + u32 cs1ctrl; + u32 ecs0ctrl; + u32 ecs1ctrl; + u32 ecs2ctrl; + u32 ecs3ctrl; + u32 ecs4ctrl; + u32 ecs5ctrl; + u32 dummy0[4]; /* 0x20 .. 0x2C */ + u32 cswcr0; + u32 cswcr1; + u32 ecswcr0; + u32 ecswcr1; + u32 ecswcr2; + u32 ecswcr3; + u32 ecswcr4; + u32 ecswcr5; + u32 exdmawcr0; + u32 exdmawcr1; + u32 exdmawcr2; + u32 dummy1[9]; /* 0x5C .. 0x7C */ + u32 cspwcr0; + u32 cspwcr1; + u32 ecspwcr0; + u32 ecspwcr1; + u32 ecspwcr2; + u32 ecspwcr3; + u32 ecspwcr4; + u32 ecspwcr5; + u32 exwtsync; + u32 dummy2[3]; /* 0xA4 .. 0xAC */ + u32 cs0bstctl; + u32 cs0btph; + u32 dummy3[2]; /* 0xB8 .. 0xBC */ + u32 cs1gdst; + u32 ecs0gdst; + u32 ecs1gdst; + u32 ecs2gdst; + u32 ecs3gdst; + u32 ecs4gdst; + u32 ecs5gdst; + u32 dummy4[5]; /* 0xDC .. 0xEC */ + u32 exdmaset0; + u32 exdmaset1; + u32 exdmaset2; + u32 dummy5[5]; /* 0xFC .. 0x10C */ + u32 exdmcr0; + u32 exdmcr1; + u32 exdmcr2; + u32 dummy6[5]; /* 0x11C .. 0x12C */ + u32 bcintsr; + u32 bcintcr; + u32 bcintmr; + u32 dummy7; /* 0x13C */ + u32 exbatlv; + u32 exwtsts; + u32 dummy8[14]; /* 0x148 .. 0x17C */ + u32 atacsctrl; + u32 dummy9[15]; /* 0x184 .. 0x1BC */ + u32 exbct; + u32 extct; +}; + +/* DBSC3 */ +struct r8a7791_dbsc3 { + u32 dummy0[3]; /* 0x00 .. 0x08 */ + u32 dbstate1; + u32 dbacen; + u32 dbrfen; + u32 dbcmd; + u32 dbwait; + u32 dbkind; + u32 dbconf0; + u32 dummy1[2]; /* 0x28 .. 0x2C */ + u32 dbphytype; + u32 dummy2[3]; /* 0x34 .. 0x3C */ + u32 dbtr0; + u32 dbtr1; + u32 dbtr2; + u32 dummy3; /* 0x4C */ + u32 dbtr3; + u32 dbtr4; + u32 dbtr5; + u32 dbtr6; + u32 dbtr7; + u32 dbtr8; + u32 dbtr9; + u32 dbtr10; + u32 dbtr11; + u32 dbtr12; + u32 dbtr13; + u32 dbtr14; + u32 dbtr15; + u32 dbtr16; + u32 dbtr17; + u32 dbtr18; + u32 dbtr19; + u32 dummy4[7]; /* 0x94 .. 0xAC */ + u32 dbbl; + u32 dummy5[3]; /* 0xB4 .. 0xBC */ + u32 dbadj0; + u32 dummy6; /* 0xC4 */ + u32 dbadj2; + u32 dummy7[5]; /* 0xCC .. 0xDC */ + u32 dbrfcnf0; + u32 dbrfcnf1; + u32 dbrfcnf2; + u32 dummy8[2]; /* 0xEC .. 0xF0 */ + u32 dbcalcnf; + u32 dbcaltr; + u32 dummy9; /* 0xFC */ + u32 dbrnk0; + u32 dummy10[31]; /* 0x104 .. 0x17C */ + u32 dbpdncnf; + u32 dummy11[47]; /* 0x184 ..0x23C */ + u32 dbdfistat; + u32 dbdficnt; + u32 dummy12[14]; /* 0x248 .. 0x27C */ + u32 dbpdlck; + u32 dummy13[3]; /* 0x284 .. 0x28C */ + u32 dbpdrga; + u32 dummy14[3]; /* 0x294 .. 0x29C */ + u32 dbpdrgd; + u32 dummy15[24]; /* 0x2A4 .. 0x300 */ + u32 dbbs0cnt1; + u32 dummy16[30]; /* 0x308 .. 0x37C */ + u32 dbwt0cnf0; + u32 dbwt0cnf1; + u32 dbwt0cnf2; + u32 dbwt0cnf3; + u32 dbwt0cnf4; +}; + +/* GPIO */ +struct r8a7791_gpio { + u32 iointsel; + u32 inoutsel; + u32 outdt; + u32 indt; + u32 intdt; + u32 intclr; + u32 intmsk; + u32 posneg; + u32 edglevel; + u32 filonoff; + u32 intmsks; + u32 mskclrs; + u32 outdtsel; + u32 outdth; + u32 outdtl; + u32 bothedge; +}; + +/* S3C(QoS) */ +struct r8a7791_s3c { + u32 s3cexcladdmsk; + u32 s3cexclidmsk; + u32 s3cadsplcr; + u32 s3cmaar; + u32 dummy0; /* 0x10 */ + u32 s3crorr; + u32 s3cworr; + u32 s3carcr22; + u32 dummy1[2]; /* 0x20 .. 0x24 */ + u32 s3cmctr; + u32 dummy2; /* 0x2C */ + u32 cconf0; + u32 cconf1; + u32 cconf2; + u32 cconf3; +}; + +struct r8a7791_s3c_qos { + u32 s3cqos0; + u32 s3cqos1; + u32 s3cqos2; + u32 s3cqos3; + u32 s3cqos4; + u32 s3cqos5; + u32 s3cqos6; + u32 s3cqos7; + u32 s3cqos8; +}; + +/* DBSC(QoS) */ +struct r8a7791_dbsc3_qos { + u32 dblgcnt; + u32 dbtmval0; + u32 dbtmval1; + u32 dbtmval2; + u32 dbtmval3; + u32 dbrqctr; + u32 dbthres0; + u32 dbthres1; + u32 dbthres2; + u32 dummy0; /* 0x24 */ + u32 dblgqon; +}; + +/* MXI(QoS) */ +struct r8a7791_mxi { + u32 mxsaar0; + u32 mxsaar1; + u32 dummy0[8]; /* 0x08 .. 0x24 */ + u32 mxs3cracr; + u32 dummy1[3]; /* 0x2C .. 0x34 */ + u32 mxs3cwacr; + u32 dummy2; /* 0x3C */ + u32 mxrtcr; + u32 mxwtcr; +}; + +struct r8a7791_mxi_qos { + u32 vspdu0; + u32 vspdu1; + u32 du0; + u32 du1; +}; + +/* AXI(QoS) */ +struct r8a7791_axi_qos { + u32 qosconf; + u32 qosctset0; + u32 qosctset1; + u32 qosctset2; + u32 qosctset3; + u32 qosreqctr; + u32 qosthres0; + u32 qosthres1; + u32 qosthres2; + u32 qosqon; +}; + +#endif + +#endif /* __ASM_ARCH_R8A7791_H */ diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h index ac17561..2382565 100644 --- a/arch/arm/include/asm/arch-rmobile/rmobile.h +++ b/arch/arm/include/asm/arch-rmobile/rmobile.h @@ -6,6 +6,10 @@ #include <asm/arch/sh73a0.h> #elif defined(CONFIG_R8A7740) #include <asm/arch/r8a7740.h> +#elif defined(CONFIG_R8A7790) +#include <asm/arch/r8a7790.h> +#elif defined(CONFIG_R8A7791) +#include <asm/arch/r8a7791.h> #else #error "SOC Name not defined" #endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h index 55ff10b..dd473c8 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h +++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h @@ -55,7 +55,7 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width); -static inline unsigned int s5p_mmc_init(int index, int bus_width) +static inline int s5p_mmc_init(int index, int bus_width) { unsigned int base = samsung_get_base_mmc() + (S5P_MMC_DEV_OFFSET * index); diff --git a/arch/arm/include/asm/arch-socfpga/freeze_controller.h b/arch/arm/include/asm/arch-socfpga/freeze_controller.h new file mode 100644 index 0000000..120f20e --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/freeze_controller.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FREEZE_CONTROLLER_H_ +#define _FREEZE_CONTROLLER_H_ + +struct socfpga_freeze_controller { + u32 vioctrl; + u32 padding[3]; + u32 hioctrl; + u32 src; + u32 hwctrl; +}; + +#define FREEZE_CHANNEL_NUM (4) + +typedef enum { + FREEZE_CTRL_FROZEN = 0, + FREEZE_CTRL_THAWED = 1 +} FREEZE_CTRL_CHAN_STATE; + +#define SYSMGR_FRZCTRL_ADDRESS 0x40 +#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0 +#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1 +#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010 +#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008 +#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004 +#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002 +#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010 +#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008 +#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004 +#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002 +#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080 +#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040 +#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100 +#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1 +#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2 + +void sys_mgr_frzctrl_freeze_req(void); +void sys_mgr_frzctrl_thaw_req(void); + +#endif /* _FREEZE_CONTROLLER_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index c3174bd..e7d0fd4 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -113,9 +113,9 @@ void reset_set_enable(enum periph_id periph_id, int enable); enum crc_reset_id { /* Things we can hold in reset for each CPU */ crc_rst_cpu = 1, - crc_rst_de = 1 << 2, /* What is de? */ - crc_rst_watchdog = 1 << 3, - crc_rst_debug = 1 << 4, + crc_rst_de = 1 << 4, /* What is de? */ + crc_rst_watchdog = 1 << 8, + crc_rst_debug = 1 << 12, }; /** diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 25d1fc4..e99f681 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -65,6 +65,7 @@ enum { SKU_ID_T25E = 0x1c, SKU_ID_T33 = 0x80, SKU_ID_T30 = 0x81, /* Cardhu value */ + SKU_ID_TM30MQS_P_A3 = 0xb1, SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */ SKU_ID_T114_1 = 0x01, }; diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 1b94a99..45668ca 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -14,11 +14,15 @@ #define _EMIF_H_ #include <asm/types.h> #include <common.h> +#include <asm/io.h> /* Base address */ #define EMIF1_BASE 0x4c000000 #define EMIF2_BASE 0x4d000000 +#define EMIF_4D 0x4 +#define EMIF_4D5 0x5 + /* Registers shifts, masks and values */ /* EMIF_MOD_ID_REV */ @@ -581,7 +585,6 @@ (0xFF << EMIF_SYS_ADDR_SHIFT)) #define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 -#define EMIF_EXT_PHY_CTRL_CONST_REG 0x14 /* Reg mapping structure */ struct emif_reg_struct { @@ -641,7 +644,9 @@ struct emif_reg_struct { u32 emif_ddr_phy_ctrl_2; u32 padding7[12]; u32 emif_rd_wr_exec_thresh; - u32 padding8[55]; + u32 padding8[7]; + u32 emif_ddr_phy_status[21]; + u32 padding9[27]; u32 emif_ddr_ext_phy_ctrl_1; u32 emif_ddr_ext_phy_ctrl_1_shdw; u32 emif_ddr_ext_phy_ctrl_2; @@ -690,6 +695,9 @@ struct emif_reg_struct { u32 emif_ddr_ext_phy_ctrl_23_shdw; u32 emif_ddr_ext_phy_ctrl_24; u32 emif_ddr_ext_phy_ctrl_24_shdw; + u32 padding[22]; + u32 emif_ddr_fifo_misaligned_clear_1; + u32 emif_ddr_fifo_misaligned_clear_2; }; struct dmm_lisa_map_regs { @@ -1139,6 +1147,33 @@ struct lpddr2_mr_regs { s8 mr16; }; +struct read_write_regs { + u32 read_reg; + u32 write_reg; +}; + +static inline u32 get_emif_rev(u32 base) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK) + >> EMIF_REG_MAJOR_REVISION_SHIFT; +} + +/* + * Get SDRAM type connected to EMIF. + * Assuming similar SDRAM parts are connected to both EMIF's + * which is typically the case. So it is sufficient to get + * SDRAM type from EMIF1. + */ +static inline u32 emif_sdram_type(void) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + + return (readl(&emif->emif_sdram_config) & + EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; +} + /* assert macros */ #if defined(DEBUG) #define emif_assert(c) ({ if (!(c)) for (;;); }) @@ -1167,4 +1202,5 @@ extern u32 *const T_den; void config_data_eye_leveling_samples(u32 emif_base); u32 emif_sdram_type(void); +const struct read_write_regs *get_bug_regs(u32 *iterations); #endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 8a395e8..a78f990 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -226,6 +226,7 @@ struct prcm_regs { u32 cm_l3init_hsusbotg_clkctrl; u32 cm_l3init_hsusbtll_clkctrl; u32 cm_l3init_p1500_clkctrl; + u32 cm_l3init_sata_clkctrl; u32 cm_l3init_fsusb_clkctrl; u32 cm_l3init_ocp2scp1_clkctrl; u32 cm_l3init_ocp2scp3_clkctrl; @@ -366,6 +367,7 @@ struct omap_sys_ctrl_regs { u32 control_ldosram_mpu_voltage_ctrl; u32 control_ldosram_core_voltage_ctrl; u32 control_usbotghs_ctrl; + u32 control_phy_power_sata; u32 control_padconf_core_base; u32 control_paconf_global; u32 control_paconf_mode; @@ -605,6 +607,14 @@ static inline u8 is_omap54xx(void) extern u32 *const omap_si_rev; return ((*omap_si_rev & 0xFF000000) == OMAP54xx); } + +#define DRA7XX 0x07000000 + +static inline u8 is_dra7xx(void) +{ + extern u32 *const omap_si_rev; + return ((*omap_si_rev & 0xFF000000) == DRA7XX); +} #endif /* diff --git a/arch/arm/include/asm/arch-am33xx/elm.h b/arch/arm/include/asm/omap_elm.h index 45454ea..45454ea 100644 --- a/arch/arm/include/asm/arch-am33xx/elm.h +++ b/arch/arm/include/asm/omap_elm.h diff --git a/arch/arm/include/asm/omap_gpmc.h b/arch/arm/include/asm/omap_gpmc.h index dd40cb6..d4143ec 100644 --- a/arch/arm/include/asm/omap_gpmc.h +++ b/arch/arm/include/asm/omap_gpmc.h @@ -68,4 +68,20 @@ } #endif +enum omap_ecc { + /* 1-bit ECC calculation by Software, Error detection by Software */ + OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */ + /* 1-bit ECC calculation by GPMC, Error detection by Software */ + /* ECC layout compatible to legacy ROMCODE. */ + OMAP_ECC_HAM1_CODE_HW, + /* 4-bit ECC calculation by GPMC, Error detection by Software */ + OMAP_ECC_BCH4_CODE_HW_DETECTION_SW, + /* 4-bit ECC calculation by GPMC, Error detection by ELM */ + OMAP_ECC_BCH4_CODE_HW, + /* 8-bit ECC calculation by GPMC, Error detection by Software */ + OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, + /* 8-bit ECC calculation by GPMC, Error detection by ELM */ + OMAP_ECC_BCH8_CODE_HW, +}; + #endif /* __ASM_OMAP_GPMC_H */ diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 34f50b0..9c72a53 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -435,7 +435,6 @@ void board_init_f(ulong bootflag) addr_sp += 128; /* leave 32 words for abort-stack */ gd->irq_sp = addr_sp; #endif - interrupt_init(); debug("New Stack Pointer is: %08lx\n", addr_sp); @@ -637,6 +636,8 @@ void board_init_r(gd_t *id, ulong dest_addr) misc_init_r(); #endif + /* set up exceptions */ + interrupt_init(); /* enable exceptions */ enable_interrupts(); diff --git a/arch/blackfin/cpu/.gitignore b/arch/blackfin/cpu/.gitignore index ba986d8..3df1fa2 100644 --- a/arch/blackfin/cpu/.gitignore +++ b/arch/blackfin/cpu/.gitignore @@ -1,4 +1,2 @@ -bootrom-asm-offsets.[chs] - init.lds init.elf diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile index 243dc22..a61594a 100644 --- a/arch/blackfin/cpu/Makefile +++ b/arch/blackfin/cpu/Makefile @@ -23,16 +23,6 @@ obj-y += traps.o extra-y += check_initcode -extra-y += bootrom-asm-offsets.h -$(obj)bootrom-asm-offsets.c: bootrom-asm-offsets.c.in bootrom-asm-offsets.awk - echo '#include <asm/mach-common/bits/bootrom.h>' | $(CPP) $(CPPFLAGS) - | gawk -f ./bootrom-asm-offsets.awk > $@.tmp - mv $@.tmp $@ -$(obj)bootrom-asm-offsets.s: $(obj)bootrom-asm-offsets.c - $(CC) $(CFLAGS) -S $^ -o $@.tmp - mv $@.tmp $@ -$(obj)bootrom-asm-offsets.h: $(obj)bootrom-asm-offsets.s - sed -ne "/^->/{s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; s:->::; p;}" $^ > $@ - # make sure our initcode (which goes into LDR) does not # have relocs or external references $(obj)initcode.o: CFLAGS += -fno-function-sections -fno-data-sections diff --git a/arch/blackfin/cpu/bootrom-asm-offsets.awk b/arch/blackfin/cpu/bootrom-asm-offsets.awk deleted file mode 100755 index 1d61824..0000000 --- a/arch/blackfin/cpu/bootrom-asm-offsets.awk +++ /dev/null @@ -1,41 +0,0 @@ -#!/usr/bin/gawk -f -BEGIN { - print "/* DO NOT EDIT: AUTOMATICALLY GENERATED" - print " * Input files: bootrom-asm-offsets.awk bootrom-asm-offsets.c.in" - print " * DO NOT EDIT: AUTOMATICALLY GENERATED" - print " */" - print "" - system("cat bootrom-asm-offsets.c.in") - print "{" -} - -{ - /* find a structure definition */ - if ($0 ~ /typedef struct .* {/) { - delete members; - i = 0; - - /* extract each member of the structure */ - while (1) { - getline - if ($1 == "}") - break; - gsub(/[*;]/, ""); - members[i++] = $NF; - } - - /* grab the structure's name */ - struct = $NF; - sub(/;$/, "", struct); - - /* output the DEFINE() macros */ - while (i-- > 0) - print "\tDEFINE(" struct ", " members[i] ");" - print "" - } -} - -END { - print "\treturn 0;" - print "}" -} diff --git a/arch/blackfin/cpu/bootrom-asm-offsets.c.in b/arch/blackfin/cpu/bootrom-asm-offsets.c.in deleted file mode 100644 index 64c2f24..0000000 --- a/arch/blackfin/cpu/bootrom-asm-offsets.c.in +++ /dev/null @@ -1,12 +0,0 @@ -/* A little trick taken from the kernel asm-offsets.h where we convert - * the C structures automatically into a bunch of defines for use in - * the assembly files. - */ - -#include <linux/stddef.h> -#include <asm/mach-common/bits/bootrom.h> - -#define _DEFINE(sym, val) asm volatile("\n->" #sym " %0 " #val : : "i" (val)) -#define DEFINE(s, m) _DEFINE(offset_##s##_##m, offsetof(s, m)) - -int main(int argc, char * const argv[]) diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c index 5e9c68a..86da706 100644 --- a/arch/blackfin/cpu/gpio.c +++ b/arch/blackfin/cpu/gpio.c @@ -12,7 +12,7 @@ #include <asm/gpio.h> #include <asm/portmux.h> -#ifdef CONFIG_ADI_GPIO1 +#ifndef CONFIG_ADI_GPIO2 #if ANOMALY_05000311 || ANOMALY_05000323 enum { AWA_data = SYSCR, diff --git a/arch/blackfin/cpu/os_log.c b/arch/blackfin/cpu/os_log.c index e1c8e29..2092d9e 100644 --- a/arch/blackfin/cpu/os_log.c +++ b/arch/blackfin/cpu/os_log.c @@ -12,12 +12,12 @@ #define OS_LOG_MAGIC_ADDR ((unsigned long *)0x4f0) #define OS_LOG_PTR_ADDR ((char **)0x4f4) -bool bfin_os_log_check(void) +int bfin_os_log_check(void) { if (*OS_LOG_MAGIC_ADDR != OS_LOG_MAGIC) - return false; + return 0; *OS_LOG_MAGIC_ADDR = 0; - return true; + return 1; } void bfin_os_log_dump(void) diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h index ab31dcb..8ea8cde 100644 --- a/arch/blackfin/include/asm/blackfin_local.h +++ b/arch/blackfin/include/asm/blackfin_local.h @@ -51,7 +51,7 @@ extern u_long get_dclk(void); # define bfin_revid() (bfin_read_CHIPID() >> 28) -extern bool bfin_os_log_check(void); +extern int bfin_os_log_check(void); extern void bfin_os_log_dump(void); extern void blackfin_icache_flush_range(const void *, const void *); diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h index 376ec02..6ebcf01 100644 --- a/arch/blackfin/include/asm/gpio.h +++ b/arch/blackfin/include/asm/gpio.h @@ -72,7 +72,7 @@ #ifndef __ASSEMBLY__ -#ifdef CONFIG_ADI_GPIO1 +#ifndef CONFIG_ADI_GPIO2 void set_gpio_dir(unsigned, unsigned short); void set_gpio_inen(unsigned, unsigned short); void set_gpio_polar(unsigned, unsigned short); diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds index 3e6204d..fdad207 100644 --- a/arch/microblaze/cpu/u-boot.lds +++ b/arch/microblaze/cpu/u-boot.lds @@ -30,7 +30,7 @@ SECTIONS { __data_start = .; #ifdef CONFIG_OF_EMBED - dts/libdts.o (.data) + dts/built-in.o (.data) #endif *(.data) __data_end = .; diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 12f656c..22bd844 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -20,15 +20,6 @@ #define RA t9 -/* - * 16kB is the maximum size of instruction and data caches on MIPS 4K, - * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. - * - * Note that the above size is the maximum size of primary cache. U-Boot - * doesn't have L2 cache support for now. - */ -#define MIPS_MAX_CACHE_SIZE 0x10000 - #define INDEX_BASE CKSEG0 .macro cache_op op addr @@ -126,12 +117,85 @@ LEAF(mips_init_dcache) */ NESTED(mips_cache_reset, 0, ra) move RA, ra - li t2, CONFIG_SYS_ICACHE_SIZE - li t3, CONFIG_SYS_DCACHE_SIZE + +#if !defined(CONFIG_SYS_ICACHE_SIZE) || !defined(CONFIG_SYS_DCACHE_SIZE) || \ + !defined(CONFIG_SYS_CACHELINE_SIZE) + /* read Config1 for use below */ + mfc0 t5, CP0_CONFIG, 1 +#endif + +#ifdef CONFIG_SYS_CACHELINE_SIZE + li t7, CONFIG_SYS_CACHELINE_SIZE li t8, CONFIG_SYS_CACHELINE_SIZE +#else + /* Detect I-cache line size. */ + srl t8, t5, MIPS_CONF1_IL_SHIFT + andi t8, t8, (MIPS_CONF1_IL >> MIPS_CONF1_IL_SHIFT) + beqz t8, 1f + li t6, 2 + sllv t8, t6, t8 - li v0, MIPS_MAX_CACHE_SIZE +1: /* Detect D-cache line size. */ + srl t7, t5, MIPS_CONF1_DL_SHIFT + andi t7, t7, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT) + beqz t7, 1f + li t6, 2 + sllv t7, t6, t7 +1: +#endif +#ifdef CONFIG_SYS_ICACHE_SIZE + li t2, CONFIG_SYS_ICACHE_SIZE +#else + /* Detect I-cache size. */ + srl t6, t5, MIPS_CONF1_IS_SHIFT + andi t6, t6, (MIPS_CONF1_IS >> MIPS_CONF1_IS_SHIFT) + li t4, 32 + xori t2, t6, 0x7 + beqz t2, 1f + addi t6, t6, 1 + sllv t4, t4, t6 +1: /* At this point t4 == I-cache sets. */ + mul t2, t4, t8 + srl t6, t5, MIPS_CONF1_IA_SHIFT + andi t6, t6, (MIPS_CONF1_IA >> MIPS_CONF1_IA_SHIFT) + addi t6, t6, 1 + /* At this point t6 == I-cache ways. */ + mul t2, t2, t6 +#endif + +#ifdef CONFIG_SYS_DCACHE_SIZE + li t3, CONFIG_SYS_DCACHE_SIZE +#else + /* Detect D-cache size. */ + srl t6, t5, MIPS_CONF1_DS_SHIFT + andi t6, t6, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT) + li t4, 32 + xori t3, t6, 0x7 + beqz t3, 1f + addi t6, t6, 1 + sllv t4, t4, t6 +1: /* At this point t4 == I-cache sets. */ + mul t3, t4, t7 + srl t6, t5, MIPS_CONF1_DA_SHIFT + andi t6, t6, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT) + addi t6, t6, 1 + /* At this point t6 == I-cache ways. */ + mul t3, t3, t6 +#endif + + /* Determine the largest L1 cache size */ +#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE) +#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE + li v0, CONFIG_SYS_ICACHE_SIZE +#else + li v0, CONFIG_SYS_DCACHE_SIZE +#endif +#else + move v0, t2 + sltu t1, t2, t3 + movn v0, t3, t1 +#endif /* * Now clear that much memory starting from zero. */ @@ -163,7 +227,7 @@ NESTED(mips_cache_reset, 0, ra) * then initialize D-cache. */ move a1, t3 - move a2, t8 + move a2, t7 PTR_LA v1, mips_init_dcache jalr v1 diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c index 28d5c45..278865b 100644 --- a/arch/mips/cpu/mips32/cpu.c +++ b/arch/mips/cpu/mips32/cpu.c @@ -34,28 +34,89 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#ifdef CONFIG_SYS_CACHELINE_SIZE + +static inline unsigned long icache_line_size(void) +{ + return CONFIG_SYS_CACHELINE_SIZE; +} + +static inline unsigned long dcache_line_size(void) +{ + return CONFIG_SYS_CACHELINE_SIZE; +} + +#else /* !CONFIG_SYS_CACHELINE_SIZE */ + +static inline unsigned long icache_line_size(void) +{ + unsigned long conf1, il; + conf1 = read_c0_config1(); + il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT; + if (!il) + return 0; + return 2 << il; +} + +static inline unsigned long dcache_line_size(void) +{ + unsigned long conf1, dl; + conf1 = read_c0_config1(); + dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT; + if (!dl) + return 0; + return 2 << dl; +} + +#endif /* !CONFIG_SYS_CACHELINE_SIZE */ + void flush_cache(ulong start_addr, ulong size) { - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + unsigned long ilsize = icache_line_size(); + unsigned long dlsize = dcache_line_size(); + unsigned long addr, aend; /* aend will be miscalculated when size is zero, so we return here */ if (size == 0) return; + addr = start_addr & ~(dlsize - 1); + aend = (start_addr + size - 1) & ~(dlsize - 1); + + if (ilsize == dlsize) { + /* flush I-cache & D-cache simultaneously */ + while (1) { + cache_op(HIT_WRITEBACK_INV_D, addr); + cache_op(HIT_INVALIDATE_I, addr); + if (addr == aend) + break; + addr += dlsize; + } + return; + } + + /* flush D-cache */ while (1) { cache_op(HIT_WRITEBACK_INV_D, addr); + if (addr == aend) + break; + addr += dlsize; + } + + /* flush I-cache */ + addr = start_addr & ~(ilsize - 1); + aend = (start_addr + size - 1) & ~(ilsize - 1); + while (1) { cache_op(HIT_INVALIDATE_I, addr); if (addr == aend) break; - addr += lsize; + addr += ilsize; } } void flush_dcache_range(ulong start_addr, ulong stop) { - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long lsize = dcache_line_size(); unsigned long addr = start_addr & ~(lsize - 1); unsigned long aend = (stop - 1) & ~(lsize - 1); @@ -69,7 +130,7 @@ void flush_dcache_range(ulong start_addr, ulong stop) void invalidate_dcache_range(ulong start_addr, ulong stop) { - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long lsize = dcache_line_size(); unsigned long addr = start_addr & ~(lsize - 1); unsigned long aend = (stop - 1) & ~(lsize - 1); diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 70ad198..68e59b5 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -51,7 +51,7 @@ _start: */ .word CONFIG_SYS_XWAY_EBU_BOOTCFG .word 0x0 -#elif defined(CONFIG_QEMU_MALTA) +#elif defined(CONFIG_MALTA) /* * Linux expects the Board ID here. */ diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index d4d44a2..9e7c045 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -1,23 +1,67 @@ /* * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> + * Copyright (C) 2013 Imagination Technologies * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _MIPS_ASM_MALTA_H #define _MIPS_ASM_MALTA_H -#define MALTA_IO_PORT_BASE 0x18000000 +#define MALTA_GT_BASE 0x1be00000 +#define MALTA_GT_PCIIO_BASE 0x18000000 +#define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8) -#define MALTA_UART_BASE (MALTA_IO_PORT_BASE + 0x3f8) +#define MALTA_MSC01_BIU_BASE 0x1bc80000 +#define MALTA_MSC01_PCI_BASE 0x1bd00000 +#define MALTA_MSC01_PBC_BASE 0x1bd40000 +#define MALTA_MSC01_IP1_BASE 0x1bc00000 +#define MALTA_MSC01_IP1_SIZE 0x00400000 +#define MALTA_MSC01_IP2_BASE1 0x10000000 +#define MALTA_MSC01_IP2_SIZE1 0x08000000 +#define MALTA_MSC01_IP2_BASE2 0x18000000 +#define MALTA_MSC01_IP2_SIZE2 0x04000000 +#define MALTA_MSC01_IP3_BASE 0x1c000000 +#define MALTA_MSC01_IP3_SIZE 0x04000000 +#define MALTA_MSC01_PCIMEM_BASE 0x10000000 +#define MALTA_MSC01_PCIMEM_SIZE 0x10000000 +#define MALTA_MSC01_PCIMEM_MAP 0x10000000 +#define MALTA_MSC01_PCIIO_BASE 0x1b000000 +#define MALTA_MSC01_PCIIO_SIZE 0x00800000 +#define MALTA_MSC01_PCIIO_MAP 0x00000000 +#define MALTA_MSC01_UART0_BASE (MALTA_MSC01_PCIIO_BASE + 0x3f8) -#define MALTA_GT_BASE 0x1be00000 +#define MALTA_ASCIIWORD 0x1f000410 +#define MALTA_ASCIIPOS0 0x1f000418 +#define MALTA_ASCIIPOS1 0x1f000420 +#define MALTA_ASCIIPOS2 0x1f000428 +#define MALTA_ASCIIPOS3 0x1f000430 +#define MALTA_ASCIIPOS4 0x1f000438 +#define MALTA_ASCIIPOS5 0x1f000440 +#define MALTA_ASCIIPOS6 0x1f000448 +#define MALTA_ASCIIPOS7 0x1f000450 -#define MALTA_RESET_BASE 0x1f000500 -#define GORESET 0x42 +#define MALTA_RESET_BASE 0x1f000500 +#define GORESET 0x42 -#define MALTA_FLASH_BASE 0x1fc00000 +#define MALTA_FLASH_BASE 0x1e000000 + +#define MALTA_REVISION 0x1fc00010 +#define MALTA_REVISION_CORID_SHF 10 +#define MALTA_REVISION_CORID_MSK (0x3f << MALTA_REVISION_CORID_SHF) +#define MALTA_REVISION_CORID_CORE_LV 1 +#define MALTA_REVISION_CORID_CORE_FPGA6 14 + +#define PCI_CFG_PIIX4_PIRQRCA 0x60 +#define PCI_CFG_PIIX4_PIRQRCB 0x61 +#define PCI_CFG_PIIX4_PIRQRCC 0x62 +#define PCI_CFG_PIIX4_PIRQRCD 0x63 +#define PCI_CFG_PIIX4_SERIRQC 0x64 +#define PCI_CFG_PIIX4_GENCFG 0xb0 + +#define PCI_CFG_PIIX4_SERIRQC_EN (1 << 7) +#define PCI_CFG_PIIX4_SERIRQC_CONT (1 << 6) + +#define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16) #endif /* _MIPS_ASM_MALTA_H */ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index be7e5c6..3571e4f 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -494,11 +494,17 @@ #define MIPS_CONF1_PC (_ULCAST_(1) << 4) #define MIPS_CONF1_MD (_ULCAST_(1) << 5) #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) +#define MIPS_CONF1_DA_SHIFT 7 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) +#define MIPS_CONF1_DL_SHIFT 10 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) +#define MIPS_CONF1_DS_SHIFT 13 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) +#define MIPS_CONF1_IA_SHIFT 16 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) +#define MIPS_CONF1_IL_SHIFT 19 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) +#define MIPS_CONF1_IS_SHIFT 22 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index 66340ea..71bb0d2 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -17,10 +17,10 @@ DECLARE_GLOBAL_DATA_PTR; #define LINUX_MAX_ENVS 256 #define LINUX_MAX_ARGS 256 -#if defined(CONFIG_QEMU_MALTA) -#define mips_boot_qemu_malta 1 +#if defined(CONFIG_MALTA) +#define mips_boot_malta 1 #else -#define mips_boot_qemu_malta 0 +#define mips_boot_malta 0 #endif static int linux_argc; @@ -139,7 +139,7 @@ static void linux_env_set(const char *env_name, const char *env_val) strcpy(linux_env_p, env_name); linux_env_p += strlen(env_name); - if (mips_boot_qemu_malta) { + if (mips_boot_malta) { linux_env_p++; linux_env[++linux_env_idx] = linux_env_p; } else { @@ -196,8 +196,10 @@ static void boot_prep_linux(bootm_headers_t *images) if (cp) linux_env_set("eth1addr", cp); - if (mips_boot_qemu_malta) - linux_env_set("modetty0", "38400n8r"); + if (mips_boot_malta) { + sprintf(env_buf, "%un8r", gd->baudrate); + linux_env_set("modetty0", env_buf); + } } static void boot_jump_linux(bootm_headers_t *images) @@ -210,7 +212,7 @@ static void boot_jump_linux(bootm_headers_t *images) bootstage_mark(BOOTSTAGE_ID_RUN_OS); - if (mips_boot_qemu_malta) + if (mips_boot_malta) linux_extra = gd->ram_size; /* we assume that the kernel is in place */ diff --git a/arch/powerpc/cpu/Makefile b/arch/powerpc/cpu/Makefile new file mode 100644 index 0000000..d630abe --- /dev/null +++ b/arch/powerpc/cpu/Makefile @@ -0,0 +1,3 @@ +ifneq ($(filter mpc83xx mpc85xx mpc86xx,$(CPU)),) +obj-y += mpc8xxx/ +endif diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile index f770350..a4934ef 100644 --- a/arch/powerpc/cpu/mpc512x/Makefile +++ b/arch/powerpc/cpu/mpc512x/Makefile @@ -4,8 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -$(shell mkdir -p $(OBJTREE)/board/freescale/common) - extra-y = start.o obj-y := cpu.o obj-y += traps.o diff --git a/arch/powerpc/cpu/mpc824x/.gitignore b/arch/powerpc/cpu/mpc824x/.gitignore deleted file mode 100644 index 2d79931..0000000 --- a/arch/powerpc/cpu/mpc824x/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/bedbug_603e.c diff --git a/arch/powerpc/cpu/mpc824x/Makefile b/arch/powerpc/cpu/mpc824x/Makefile index 67b0d17..2c8be92 100644 --- a/arch/powerpc/cpu/mpc824x/Makefile +++ b/arch/powerpc/cpu/mpc824x/Makefile @@ -5,15 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)drivers/epic $(obj)drivers/i2c) -endif - extra-y = start.o obj-y = traps.o cpu.o cpu_init.o interrupts.o speed.o \ drivers/epic/epic1.o drivers/i2c/i2c.o pci.o -obj-y += bedbug_603e.o - -SRCS += $(obj)bedbug_603e.c -$(obj)bedbug_603e.c: - ln -sf $(src)../mpc8260/bedbug_603e.c $(obj)bedbug_603e.c +obj-y += ../mpc8260/bedbug_603e.o diff --git a/arch/powerpc/cpu/mpc824x/cpu_init.c b/arch/powerpc/cpu/mpc824x/cpu_init.c index 37d796e..47ac18e 100644 --- a/arch/powerpc/cpu/mpc824x/cpu_init.c +++ b/arch/powerpc/cpu/mpc824x/cpu_init.c @@ -52,7 +52,7 @@ cpu_init_f (void) CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/ /* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/ -#if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62) +#if defined(CONFIG_MUSENKI) /* Why is this here, you ask? Try, just try setting 0x8000 * in PCIACR with CONFIG_WRITE_HALFWORD() * this one was a stumper, and we are annoyed @@ -142,9 +142,7 @@ cpu_init_f (void) CONFIG_READ_WORD(PICR2, val); val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/ -#ifndef CONFIG_PN62 val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/ -#endif CONFIG_WRITE_WORD(PICR2, val); CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR); @@ -186,7 +184,7 @@ cpu_init_f (void) * should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if * its not set, we define it to zero in this file */ -#if defined(CONFIG_CU824) || defined(CONFIG_PN62) +#if defined(CONFIG_CU824) CONFIG_WRITE_WORD(MCCR4, (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index b7142f0..cf91162 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -38,21 +38,9 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o # Stub implementations of cache management functions for USB obj-y += cache.o -ifdef CONFIG_FSL_DDR2 -obj-$(CONFIG_MPC8349) += ddr-gen2.o -SRCS += $(obj)ddr-gen2.c -else +ifndef CONFIG_SYS_FSL_DDRC_GEN2 obj-y += spd_sdram.o endif -obj-$(CONFIG_FSL_DDR2) += law.o +obj-$(CONFIG_SYS_FSL_DDR2) += law.o endif # not minimal - -$(obj)ddr-gen1.c: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen1.c $(obj)ddr-gen1.c - -$(obj)ddr-gen2.c: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen2.c $(obj)ddr-gen2.c - -$(obj)ddr-gen3.c: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen3.c $(obj)ddr-gen3.c diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c index 120b37b..985a024 100644 --- a/arch/powerpc/cpu/mpc83xx/ecc.c +++ b/arch/powerpc/cpu/mpc83xx/ecc.c @@ -15,8 +15,8 @@ void ecc_print_status(void) { immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; -#ifdef CONFIG_FSL_DDR2 - ccsr_ddr_t *ddr = &immap->ddr; +#ifdef CONFIG_SYS_FSL_DDR2 + struct ccsr_ddr __iomem *ddr = &immap->ddr; #else ddr83xx_t *ddr = &immap->ddr; #endif @@ -99,8 +99,8 @@ void ecc_print_status(void) int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; -#ifdef CONFIG_FSL_DDR2 - ccsr_ddr_t *ddr = &immap->ddr; +#ifdef CONFIG_SYS_FSL_DDR2 + struct ccsr_ddr __iomem *ddr = &immap->ddr; #else ddr83xx_t *ddr = &immap->ddr; #endif diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 50ddb50..ef7637a 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -29,48 +29,6 @@ obj-$(CONFIG_MP) += release.o obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o obj-$(CONFIG_CPM2) += commproc.o -# supports ddr1 -obj-$(CONFIG_MPC8540) += ddr-gen1.o -obj-$(CONFIG_MPC8560) += ddr-gen1.o -obj-$(CONFIG_MPC8541) += ddr-gen1.o -obj-$(CONFIG_MPC8555) += ddr-gen1.o - -# supports ddr1/2 -obj-$(CONFIG_MPC8548) += ddr-gen2.o -obj-$(CONFIG_MPC8568) += ddr-gen2.o -obj-$(CONFIG_MPC8544) += ddr-gen2.o - -# supports ddr1/2/3 -obj-$(CONFIG_PPC_C29X) += ddr-gen3.o -obj-$(CONFIG_MPC8572) += ddr-gen3.o -obj-$(CONFIG_MPC8536) += ddr-gen3.o -obj-$(CONFIG_MPC8569) += ddr-gen3.o -obj-$(CONFIG_P1010) += ddr-gen3.o -obj-$(CONFIG_P1011) += ddr-gen3.o -obj-$(CONFIG_P1012) += ddr-gen3.o -obj-$(CONFIG_P1013) += ddr-gen3.o -obj-$(CONFIG_P1014) += ddr-gen3.o -obj-$(CONFIG_P1020) += ddr-gen3.o -obj-$(CONFIG_P1021) += ddr-gen3.o -obj-$(CONFIG_P1022) += ddr-gen3.o -obj-$(CONFIG_P1023) += ddr-gen3.o -obj-$(CONFIG_P1024) += ddr-gen3.o -obj-$(CONFIG_P1025) += ddr-gen3.o -obj-$(CONFIG_P2010) += ddr-gen3.o -obj-$(CONFIG_P2020) += ddr-gen3.o -obj-$(CONFIG_PPC_P2041) += ddr-gen3.o -obj-$(CONFIG_PPC_P3041) += ddr-gen3.o -obj-$(CONFIG_PPC_P4080) += ddr-gen3.o -obj-$(CONFIG_PPC_P5020) += ddr-gen3.o -obj-$(CONFIG_PPC_P5040) += ddr-gen3.o -obj-$(CONFIG_PPC_T4240) += ddr-gen3.o -obj-$(CONFIG_PPC_T4160) += ddr-gen3.o -obj-$(CONFIG_PPC_B4420) += ddr-gen3.o -obj-$(CONFIG_PPC_B4860) += ddr-gen3.o -obj-$(CONFIG_BSC9131) += ddr-gen3.o -obj-$(CONFIG_BSC9132) += ddr-gen3.o -obj-$(CONFIG_PPC_T1040) += ddr-gen3.o - obj-$(CONFIG_CPM2) += ether_fcc.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_FSL_CORENET) += liodn.o @@ -89,6 +47,12 @@ obj-$(CONFIG_PPC_T4160) += t4240_ids.o obj-$(CONFIG_PPC_B4420) += b4860_ids.o obj-$(CONFIG_PPC_B4860) += b4860_ids.o obj-$(CONFIG_PPC_T1040) += t1040_ids.o +obj-$(CONFIG_PPC_T1042) += t1040_ids.o +obj-$(CONFIG_PPC_T1020) += t1040_ids.o +obj-$(CONFIG_PPC_T1022) += t1040_ids.o +obj-$(CONFIG_PPC_T2080) += t2080_ids.o +obj-$(CONFIG_PPC_T2081) += t2080_ids.o + obj-$(CONFIG_QE) += qe_io.o obj-$(CONFIG_CPM2) += serial_scc.o @@ -128,6 +92,11 @@ obj-$(CONFIG_PPC_B4420) += b4860_serdes.o obj-$(CONFIG_PPC_B4860) += b4860_serdes.o obj-$(CONFIG_BSC9132) += bsc9132_serdes.o obj-$(CONFIG_PPC_T1040) += t1040_serdes.o +obj-$(CONFIG_PPC_T1042) += t1040_serdes.o +obj-$(CONFIG_PPC_T1020) += t1040_serdes.o +obj-$(CONFIG_PPC_T1022) += t1040_serdes.o +obj-$(CONFIG_PPC_T2080) += t2080_serdes.o +obj-$(CONFIG_PPC_T2081) += t2080_serdes.o obj-y += cpu.o obj-y += cpu_init.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 1a0196c..3e99b07 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -17,12 +17,12 @@ #include <asm/cache.h> #include <asm/io.h> #include <asm/mmu.h> -#include <asm/fsl_ifc.h> +#include <fsl_ifc.h> #include <asm/fsl_law.h> #include <asm/fsl_lbc.h> #include <post.h> #include <asm/processor.h> -#include <asm/fsl_ddr_sdram.h> +#include <fsl_ddr_sdram.h> DECLARE_GLOBAL_DATA_PTR; @@ -416,7 +416,7 @@ static void dump_spd_ddr_reg(void) int i, j, k, m; u8 *p_8; u32 *p_32; - ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; + struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS]; generic_spd_eeprom_t spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; @@ -453,21 +453,21 @@ static void dump_spd_ddr_reg(void) for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { switch (i) { case 0: - ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) case 1: - ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR; + ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) case 2: - ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR; + ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR; break; #endif -#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) case 3: - ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR; + ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR; break; #endif default: @@ -482,7 +482,7 @@ static void dump_spd_ddr_reg(void) for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); puts("\n"); - for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { + for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) { m = 0; printf("%6d (0x%04x)", k * 4, k * 4); for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c deleted file mode 100644 index 4dd8c0b..0000000 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/fsl_ddr_sdram.h> - -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) -#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL -#endif - -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num, int step) -{ - unsigned int i; - volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - - if (ctrl_num != 0) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i == 0) { - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_config, regs->cs[i].config); - - } else if (i == 1) { - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs1_config, regs->cs[i].config); - - } else if (i == 2) { - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs2_config, regs->cs[i].config); - - } else if (i == 3) { - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs3_config, regs->cs[i].config); - } - } - - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); -#if defined(CONFIG_MPC8555) || defined(CONFIG_MPC8541) - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); -#endif - - /* - * 200 painful micro-seconds must elapse between - * the DDR clock setup and the DDR config enable. - */ - udelay(200); - asm volatile("sync;isync"); - - out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); - - asm("sync;isync;msync"); - udelay(500); -} - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -/* - * Initialize all of memory for ECC, then enable errors. - */ - -void -ddr_enable_ecc(unsigned int dram_size) -{ - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); - - dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); - - /* - * Enable errors for ECC. - */ - debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); - ddr->err_disable = 0x00000000; - asm("sync;isync;msync"); - debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); -} - -#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */ diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c deleted file mode 100644 index 542bc84..0000000 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2008-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/fsl_ddr_sdram.h> - -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) -#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL -#endif - -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num, int step) -{ - unsigned int i; - ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - -#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx) - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint svr; -#endif - - if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - -#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 - /* - * Set the DDR IO receiver to an acceptable bias point. - * Fixed in Rev 2.1. - */ - svr = get_svr(); - if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) { - if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) == - SDRAM_CFG_SDRAM_TYPE_DDR2) - out_be32(&gur->ddrioovcr, 0x90000000); - else - out_be32(&gur->ddrioovcr, 0xA8000000); - } -#endif - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i == 0) { - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_config, regs->cs[i].config); - - } else if (i == 1) { - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs1_config, regs->cs[i].config); - - } else if (i == 2) { - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs2_config, regs->cs[i].config); - - } else if (i == 3) { - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs3_config, regs->cs[i].config); - } - } - - out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); - out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); - out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); - out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); - out_be32(&ddr->sdram_data_init, regs->ddr_data_init); - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); - out_be32(&ddr->init_addr, regs->ddr_init_addr); - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); - - /* - * 200 painful micro-seconds must elapse between - * the DDR clock setup and the DDR config enable. - */ - udelay(200); - asm volatile("sync;isync"); - - out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); - - /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ - while (in_be32(&ddr->sdram_cfg_2) & 0x10) { - udelay(10000); /* throttle polling rate */ - } -} diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c deleted file mode 100644 index 1be51d3..0000000 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ /dev/null @@ -1,464 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/fsl_ddr_sdram.h> -#include <asm/processor.h> - -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) -#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL -#endif - - -/* - * regs has the to-be-set values for DDR controller registers - * ctrl_num is the DDR controller number - * step: 0 goes through the initialization in one pass - * 1 sets registers and returns before enabling controller - * 2 resumes from step 1 and continues to initialize - * Dividing the initialization to two steps to deassert DDR reset signal - * to comply with JEDEC specs for RDIMMs. - */ -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num, int step) -{ - unsigned int i, bus_width; - volatile ccsr_ddr_t *ddr; - u32 temp_sdram_cfg; - u32 total_gb_size_per_controller; - int timeout; -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 - int timeout_save; - volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR; - unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t; - int csn = -1; -#endif - - switch (ctrl_num) { - case 0: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - break; -#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) - case 1: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR; - break; -#endif -#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) - case 2: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR; - break; -#endif -#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) - case 3: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR; - break; -#endif - default: - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - if (step == 2) - goto step2; - - if (regs->ddr_eor) - out_be32(&ddr->eor, regs->ddr_eor); -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 - debug("Workaround for ERRATUM_DDR111_DDR134\n"); - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; - cs_ea = regs->cs[i].bnds & 0xfff; - if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) { - csn = i; - csn_bnds_backup = regs->cs[i].bnds; - csn_bnds_t = (unsigned int *) ®s->cs[i].bnds; - if (cs_ea > 0xeff) - *csn_bnds_t = regs->cs[i].bnds + 0x01000000; - else - *csn_bnds_t = regs->cs[i].bnds + 0x01000100; - debug("Found cs%d_bns (0x%08x) covering 0xff000000, " - "change it to 0x%x\n", - csn, csn_bnds_backup, regs->cs[i].bnds); - break; - } - } -#endif - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i == 0) { - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_config, regs->cs[i].config); - out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); - - } else if (i == 1) { - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs1_config, regs->cs[i].config); - out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); - - } else if (i == 2) { - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs2_config, regs->cs[i].config); - out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); - - } else if (i == 3) { - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs3_config, regs->cs[i].config); - out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); - } - } - - out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); - out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); - out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); - out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); - out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); - out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); - out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); - out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); - out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); - out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); - out_be32(&ddr->sdram_data_init, regs->ddr_data_init); - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); - out_be32(&ddr->init_addr, regs->ddr_init_addr); - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); - - out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); - out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); - out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); - out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); -#ifndef CONFIG_SYS_FSL_DDR_EMU - /* - * Skip these two registers if running on emulator - * because emulator doesn't have skew between bytes. - */ - - if (regs->ddr_wrlvl_cntl_2) - out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); - if (regs->ddr_wrlvl_cntl_3) - out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); -#endif - - out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); - out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); - out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); - out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); - out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); - out_be32(&ddr->err_disable, regs->err_disable); - out_be32(&ddr->err_int_en, regs->err_int_en); - for (i = 0; i < 32; i++) { - if (regs->debug[i]) { - debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]); - out_be32(&ddr->debug[i], regs->debug[i]); - } - } -#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 - out_be32(&ddr->debug[28], 0x30003000); -#endif - -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 - out_be32(&ddr->debug[12], 0x00000015); - out_be32(&ddr->debug[21], 0x24000000); -#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */ - - /* - * For RDIMMs, JEDEC spec requires clocks to be stable before reset is - * deasserted. Clocks start when any chip select is enabled and clock - * control register is set. Because all DDR components are connected to - * one reset signal, this needs to be done in two steps. Step 1 is to - * get the clocks started. Step 2 resumes after reset signal is - * deasserted. - */ - if (step == 1) { - udelay(200); - return; - } - -step2: - /* Set, but do not enable the memory */ - temp_sdram_cfg = regs->ddr_sdram_cfg; - temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); - out_be32(&ddr->sdram_cfg, temp_sdram_cfg); -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 - debug("Workaround for ERRATUM_DDR_A003\n"); - if (regs->ddr_sdram_rcw_2 & 0x00f00000) { - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); - out_be32(&ddr->debug[2], 0x00000400); - out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff); - out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); - out_be32(&ddr->mtcr, 0); - out_be32(&ddr->debug[12], 0x00000015); - out_be32(&ddr->debug[21], 0x24000000); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff); - out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN); - - asm volatile("sync;isync"); - while (!(in_be32(&ddr->debug[1]) & 0x2)) - ; - - switch (regs->ddr_sdram_rcw_2 & 0x00f00000) { - case 0x00000000: - out_be32(&ddr->sdram_md_cntl, - MD_CNTL_MD_EN | - MD_CNTL_CS_SEL_CS0_CS1 | - 0x04000000 | - MD_CNTL_WRCW | - MD_CNTL_MD_VALUE(0x02)); - break; - case 0x00100000: - out_be32(&ddr->sdram_md_cntl, - MD_CNTL_MD_EN | - MD_CNTL_CS_SEL_CS0_CS1 | - 0x04000000 | - MD_CNTL_WRCW | - MD_CNTL_MD_VALUE(0x0a)); - break; - case 0x00200000: - out_be32(&ddr->sdram_md_cntl, - MD_CNTL_MD_EN | - MD_CNTL_CS_SEL_CS0_CS1 | - 0x04000000 | - MD_CNTL_WRCW | - MD_CNTL_MD_VALUE(0x12)); - break; - case 0x00300000: - out_be32(&ddr->sdram_md_cntl, - MD_CNTL_MD_EN | - MD_CNTL_CS_SEL_CS0_CS1 | - 0x04000000 | - MD_CNTL_WRCW | - MD_CNTL_MD_VALUE(0x1a)); - break; - default: - out_be32(&ddr->sdram_md_cntl, - MD_CNTL_MD_EN | - MD_CNTL_CS_SEL_CS0_CS1 | - 0x04000000 | - MD_CNTL_WRCW | - MD_CNTL_MD_VALUE(0x02)); - printf("Unsupported RC10\n"); - break; - } - - while (in_be32(&ddr->sdram_md_cntl) & 0x80000000) - ; - udelay(6); - out_be32(&ddr->sdram_cfg, temp_sdram_cfg); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->debug[2], 0x0); - out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); - out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->debug[12], 0x0); - out_be32(&ddr->debug[21], 0x0); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); - - } -#endif - /* - * For 8572 DDR1 erratum - DDR controller may enter illegal state - * when operatiing in 32-bit bus mode with 4-beat bursts, - * This erratum does not affect DDR3 mode, only for DDR2 mode. - */ -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 - debug("Workaround for ERRATUM_DDR_115\n"); - if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) - && in_be32(&ddr->sdram_cfg) & 0x80000) { - /* set DEBUG_1[31] */ - setbits_be32(&ddr->debug[0], 1); - } -#endif -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 - debug("Workaround for ERRATUM_DDR111_DDR134\n"); - /* - * This is the combined workaround for DDR111 and DDR134 - * following the published errata for MPC8572 - */ - - /* 1. Set EEBACR[3] */ - setbits_be32(&ecm->eebacr, 0x10000000); - debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); - - /* 2. Set DINIT in SDRAM_CFG_2*/ - setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); - debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n", - in_be32(&ddr->sdram_cfg_2)); - - /* 3. Set DEBUG_3[21] */ - setbits_be32(&ddr->debug[2], 0x400); - debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); - -#endif /* part 1 of the workaound */ - - /* - * 500 painful micro-seconds must elapse between - * the DDR clock setup and the DDR config enable. - * DDR2 need 200 us, and DDR3 need 500 us from spec, - * we choose the max, that is 500 us for all of case. - */ - udelay(500); - asm volatile("sync;isync"); - - /* Let the controller go */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; - out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); - asm volatile("sync;isync"); - - total_gb_size_per_controller = 0; - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (!(regs->cs[i].config & 0x80000000)) - continue; - total_gb_size_per_controller += 1 << ( - ((regs->cs[i].config >> 14) & 0x3) + 2 + - ((regs->cs[i].config >> 8) & 0x7) + 12 + - ((regs->cs[i].config >> 0) & 0x7) + 8 + - 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - - 26); /* minus 26 (count of 64M) */ - } - if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ - total_gb_size_per_controller *= 3; - else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ - total_gb_size_per_controller <<= 1; - /* - * total memory / bus width = transactions needed - * transactions needed / data rate = seconds - * to add plenty of buffer, double the time - * For example, 2GB on 666MT/s 64-bit bus takes about 402ms - * Let's wait for 800ms - */ - bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) - >> SDRAM_CFG_DBW_SHIFT); - timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / - (get_ddr_freq(0) >> 20)) << 1; -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 - timeout_save = timeout; -#endif - total_gb_size_per_controller >>= 4; /* shift down to gb size */ - debug("total %d GB\n", total_gb_size_per_controller); - debug("Need to wait up to %d * 10ms\n", timeout); - - /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ - while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && - (timeout >= 0)) { - udelay(10000); /* throttle polling rate */ - timeout--; - } - - if (timeout <= 0) - printf("Waiting for D_INIT timeout. Memory may not work.\n"); - -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 - /* continue this workaround */ - - /* 4. Clear DEBUG3[21] */ - clrbits_be32(&ddr->debug[2], 0x400); - debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); - - /* DDR134 workaround starts */ - /* A: Clear sdram_cfg_2[odt_cfg] */ - clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK); - debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n", - in_be32(&ddr->sdram_cfg_2)); - - /* B: Set DEBUG1[15] */ - setbits_be32(&ddr->debug[0], 0x10000); - debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); - - /* C: Set timing_cfg_2[cpo] to 0b11111 */ - setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); - debug("Setting TMING_CFG_2[CPO] to 0x%08x\n", - in_be32(&ddr->timing_cfg_2)); - - /* D: Set D6 to 0x9f9f9f9f */ - out_be32(&ddr->debug[5], 0x9f9f9f9f); - debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5])); - - /* E: Set D7 to 0x9f9f9f9f */ - out_be32(&ddr->debug[6], 0x9f9f9f9f); - debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6])); - - /* F: Set D2[20] */ - setbits_be32(&ddr->debug[1], 0x800); - debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1])); - - /* G: Poll on D2[20] until cleared */ - while (in_be32(&ddr->debug[1]) & 0x800) - udelay(10000); /* throttle polling rate */ - - /* H: Clear D1[15] */ - clrbits_be32(&ddr->debug[0], 0x10000); - debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); - - /* I: Set sdram_cfg_2[odt_cfg] */ - setbits_be32(&ddr->sdram_cfg_2, - regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK); - debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); - - /* Continuing with the DDR111 workaround */ - /* 5. Set D2[21] */ - setbits_be32(&ddr->debug[1], 0x400); - debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1])); - - /* 6. Poll D2[21] until its cleared */ - while (in_be32(&ddr->debug[1]) & 0x400) - udelay(10000); /* throttle polling rate */ - - /* 7. Wait for state machine 2nd run, roughly 400ms/GB */ - debug("Wait for %d * 10ms\n", timeout_save); - udelay(timeout_save * 10000); - - /* 8. Set sdram_cfg_2[dinit] if options requires */ - setbits_be32(&ddr->sdram_cfg_2, - regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT); - debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); - - /* 9. Poll until dinit is cleared */ - timeout = timeout_save; - debug("Need to wait up to %d * 10ms\n", timeout); - while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && - (timeout >= 0)) { - udelay(10000); /* throttle polling rate */ - timeout--; - } - - if (timeout <= 0) - printf("Waiting for D_INIT timeout. Memory may not work.\n"); - - /* 10. Clear EEBACR[3] */ - clrbits_be32(&ecm->eebacr, 10000000); - debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); - - if (csn != -1) { - csn_bnds_t = (unsigned int *) ®s->cs[csn].bnds; - *csn_bnds_t = csn_bnds_backup; - debug("Change cs%d_bnds back to 0x%08x\n", - csn, regs->cs[csn].bnds); - setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */ - switch (csn) { - case 0: - out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds); - break; - case 1: - out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds); - break; - case 2: - out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds); - break; - case 3: - out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds); - break; - } - clrbits_be32(&ddr->sdram_cfg, 0x2); - } -#endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ -} diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 2ccd9c7..33bc900 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -586,6 +586,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) { int off; int val; + int len; sys_info_t sysinfo; /* delete crypto node if not on an E-processor */ @@ -615,8 +616,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) get_sys_info(&sysinfo); off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); while (off != -FDT_ERR_NOTFOUND) { - u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); - val = cpu_to_fdt32(sysinfo.freq_processor[*reg]); + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len); + val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]); fdt_setprop(blob, off, "clock-frequency", &val, 4); off = fdt_node_offset_by_prop_value(blob, off, "device_type", "cpu", 4); diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index 4b00da9..19e130e 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -239,9 +239,9 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl) #endif #define CONFIG_SYS_MAX_PCI_EPS 8 -#define CONFIG_SYS_PCI_EP_LIODN_START 256 -static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat) +static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat, + int ep_liodn_start) { int off, pci_idx = 0, pci_cnt = 0, i, rc; const uint32_t *base_liodn; @@ -271,7 +271,7 @@ static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat) continue; } for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++) - liodn_offs[i + 1] = CONFIG_SYS_PCI_EP_LIODN_START + + liodn_offs[i + 1] = ep_liodn_start + i * pci_cnt + pci_idx - *base_liodn; rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list", liodn_offs, sizeof(liodn_offs)); @@ -338,5 +338,22 @@ void fdt_fixup_liodn(void *blob) fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz); #endif - fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie-v2.4"); + ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR; + int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0; + + if (pci_ver >= 0x0204) { + if (pci_ver >= 0x0300) + liodn_base = 1024; + else + liodn_base = 256; + } + + if (liodn_base) { + char compat[32]; + + sprintf(compat, "fsl,qoriq-pcie-v%d.%d", + (pci_ver & 0xff00) >> 8, pci_ver & 0xff); + fdt_fixup_pci_liodn_offsets(blob, compat, liodn_base); + fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie", liodn_base); + } } diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 5f198eb..88c8e65 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -11,7 +11,7 @@ #include <asm/io.h> #include <asm/mmu.h> #include <asm/fsl_law.h> -#include <asm/fsl_ddr_sdram.h> +#include <fsl_ddr_sdram.h> #include "mp.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index d08a8d2..46ae80c 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -86,6 +86,14 @@ void get_sys_info(sys_info_t *sys_info) mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of + * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 + * it uses 6. + */ +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) + if (SVR_MAJ(get_svr()) >= 2) + mem_pll_rat *= 2; +#endif if (mem_pll_rat > 2) sys_info->freq_ddrbus *= mem_pll_rat; else @@ -122,7 +130,7 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_processor[cpu] = freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } -#ifdef CONFIG_PPC_B4860 +#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) #define FM1_CLK_SEL 0xe0000000 #define FM1_CLK_SHIFT 29 #else diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index 199b33e..9e4c6c9 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -7,7 +7,7 @@ #include <common.h> #include <asm/processor.h> #include <asm/global_data.h> -#include <asm/fsl_ifc.h> +#include <fsl_ifc.h> #include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 6a81fa7..db84d10 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -886,7 +886,11 @@ delete_ccsr_l2_tlb: erratum_set_dcsr 0xb0008 0x00900000 erratum_set_dcsr 0xb0e40 0xe00a0000 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY +#ifdef CONFIG_RAMBOOT_PBL + erratum_set_ccsr 0x10f00 0x495e5000 +#else erratum_set_ccsr 0x10f00 0x415e5000 +#endif erratum_set_ccsr 0x11f00 0x415e5000 /* Make temp mapping uncacheable again, if it was initially */ diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c new file mode 100644 index 0000000..068e1f2 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c @@ -0,0 +1,142 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 27, 1, 0), + SET_QP_INFO(2, 28, 1, 0), + SET_QP_INFO(3, 29, 1, 1), + SET_QP_INFO(4, 30, 1, 1), + SET_QP_INFO(5, 31, 1, 2), + SET_QP_INFO(6, 32, 1, 2), + SET_QP_INFO(7, 33, 1, 3), + SET_QP_INFO(8, 34, 1, 3), + SET_QP_INFO(9, 35, 1, 0), + SET_QP_INFO(10, 36, 1, 0), + SET_QP_INFO(11, 37, 1, 1), + SET_QP_INFO(12, 38, 1, 1), + SET_QP_INFO(13, 39, 1, 2), + SET_QP_INFO(14, 40, 1, 2), + SET_QP_INFO(15, 41, 1, 3), + SET_QP_INFO(16, 42, 1, 3), + SET_QP_INFO(17, 43, 1, 0), + SET_QP_INFO(18, 44, 1, 0), +}; +#endif + +#ifdef CONFIG_SYS_SRIO +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_BASE(1, 307), + SET_SRIO_LIODN_BASE(2, 387), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); +#endif + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(62), + SET_BMAN_LIODN(63), +#endif + + SET_SDHC_LIODN(1, 552), + + SET_PME_LIODN(117), + + SET_USB_LIODN(1, "fsl-usb2-mph", 553), + SET_USB_LIODN(2, "fsl-usb2-dr", 554), + + SET_SATA_LIODN(1, 555), + SET_SATA_LIODN(2, 556), + + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), + + SET_DMA_LIODN(1, 147), + SET_DMA_LIODN(2, 227), + SET_DMA_LIODN(3, 226), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), + +#ifdef CONFIG_SYS_PMAN + SET_PMAN_LIODN(1, 513), + SET_PMAN_LIODN(2, 514), + SET_PMAN_LIODN(3, 515), +#endif + + /* SET_NEXUS_LIODN(557), -- not yet implemented */ +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 88), + SET_FMAN_RX_1G_LIODN(1, 1, 89), + SET_FMAN_RX_1G_LIODN(1, 2, 90), + SET_FMAN_RX_1G_LIODN(1, 3, 91), + SET_FMAN_RX_1G_LIODN(1, 4, 92), + SET_FMAN_RX_1G_LIODN(1, 5, 93), + SET_FMAN_RX_10G_LIODN(1, 0, 94), + SET_FMAN_RX_10G_LIODN(1, 1, 95), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 454, 458), + SET_SEC_JR_LIODN_ENTRY(1, 455, 459), + SET_SEC_JR_LIODN_ENTRY(2, 456, 460), + SET_SEC_JR_LIODN_ENTRY(3, 457, 461), + SET_SEC_RTIC_LIODN_ENTRY(a, 453), + SET_SEC_RTIC_LIODN_ENTRY(b, 549), + SET_SEC_RTIC_LIODN_ENTRY(c, 550), + SET_SEC_RTIC_LIODN_ENTRY(d, 551), + SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), + SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), + SET_SEC_DECO_LIODN_ENTRY(2, 543, 612), + SET_SEC_DECO_LIODN_ENTRY(3, 544, 613), + SET_SEC_DECO_LIODN_ENTRY(4, 545, 614), + SET_SEC_DECO_LIODN_ENTRY(5, 546, 615), + SET_SEC_DECO_LIODN_ENTRY(6, 547, 616), + SET_SEC_DECO_LIODN_ENTRY(7, 548, 617), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_RMAN +struct liodn_id_table rman_liodn_tbl[] = { + /* Set RMan block 0-3 liodn offset */ + SET_RMAN_LIODN(0, 6), + SET_RMAN_LIODN(1, 7), + SET_RMAN_LIODN(2, 8), + SET_RMAN_LIODN(3, 9), +}; +int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); +#endif + +struct liodn_id_table liodn_bases[] = { +#ifdef CONFIG_SYS_DPAA_DCE + [FSL_HW_PORTAL_DCE] = SET_LIODN_BASE_2(618, 694), +#endif + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846), +#endif +#ifdef CONFIG_SYS_DPAA_RMAN + [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922), +#endif +}; diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c new file mode 100644 index 0000000..f2fbdeb --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c @@ -0,0 +1,208 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Shengzhou Liu <Shengzhou.Liu@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include "fsl_corenet2_serdes.h" + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static const struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xDE, {PCIE3, PCIE3, PCIE3, PCIE3, + PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, + {0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, + PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, + {0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, + {0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE1, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, +#if defined(CONFIG_PPC_T2080) + {0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC9, XAUI_FM1_MAC9, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM1_MAC1, XFI_FM1_MAC2, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, + SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, + PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, + PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, + PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM1_MAC1, XFI_FM1_MAC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xAB, {PCIE3, PCIE3, PCIE3, PCIE3, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xDA, {PCIE3, PCIE3, PCIE3, PCIE3, + PCIE3, PCIE3, PCIE3, PCIE3} }, + {0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM1_MAC1, XFI_FM1_MAC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + +#elif defined(CONFIG_PPC_T2081) + {0xAA, {PCIE3, PCIE3, PCIE3, PCIE3, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, +#endif + {} +}; + +#ifndef CONFIG_PPC_T2081 +static const struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, + {0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, + {0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, + {0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, + {0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, + {0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, + {0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} }, + {0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, + {0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} }, + {} +}; +#endif + +static const struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, +#ifndef CONFIG_PPC_T2081 + serdes2_cfg_tbl, +#endif +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + const struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + const struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index 54c1cfd..f181315 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -86,10 +86,10 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 555), SET_SATA_LIODN(2, 556), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), SET_DMA_LIODN(1, 147), SET_DMA_LIODN(2, 227), diff --git a/arch/powerpc/cpu/mpc86xx/Makefile b/arch/powerpc/cpu/mpc86xx/Makefile index bcb786d..0f790b0 100644 --- a/arch/powerpc/cpu/mpc86xx/Makefile +++ b/arch/powerpc/cpu/mpc86xx/Makefile @@ -16,9 +16,6 @@ obj-$(CONFIG_MP) += release.o obj-y += cpu.o obj-y += cpu_init.o -# 8610 & 8641 are identical w/regards to DDR -obj-$(CONFIG_MPC8610) += ddr-8641.o -obj-$(CONFIG_MPC8641) += ddr-8641.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-y += interrupts.o obj-$(CONFIG_MP) += mp.o diff --git a/arch/powerpc/cpu/mpc86xx/ddr-8641.c b/arch/powerpc/cpu/mpc86xx/ddr-8641.c deleted file mode 100644 index 33a91f9..0000000 --- a/arch/powerpc/cpu/mpc86xx/ddr-8641.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/fsl_ddr_sdram.h> - -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) -#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL -#endif - -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num, int step) -{ - unsigned int i; - volatile ccsr_ddr_t *ddr; - - switch (ctrl_num) { - case 0: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - break; - case 1: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR; - break; - default: - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i == 0) { - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_config, regs->cs[i].config); - - } else if (i == 1) { - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs1_config, regs->cs[i].config); - - } else if (i == 2) { - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs2_config, regs->cs[i].config); - - } else if (i == 3) { - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs3_config, regs->cs[i].config); - } - } - - out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); - out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); - out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); - out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); - out_be32(&ddr->sdram_data_init, regs->ddr_data_init); - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); - out_be32(&ddr->init_addr, regs->ddr_init_addr); - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); - - debug("before go\n"); - - /* - * 200 painful micro-seconds must elapse between - * the DDR clock setup and the DDR config enable. - */ - udelay(200); - asm volatile("sync;isync"); - - out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); - - /* - * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done - */ - while (in_be32(&ddr->sdram_cfg_2) & 0x10) { - udelay(10000); /* throttle polling rate */ - } -} diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 395fed1..f66ee2e 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -25,7 +25,6 @@ obj-y += cpu.o endif obj-$(CONFIG_OF_LIBFDT) += fdt.o -obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_FSL_LBC) += fsl_lbc.o obj-$(CONFIG_SYS_SRIO) += srio.o obj-$(CONFIG_FSL_LAW) += law.o diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index c67be4e..35795c4 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -75,6 +75,8 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(T1020, T1020, 0), CPU_TYPE_ENTRY(T1021, T1021, 0), CPU_TYPE_ENTRY(T1022, T1022, 0), + CPU_TYPE_ENTRY(T2080, T2080, 0), + CPU_TYPE_ENTRY(T2081, T2081, 0), CPU_TYPE_ENTRY(BSC9130, 9130, 1), CPU_TYPE_ENTRY(BSC9131, 9131, 1), CPU_TYPE_ENTRY(BSC9132, 9132, 2), diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile deleted file mode 100644 index 8cbc06c..0000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# Copyright 2008-2011 Freescale Semiconductor, Inc. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# Version 2 as published by the Free Software Foundation. -# - -obj-$(CONFIG_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \ - lc_common_dimm_params.o - -obj-$(CONFIG_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \ - lc_common_dimm_params.o - -obj-$(CONFIG_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \ - lc_common_dimm_params.o -ifdef CONFIG_DDR_SPD -SPD := y -endif -ifdef CONFIG_SPD_EEPROM -SPD := y -endif -ifdef SPD -obj-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o -obj-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o -obj-$(CONFIG_FSL_DDR3) += ddr3_dimm_params.o -endif - -obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h deleted file mode 100644 index 76338d4..0000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#ifndef COMMON_TIMING_PARAMS_H -#define COMMON_TIMING_PARAMS_H - -typedef struct { - /* parameters to constrict */ - - unsigned int tckmin_x_ps; - unsigned int tckmax_ps; - unsigned int tckmax_max_ps; - unsigned int trcd_ps; - unsigned int trp_ps; - unsigned int tras_ps; - - unsigned int twr_ps; /* maximum = 63750 ps */ - unsigned int twtr_ps; /* maximum = 63750 ps */ - unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns - = 511750 ps */ - - unsigned int trrd_ps; /* maximum = 63750 ps */ - unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ - - unsigned int refresh_rate_ps; - unsigned int extended_op_srt; - - unsigned int tis_ps; /* byte 32, spd->ca_setup */ - unsigned int tih_ps; /* byte 33, spd->ca_hold */ - unsigned int tds_ps; /* byte 34, spd->data_setup */ - unsigned int tdh_ps; /* byte 35, spd->data_hold */ - unsigned int trtp_ps; /* byte 38, spd->trtp */ - unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ - unsigned int tqhs_ps; /* byte 45, spd->tqhs */ - - unsigned int ndimms_present; - unsigned int lowest_common_SPD_caslat; - unsigned int highest_common_derated_caslat; - unsigned int additive_latency; - unsigned int all_dimms_burst_lengths_bitmask; - unsigned int all_dimms_registered; - unsigned int all_dimms_unbuffered; - unsigned int all_dimms_ecc_capable; - - unsigned long long total_mem; - unsigned long long base_address; - - /* DDR3 RDIMM */ - unsigned char rcw[16]; /* Register Control Word 0-15 */ -} common_timing_params_t; - -#endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c deleted file mode 100644 index dcfc48a..0000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ /dev/null @@ -1,1656 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. - * Based on code from spd_sdram.c - * Author: James Yang [at freescale.com] - */ - -#include <common.h> -#include <asm/fsl_ddr_sdram.h> - -#include "ddr.h" - -#define _DDR_ADDR CONFIG_SYS_MPC8xxx_DDR_ADDR - -static u32 fsl_ddr_get_version(void) -{ - ccsr_ddr_t *ddr; - u32 ver_major_minor_errata; - - ddr = (void *)_DDR_ADDR; - ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8; - ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8; - - return ver_major_minor_errata; -} - -unsigned int picos_to_mclk(unsigned int picos); - -/* - * Determine Rtt value. - * - * This should likely be either board or controller specific. - * - * Rtt(nominal) - DDR2: - * 0 = Rtt disabled - * 1 = 75 ohm - * 2 = 150 ohm - * 3 = 50 ohm - * Rtt(nominal) - DDR3: - * 0 = Rtt disabled - * 1 = 60 ohm - * 2 = 120 ohm - * 3 = 40 ohm - * 4 = 20 ohm - * 5 = 30 ohm - * - * FIXME: Apparently 8641 needs a value of 2 - * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572 - * - * FIXME: There was some effort down this line earlier: - * - * unsigned int i; - * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) { - * if (popts->dimmslot[i].num_valid_cs - * && (popts->cs_local_opts[2*i].odt_rd_cfg - * || popts->cs_local_opts[2*i].odt_wr_cfg)) { - * rtt = 2; - * break; - * } - * } - */ -static inline int fsl_ddr_get_rtt(void) -{ - int rtt; - -#if defined(CONFIG_FSL_DDR1) - rtt = 0; -#elif defined(CONFIG_FSL_DDR2) - rtt = 3; -#else - rtt = 0; -#endif - - return rtt; -} - -/* - * compute the CAS write latency according to DDR3 spec - * CWL = 5 if tCK >= 2.5ns - * 6 if 2.5ns > tCK >= 1.875ns - * 7 if 1.875ns > tCK >= 1.5ns - * 8 if 1.5ns > tCK >= 1.25ns - * 9 if 1.25ns > tCK >= 1.07ns - * 10 if 1.07ns > tCK >= 0.935ns - * 11 if 0.935ns > tCK >= 0.833ns - * 12 if 0.833ns > tCK >= 0.75ns - */ -static inline unsigned int compute_cas_write_latency(void) -{ - unsigned int cwl; - const unsigned int mclk_ps = get_memory_clk_period_ps(); - - if (mclk_ps >= 2500) - cwl = 5; - else if (mclk_ps >= 1875) - cwl = 6; - else if (mclk_ps >= 1500) - cwl = 7; - else if (mclk_ps >= 1250) - cwl = 8; - else if (mclk_ps >= 1070) - cwl = 9; - else if (mclk_ps >= 935) - cwl = 10; - else if (mclk_ps >= 833) - cwl = 11; - else if (mclk_ps >= 750) - cwl = 12; - else { - cwl = 12; - printf("Warning: CWL is out of range\n"); - } - return cwl; -} - -/* Chip Select Configuration (CSn_CONFIG) */ -static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const dimm_params_t *dimm_params) -{ - unsigned int cs_n_en = 0; /* Chip Select enable */ - unsigned int intlv_en = 0; /* Memory controller interleave enable */ - unsigned int intlv_ctl = 0; /* Interleaving control */ - unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ - unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */ - unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */ - unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */ - unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */ - unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */ - int go_config = 0; - - /* Compute CS_CONFIG only for existing ranks of each DIMM. */ - switch (i) { - case 0: - if (dimm_params[dimm_number].n_ranks > 0) { - go_config = 1; - /* These fields only available in CS0_CONFIG */ - if (!popts->memctl_interleaving) - break; - switch (popts->memctl_interleaving_mode) { - case FSL_DDR_CACHE_LINE_INTERLEAVING: - case FSL_DDR_PAGE_INTERLEAVING: - case FSL_DDR_BANK_INTERLEAVING: - case FSL_DDR_SUPERBANK_INTERLEAVING: - intlv_en = popts->memctl_interleaving; - intlv_ctl = popts->memctl_interleaving_mode; - break; - default: - break; - } - } - break; - case 1: - if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \ - (dimm_number == 1 && dimm_params[1].n_ranks > 0)) - go_config = 1; - break; - case 2: - if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \ - (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0)) - go_config = 1; - break; - case 3: - if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \ - (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \ - (dimm_number == 3 && dimm_params[3].n_ranks > 0)) - go_config = 1; - break; - default: - break; - } - if (go_config) { - unsigned int n_banks_per_sdram_device; - cs_n_en = 1; - ap_n_en = popts->cs_local_opts[i].auto_precharge; - odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; - odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; - n_banks_per_sdram_device - = dimm_params[dimm_number].n_banks_per_sdram_device; - ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2; - row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12; - col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8; - } - ddr->cs[i].config = (0 - | ((cs_n_en & 0x1) << 31) - | ((intlv_en & 0x3) << 29) - | ((intlv_ctl & 0xf) << 24) - | ((ap_n_en & 0x1) << 23) - - /* XXX: some implementation only have 1 bit starting at left */ - | ((odt_rd_cfg & 0x7) << 20) - - /* XXX: Some implementation only have 1 bit starting at left */ - | ((odt_wr_cfg & 0x7) << 16) - - | ((ba_bits_cs_n & 0x3) << 14) - | ((row_bits_cs_n & 0x7) << 8) - | ((col_bits_cs_n & 0x7) << 0) - ); - debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); -} - -/* Chip Select Configuration 2 (CSn_CONFIG_2) */ -/* FIXME: 8572 */ -static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int pasr_cfg = 0; /* Partial array self refresh config */ - - ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); - debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); -} - -/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */ - -#if !defined(CONFIG_FSL_DDR1) -static inline int avoid_odt_overlap(const dimm_params_t *dimm_params) -{ -#if CONFIG_DIMM_SLOTS_PER_CTLR == 1 - if (dimm_params[0].n_ranks == 4) - return 1; -#endif - -#if CONFIG_DIMM_SLOTS_PER_CTLR == 2 - if ((dimm_params[0].n_ranks == 2) && - (dimm_params[1].n_ranks == 2)) - return 1; - -#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - if (dimm_params[0].n_ranks == 4) - return 1; -#endif -#endif - return 0; -} - -/* - * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) - * - * Avoid writing for DDR I. The new PQ38 DDR controller - * dreams up non-zero default values to be backwards compatible. - */ -static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const dimm_params_t *dimm_params) -{ - unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ - unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ - /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */ - unsigned char trrt_mclk = 0; /* Read-to-read turnaround */ - unsigned char twwt_mclk = 0; /* Write-to-write turnaround */ - - /* Active powerdown exit timing (tXARD and tXARDS). */ - unsigned char act_pd_exit_mclk; - /* Precharge powerdown exit timing (tXP). */ - unsigned char pre_pd_exit_mclk; - /* ODT powerdown exit timing (tAXPD). */ - unsigned char taxpd_mclk; - /* Mode register set cycle time (tMRD). */ - unsigned char tmrd_mclk; - -#ifdef CONFIG_FSL_DDR3 - /* - * (tXARD and tXARDS). Empirical? - * The DDR3 spec has not tXARD, - * we use the tXP instead of it. - * tXP=max(3nCK, 7.5ns) for DDR3. - * spec has not the tAXPD, we use - * tAXPD=1, need design to confirm. - */ - int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ - unsigned int data_rate = get_ddr_freq(0); - tmrd_mclk = 4; - /* set the turnaround time */ - - /* - * for single quad-rank DIMM and two dual-rank DIMMs - * to avoid ODT overlap - */ - if (avoid_odt_overlap(dimm_params)) { - twwt_mclk = 2; - trrt_mclk = 1; - } - /* for faster clock, need more time for data setup */ - trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1; - - if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving)) - twrt_mclk = 1; - - if (popts->dynamic_power == 0) { /* powerdown is not used */ - act_pd_exit_mclk = 1; - pre_pd_exit_mclk = 1; - taxpd_mclk = 1; - } else { - /* act_pd_exit_mclk = tXARD, see above */ - act_pd_exit_mclk = picos_to_mclk(tXP); - /* Mode register MR0[A12] is '1' - fast exit */ - pre_pd_exit_mclk = act_pd_exit_mclk; - taxpd_mclk = 1; - } -#else /* CONFIG_FSL_DDR2 */ - /* - * (tXARD and tXARDS). Empirical? - * tXARD = 2 for DDR2 - * tXP=2 - * tAXPD=8 - */ - act_pd_exit_mclk = 2; - pre_pd_exit_mclk = 2; - taxpd_mclk = 8; - tmrd_mclk = 2; -#endif - - if (popts->trwt_override) - trwt_mclk = popts->trwt; - - ddr->timing_cfg_0 = (0 - | ((trwt_mclk & 0x3) << 30) /* RWT */ - | ((twrt_mclk & 0x3) << 28) /* WRT */ - | ((trrt_mclk & 0x3) << 26) /* RRT */ - | ((twwt_mclk & 0x3) << 24) /* WWT */ - | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */ - | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */ - | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */ - | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */ - ); - debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); -} -#endif /* defined(CONFIG_FSL_DDR2) */ - -/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */ -static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency) -{ - /* Extended precharge to activate interval (tRP) */ - unsigned int ext_pretoact = 0; - /* Extended Activate to precharge interval (tRAS) */ - unsigned int ext_acttopre = 0; - /* Extended activate to read/write interval (tRCD) */ - unsigned int ext_acttorw = 0; - /* Extended refresh recovery time (tRFC) */ - unsigned int ext_refrec; - /* Extended MCAS latency from READ cmd */ - unsigned int ext_caslat = 0; - /* Extended last data to precharge interval (tWR) */ - unsigned int ext_wrrec = 0; - /* Control Adjust */ - unsigned int cntl_adj = 0; - - ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4; - ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4; - ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4; - ext_caslat = (2 * cas_latency - 1) >> 4; - ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4; - /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */ - ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) + - (popts->otf_burst_chop_en ? 2 : 0)) >> 4; - - ddr->timing_cfg_3 = (0 - | ((ext_pretoact & 0x1) << 28) - | ((ext_acttopre & 0x3) << 24) - | ((ext_acttorw & 0x1) << 22) - | ((ext_refrec & 0x1F) << 16) - | ((ext_caslat & 0x3) << 12) - | ((ext_wrrec & 0x1) << 8) - | ((cntl_adj & 0x7) << 0) - ); - debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); -} - -/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */ -static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency) -{ - /* Precharge-to-activate interval (tRP) */ - unsigned char pretoact_mclk; - /* Activate to precharge interval (tRAS) */ - unsigned char acttopre_mclk; - /* Activate to read/write interval (tRCD) */ - unsigned char acttorw_mclk; - /* CASLAT */ - unsigned char caslat_ctrl; - /* Refresh recovery time (tRFC) ; trfc_low */ - unsigned char refrec_ctrl; - /* Last data to precharge minimum interval (tWR) */ - unsigned char wrrec_mclk; - /* Activate-to-activate interval (tRRD) */ - unsigned char acttoact_mclk; - /* Last write data pair to read command issue interval (tWTR) */ - unsigned char wrtord_mclk; - /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */ - static const u8 wrrec_table[] = { - 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0}; - - pretoact_mclk = picos_to_mclk(common_dimm->trp_ps); - acttopre_mclk = picos_to_mclk(common_dimm->tras_ps); - acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps); - - /* - * Translate CAS Latency to a DDR controller field value: - * - * CAS Lat DDR I DDR II Ctrl - * Clocks SPD Bit SPD Bit Value - * ------- ------- ------- ----- - * 1.0 0 0001 - * 1.5 1 0010 - * 2.0 2 2 0011 - * 2.5 3 0100 - * 3.0 4 3 0101 - * 3.5 5 0110 - * 4.0 4 0111 - * 4.5 1000 - * 5.0 5 1001 - */ -#if defined(CONFIG_FSL_DDR1) - caslat_ctrl = (cas_latency + 1) & 0x07; -#elif defined(CONFIG_FSL_DDR2) - caslat_ctrl = 2 * cas_latency - 1; -#else - /* - * if the CAS latency more than 8 cycle, - * we need set extend bit for it at - * TIMING_CFG_3[EXT_CASLAT] - */ - caslat_ctrl = 2 * cas_latency - 1; -#endif - - refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8; - wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); - - if (wrrec_mclk > 16) - printf("Error: WRREC doesn't support more than 16 clocks\n"); - else - wrrec_mclk = wrrec_table[wrrec_mclk - 1]; - if (popts->otf_burst_chop_en) - wrrec_mclk += 2; - - acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps); - /* - * JEDEC has min requirement for tRRD - */ -#if defined(CONFIG_FSL_DDR3) - if (acttoact_mclk < 4) - acttoact_mclk = 4; -#endif - wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps); - /* - * JEDEC has some min requirements for tWTR - */ -#if defined(CONFIG_FSL_DDR2) - if (wrtord_mclk < 2) - wrtord_mclk = 2; -#elif defined(CONFIG_FSL_DDR3) - if (wrtord_mclk < 4) - wrtord_mclk = 4; -#endif - if (popts->otf_burst_chop_en) - wrtord_mclk += 2; - - ddr->timing_cfg_1 = (0 - | ((pretoact_mclk & 0x0F) << 28) - | ((acttopre_mclk & 0x0F) << 24) - | ((acttorw_mclk & 0xF) << 20) - | ((caslat_ctrl & 0xF) << 16) - | ((refrec_ctrl & 0xF) << 12) - | ((wrrec_mclk & 0x0F) << 8) - | ((acttoact_mclk & 0x0F) << 4) - | ((wrtord_mclk & 0x0F) << 0) - ); - debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); -} - -/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */ -static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency, - unsigned int additive_latency) -{ - /* Additive latency */ - unsigned char add_lat_mclk; - /* CAS-to-preamble override */ - unsigned short cpo; - /* Write latency */ - unsigned char wr_lat; - /* Read to precharge (tRTP) */ - unsigned char rd_to_pre; - /* Write command to write data strobe timing adjustment */ - unsigned char wr_data_delay; - /* Minimum CKE pulse width (tCKE) */ - unsigned char cke_pls; - /* Window for four activates (tFAW) */ - unsigned short four_act; - - /* FIXME add check that this must be less than acttorw_mclk */ - add_lat_mclk = additive_latency; - cpo = popts->cpo_override; - -#if defined(CONFIG_FSL_DDR1) - /* - * This is a lie. It should really be 1, but if it is - * set to 1, bits overlap into the old controller's - * otherwise unused ACSM field. If we leave it 0, then - * the HW will magically treat it as 1 for DDR 1. Oh Yea. - */ - wr_lat = 0; -#elif defined(CONFIG_FSL_DDR2) - wr_lat = cas_latency - 1; -#else - wr_lat = compute_cas_write_latency(); -#endif - - rd_to_pre = picos_to_mclk(common_dimm->trtp_ps); - /* - * JEDEC has some min requirements for tRTP - */ -#if defined(CONFIG_FSL_DDR2) - if (rd_to_pre < 2) - rd_to_pre = 2; -#elif defined(CONFIG_FSL_DDR3) - if (rd_to_pre < 4) - rd_to_pre = 4; -#endif - if (additive_latency) - rd_to_pre += additive_latency; - if (popts->otf_burst_chop_en) - rd_to_pre += 2; /* according to UM */ - - wr_data_delay = popts->write_data_delay; - cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps); - four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps); - - ddr->timing_cfg_2 = (0 - | ((add_lat_mclk & 0xf) << 28) - | ((cpo & 0x1f) << 23) - | ((wr_lat & 0xf) << 19) - | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) - | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) - | ((cke_pls & 0x7) << 6) - | ((four_act & 0x3f) << 0) - ); - debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); -} - -/* DDR SDRAM Register Control Word */ -static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm) -{ - if (common_dimm->all_dimms_registered && - !common_dimm->all_dimms_unbuffered) { - if (popts->rcw_override) { - ddr->ddr_sdram_rcw_1 = popts->rcw_1; - ddr->ddr_sdram_rcw_2 = popts->rcw_2; - } else { - ddr->ddr_sdram_rcw_1 = - common_dimm->rcw[0] << 28 | \ - common_dimm->rcw[1] << 24 | \ - common_dimm->rcw[2] << 20 | \ - common_dimm->rcw[3] << 16 | \ - common_dimm->rcw[4] << 12 | \ - common_dimm->rcw[5] << 8 | \ - common_dimm->rcw[6] << 4 | \ - common_dimm->rcw[7]; - ddr->ddr_sdram_rcw_2 = - common_dimm->rcw[8] << 28 | \ - common_dimm->rcw[9] << 24 | \ - common_dimm->rcw[10] << 20 | \ - common_dimm->rcw[11] << 16 | \ - common_dimm->rcw[12] << 12 | \ - common_dimm->rcw[13] << 8 | \ - common_dimm->rcw[14] << 4 | \ - common_dimm->rcw[15]; - } - debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1); - debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2); - } -} - -/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */ -static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm) -{ - unsigned int mem_en; /* DDR SDRAM interface logic enable */ - unsigned int sren; /* Self refresh enable (during sleep) */ - unsigned int ecc_en; /* ECC enable. */ - unsigned int rd_en; /* Registered DIMM enable */ - unsigned int sdram_type; /* Type of SDRAM */ - unsigned int dyn_pwr; /* Dynamic power management mode */ - unsigned int dbw; /* DRAM dta bus width */ - unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ - unsigned int ncap = 0; /* Non-concurrent auto-precharge */ - unsigned int threet_en; /* Enable 3T timing */ - unsigned int twot_en; /* Enable 2T timing */ - unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */ - unsigned int x32_en = 0; /* x32 enable */ - unsigned int pchb8 = 0; /* precharge bit 8 enable */ - unsigned int hse; /* Global half strength override */ - unsigned int mem_halt = 0; /* memory controller halt */ - unsigned int bi = 0; /* Bypass initialization */ - - mem_en = 1; - sren = popts->self_refresh_in_sleep; - if (common_dimm->all_dimms_ecc_capable) { - /* Allow setting of ECC only if all DIMMs are ECC. */ - ecc_en = popts->ecc_mode; - } else { - ecc_en = 0; - } - - if (common_dimm->all_dimms_registered && - !common_dimm->all_dimms_unbuffered) { - rd_en = 1; - twot_en = 0; - } else { - rd_en = 0; - twot_en = popts->twot_en; - } - - sdram_type = CONFIG_FSL_SDRAM_TYPE; - - dyn_pwr = popts->dynamic_power; - dbw = popts->data_bus_width; - /* 8-beat burst enable DDR-III case - * we must clear it when use the on-the-fly mode, - * must set it when use the 32-bits bus mode. - */ - if (sdram_type == SDRAM_TYPE_DDR3) { - if (popts->burst_length == DDR_BL8) - eight_be = 1; - if (popts->burst_length == DDR_OTF) - eight_be = 0; - if (dbw == 0x1) - eight_be = 1; - } - - threet_en = popts->threet_en; - ba_intlv_ctl = popts->ba_intlv_ctl; - hse = popts->half_strength_driver_enable; - - ddr->ddr_sdram_cfg = (0 - | ((mem_en & 0x1) << 31) - | ((sren & 0x1) << 30) - | ((ecc_en & 0x1) << 29) - | ((rd_en & 0x1) << 28) - | ((sdram_type & 0x7) << 24) - | ((dyn_pwr & 0x1) << 21) - | ((dbw & 0x3) << 19) - | ((eight_be & 0x1) << 18) - | ((ncap & 0x1) << 17) - | ((threet_en & 0x1) << 16) - | ((twot_en & 0x1) << 15) - | ((ba_intlv_ctl & 0x7F) << 8) - | ((x32_en & 0x1) << 5) - | ((pchb8 & 0x1) << 4) - | ((hse & 0x1) << 3) - | ((mem_halt & 0x1) << 1) - | ((bi & 0x1) << 0) - ); - debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); -} - -/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ -static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const unsigned int unq_mrs_en) -{ - unsigned int frc_sr = 0; /* Force self refresh */ - unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ - unsigned int dll_rst_dis; /* DLL reset disable */ - unsigned int dqs_cfg; /* DQS configuration */ - unsigned int odt_cfg = 0; /* ODT configuration */ - unsigned int num_pr; /* Number of posted refreshes */ - unsigned int slow = 0; /* DDR will be run less than 1250 */ - unsigned int x4_en = 0; /* x4 DRAM enable */ - unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ - unsigned int ap_en; /* Address Parity Enable */ - unsigned int d_init; /* DRAM data initialization */ - unsigned int rcw_en = 0; /* Register Control Word Enable */ - unsigned int md_en = 0; /* Mirrored DIMM Enable */ - unsigned int qd_en = 0; /* quad-rank DIMM Enable */ - int i; - - dll_rst_dis = 1; /* Make this configurable */ - dqs_cfg = popts->dqs_config; - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (popts->cs_local_opts[i].odt_rd_cfg - || popts->cs_local_opts[i].odt_wr_cfg) { - odt_cfg = SDRAM_CFG2_ODT_ONLY_READ; - break; - } - } - - num_pr = 1; /* Make this configurable */ - - /* - * 8572 manual says - * {TIMING_CFG_1[PRETOACT] - * + [DDR_SDRAM_CFG_2[NUM_PR] - * * ({EXT_REFREC || REFREC} + 8 + 2)]} - * << DDR_SDRAM_INTERVAL[REFINT] - */ -#if defined(CONFIG_FSL_DDR3) - obc_cfg = popts->otf_burst_chop_en; -#else - obc_cfg = 0; -#endif - -#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7) - slow = get_ddr_freq(0) < 1249000000; -#endif - - if (popts->registered_dimm_en) { - rcw_en = 1; - ap_en = popts->ap_en; - } else { - ap_en = 0; - } - - x4_en = popts->x4_en ? 1 : 0; - -#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* Use the DDR controller to auto initialize memory. */ - d_init = popts->ecc_init_using_memctl; - ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; - debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); -#else - /* Memory will be initialized via DMA, or not at all. */ - d_init = 0; -#endif - -#if defined(CONFIG_FSL_DDR3) - md_en = popts->mirrored_dimm; -#endif - qd_en = popts->quad_rank_present ? 1 : 0; - ddr->ddr_sdram_cfg_2 = (0 - | ((frc_sr & 0x1) << 31) - | ((sr_ie & 0x1) << 30) - | ((dll_rst_dis & 0x1) << 29) - | ((dqs_cfg & 0x3) << 26) - | ((odt_cfg & 0x3) << 21) - | ((num_pr & 0xf) << 12) - | ((slow & 1) << 11) - | (x4_en << 10) - | (qd_en << 9) - | (unq_mrs_en << 8) - | ((obc_cfg & 0x1) << 6) - | ((ap_en & 0x1) << 5) - | ((d_init & 0x1) << 4) - | ((rcw_en & 0x1) << 2) - | ((md_en & 0x1) << 0) - ); - debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); -} - -/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ -static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - const unsigned int unq_mrs_en) -{ - unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ - unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ - -#if defined(CONFIG_FSL_DDR3) - int i; - unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ - unsigned int srt = 0; /* self-refresh temerature, normal range */ - unsigned int asr = 0; /* auto self-refresh disable */ - unsigned int cwl = compute_cas_write_latency() - 5; - unsigned int pasr = 0; /* partial array self refresh disable */ - - if (popts->rtt_override) - rtt_wr = popts->rtt_wr_override_value; - else - rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; - - if (common_dimm->extended_op_srt) - srt = common_dimm->extended_op_srt; - - esdmode2 = (0 - | ((rtt_wr & 0x3) << 9) - | ((srt & 0x1) << 7) - | ((asr & 0x1) << 6) - | ((cwl & 0x7) << 3) - | ((pasr & 0x7) << 0)); -#endif - ddr->ddr_sdram_mode_2 = (0 - | ((esdmode2 & 0xFFFF) << 16) - | ((esdmode3 & 0xFFFF) << 0) - ); - debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); - -#ifdef CONFIG_FSL_DDR3 - if (unq_mrs_en) { /* unique mode registers are supported */ - for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (popts->rtt_override) - rtt_wr = popts->rtt_wr_override_value; - else - rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; - - esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ - esdmode2 |= (rtt_wr & 0x3) << 9; - switch (i) { - case 1: - ddr->ddr_sdram_mode_4 = (0 - | ((esdmode2 & 0xFFFF) << 16) - | ((esdmode3 & 0xFFFF) << 0) - ); - break; - case 2: - ddr->ddr_sdram_mode_6 = (0 - | ((esdmode2 & 0xFFFF) << 16) - | ((esdmode3 & 0xFFFF) << 0) - ); - break; - case 3: - ddr->ddr_sdram_mode_8 = (0 - | ((esdmode2 & 0xFFFF) << 16) - | ((esdmode3 & 0xFFFF) << 0) - ); - break; - } - } - debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", - ddr->ddr_sdram_mode_4); - debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", - ddr->ddr_sdram_mode_6); - debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", - ddr->ddr_sdram_mode_8); - } -#endif -} - -/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ -static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm) -{ - unsigned int refint; /* Refresh interval */ - unsigned int bstopre; /* Precharge interval */ - - refint = picos_to_mclk(common_dimm->refresh_rate_ps); - - bstopre = popts->bstopre; - - /* refint field used 0x3FFF in earlier controllers */ - ddr->ddr_sdram_interval = (0 - | ((refint & 0xFFFF) << 16) - | ((bstopre & 0x3FFF) << 0) - ); - debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); -} - -#if defined(CONFIG_FSL_DDR3) -/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ -static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency, - unsigned int additive_latency, - const unsigned int unq_mrs_en) -{ - unsigned short esdmode; /* Extended SDRAM mode */ - unsigned short sdmode; /* SDRAM mode */ - - /* Mode Register - MR1 */ - unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ - unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ - unsigned int rtt; - unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ - unsigned int al = 0; /* Posted CAS# additive latency (AL) */ - unsigned int dic = 0; /* Output driver impedance, 40ohm */ - unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), - 1=Disable (Test/Debug) */ - - /* Mode Register - MR0 */ - unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */ - unsigned int wr = 0; /* Write Recovery */ - unsigned int dll_rst; /* DLL Reset */ - unsigned int mode; /* Normal=0 or Test=1 */ - unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ - /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ - unsigned int bt; - unsigned int bl; /* BL: Burst Length */ - - unsigned int wr_mclk; - /* - * DDR_SDRAM_MODE doesn't support 9,11,13,15 - * Please refer JEDEC Standard No. 79-3E for Mode Register MR0 - * for this table - */ - static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0}; - - const unsigned int mclk_ps = get_memory_clk_period_ps(); - int i; - - if (popts->rtt_override) - rtt = popts->rtt_override_value; - else - rtt = popts->cs_local_opts[0].odt_rtt_norm; - - if (additive_latency == (cas_latency - 1)) - al = 1; - if (additive_latency == (cas_latency - 2)) - al = 2; - - if (popts->quad_rank_present) - dic = 1; /* output driver impedance 240/7 ohm */ - - /* - * The esdmode value will also be used for writing - * MR1 during write leveling for DDR3, although the - * bits specifically related to the write leveling - * scheme will be handled automatically by the DDR - * controller. so we set the wrlvl_en = 0 here. - */ - esdmode = (0 - | ((qoff & 0x1) << 12) - | ((tdqs_en & 0x1) << 11) - | ((rtt & 0x4) << 7) /* rtt field is split */ - | ((wrlvl_en & 0x1) << 7) - | ((rtt & 0x2) << 5) /* rtt field is split */ - | ((dic & 0x2) << 4) /* DIC field is split */ - | ((al & 0x3) << 3) - | ((rtt & 0x1) << 2) /* rtt field is split */ - | ((dic & 0x1) << 1) /* DIC field is split */ - | ((dll_en & 0x1) << 0) - ); - - /* - * DLL control for precharge PD - * 0=slow exit DLL off (tXPDLL) - * 1=fast exit DLL on (tXP) - */ - dll_on = 1; - - wr_mclk = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps; - if (wr_mclk <= 16) { - wr = wr_table[wr_mclk - 5]; - } else { - printf("Error: unsupported write recovery for mode register " - "wr_mclk = %d\n", wr_mclk); - } - - dll_rst = 0; /* dll no reset */ - mode = 0; /* normal mode */ - - /* look up table to get the cas latency bits */ - if (cas_latency >= 5 && cas_latency <= 16) { - unsigned char cas_latency_table[] = { - 0x2, /* 5 clocks */ - 0x4, /* 6 clocks */ - 0x6, /* 7 clocks */ - 0x8, /* 8 clocks */ - 0xa, /* 9 clocks */ - 0xc, /* 10 clocks */ - 0xe, /* 11 clocks */ - 0x1, /* 12 clocks */ - 0x3, /* 13 clocks */ - 0x5, /* 14 clocks */ - 0x7, /* 15 clocks */ - 0x9, /* 16 clocks */ - }; - caslat = cas_latency_table[cas_latency - 5]; - } else { - printf("Error: unsupported cas latency for mode register\n"); - } - - bt = 0; /* Nibble sequential */ - - switch (popts->burst_length) { - case DDR_BL8: - bl = 0; - break; - case DDR_OTF: - bl = 1; - break; - case DDR_BC4: - bl = 2; - break; - default: - printf("Error: invalid burst length of %u specified. " - " Defaulting to on-the-fly BC4 or BL8 beats.\n", - popts->burst_length); - bl = 1; - break; - } - - sdmode = (0 - | ((dll_on & 0x1) << 12) - | ((wr & 0x7) << 9) - | ((dll_rst & 0x1) << 8) - | ((mode & 0x1) << 7) - | (((caslat >> 1) & 0x7) << 4) - | ((bt & 0x1) << 3) - | ((caslat & 1) << 2) - | ((bl & 0x3) << 0) - ); - - ddr->ddr_sdram_mode = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - - debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); - - if (unq_mrs_en) { /* unique mode registers are supported */ - for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (popts->rtt_override) - rtt = popts->rtt_override_value; - else - rtt = popts->cs_local_opts[i].odt_rtt_norm; - - esdmode &= 0xFDBB; /* clear bit 9,6,2 */ - esdmode |= (0 - | ((rtt & 0x4) << 7) /* rtt field is split */ - | ((rtt & 0x2) << 5) /* rtt field is split */ - | ((rtt & 0x1) << 2) /* rtt field is split */ - ); - switch (i) { - case 1: - ddr->ddr_sdram_mode_3 = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - break; - case 2: - ddr->ddr_sdram_mode_5 = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - break; - case 3: - ddr->ddr_sdram_mode_7 = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - break; - } - } - debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", - ddr->ddr_sdram_mode_3); - debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", - ddr->ddr_sdram_mode_5); - debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", - ddr->ddr_sdram_mode_5); - } -} - -#else /* !CONFIG_FSL_DDR3 */ - -/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ -static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency, - unsigned int additive_latency, - const unsigned int unq_mrs_en) -{ - unsigned short esdmode; /* Extended SDRAM mode */ - unsigned short sdmode; /* SDRAM mode */ - - /* - * FIXME: This ought to be pre-calculated in a - * technology-specific routine, - * e.g. compute_DDR2_mode_register(), and then the - * sdmode and esdmode passed in as part of common_dimm. - */ - - /* Extended Mode Register */ - unsigned int mrs = 0; /* Mode Register Set */ - unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */ - unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */ - unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */ - unsigned int ocd = 0; /* 0x0=OCD not supported, - 0x7=OCD default state */ - unsigned int rtt; - unsigned int al; /* Posted CAS# additive latency (AL) */ - unsigned int ods = 0; /* Output Drive Strength: - 0 = Full strength (18ohm) - 1 = Reduced strength (4ohm) */ - unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), - 1=Disable (Test/Debug) */ - - /* Mode Register (MR) */ - unsigned int mr; /* Mode Register Definition */ - unsigned int pd; /* Power-Down Mode */ - unsigned int wr; /* Write Recovery */ - unsigned int dll_res; /* DLL Reset */ - unsigned int mode; /* Normal=0 or Test=1 */ - unsigned int caslat = 0;/* CAS# latency */ - /* BT: Burst Type (0=Sequential, 1=Interleaved) */ - unsigned int bt; - unsigned int bl; /* BL: Burst Length */ - -#if defined(CONFIG_FSL_DDR2) - const unsigned int mclk_ps = get_memory_clk_period_ps(); -#endif - dqs_en = !popts->dqs_config; - rtt = fsl_ddr_get_rtt(); - - al = additive_latency; - - esdmode = (0 - | ((mrs & 0x3) << 14) - | ((outputs & 0x1) << 12) - | ((rdqs_en & 0x1) << 11) - | ((dqs_en & 0x1) << 10) - | ((ocd & 0x7) << 7) - | ((rtt & 0x2) << 5) /* rtt field is split */ - | ((al & 0x7) << 3) - | ((rtt & 0x1) << 2) /* rtt field is split */ - | ((ods & 0x1) << 1) - | ((dll_en & 0x1) << 0) - ); - - mr = 0; /* FIXME: CHECKME */ - - /* - * 0 = Fast Exit (Normal) - * 1 = Slow Exit (Low Power) - */ - pd = 0; - -#if defined(CONFIG_FSL_DDR1) - wr = 0; /* Historical */ -#elif defined(CONFIG_FSL_DDR2) - wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1; -#endif - dll_res = 0; - mode = 0; - -#if defined(CONFIG_FSL_DDR1) - if (1 <= cas_latency && cas_latency <= 4) { - unsigned char mode_caslat_table[4] = { - 0x5, /* 1.5 clocks */ - 0x2, /* 2.0 clocks */ - 0x6, /* 2.5 clocks */ - 0x3 /* 3.0 clocks */ - }; - caslat = mode_caslat_table[cas_latency - 1]; - } else { - printf("Warning: unknown cas_latency %d\n", cas_latency); - } -#elif defined(CONFIG_FSL_DDR2) - caslat = cas_latency; -#endif - bt = 0; - - switch (popts->burst_length) { - case DDR_BL4: - bl = 2; - break; - case DDR_BL8: - bl = 3; - break; - default: - printf("Error: invalid burst length of %u specified. " - " Defaulting to 4 beats.\n", - popts->burst_length); - bl = 2; - break; - } - - sdmode = (0 - | ((mr & 0x3) << 14) - | ((pd & 0x1) << 12) - | ((wr & 0x7) << 9) - | ((dll_res & 0x1) << 8) - | ((mode & 0x1) << 7) - | ((caslat & 0x7) << 4) - | ((bt & 0x1) << 3) - | ((bl & 0x7) << 0) - ); - - ddr->ddr_sdram_mode = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); -} -#endif - -/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */ -static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int init_value; /* Initialization value */ - -#ifdef CONFIG_MEM_INIT_VALUE - init_value = CONFIG_MEM_INIT_VALUE; -#else - init_value = 0xDEADBEEF; -#endif - ddr->ddr_data_init = init_value; -} - -/* - * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) - * The old controller on the 8540/60 doesn't have this register. - * Hope it's OK to set it (to 0) anyway. - */ -static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts) -{ - unsigned int clk_adjust; /* Clock adjust */ - - clk_adjust = popts->clk_adjust; - ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23; - debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); -} - -/* DDR Initialization Address (DDR_INIT_ADDR) */ -static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int init_addr = 0; /* Initialization address */ - - ddr->ddr_init_addr = init_addr; -} - -/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */ -static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int uia = 0; /* Use initialization address */ - unsigned int init_ext_addr = 0; /* Initialization address */ - - ddr->ddr_init_ext_addr = (0 - | ((uia & 0x1) << 31) - | (init_ext_addr & 0xF) - ); -} - -/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */ -static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts) -{ - unsigned int rwt = 0; /* Read-to-write turnaround for same CS */ - unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ - unsigned int rrt = 0; /* Read-to-read turnaround for same CS */ - unsigned int wwt = 0; /* Write-to-write turnaround for same CS */ - unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ - -#if defined(CONFIG_FSL_DDR3) - if (popts->burst_length == DDR_BL8) { - /* We set BL/2 for fixed BL8 */ - rrt = 0; /* BL/2 clocks */ - wwt = 0; /* BL/2 clocks */ - } else { - /* We need to set BL/2 + 2 to BC4 and OTF */ - rrt = 2; /* BL/2 + 2 clocks */ - wwt = 2; /* BL/2 + 2 clocks */ - } - dll_lock = 1; /* tDLLK = 512 clocks from spec */ -#endif - ddr->timing_cfg_4 = (0 - | ((rwt & 0xf) << 28) - | ((wrt & 0xf) << 24) - | ((rrt & 0xf) << 20) - | ((wwt & 0xf) << 16) - | (dll_lock & 0x3) - ); - debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); -} - -/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */ -static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency) -{ - unsigned int rodt_on = 0; /* Read to ODT on */ - unsigned int rodt_off = 0; /* Read to ODT off */ - unsigned int wodt_on = 0; /* Write to ODT on */ - unsigned int wodt_off = 0; /* Write to ODT off */ - -#if defined(CONFIG_FSL_DDR3) - /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */ - rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1; - rodt_off = 4; /* 4 clocks */ - wodt_on = 1; /* 1 clocks */ - wodt_off = 4; /* 4 clocks */ -#endif - - ddr->timing_cfg_5 = (0 - | ((rodt_on & 0x1f) << 24) - | ((rodt_off & 0x7) << 20) - | ((wodt_on & 0x1f) << 12) - | ((wodt_off & 0x7) << 8) - ); - debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); -} - -/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */ -static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) -{ - unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */ - /* Normal Operation Full Calibration Time (tZQoper) */ - unsigned int zqoper = 0; - /* Normal Operation Short Calibration Time (tZQCS) */ - unsigned int zqcs = 0; - - if (zq_en) { - zqinit = 9; /* 512 clocks */ - zqoper = 8; /* 256 clocks */ - zqcs = 6; /* 64 clocks */ - } - - ddr->ddr_zq_cntl = (0 - | ((zq_en & 0x1) << 31) - | ((zqinit & 0xF) << 24) - | ((zqoper & 0xF) << 16) - | ((zqcs & 0xF) << 8) - ); - debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); -} - -/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ -static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, - const memctl_options_t *popts) -{ - /* - * First DQS pulse rising edge after margining mode - * is programmed (tWL_MRD) - */ - unsigned int wrlvl_mrd = 0; - /* ODT delay after margining mode is programmed (tWL_ODTEN) */ - unsigned int wrlvl_odten = 0; - /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */ - unsigned int wrlvl_dqsen = 0; - /* WRLVL_SMPL: Write leveling sample time */ - unsigned int wrlvl_smpl = 0; - /* WRLVL_WLR: Write leveling repeition time */ - unsigned int wrlvl_wlr = 0; - /* WRLVL_START: Write leveling start time */ - unsigned int wrlvl_start = 0; - - /* suggest enable write leveling for DDR3 due to fly-by topology */ - if (wrlvl_en) { - /* tWL_MRD min = 40 nCK, we set it 64 */ - wrlvl_mrd = 0x6; - /* tWL_ODTEN 128 */ - wrlvl_odten = 0x7; - /* tWL_DQSEN min = 25 nCK, we set it 32 */ - wrlvl_dqsen = 0x5; - /* - * Write leveling sample time at least need 6 clocks - * higher than tWLO to allow enough time for progagation - * delay and sampling the prime data bits. - */ - wrlvl_smpl = 0xf; - /* - * Write leveling repetition time - * at least tWLO + 6 clocks clocks - * we set it 64 - */ - wrlvl_wlr = 0x6; - /* - * Write leveling start time - * The value use for the DQS_ADJUST for the first sample - * when write leveling is enabled. It probably needs to be - * overriden per platform. - */ - wrlvl_start = 0x8; - /* - * Override the write leveling sample and start time - * according to specific board - */ - if (popts->wrlvl_override) { - wrlvl_smpl = popts->wrlvl_sample; - wrlvl_start = popts->wrlvl_start; - } - } - - ddr->ddr_wrlvl_cntl = (0 - | ((wrlvl_en & 0x1) << 31) - | ((wrlvl_mrd & 0x7) << 24) - | ((wrlvl_odten & 0x7) << 20) - | ((wrlvl_dqsen & 0x7) << 16) - | ((wrlvl_smpl & 0xf) << 12) - | ((wrlvl_wlr & 0x7) << 8) - | ((wrlvl_start & 0x1F) << 0) - ); - debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); - ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2; - debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2); - ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3; - debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3); - -} - -/* DDR Self Refresh Counter (DDR_SR_CNTR) */ -static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) -{ - /* Self Refresh Idle Threshold */ - ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; -} - -static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) -{ - if (popts->addr_hash) { - ddr->ddr_eor = 0x40000000; /* address hash enable */ - puts("Address hashing enabled.\n"); - } -} - -static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) -{ - ddr->ddr_cdr1 = popts->ddr_cdr1; - debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1); -} - -static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) -{ - ddr->ddr_cdr2 = popts->ddr_cdr2; - debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2); -} - -unsigned int -check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int res = 0; - - /* - * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are - * not set at the same time. - */ - if (ddr->ddr_sdram_cfg & 0x10000000 - && ddr->ddr_sdram_cfg & 0x00008000) { - printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] " - " should not be set at the same time.\n"); - res++; - } - - return res; -} - -unsigned int -compute_fsl_memctl_config_regs(const memctl_options_t *popts, - fsl_ddr_cfg_regs_t *ddr, - const common_timing_params_t *common_dimm, - const dimm_params_t *dimm_params, - unsigned int dbw_cap_adj, - unsigned int size_only) -{ - unsigned int i; - unsigned int cas_latency; - unsigned int additive_latency; - unsigned int sr_it; - unsigned int zq_en; - unsigned int wrlvl_en; - unsigned int ip_rev = 0; - unsigned int unq_mrs_en = 0; - int cs_en = 1; - - memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); - - if (common_dimm == NULL) { - printf("Error: subset DIMM params struct null pointer\n"); - return 1; - } - - /* - * Process overrides first. - * - * FIXME: somehow add dereated caslat to this - */ - cas_latency = (popts->cas_latency_override) - ? popts->cas_latency_override_value - : common_dimm->lowest_common_SPD_caslat; - - additive_latency = (popts->additive_latency_override) - ? popts->additive_latency_override_value - : common_dimm->additive_latency; - - sr_it = (popts->auto_self_refresh_en) - ? popts->sr_it - : 0; - /* ZQ calibration */ - zq_en = (popts->zq_en) ? 1 : 0; - /* write leveling */ - wrlvl_en = (popts->wrlvl_en) ? 1 : 0; - - /* Chip Select Memory Bounds (CSn_BNDS) */ - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - unsigned long long ea, sa; - unsigned int cs_per_dimm - = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR; - unsigned int dimm_number - = i / cs_per_dimm; - unsigned long long rank_density - = dimm_params[dimm_number].rank_density >> dbw_cap_adj; - - if (dimm_params[dimm_number].n_ranks == 0) { - debug("Skipping setup of CS%u " - "because n_ranks on DIMM %u is 0\n", i, dimm_number); - continue; - } - if (popts->memctl_interleaving) { - switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { - case FSL_DDR_CS0_CS1_CS2_CS3: - break; - case FSL_DDR_CS0_CS1: - case FSL_DDR_CS0_CS1_AND_CS2_CS3: - if (i > 1) - cs_en = 0; - break; - case FSL_DDR_CS2_CS3: - default: - if (i > 0) - cs_en = 0; - break; - } - sa = common_dimm->base_address; - ea = sa + common_dimm->total_mem - 1; - } else if (!popts->memctl_interleaving) { - /* - * If memory interleaving between controllers is NOT - * enabled, the starting address for each memory - * controller is distinct. However, because rank - * interleaving is enabled, the starting and ending - * addresses of the total memory on that memory - * controller needs to be programmed into its - * respective CS0_BNDS. - */ - switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { - case FSL_DDR_CS0_CS1_CS2_CS3: - sa = common_dimm->base_address; - ea = sa + common_dimm->total_mem - 1; - break; - case FSL_DDR_CS0_CS1_AND_CS2_CS3: - if ((i >= 2) && (dimm_number == 0)) { - sa = dimm_params[dimm_number].base_address + - 2 * rank_density; - ea = sa + 2 * rank_density - 1; - } else { - sa = dimm_params[dimm_number].base_address; - ea = sa + 2 * rank_density - 1; - } - break; - case FSL_DDR_CS0_CS1: - if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { - sa = dimm_params[dimm_number].base_address; - ea = sa + rank_density - 1; - if (i != 1) - sa += (i % cs_per_dimm) * rank_density; - ea += (i % cs_per_dimm) * rank_density; - } else { - sa = 0; - ea = 0; - } - if (i == 0) - ea += rank_density; - break; - case FSL_DDR_CS2_CS3: - if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { - sa = dimm_params[dimm_number].base_address; - ea = sa + rank_density - 1; - if (i != 3) - sa += (i % cs_per_dimm) * rank_density; - ea += (i % cs_per_dimm) * rank_density; - } else { - sa = 0; - ea = 0; - } - if (i == 2) - ea += (rank_density >> dbw_cap_adj); - break; - default: /* No bank(chip-select) interleaving */ - sa = dimm_params[dimm_number].base_address; - ea = sa + rank_density - 1; - if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { - sa += (i % cs_per_dimm) * rank_density; - ea += (i % cs_per_dimm) * rank_density; - } else { - sa = 0; - ea = 0; - } - break; - } - } - - sa >>= 24; - ea >>= 24; - - if (cs_en) { - ddr->cs[i].bnds = (0 - | ((sa & 0xFFF) << 16)/* starting address MSB */ - | ((ea & 0xFFF) << 0) /* ending address MSB */ - ); - } else { - /* setting bnds to 0xffffffff for inactive CS */ - ddr->cs[i].bnds = 0xffffffff; - } - - debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); - set_csn_config(dimm_number, i, ddr, popts, dimm_params); - set_csn_config_2(i, ddr); - } - - /* - * In the case we only need to compute the ddr sdram size, we only need - * to set csn registers, so return from here. - */ - if (size_only) - return 0; - - set_ddr_eor(ddr, popts); - -#if !defined(CONFIG_FSL_DDR1) - set_timing_cfg_0(ddr, popts, dimm_params); -#endif - - set_timing_cfg_3(ddr, popts, common_dimm, cas_latency); - set_timing_cfg_1(ddr, popts, common_dimm, cas_latency); - set_timing_cfg_2(ddr, popts, common_dimm, - cas_latency, additive_latency); - - set_ddr_cdr1(ddr, popts); - set_ddr_cdr2(ddr, popts); - set_ddr_sdram_cfg(ddr, popts, common_dimm); - ip_rev = fsl_ddr_get_version(); - if (ip_rev > 0x40400) - unq_mrs_en = 1; - - set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en); - set_ddr_sdram_mode(ddr, popts, common_dimm, - cas_latency, additive_latency, unq_mrs_en); - set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en); - set_ddr_sdram_interval(ddr, popts, common_dimm); - set_ddr_data_init(ddr); - set_ddr_sdram_clk_cntl(ddr, popts); - set_ddr_init_addr(ddr); - set_ddr_init_ext_addr(ddr); - set_timing_cfg_4(ddr, popts); - set_timing_cfg_5(ddr, cas_latency); - - set_ddr_zq_cntl(ddr, zq_en); - set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); - - set_ddr_sr_cntr(ddr, sr_it); - - set_ddr_sdram_rcw(ddr, popts, common_dimm); - -#ifdef CONFIG_SYS_FSL_DDR_EMU - /* disble DDR training for emulator */ - ddr->debug[2] = 0x00000400; - ddr->debug[4] = 0xff800000; -#endif - return check_fsl_memctl_config_regs(ddr); -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h deleted file mode 100644 index e3b414e..0000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright 2008-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#ifndef FSL_DDR_MAIN_H -#define FSL_DDR_MAIN_H - -#include <asm/fsl_ddr_sdram.h> -#include <asm/fsl_ddr_dimm_params.h> - -#include "common_timing_params.h" - -#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) -/* - * Bind the main DDR setup driver's generic names - * to this specific DDR technology. - */ -static __inline__ int -compute_dimm_parameters(const generic_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) -{ - return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); -} -#endif - -/* - * Data Structures - * - * All data structures have to be on the stack - */ -#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS -#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR - -typedef struct { - generic_spd_eeprom_t - spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; - struct dimm_params_s - dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; - memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; - common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; - fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; -} fsl_ddr_info_t; - -/* Compute steps */ -#define STEP_GET_SPD (1 << 0) -#define STEP_COMPUTE_DIMM_PARMS (1 << 1) -#define STEP_COMPUTE_COMMON_PARMS (1 << 2) -#define STEP_GATHER_OPTS (1 << 3) -#define STEP_ASSIGN_ADDRESSES (1 << 4) -#define STEP_COMPUTE_REGS (1 << 5) -#define STEP_PROGRAM_REGS (1 << 6) -#define STEP_ALL 0xFFF - -unsigned long long -fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, - unsigned int size_only); - -const char *step_to_string(unsigned int step); - -unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts, - fsl_ddr_cfg_regs_t *ddr, - const common_timing_params_t *common_dimm, - const dimm_params_t *dimm_parameters, - unsigned int dbw_capacity_adjust, - unsigned int size_only); -unsigned int compute_lowest_common_dimm_parameters( - const dimm_params_t *dimm_params, - common_timing_params_t *outpdimm, - unsigned int number_of_dimms); -unsigned int populate_memctl_options(int all_dimms_registered, - memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num); -void check_interleaving_options(fsl_ddr_info_t *pinfo); - -unsigned int mclk_to_picos(unsigned int mclk); -unsigned int get_memory_clk_period_ps(void); -unsigned int picos_to_mclk(unsigned int picos); -void fsl_ddr_set_lawbar( - const common_timing_params_t *memctl_common_params, - unsigned int memctl_interleaved, - unsigned int ctrl_num); - -int fsl_ddr_interactive_env_var_exists(void); -unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); -void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num); - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); -unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); - -/* processor specific function */ -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num, int step); - -/* board specific function */ -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number); -#endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c deleted file mode 100644 index f137fce..0000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c +++ /dev/null @@ -1,343 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> -#include <asm/fsl_ddr_sdram.h> - -#include "ddr.h" - -/* - * Calculate the Density of each Physical Rank. - * Returned size is in bytes. - * - * Study these table from Byte 31 of JEDEC SPD Spec. - * - * DDR I DDR II - * Bit Size Size - * --- ----- ------ - * 7 high 512MB 512MB - * 6 256MB 256MB - * 5 128MB 128MB - * 4 64MB 16GB - * 3 32MB 8GB - * 2 16MB 4GB - * 1 2GB 2GB - * 0 low 1GB 1GB - * - * Reorder Table to be linear by stripping the bottom - * 2 or 5 bits off and shifting them up to the top. - */ - -static unsigned long long -compute_ranksize(unsigned int mem_type, unsigned char row_dens) -{ - unsigned long long bsize; - - /* Bottom 2 bits up to the top. */ - bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)); - bsize <<= 24ULL; - debug("DDR: DDR I rank density = 0x%16llx\n", bsize); - - return bsize; -} - -/* - * Convert a two-nibble BCD value into a cycle time. - * While the spec calls for nano-seconds, picos are returned. - * - * This implements the tables for bytes 9, 23 and 25 for both - * DDR I and II. No allowance for distinguishing the invalid - * fields absent for DDR I yet present in DDR II is made. - * (That is, cycle times of .25, .33, .66 and .75 ns are - * allowed for both DDR II and I.) - */ -static unsigned int -convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) -{ - /* Table look up the lower nibble, allow DDR I & II. */ - unsigned int tenths_ps[16] = { - 0, - 100, - 200, - 300, - 400, - 500, - 600, - 700, - 800, - 900, - 250, /* This and the next 3 entries valid ... */ - 330, /* ... only for tCK calculations. */ - 660, - 750, - 0, /* undefined */ - 0 /* undefined */ - }; - - unsigned int whole_ns = (spd_val & 0xF0) >> 4; - unsigned int tenth_ns = spd_val & 0x0F; - unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; - - return ps; -} - -static unsigned int -convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val) -{ - unsigned int tenth_ns = (spd_val & 0xF0) >> 4; - unsigned int hundredth_ns = spd_val & 0x0F; - unsigned int ps = tenth_ns * 100 + hundredth_ns * 10; - - return ps; -} - -static unsigned int byte40_table_ps[8] = { - 0, - 250, - 330, - 500, - 660, - 750, - 0, /* supposed to be RFC, but not sure what that means */ - 0 /* Undefined */ -}; - -static unsigned int -compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc) -{ - unsigned int trfc_ps; - - trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000 - + byte40_table_ps[(trctrfc_ext >> 1) & 0x7]; - - return trfc_ps; -} - -static unsigned int -compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc) -{ - unsigned int trc_ps; - - trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7]; - - return trc_ps; -} - -/* - * tCKmax from DDR I SPD Byte 43 - * - * Bits 7:2 == whole ns - * Bits 1:0 == quarter ns - * 00 == 0.00 ns - * 01 == 0.25 ns - * 10 == 0.50 ns - * 11 == 0.75 ns - * - * Returns picoseconds. - */ -static unsigned int -compute_tckmax_from_spd_ps(unsigned int byte43) -{ - return (byte43 >> 2) * 1000 + (byte43 & 0x3) * 250; -} - -/* - * Determine Refresh Rate. Ignore self refresh bit on DDR I. - * Table from SPD Spec, Byte 12, converted to picoseconds and - * filled in with "default" normal values. - */ -static unsigned int -determine_refresh_rate_ps(const unsigned int spd_refresh) -{ - unsigned int refresh_time_ps[8] = { - 15625000, /* 0 Normal 1.00x */ - 3900000, /* 1 Reduced .25x */ - 7800000, /* 2 Extended .50x */ - 31300000, /* 3 Extended 2.00x */ - 62500000, /* 4 Extended 4.00x */ - 125000000, /* 5 Extended 8.00x */ - 15625000, /* 6 Normal 1.00x filler */ - 15625000, /* 7 Normal 1.00x filler */ - }; - - return refresh_time_ps[spd_refresh & 0x7]; -} - -/* - * The purpose of this function is to compute a suitable - * CAS latency given the DRAM clock period. The SPD only - * defines at most 3 CAS latencies. Typically the slower in - * frequency the DIMM runs at, the shorter its CAS latency can be. - * If the DIMM is operating at a sufficiently low frequency, - * it may be able to run at a CAS latency shorter than the - * shortest SPD-defined CAS latency. - * - * If a CAS latency is not found, 0 is returned. - * - * Do this by finding in the standard speed bin table the longest - * tCKmin that doesn't exceed the value of mclk_ps (tCK). - * - * An assumption made is that the SDRAM device allows the - * CL to be programmed for a value that is lower than those - * advertised by the SPD. This is not always the case, - * as those modes not defined in the SPD are optional. - * - * CAS latency de-rating based upon values JEDEC Standard No. 79-E - * Table 11. - * - * ordinal 2, ddr1_speed_bins[1] contains tCK for CL=2 - */ - /* CL2.0 CL2.5 CL3.0 */ -unsigned short ddr1_speed_bins[] = {0, 7500, 6000, 5000 }; - -unsigned int -compute_derated_DDR1_CAS_latency(unsigned int mclk_ps) -{ - const unsigned int num_speed_bins = ARRAY_SIZE(ddr1_speed_bins); - unsigned int lowest_tCKmin_found = 0; - unsigned int lowest_tCKmin_CL = 0; - unsigned int i; - - debug("mclk_ps = %u\n", mclk_ps); - - for (i = 0; i < num_speed_bins; i++) { - unsigned int x = ddr1_speed_bins[i]; - debug("i=%u, x = %u, lowest_tCKmin_found = %u\n", - i, x, lowest_tCKmin_found); - if (x && lowest_tCKmin_found <= x && x <= mclk_ps) { - lowest_tCKmin_found = x; - lowest_tCKmin_CL = i + 1; - } - } - - debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL); - - return lowest_tCKmin_CL; -} - -/* - * ddr_compute_dimm_parameters for DDR1 SPD - * - * Compute DIMM parameters based upon the SPD information in spd. - * Writes the results to the dimm_params_t structure pointed by pdimm. - * - * FIXME: use #define for the retvals - */ -unsigned int -ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) -{ - unsigned int retval; - - if (spd->mem_type) { - if (spd->mem_type != SPD_MEMTYPE_DDR) { - printf("DIMM %u: is not a DDR1 SPD.\n", dimm_number); - return 1; - } - } else { - memset(pdimm, 0, sizeof(dimm_params_t)); - return 1; - } - - retval = ddr1_spd_check(spd); - if (retval) { - printf("DIMM %u: failed checksum\n", dimm_number); - return 2; - } - - /* - * The part name in ASCII in the SPD EEPROM is not null terminated. - * Guarantee null termination here by presetting all bytes to 0 - * and copying the part name in ASCII from the SPD onto it - */ - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); - - /* DIMM organization parameters */ - pdimm->n_ranks = spd->nrows; - pdimm->rank_density = compute_ranksize(spd->mem_type, spd->bank_dens); - pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; - pdimm->data_width = spd->dataw_lsb; - pdimm->primary_sdram_width = spd->primw; - pdimm->ec_sdram_width = spd->ecw; - - /* - * FIXME: Need to determine registered_dimm status. - * 1 == register buffered - * 0 == unbuffered - */ - pdimm->registered_dimm = 0; /* unbuffered */ - - /* SDRAM device parameters */ - pdimm->n_row_addr = spd->nrow_addr; - pdimm->n_col_addr = spd->ncol_addr; - pdimm->n_banks_per_sdram_device = spd->nbanks; - pdimm->edc_config = spd->config; - pdimm->burst_lengths_bitmask = spd->burstl; - pdimm->row_density = spd->bank_dens; - - /* - * Calculate the Maximum Data Rate based on the Minimum Cycle time. - * The SPD clk_cycle field (tCKmin) is measured in tenths of - * nanoseconds and represented as BCD. - */ - pdimm->tckmin_x_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle); - pdimm->tckmin_x_minus_1_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2); - pdimm->tckmin_x_minus_2_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3); - - pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax); - - /* - * Compute CAS latencies defined by SPD - * The SPD caslat_x should have at least 1 and at most 3 bits set. - * - * If cas_lat after masking is 0, the __ilog2 function returns - * 255 into the variable. This behavior is abused once. - */ - pdimm->caslat_x = __ilog2(spd->cas_lat); - pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_x)); - pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_x) - & ~(1 << pdimm->caslat_x_minus_1)); - - /* Compute CAS latencies below that defined by SPD */ - pdimm->caslat_lowest_derated - = compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps()); - - /* Compute timing parameters */ - pdimm->trcd_ps = spd->trcd * 250; - pdimm->trp_ps = spd->trp * 250; - pdimm->tras_ps = spd->tras * 1000; - - pdimm->twr_ps = mclk_to_picos(3); - pdimm->twtr_ps = mclk_to_picos(1); - pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc); - - pdimm->trrd_ps = spd->trrd * 250; - pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc); - - pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh); - - pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); - pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); - pdimm->tds_ps - = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup); - pdimm->tdh_ps - = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); - - pdimm->trtp_ps = mclk_to_picos(2); /* By the book. */ - pdimm->tdqsq_max_ps = spd->tdqsq * 10; - pdimm->tqhs_ps = spd->tqhs * 10; - - return 0; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c deleted file mode 100644 index e4d02e8..0000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> -#include <asm/fsl_ddr_sdram.h> - -#include "ddr.h" -/* - * Calculate the Density of each Physical Rank. - * Returned size is in bytes. - * - * Study these table from Byte 31 of JEDEC SPD Spec. - * - * DDR I DDR II - * Bit Size Size - * --- ----- ------ - * 7 high 512MB 512MB - * 6 256MB 256MB - * 5 128MB 128MB - * 4 64MB 16GB - * 3 32MB 8GB - * 2 16MB 4GB - * 1 2GB 2GB - * 0 low 1GB 1GB - * - * Reorder Table to be linear by stripping the bottom - * 2 or 5 bits off and shifting them up to the top. - * - */ -static unsigned long long -compute_ranksize(unsigned int mem_type, unsigned char row_dens) -{ - unsigned long long bsize; - - /* Bottom 5 bits up to the top. */ - bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)); - bsize <<= 27ULL; - debug("DDR: DDR II rank density = 0x%16llx\n", bsize); - - return bsize; -} - -/* - * Convert a two-nibble BCD value into a cycle time. - * While the spec calls for nano-seconds, picos are returned. - * - * This implements the tables for bytes 9, 23 and 25 for both - * DDR I and II. No allowance for distinguishing the invalid - * fields absent for DDR I yet present in DDR II is made. - * (That is, cycle times of .25, .33, .66 and .75 ns are - * allowed for both DDR II and I.) - */ -static unsigned int -convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) -{ - /* Table look up the lower nibble, allow DDR I & II. */ - unsigned int tenths_ps[16] = { - 0, - 100, - 200, - 300, - 400, - 500, - 600, - 700, - 800, - 900, - 250, /* This and the next 3 entries valid ... */ - 330, /* ... only for tCK calculations. */ - 660, - 750, - 0, /* undefined */ - 0 /* undefined */ - }; - - unsigned int whole_ns = (spd_val & 0xF0) >> 4; - unsigned int tenth_ns = spd_val & 0x0F; - unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; - - return ps; -} - -static unsigned int -convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val) -{ - unsigned int tenth_ns = (spd_val & 0xF0) >> 4; - unsigned int hundredth_ns = spd_val & 0x0F; - unsigned int ps = tenth_ns * 100 + hundredth_ns * 10; - - return ps; -} - -static unsigned int byte40_table_ps[8] = { - 0, - 250, - 330, - 500, - 660, - 750, - 0, /* supposed to be RFC, but not sure what that means */ - 0 /* Undefined */ -}; - -static unsigned int -compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc) -{ - unsigned int trfc_ps; - - trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000 - + byte40_table_ps[(trctrfc_ext >> 1) & 0x7]; - - return trfc_ps; -} - -static unsigned int -compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc) -{ - unsigned int trc_ps; - - trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7]; - - return trc_ps; -} - -/* - * Determine Refresh Rate. Ignore self refresh bit on DDR I. - * Table from SPD Spec, Byte 12, converted to picoseconds and - * filled in with "default" normal values. - */ -static unsigned int -determine_refresh_rate_ps(const unsigned int spd_refresh) -{ - unsigned int refresh_time_ps[8] = { - 15625000, /* 0 Normal 1.00x */ - 3900000, /* 1 Reduced .25x */ - 7800000, /* 2 Extended .50x */ - 31300000, /* 3 Extended 2.00x */ - 62500000, /* 4 Extended 4.00x */ - 125000000, /* 5 Extended 8.00x */ - 15625000, /* 6 Normal 1.00x filler */ - 15625000, /* 7 Normal 1.00x filler */ - }; - - return refresh_time_ps[spd_refresh & 0x7]; -} - -/* - * The purpose of this function is to compute a suitable - * CAS latency given the DRAM clock period. The SPD only - * defines at most 3 CAS latencies. Typically the slower in - * frequency the DIMM runs at, the shorter its CAS latency can. - * be. If the DIMM is operating at a sufficiently low frequency, - * it may be able to run at a CAS latency shorter than the - * shortest SPD-defined CAS latency. - * - * If a CAS latency is not found, 0 is returned. - * - * Do this by finding in the standard speed bin table the longest - * tCKmin that doesn't exceed the value of mclk_ps (tCK). - * - * An assumption made is that the SDRAM device allows the - * CL to be programmed for a value that is lower than those - * advertised by the SPD. This is not always the case, - * as those modes not defined in the SPD are optional. - * - * CAS latency de-rating based upon values JEDEC Standard No. 79-2C - * Table 40, "DDR2 SDRAM stanadard speed bins and tCK, tRCD, tRP, tRAS, - * and tRC for corresponding bin" - * - * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3 - * Not certain if any good value exists for CL=2 - */ - /* CL2 CL3 CL4 CL5 CL6 CL7*/ -unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500, 1875 }; - -unsigned int -compute_derated_DDR2_CAS_latency(unsigned int mclk_ps) -{ - const unsigned int num_speed_bins = ARRAY_SIZE(ddr2_speed_bins); - unsigned int lowest_tCKmin_found = 0; - unsigned int lowest_tCKmin_CL = 0; - unsigned int i; - - debug("mclk_ps = %u\n", mclk_ps); - - for (i = 0; i < num_speed_bins; i++) { - unsigned int x = ddr2_speed_bins[i]; - debug("i=%u, x = %u, lowest_tCKmin_found = %u\n", - i, x, lowest_tCKmin_found); - if (x && x <= mclk_ps && x >= lowest_tCKmin_found ) { - lowest_tCKmin_found = x; - lowest_tCKmin_CL = i + 2; - } - } - - debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL); - - return lowest_tCKmin_CL; -} - -/* - * ddr_compute_dimm_parameters for DDR2 SPD - * - * Compute DIMM parameters based upon the SPD information in spd. - * Writes the results to the dimm_params_t structure pointed by pdimm. - * - * FIXME: use #define for the retvals - */ -unsigned int -ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) -{ - unsigned int retval; - - if (spd->mem_type) { - if (spd->mem_type != SPD_MEMTYPE_DDR2) { - printf("DIMM %u: is not a DDR2 SPD.\n", dimm_number); - return 1; - } - } else { - memset(pdimm, 0, sizeof(dimm_params_t)); - return 1; - } - - retval = ddr2_spd_check(spd); - if (retval) { - printf("DIMM %u: failed checksum\n", dimm_number); - return 2; - } - - /* - * The part name in ASCII in the SPD EEPROM is not null terminated. - * Guarantee null termination here by presetting all bytes to 0 - * and copying the part name in ASCII from the SPD onto it - */ - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); - - /* DIMM organization parameters */ - pdimm->n_ranks = (spd->mod_ranks & 0x7) + 1; - pdimm->rank_density = compute_ranksize(spd->mem_type, spd->rank_dens); - pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; - pdimm->data_width = spd->dataw; - pdimm->primary_sdram_width = spd->primw; - pdimm->ec_sdram_width = spd->ecw; - - /* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */ - switch (spd->dimm_type) { - case DDR2_SPD_DIMMTYPE_RDIMM: - case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM: - case DDR2_SPD_DIMMTYPE_MINI_RDIMM: - /* Registered/buffered DIMMs */ - pdimm->registered_dimm = 1; - break; - - case DDR2_SPD_DIMMTYPE_UDIMM: - case DDR2_SPD_DIMMTYPE_SO_DIMM: - case DDR2_SPD_DIMMTYPE_MICRO_DIMM: - case DDR2_SPD_DIMMTYPE_MINI_UDIMM: - /* Unbuffered DIMMs */ - pdimm->registered_dimm = 0; - break; - - case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM: - default: - printf("unknown dimm_type 0x%02X\n", spd->dimm_type); - return 1; - } - - /* SDRAM device parameters */ - pdimm->n_row_addr = spd->nrow_addr; - pdimm->n_col_addr = spd->ncol_addr; - pdimm->n_banks_per_sdram_device = spd->nbanks; - pdimm->edc_config = spd->config; - pdimm->burst_lengths_bitmask = spd->burstl; - pdimm->row_density = spd->rank_dens; - - /* - * Calculate the Maximum Data Rate based on the Minimum Cycle time. - * The SPD clk_cycle field (tCKmin) is measured in tenths of - * nanoseconds and represented as BCD. - */ - pdimm->tckmin_x_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle); - pdimm->tckmin_x_minus_1_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2); - pdimm->tckmin_x_minus_2_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3); - - pdimm->tckmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax); - - /* - * Compute CAS latencies defined by SPD - * The SPD caslat_x should have at least 1 and at most 3 bits set. - * - * If cas_lat after masking is 0, the __ilog2 function returns - * 255 into the variable. This behavior is abused once. - */ - pdimm->caslat_x = __ilog2(spd->cas_lat); - pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_x)); - pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_x) - & ~(1 << pdimm->caslat_x_minus_1)); - - /* Compute CAS latencies below that defined by SPD */ - pdimm->caslat_lowest_derated - = compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps()); - - /* Compute timing parameters */ - pdimm->trcd_ps = spd->trcd * 250; - pdimm->trp_ps = spd->trp * 250; - pdimm->tras_ps = spd->tras * 1000; - - pdimm->twr_ps = spd->twr * 250; - pdimm->twtr_ps = spd->twtr * 250; - pdimm->trfc_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc); - - pdimm->trrd_ps = spd->trrd * 250; - pdimm->trc_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc); - - pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh); - - pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); - pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); - pdimm->tds_ps - = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup); - pdimm->tdh_ps - = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); - - pdimm->trtp_ps = spd->trtp * 250; - pdimm->tdqsq_max_ps = spd->tdqsq * 10; - pdimm->tqhs_ps = spd->tqhs * 10; - - return 0; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c deleted file mode 100644 index 4c8645d..0000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ /dev/null @@ -1,341 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * Dave Liu <daveliu@freescale.com> - * - * calculate the organization and timing parameter - * from ddr3 spd, please refer to the spec - * JEDEC standard No.21-C 4_01_02_11R18.pdf - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> -#include <asm/fsl_ddr_sdram.h> - -#include "ddr.h" - -/* - * Calculate the Density of each Physical Rank. - * Returned size is in bytes. - * - * each rank size = - * sdram capacity(bit) / 8 * primary bus width / sdram width - * - * where: sdram capacity = spd byte4[3:0] - * primary bus width = spd byte8[2:0] - * sdram width = spd byte7[2:0] - * - * SPD byte4 - sdram density and banks - * bit[3:0] size(bit) size(byte) - * 0000 256Mb 32MB - * 0001 512Mb 64MB - * 0010 1Gb 128MB - * 0011 2Gb 256MB - * 0100 4Gb 512MB - * 0101 8Gb 1GB - * 0110 16Gb 2GB - * - * SPD byte8 - module memory bus width - * bit[2:0] primary bus width - * 000 8bits - * 001 16bits - * 010 32bits - * 011 64bits - * - * SPD byte7 - module organiztion - * bit[2:0] sdram device width - * 000 4bits - * 001 8bits - * 010 16bits - * 011 32bits - * - */ -static unsigned long long -compute_ranksize(const ddr3_spd_eeprom_t *spd) -{ - unsigned long long bsize; - - int nbit_sdram_cap_bsize = 0; - int nbit_primary_bus_width = 0; - int nbit_sdram_width = 0; - - if ((spd->density_banks & 0xf) < 7) - nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28; - if ((spd->bus_width & 0x7) < 4) - nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; - if ((spd->organization & 0x7) < 4) - nbit_sdram_width = (spd->organization & 0x7) + 2; - - bsize = 1ULL << (nbit_sdram_cap_bsize - 3 - + nbit_primary_bus_width - nbit_sdram_width); - - debug("DDR: DDR III rank density = 0x%16llx\n", bsize); - - return bsize; -} - -/* - * ddr_compute_dimm_parameters for DDR3 SPD - * - * Compute DIMM parameters based upon the SPD information in spd. - * Writes the results to the dimm_params_t structure pointed by pdimm. - * - */ -unsigned int -ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) -{ - unsigned int retval; - unsigned int mtb_ps; - int ftb_10th_ps; - int i; - - if (spd->mem_type) { - if (spd->mem_type != SPD_MEMTYPE_DDR3) { - printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number); - return 1; - } - } else { - memset(pdimm, 0, sizeof(dimm_params_t)); - return 1; - } - - retval = ddr3_spd_check(spd); - if (retval) { - printf("DIMM %u: failed checksum\n", dimm_number); - return 2; - } - - /* - * The part name in ASCII in the SPD EEPROM is not null terminated. - * Guarantee null termination here by presetting all bytes to 0 - * and copying the part name in ASCII from the SPD onto it - */ - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - if ((spd->info_size_crc & 0xF) > 1) - memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); - - /* DIMM organization parameters */ - pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1; - pdimm->rank_density = compute_ranksize(spd); - pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; - pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); - if ((spd->bus_width >> 3) & 0x3) - pdimm->ec_sdram_width = 8; - else - pdimm->ec_sdram_width = 0; - pdimm->data_width = pdimm->primary_sdram_width - + pdimm->ec_sdram_width; - pdimm->device_width = 1 << ((spd->organization & 0x7) + 2); - - /* These are the types defined by the JEDEC DDR3 SPD spec */ - pdimm->mirrored_dimm = 0; - pdimm->registered_dimm = 0; - switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) { - case DDR3_SPD_MODULETYPE_RDIMM: - case DDR3_SPD_MODULETYPE_MINI_RDIMM: - case DDR3_SPD_MODULETYPE_72B_SO_RDIMM: - /* Registered/buffered DIMMs */ - pdimm->registered_dimm = 1; - for (i = 0; i < 16; i += 2) { - u8 rcw = spd->mod_section.registered.rcw[i/2]; - pdimm->rcw[i] = (rcw >> 0) & 0x0F; - pdimm->rcw[i+1] = (rcw >> 4) & 0x0F; - } - break; - - case DDR3_SPD_MODULETYPE_UDIMM: - case DDR3_SPD_MODULETYPE_SO_DIMM: - case DDR3_SPD_MODULETYPE_MICRO_DIMM: - case DDR3_SPD_MODULETYPE_MINI_UDIMM: - case DDR3_SPD_MODULETYPE_MINI_CDIMM: - case DDR3_SPD_MODULETYPE_72B_SO_UDIMM: - case DDR3_SPD_MODULETYPE_72B_SO_CDIMM: - case DDR3_SPD_MODULETYPE_LRDIMM: - case DDR3_SPD_MODULETYPE_16B_SO_DIMM: - case DDR3_SPD_MODULETYPE_32B_SO_DIMM: - /* Unbuffered DIMMs */ - if (spd->mod_section.unbuffered.addr_mapping & 0x1) - pdimm->mirrored_dimm = 1; - break; - - default: - printf("unknown module_type 0x%02X\n", spd->module_type); - return 1; - } - - /* SDRAM device parameters */ - pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12; - pdimm->n_col_addr = (spd->addressing & 0x7) + 9; - pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7); - - /* - * The SPD spec has not the ECC bit, - * We consider the DIMM as ECC capability - * when the extension bus exist - */ - if (pdimm->ec_sdram_width) - pdimm->edc_config = 0x02; - else - pdimm->edc_config = 0x00; - - /* - * The SPD spec has not the burst length byte - * but DDR3 spec has nature BL8 and BC4, - * BL8 -bit3, BC4 -bit2 - */ - pdimm->burst_lengths_bitmask = 0x0c; - pdimm->row_density = __ilog2(pdimm->rank_density); - - /* MTB - medium timebase - * The unit in the SPD spec is ns, - * We convert it to ps. - * eg: MTB = 0.125ns (125ps) - */ - mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor; - pdimm->mtb_ps = mtb_ps; - - /* - * FTB - fine timebase - * use 1/10th of ps as our unit to avoid floating point - * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps - */ - ftb_10th_ps = - ((spd->ftb_div & 0xf0) >> 4) * 10 / (spd->ftb_div & 0x0f); - pdimm->ftb_10th_ps = ftb_10th_ps; - /* - * sdram minimum cycle time - * we assume the MTB is 0.125ns - * eg: - * tck_min=15 MTB (1.875ns) ->DDR3-1066 - * =12 MTB (1.5ns) ->DDR3-1333 - * =10 MTB (1.25ns) ->DDR3-1600 - */ - pdimm->tckmin_x_ps = spd->tck_min * mtb_ps + - (spd->fine_tck_min * ftb_10th_ps) / 10; - - /* - * CAS latency supported - * bit4 - CL4 - * bit5 - CL5 - * bit18 - CL18 - */ - pdimm->caslat_x = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4; - - /* - * min CAS latency time - * eg: taa_min = - * DDR3-800D 100 MTB (12.5ns) - * DDR3-1066F 105 MTB (13.125ns) - * DDR3-1333H 108 MTB (13.5ns) - * DDR3-1600H 90 MTB (11.25ns) - */ - pdimm->taa_ps = spd->taa_min * mtb_ps + - (spd->fine_taa_min * ftb_10th_ps) / 10; - - /* - * min write recovery time - * eg: - * twr_min = 120 MTB (15ns) -> all speed grades. - */ - pdimm->twr_ps = spd->twr_min * mtb_ps; - - /* - * min RAS to CAS delay time - * eg: trcd_min = - * DDR3-800 100 MTB (12.5ns) - * DDR3-1066F 105 MTB (13.125ns) - * DDR3-1333H 108 MTB (13.5ns) - * DDR3-1600H 90 MTB (11.25) - */ - pdimm->trcd_ps = spd->trcd_min * mtb_ps + - (spd->fine_trcd_min * ftb_10th_ps) / 10; - - /* - * min row active to row active delay time - * eg: trrd_min = - * DDR3-800(1KB page) 80 MTB (10ns) - * DDR3-1333(1KB page) 48 MTB (6ns) - */ - pdimm->trrd_ps = spd->trrd_min * mtb_ps; - - /* - * min row precharge delay time - * eg: trp_min = - * DDR3-800D 100 MTB (12.5ns) - * DDR3-1066F 105 MTB (13.125ns) - * DDR3-1333H 108 MTB (13.5ns) - * DDR3-1600H 90 MTB (11.25ns) - */ - pdimm->trp_ps = spd->trp_min * mtb_ps + - (spd->fine_trp_min * ftb_10th_ps) / 10; - - /* min active to precharge delay time - * eg: tRAS_min = - * DDR3-800D 300 MTB (37.5ns) - * DDR3-1066F 300 MTB (37.5ns) - * DDR3-1333H 288 MTB (36ns) - * DDR3-1600H 280 MTB (35ns) - */ - pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb) - * mtb_ps; - /* - * min active to actice/refresh delay time - * eg: tRC_min = - * DDR3-800D 400 MTB (50ns) - * DDR3-1066F 405 MTB (50.625ns) - * DDR3-1333H 396 MTB (49.5ns) - * DDR3-1600H 370 MTB (46.25ns) - */ - pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb) - * mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10; - /* - * min refresh recovery delay time - * eg: tRFC_min = - * 512Mb 720 MTB (90ns) - * 1Gb 880 MTB (110ns) - * 2Gb 1280 MTB (160ns) - */ - pdimm->trfc_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb) - * mtb_ps; - /* - * min internal write to read command delay time - * eg: twtr_min = 40 MTB (7.5ns) - all speed bins. - * tWRT is at least 4 mclk independent of operating freq. - */ - pdimm->twtr_ps = spd->twtr_min * mtb_ps; - - /* - * min internal read to precharge command delay time - * eg: trtp_min = 40 MTB (7.5ns) - all speed bins. - * tRTP is at least 4 mclk independent of operating freq. - */ - pdimm->trtp_ps = spd->trtp_min * mtb_ps; - - /* - * Average periodic refresh interval - * tREFI = 7.8 us at normal temperature range - * = 3.9 us at ext temperature range - */ - pdimm->refresh_rate_ps = 7800000; - if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) { - pdimm->refresh_rate_ps = 3900000; - pdimm->extended_op_srt = 1; - } - - /* - * min four active window delay time - * eg: tfaw_min = - * DDR3-800(1KB page) 320 MTB (40ns) - * DDR3-1066(1KB page) 300 MTB (37.5ns) - * DDR3-1333(1KB page) 240 MTB (30ns) - * DDR3-1600(1KB page) 240 MTB (30ns) - */ - pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) - * mtb_ps; - - return 0; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c deleted file mode 100644 index 3b66112..0000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c +++ /dev/null @@ -1,1870 +0,0 @@ -/* - * Copyright 2010-2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. - * Based on code from spd_sdram.c - * Author: James Yang [at freescale.com] - * York Sun [at freescale.com] - */ - -#include <common.h> -#include <linux/ctype.h> -#include <asm/types.h> - -#include <asm/fsl_ddr_sdram.h> -#include "ddr.h" - -/* Option parameter Structures */ -struct options_string { - const char *option_name; - size_t offset; - unsigned int size; - const char printhex; -}; - -static unsigned int picos_to_mhz(unsigned int picos) -{ - return 1000000 / picos; -} - -static void print_option_table(const struct options_string *table, - int table_size, - const void *base) -{ - unsigned int i; - unsigned int *ptr; - unsigned long long *ptr_l; - - for (i = 0; i < table_size; i++) { - switch (table[i].size) { - case 4: - ptr = (unsigned int *) (base + table[i].offset); - if (table[i].printhex) { - printf("%s = 0x%08X\n", - table[i].option_name, *ptr); - } else { - printf("%s = %u\n", - table[i].option_name, *ptr); - } - break; - case 8: - ptr_l = (unsigned long long *) (base + table[i].offset); - printf("%s = %llu\n", - table[i].option_name, *ptr_l); - break; - default: - printf("Unrecognized size!\n"); - break; - } - } -} - -static int handle_option_table(const struct options_string *table, - int table_size, - void *base, - const char *opt, - const char *val) -{ - unsigned int i; - unsigned int value, *ptr; - unsigned long long value_l, *ptr_l; - - for (i = 0; i < table_size; i++) { - if (strcmp(table[i].option_name, opt) != 0) - continue; - switch (table[i].size) { - case 4: - value = simple_strtoul(val, NULL, 0); - ptr = base + table[i].offset; - *ptr = value; - break; - case 8: - value_l = simple_strtoull(val, NULL, 0); - ptr_l = base + table[i].offset; - *ptr_l = value_l; - break; - default: - printf("Unrecognized size!\n"); - break; - } - return 1; - } - - return 0; -} - -static void fsl_ddr_generic_edit(void *pdata, - void *pend, - unsigned int element_size, - unsigned int element_num, - unsigned int value) -{ - char *pcdata = (char *)pdata; /* BIG ENDIAN ONLY */ - - pcdata += element_num * element_size; - if ((pcdata + element_size) > (char *) pend) { - printf("trying to write past end of data\n"); - return; - } - - switch (element_size) { - case 1: - __raw_writeb(value, pcdata); - break; - case 2: - __raw_writew(value, pcdata); - break; - case 4: - __raw_writel(value, pcdata); - break; - default: - printf("unexpected element size %u\n", element_size); - break; - } -} - -static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo, - unsigned int ctrl_num, - unsigned int dimm_num, - unsigned int element_num, - unsigned int value) -{ - generic_spd_eeprom_t *pspd; - - pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]); - fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value); -} - -#define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \ - sizeof((common_timing_params_t *)0)->x, 0} - -static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo, - unsigned int ctrl_num, - const char *optname_str, - const char *value_str) -{ - common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num]; - - static const struct options_string options[] = { - COMMON_TIMING(tckmin_x_ps), - COMMON_TIMING(tckmax_ps), - COMMON_TIMING(tckmax_max_ps), - COMMON_TIMING(trcd_ps), - COMMON_TIMING(trp_ps), - COMMON_TIMING(tras_ps), - COMMON_TIMING(twr_ps), - COMMON_TIMING(twtr_ps), - COMMON_TIMING(trfc_ps), - COMMON_TIMING(trrd_ps), - COMMON_TIMING(trc_ps), - COMMON_TIMING(refresh_rate_ps), - COMMON_TIMING(tis_ps), - COMMON_TIMING(tih_ps), - COMMON_TIMING(tds_ps), - COMMON_TIMING(tdh_ps), - COMMON_TIMING(trtp_ps), - COMMON_TIMING(tdqsq_max_ps), - COMMON_TIMING(tqhs_ps), - COMMON_TIMING(ndimms_present), - COMMON_TIMING(lowest_common_SPD_caslat), - COMMON_TIMING(highest_common_derated_caslat), - COMMON_TIMING(additive_latency), - COMMON_TIMING(all_dimms_burst_lengths_bitmask), - COMMON_TIMING(all_dimms_registered), - COMMON_TIMING(all_dimms_unbuffered), - COMMON_TIMING(all_dimms_ecc_capable), - COMMON_TIMING(total_mem), - COMMON_TIMING(base_address), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - if (handle_option_table(options, n_opts, p, optname_str, value_str)) - return; - - printf("Error: couldn't find option string %s\n", optname_str); -} - -#define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \ - sizeof((dimm_params_t *)0)->x, 0} - -static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo, - unsigned int ctrl_num, - unsigned int dimm_num, - const char *optname_str, - const char *value_str) -{ - dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]); - - static const struct options_string options[] = { - DIMM_PARM(n_ranks), - DIMM_PARM(data_width), - DIMM_PARM(primary_sdram_width), - DIMM_PARM(ec_sdram_width), - DIMM_PARM(registered_dimm), - DIMM_PARM(device_width), - - DIMM_PARM(n_row_addr), - DIMM_PARM(n_col_addr), - DIMM_PARM(edc_config), - DIMM_PARM(n_banks_per_sdram_device), - DIMM_PARM(burst_lengths_bitmask), - DIMM_PARM(row_density), - - DIMM_PARM(tckmin_x_ps), - DIMM_PARM(tckmin_x_minus_1_ps), - DIMM_PARM(tckmin_x_minus_2_ps), - DIMM_PARM(tckmax_ps), - - DIMM_PARM(caslat_x), - DIMM_PARM(caslat_x_minus_1), - DIMM_PARM(caslat_x_minus_2), - - DIMM_PARM(caslat_lowest_derated), - - DIMM_PARM(trcd_ps), - DIMM_PARM(trp_ps), - DIMM_PARM(tras_ps), - DIMM_PARM(twr_ps), - DIMM_PARM(twtr_ps), - DIMM_PARM(trfc_ps), - DIMM_PARM(trrd_ps), - DIMM_PARM(trc_ps), - DIMM_PARM(refresh_rate_ps), - - DIMM_PARM(tis_ps), - DIMM_PARM(tih_ps), - DIMM_PARM(tds_ps), - DIMM_PARM(tdh_ps), - DIMM_PARM(trtp_ps), - DIMM_PARM(tdqsq_max_ps), - DIMM_PARM(tqhs_ps), - - DIMM_PARM(rank_density), - DIMM_PARM(capacity), - DIMM_PARM(base_address), - }; - - static const unsigned int n_opts = ARRAY_SIZE(options); - - if (handle_option_table(options, n_opts, p, optname_str, value_str)) - return; - - printf("couldn't find option string %s\n", optname_str); -} - -static void print_dimm_parameters(const dimm_params_t *pdimm) -{ - static const struct options_string options[] = { - DIMM_PARM(n_ranks), - DIMM_PARM(data_width), - DIMM_PARM(primary_sdram_width), - DIMM_PARM(ec_sdram_width), - DIMM_PARM(registered_dimm), - DIMM_PARM(device_width), - - DIMM_PARM(n_row_addr), - DIMM_PARM(n_col_addr), - DIMM_PARM(edc_config), - DIMM_PARM(n_banks_per_sdram_device), - - DIMM_PARM(tckmin_x_ps), - DIMM_PARM(tckmin_x_minus_1_ps), - DIMM_PARM(tckmin_x_minus_2_ps), - DIMM_PARM(tckmax_ps), - - DIMM_PARM(caslat_x), - DIMM_PARM(taa_ps), - DIMM_PARM(caslat_x_minus_1), - DIMM_PARM(caslat_x_minus_2), - DIMM_PARM(caslat_lowest_derated), - - DIMM_PARM(trcd_ps), - DIMM_PARM(trp_ps), - DIMM_PARM(tras_ps), - DIMM_PARM(twr_ps), - DIMM_PARM(twtr_ps), - DIMM_PARM(trfc_ps), - DIMM_PARM(trrd_ps), - DIMM_PARM(trc_ps), - DIMM_PARM(refresh_rate_ps), - - DIMM_PARM(tis_ps), - DIMM_PARM(tih_ps), - DIMM_PARM(tds_ps), - DIMM_PARM(tdh_ps), - DIMM_PARM(trtp_ps), - DIMM_PARM(tdqsq_max_ps), - DIMM_PARM(tqhs_ps), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - if (pdimm->n_ranks == 0) { - printf("DIMM not present\n"); - return; - } - printf("DIMM organization parameters:\n"); - printf("module part name = %s\n", pdimm->mpart); - printf("rank_density = %llu bytes (%llu megabytes)\n", - pdimm->rank_density, pdimm->rank_density / 0x100000); - printf("capacity = %llu bytes (%llu megabytes)\n", - pdimm->capacity, pdimm->capacity / 0x100000); - printf("burst_lengths_bitmask = %02X\n", - pdimm->burst_lengths_bitmask); - printf("base_addresss = %llu (%08llX %08llX)\n", - pdimm->base_address, - (pdimm->base_address >> 32), - pdimm->base_address & 0xFFFFFFFF); - print_option_table(options, n_opts, pdimm); -} - -static void print_lowest_common_dimm_parameters( - const common_timing_params_t *plcd_dimm_params) -{ - static const struct options_string options[] = { - COMMON_TIMING(tckmax_max_ps), - COMMON_TIMING(trcd_ps), - COMMON_TIMING(trp_ps), - COMMON_TIMING(tras_ps), - COMMON_TIMING(twr_ps), - COMMON_TIMING(twtr_ps), - COMMON_TIMING(trfc_ps), - COMMON_TIMING(trrd_ps), - COMMON_TIMING(trc_ps), - COMMON_TIMING(refresh_rate_ps), - COMMON_TIMING(tis_ps), - COMMON_TIMING(tds_ps), - COMMON_TIMING(tdh_ps), - COMMON_TIMING(trtp_ps), - COMMON_TIMING(tdqsq_max_ps), - COMMON_TIMING(tqhs_ps), - COMMON_TIMING(lowest_common_SPD_caslat), - COMMON_TIMING(highest_common_derated_caslat), - COMMON_TIMING(additive_latency), - COMMON_TIMING(ndimms_present), - COMMON_TIMING(all_dimms_registered), - COMMON_TIMING(all_dimms_unbuffered), - COMMON_TIMING(all_dimms_ecc_capable), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - /* Clock frequencies */ - printf("tckmin_x_ps = %u (%u MHz)\n", - plcd_dimm_params->tckmin_x_ps, - picos_to_mhz(plcd_dimm_params->tckmin_x_ps)); - printf("tckmax_ps = %u (%u MHz)\n", - plcd_dimm_params->tckmax_ps, - picos_to_mhz(plcd_dimm_params->tckmax_ps)); - printf("all_dimms_burst_lengths_bitmask = %02X\n", - plcd_dimm_params->all_dimms_burst_lengths_bitmask); - - print_option_table(options, n_opts, plcd_dimm_params); - - printf("total_mem = %llu (%llu megabytes)\n", - plcd_dimm_params->total_mem, - plcd_dimm_params->total_mem / 0x100000); - printf("base_address = %llu (%llu megabytes)\n", - plcd_dimm_params->base_address, - plcd_dimm_params->base_address / 0x100000); -} - -#define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \ - sizeof((memctl_options_t *)0)->x, 0} -#define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \ - offsetof(memctl_options_t, cs_local_opts[x].y), \ - sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0} - -static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, - unsigned int ctl_num, - const char *optname_str, - const char *value_str) -{ - memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]); - /* - * This array all on the stack and *computed* each time this - * function is rung. - */ - static const struct options_string options[] = { - CTRL_OPTIONS_CS(0, odt_rd_cfg), - CTRL_OPTIONS_CS(0, odt_wr_cfg), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CTRL_OPTIONS_CS(1, odt_rd_cfg), - CTRL_OPTIONS_CS(1, odt_wr_cfg), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(2, odt_rd_cfg), - CTRL_OPTIONS_CS(2, odt_wr_cfg), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(3, odt_rd_cfg), - CTRL_OPTIONS_CS(3, odt_wr_cfg), -#endif -#if defined(CONFIG_FSL_DDR3) - CTRL_OPTIONS_CS(0, odt_rtt_norm), - CTRL_OPTIONS_CS(0, odt_rtt_wr), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CTRL_OPTIONS_CS(1, odt_rtt_norm), - CTRL_OPTIONS_CS(1, odt_rtt_wr), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(2, odt_rtt_norm), - CTRL_OPTIONS_CS(2, odt_rtt_wr), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(3, odt_rtt_norm), - CTRL_OPTIONS_CS(3, odt_rtt_wr), -#endif -#endif - CTRL_OPTIONS(memctl_interleaving), - CTRL_OPTIONS(memctl_interleaving_mode), - CTRL_OPTIONS(ba_intlv_ctl), - CTRL_OPTIONS(ecc_mode), - CTRL_OPTIONS(ecc_init_using_memctl), - CTRL_OPTIONS(dqs_config), - CTRL_OPTIONS(self_refresh_in_sleep), - CTRL_OPTIONS(dynamic_power), - CTRL_OPTIONS(data_bus_width), - CTRL_OPTIONS(burst_length), - CTRL_OPTIONS(cas_latency_override), - CTRL_OPTIONS(cas_latency_override_value), - CTRL_OPTIONS(use_derated_caslat), - CTRL_OPTIONS(additive_latency_override), - CTRL_OPTIONS(additive_latency_override_value), - CTRL_OPTIONS(clk_adjust), - CTRL_OPTIONS(cpo_override), - CTRL_OPTIONS(write_data_delay), - CTRL_OPTIONS(half_strength_driver_enable), - - /* - * These can probably be changed to 2T_EN and 3T_EN - * (using a leading numerical character) without problem - */ - CTRL_OPTIONS(twot_en), - CTRL_OPTIONS(threet_en), - CTRL_OPTIONS(ap_en), - CTRL_OPTIONS(x4_en), - CTRL_OPTIONS(bstopre), - CTRL_OPTIONS(wrlvl_override), - CTRL_OPTIONS(wrlvl_sample), - CTRL_OPTIONS(wrlvl_start), - CTRL_OPTIONS(rcw_override), - CTRL_OPTIONS(rcw_1), - CTRL_OPTIONS(rcw_2), - CTRL_OPTIONS(ddr_cdr1), - CTRL_OPTIONS(ddr_cdr2), - CTRL_OPTIONS(tcke_clock_pulse_width_ps), - CTRL_OPTIONS(tfaw_window_four_activates_ps), - CTRL_OPTIONS(trwt_override), - CTRL_OPTIONS(trwt), - }; - - static const unsigned int n_opts = ARRAY_SIZE(options); - - if (handle_option_table(options, n_opts, p, - optname_str, value_str)) - return; - - printf("couldn't find option string %s\n", optname_str); -} - -#define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \ - sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1} -#define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \ - offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \ - sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1} - -static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int i; - static const struct options_string options[] = { - CFG_REGS_CS(0, bnds), - CFG_REGS_CS(0, config), - CFG_REGS_CS(0, config_2), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CFG_REGS_CS(1, bnds), - CFG_REGS_CS(1, config), - CFG_REGS_CS(1, config_2), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CFG_REGS_CS(2, bnds), - CFG_REGS_CS(2, config), - CFG_REGS_CS(2, config_2), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CFG_REGS_CS(3, bnds), - CFG_REGS_CS(3, config), - CFG_REGS_CS(3, config_2), -#endif - CFG_REGS(timing_cfg_3), - CFG_REGS(timing_cfg_0), - CFG_REGS(timing_cfg_1), - CFG_REGS(timing_cfg_2), - CFG_REGS(ddr_sdram_cfg), - CFG_REGS(ddr_sdram_cfg_2), - CFG_REGS(ddr_sdram_mode), - CFG_REGS(ddr_sdram_mode_2), - CFG_REGS(ddr_sdram_mode_3), - CFG_REGS(ddr_sdram_mode_4), - CFG_REGS(ddr_sdram_mode_5), - CFG_REGS(ddr_sdram_mode_6), - CFG_REGS(ddr_sdram_mode_7), - CFG_REGS(ddr_sdram_mode_8), - CFG_REGS(ddr_sdram_interval), - CFG_REGS(ddr_data_init), - CFG_REGS(ddr_sdram_clk_cntl), - CFG_REGS(ddr_init_addr), - CFG_REGS(ddr_init_ext_addr), - CFG_REGS(timing_cfg_4), - CFG_REGS(timing_cfg_5), - CFG_REGS(ddr_zq_cntl), - CFG_REGS(ddr_wrlvl_cntl), - CFG_REGS(ddr_wrlvl_cntl_2), - CFG_REGS(ddr_wrlvl_cntl_3), - CFG_REGS(ddr_sr_cntr), - CFG_REGS(ddr_sdram_rcw_1), - CFG_REGS(ddr_sdram_rcw_2), - CFG_REGS(ddr_cdr1), - CFG_REGS(ddr_cdr2), - CFG_REGS(err_disable), - CFG_REGS(err_int_en), - CFG_REGS(ddr_eor), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - print_option_table(options, n_opts, ddr); - - for (i = 0; i < 32; i++) - printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]); -} - -static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo, - unsigned int ctrl_num, - const char *regname, - const char *value_str) -{ - unsigned int i; - fsl_ddr_cfg_regs_t *ddr; - char buf[20]; - static const struct options_string options[] = { - CFG_REGS_CS(0, bnds), - CFG_REGS_CS(0, config), - CFG_REGS_CS(0, config_2), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CFG_REGS_CS(1, bnds), - CFG_REGS_CS(1, config), - CFG_REGS_CS(1, config_2), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CFG_REGS_CS(2, bnds), - CFG_REGS_CS(2, config), - CFG_REGS_CS(2, config_2), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) - CFG_REGS_CS(3, bnds), - CFG_REGS_CS(3, config), - CFG_REGS_CS(3, config_2), -#endif - CFG_REGS(timing_cfg_3), - CFG_REGS(timing_cfg_0), - CFG_REGS(timing_cfg_1), - CFG_REGS(timing_cfg_2), - CFG_REGS(ddr_sdram_cfg), - CFG_REGS(ddr_sdram_cfg_2), - CFG_REGS(ddr_sdram_mode), - CFG_REGS(ddr_sdram_mode_2), - CFG_REGS(ddr_sdram_mode_3), - CFG_REGS(ddr_sdram_mode_4), - CFG_REGS(ddr_sdram_mode_5), - CFG_REGS(ddr_sdram_mode_6), - CFG_REGS(ddr_sdram_mode_7), - CFG_REGS(ddr_sdram_mode_8), - CFG_REGS(ddr_sdram_interval), - CFG_REGS(ddr_data_init), - CFG_REGS(ddr_sdram_clk_cntl), - CFG_REGS(ddr_init_addr), - CFG_REGS(ddr_init_ext_addr), - CFG_REGS(timing_cfg_4), - CFG_REGS(timing_cfg_5), - CFG_REGS(ddr_zq_cntl), - CFG_REGS(ddr_wrlvl_cntl), - CFG_REGS(ddr_wrlvl_cntl_2), - CFG_REGS(ddr_wrlvl_cntl_3), - CFG_REGS(ddr_sr_cntr), - CFG_REGS(ddr_sdram_rcw_1), - CFG_REGS(ddr_sdram_rcw_2), - CFG_REGS(ddr_cdr1), - CFG_REGS(ddr_cdr2), - CFG_REGS(err_disable), - CFG_REGS(err_int_en), - CFG_REGS(ddr_sdram_rcw_2), - CFG_REGS(ddr_sdram_rcw_2), - CFG_REGS(ddr_eor), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - debug("fsl_ddr_regs_edit: ctrl_num = %u, " - "regname = %s, value = %s\n", - ctrl_num, regname, value_str); - if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS) - return; - - ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]); - - if (handle_option_table(options, n_opts, ddr, regname, value_str)) - return; - - for (i = 0; i < 32; i++) { - unsigned int value = simple_strtoul(value_str, NULL, 0); - sprintf(buf, "debug_%u", i + 1); - if (strcmp(buf, regname) == 0) { - ddr->debug[i] = value; - return; - } - } - printf("Error: couldn't find register string %s\n", regname); -} - -#define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \ - sizeof((memctl_options_t *)0)->x, 1} - -static void print_memctl_options(const memctl_options_t *popts) -{ - static const struct options_string options[] = { - CTRL_OPTIONS_CS(0, odt_rd_cfg), - CTRL_OPTIONS_CS(0, odt_wr_cfg), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CTRL_OPTIONS_CS(1, odt_rd_cfg), - CTRL_OPTIONS_CS(1, odt_wr_cfg), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(2, odt_rd_cfg), - CTRL_OPTIONS_CS(2, odt_wr_cfg), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) - CTRL_OPTIONS_CS(3, odt_rd_cfg), - CTRL_OPTIONS_CS(3, odt_wr_cfg), -#endif -#if defined(CONFIG_FSL_DDR3) - CTRL_OPTIONS_CS(0, odt_rtt_norm), - CTRL_OPTIONS_CS(0, odt_rtt_wr), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CTRL_OPTIONS_CS(1, odt_rtt_norm), - CTRL_OPTIONS_CS(1, odt_rtt_wr), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(2, odt_rtt_norm), - CTRL_OPTIONS_CS(2, odt_rtt_wr), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) - CTRL_OPTIONS_CS(3, odt_rtt_norm), - CTRL_OPTIONS_CS(3, odt_rtt_wr), -#endif -#endif - CTRL_OPTIONS(memctl_interleaving), - CTRL_OPTIONS(memctl_interleaving_mode), - CTRL_OPTIONS_HEX(ba_intlv_ctl), - CTRL_OPTIONS(ecc_mode), - CTRL_OPTIONS(ecc_init_using_memctl), - CTRL_OPTIONS(dqs_config), - CTRL_OPTIONS(self_refresh_in_sleep), - CTRL_OPTIONS(dynamic_power), - CTRL_OPTIONS(data_bus_width), - CTRL_OPTIONS(burst_length), - CTRL_OPTIONS(cas_latency_override), - CTRL_OPTIONS(cas_latency_override_value), - CTRL_OPTIONS(use_derated_caslat), - CTRL_OPTIONS(additive_latency_override), - CTRL_OPTIONS(additive_latency_override_value), - CTRL_OPTIONS(clk_adjust), - CTRL_OPTIONS(cpo_override), - CTRL_OPTIONS(write_data_delay), - CTRL_OPTIONS(half_strength_driver_enable), - /* - * These can probably be changed to 2T_EN and 3T_EN - * (using a leading numerical character) without problem - */ - CTRL_OPTIONS(twot_en), - CTRL_OPTIONS(threet_en), - CTRL_OPTIONS(registered_dimm_en), - CTRL_OPTIONS(ap_en), - CTRL_OPTIONS(x4_en), - CTRL_OPTIONS(bstopre), - CTRL_OPTIONS(wrlvl_override), - CTRL_OPTIONS(wrlvl_sample), - CTRL_OPTIONS(wrlvl_start), - CTRL_OPTIONS(rcw_override), - CTRL_OPTIONS(rcw_1), - CTRL_OPTIONS(rcw_2), - CTRL_OPTIONS_HEX(ddr_cdr1), - CTRL_OPTIONS_HEX(ddr_cdr2), - CTRL_OPTIONS(tcke_clock_pulse_width_ps), - CTRL_OPTIONS(tfaw_window_four_activates_ps), - CTRL_OPTIONS(trwt_override), - CTRL_OPTIONS(trwt), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - print_option_table(options, n_opts, popts); -} - -#ifdef CONFIG_FSL_DDR1 -void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd) -{ - unsigned int i; - - printf("%-3d : %02x %s\n", 0, spd->info_size, - " spd->info_size, * 0 # bytes written into serial memory *"); - printf("%-3d : %02x %s\n", 1, spd->chip_size, - " spd->chip_size, * 1 Total # bytes of SPD memory device *"); - printf("%-3d : %02x %s\n", 2, spd->mem_type, - " spd->mem_type, * 2 Fundamental memory type *"); - printf("%-3d : %02x %s\n", 3, spd->nrow_addr, - " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); - printf("%-3d : %02x %s\n", 4, spd->ncol_addr, - " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); - printf("%-3d : %02x %s\n", 5, spd->nrows, - " spd->nrows * 5 # of DIMM Banks *"); - printf("%-3d : %02x %s\n", 6, spd->dataw_lsb, - " spd->dataw_lsb, * 6 Data Width lsb of this assembly *"); - printf("%-3d : %02x %s\n", 7, spd->dataw_msb, - " spd->dataw_msb, * 7 Data Width msb of this assembly *"); - printf("%-3d : %02x %s\n", 8, spd->voltage, - " spd->voltage, * 8 Voltage intf std of this assembly *"); - printf("%-3d : %02x %s\n", 9, spd->clk_cycle, - " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); - printf("%-3d : %02x %s\n", 10, spd->clk_access, - " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); - printf("%-3d : %02x %s\n", 11, spd->config, - " spd->config, * 11 DIMM Configuration type *"); - printf("%-3d : %02x %s\n", 12, spd->refresh, - " spd->refresh, * 12 Refresh Rate/Type *"); - printf("%-3d : %02x %s\n", 13, spd->primw, - " spd->primw, * 13 Primary SDRAM Width *"); - printf("%-3d : %02x %s\n", 14, spd->ecw, - " spd->ecw, * 14 Error Checking SDRAM width *"); - printf("%-3d : %02x %s\n", 15, spd->min_delay, - " spd->min_delay, * 15 Back to Back Random Access *"); - printf("%-3d : %02x %s\n", 16, spd->burstl, - " spd->burstl, * 16 Burst Lengths Supported *"); - printf("%-3d : %02x %s\n", 17, spd->nbanks, - " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); - printf("%-3d : %02x %s\n", 18, spd->cas_lat, - " spd->cas_lat, * 18 CAS# Latencies Supported *"); - printf("%-3d : %02x %s\n", 19, spd->cs_lat, - " spd->cs_lat, * 19 Chip Select Latency *"); - printf("%-3d : %02x %s\n", 20, spd->write_lat, - " spd->write_lat, * 20 Write Latency/Recovery *"); - printf("%-3d : %02x %s\n", 21, spd->mod_attr, - " spd->mod_attr, * 21 SDRAM Module Attributes *"); - printf("%-3d : %02x %s\n", 22, spd->dev_attr, - " spd->dev_attr, * 22 SDRAM Device Attributes *"); - printf("%-3d : %02x %s\n", 23, spd->clk_cycle2, - " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); - printf("%-3d : %02x %s\n", 24, spd->clk_access2, - " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); - printf("%-3d : %02x %s\n", 25, spd->clk_cycle3, - " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); - printf("%-3d : %02x %s\n", 26, spd->clk_access3, - " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); - printf("%-3d : %02x %s\n", 27, spd->trp, - " spd->trp, * 27 Min Row Precharge Time (tRP)*"); - printf("%-3d : %02x %s\n", 28, spd->trrd, - " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); - printf("%-3d : %02x %s\n", 29, spd->trcd, - " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); - printf("%-3d : %02x %s\n", 30, spd->tras, - " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); - printf("%-3d : %02x %s\n", 31, spd->bank_dens, - " spd->bank_dens, * 31 Density of each bank on module *"); - printf("%-3d : %02x %s\n", 32, spd->ca_setup, - " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); - printf("%-3d : %02x %s\n", 33, spd->ca_hold, - " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); - printf("%-3d : %02x %s\n", 34, spd->data_setup, - " spd->data_setup, * 34 Data signal input setup time *"); - printf("%-3d : %02x %s\n", 35, spd->data_hold, - " spd->data_hold, * 35 Data signal input hold time *"); - printf("%-3d : %02x %s\n", 36, spd->res_36_40[0], - " spd->res_36_40[0], * 36 Reserved / tWR *"); - printf("%-3d : %02x %s\n", 37, spd->res_36_40[1], - " spd->res_36_40[1], * 37 Reserved / tWTR *"); - printf("%-3d : %02x %s\n", 38, spd->res_36_40[2], - " spd->res_36_40[2], * 38 Reserved / tRTP *"); - printf("%-3d : %02x %s\n", 39, spd->res_36_40[3], - " spd->res_36_40[3], * 39 Reserved / mem_probe *"); - printf("%-3d : %02x %s\n", 40, spd->res_36_40[4], - " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *"); - printf("%-3d : %02x %s\n", 41, spd->trc, - " spd->trc, * 41 Min Active to Auto refresh time tRC *"); - printf("%-3d : %02x %s\n", 42, spd->trfc, - " spd->trfc, * 42 Min Auto to Active period tRFC *"); - printf("%-3d : %02x %s\n", 43, spd->tckmax, - " spd->tckmax, * 43 Max device cycle time tCKmax *"); - printf("%-3d : %02x %s\n", 44, spd->tdqsq, - " spd->tdqsq, * 44 Max DQS to DQ skew *"); - printf("%-3d : %02x %s\n", 45, spd->tqhs, - " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); - printf("%-3d : %02x %s\n", 46, spd->res_46, - " spd->res_46, * 46 Reserved/ PLL Relock time *"); - printf("%-3d : %02x %s\n", 47, spd->dimm_height, - " spd->dimm_height * 47 SDRAM DIMM Height *"); - - printf("%-3d-%3d: ", 48, 61); - - for (i = 0; i < 14; i++) - printf("%02x", spd->res_48_61[i]); - - printf(" * 48-61 IDD in SPD and Reserved space *\n"); - - printf("%-3d : %02x %s\n", 62, spd->spd_rev, - " spd->spd_rev, * 62 SPD Data Revision Code *"); - printf("%-3d : %02x %s\n", 63, spd->cksum, - " spd->cksum, * 63 Checksum for bytes 0-62 *"); - printf("%-3d-%3d: ", 64, 71); - - for (i = 0; i < 8; i++) - printf("%02x", spd->mid[i]); - - printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); - printf("%-3d : %02x %s\n", 72, spd->mloc, - " spd->mloc, * 72 Manufacturing Location *"); - - printf("%-3d-%3d: >>", 73, 90); - - for (i = 0; i < 18; i++) - printf("%c", spd->mpart[i]); - - printf("<<* 73 Manufacturer's Part Number *\n"); - - printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], - "* 91 Revision Code *"); - printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1], - "* 93 Manufacturing Date *"); - printf("%-3d-%3d: ", 95, 98); - - for (i = 0; i < 4; i++) - printf("%02x", spd->sernum[i]); - - printf("* 95 Assembly Serial Number *\n"); - - printf("%-3d-%3d: ", 99, 127); - - for (i = 0; i < 27; i++) - printf("%02x", spd->mspec[i]); - - printf("* 99 Manufacturer Specific Data *\n"); -} -#endif - -#ifdef CONFIG_FSL_DDR2 -void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd) -{ - unsigned int i; - - printf("%-3d : %02x %s\n", 0, spd->info_size, - " spd->info_size, * 0 # bytes written into serial memory *"); - printf("%-3d : %02x %s\n", 1, spd->chip_size, - " spd->chip_size, * 1 Total # bytes of SPD memory device *"); - printf("%-3d : %02x %s\n", 2, spd->mem_type, - " spd->mem_type, * 2 Fundamental memory type *"); - printf("%-3d : %02x %s\n", 3, spd->nrow_addr, - " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); - printf("%-3d : %02x %s\n", 4, spd->ncol_addr, - " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); - printf("%-3d : %02x %s\n", 5, spd->mod_ranks, - " spd->mod_ranks * 5 # of Module Rows on this assembly *"); - printf("%-3d : %02x %s\n", 6, spd->dataw, - " spd->dataw, * 6 Data Width of this assembly *"); - printf("%-3d : %02x %s\n", 7, spd->res_7, - " spd->res_7, * 7 Reserved *"); - printf("%-3d : %02x %s\n", 8, spd->voltage, - " spd->voltage, * 8 Voltage intf std of this assembly *"); - printf("%-3d : %02x %s\n", 9, spd->clk_cycle, - " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); - printf("%-3d : %02x %s\n", 10, spd->clk_access, - " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); - printf("%-3d : %02x %s\n", 11, spd->config, - " spd->config, * 11 DIMM Configuration type *"); - printf("%-3d : %02x %s\n", 12, spd->refresh, - " spd->refresh, * 12 Refresh Rate/Type *"); - printf("%-3d : %02x %s\n", 13, spd->primw, - " spd->primw, * 13 Primary SDRAM Width *"); - printf("%-3d : %02x %s\n", 14, spd->ecw, - " spd->ecw, * 14 Error Checking SDRAM width *"); - printf("%-3d : %02x %s\n", 15, spd->res_15, - " spd->res_15, * 15 Reserved *"); - printf("%-3d : %02x %s\n", 16, spd->burstl, - " spd->burstl, * 16 Burst Lengths Supported *"); - printf("%-3d : %02x %s\n", 17, spd->nbanks, - " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); - printf("%-3d : %02x %s\n", 18, spd->cas_lat, - " spd->cas_lat, * 18 CAS# Latencies Supported *"); - printf("%-3d : %02x %s\n", 19, spd->mech_char, - " spd->mech_char, * 19 Mechanical Characteristics *"); - printf("%-3d : %02x %s\n", 20, spd->dimm_type, - " spd->dimm_type, * 20 DIMM type *"); - printf("%-3d : %02x %s\n", 21, spd->mod_attr, - " spd->mod_attr, * 21 SDRAM Module Attributes *"); - printf("%-3d : %02x %s\n", 22, spd->dev_attr, - " spd->dev_attr, * 22 SDRAM Device Attributes *"); - printf("%-3d : %02x %s\n", 23, spd->clk_cycle2, - " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); - printf("%-3d : %02x %s\n", 24, spd->clk_access2, - " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); - printf("%-3d : %02x %s\n", 25, spd->clk_cycle3, - " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); - printf("%-3d : %02x %s\n", 26, spd->clk_access3, - " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); - printf("%-3d : %02x %s\n", 27, spd->trp, - " spd->trp, * 27 Min Row Precharge Time (tRP)*"); - printf("%-3d : %02x %s\n", 28, spd->trrd, - " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); - printf("%-3d : %02x %s\n", 29, spd->trcd, - " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); - printf("%-3d : %02x %s\n", 30, spd->tras, - " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); - printf("%-3d : %02x %s\n", 31, spd->rank_dens, - " spd->rank_dens, * 31 Density of each rank on module *"); - printf("%-3d : %02x %s\n", 32, spd->ca_setup, - " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); - printf("%-3d : %02x %s\n", 33, spd->ca_hold, - " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); - printf("%-3d : %02x %s\n", 34, spd->data_setup, - " spd->data_setup, * 34 Data signal input setup time *"); - printf("%-3d : %02x %s\n", 35, spd->data_hold, - " spd->data_hold, * 35 Data signal input hold time *"); - printf("%-3d : %02x %s\n", 36, spd->twr, - " spd->twr, * 36 Write Recovery time tWR *"); - printf("%-3d : %02x %s\n", 37, spd->twtr, - " spd->twtr, * 37 Int write to read delay tWTR *"); - printf("%-3d : %02x %s\n", 38, spd->trtp, - " spd->trtp, * 38 Int read to precharge delay tRTP *"); - printf("%-3d : %02x %s\n", 39, spd->mem_probe, - " spd->mem_probe, * 39 Mem analysis probe characteristics *"); - printf("%-3d : %02x %s\n", 40, spd->trctrfc_ext, - " spd->trctrfc_ext, * 40 Extensions to trc and trfc *"); - printf("%-3d : %02x %s\n", 41, spd->trc, - " spd->trc, * 41 Min Active to Auto refresh time tRC *"); - printf("%-3d : %02x %s\n", 42, spd->trfc, - " spd->trfc, * 42 Min Auto to Active period tRFC *"); - printf("%-3d : %02x %s\n", 43, spd->tckmax, - " spd->tckmax, * 43 Max device cycle time tCKmax *"); - printf("%-3d : %02x %s\n", 44, spd->tdqsq, - " spd->tdqsq, * 44 Max DQS to DQ skew *"); - printf("%-3d : %02x %s\n", 45, spd->tqhs, - " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); - printf("%-3d : %02x %s\n", 46, spd->pll_relock, - " spd->pll_relock, * 46 PLL Relock time *"); - printf("%-3d : %02x %s\n", 47, spd->t_casemax, - " spd->t_casemax, * 47 t_casemax *"); - printf("%-3d : %02x %s\n", 48, spd->psi_ta_dram, - " spd->psi_ta_dram, * 48 Thermal Resistance of DRAM Package " - "from Top (Case) to Ambient (Psi T-A DRAM) *"); - printf("%-3d : %02x %s\n", 49, spd->dt0_mode, - " spd->dt0_mode, * 49 DRAM Case Temperature Rise from " - "Ambient due to Activate-Precharge/Mode Bits " - "(DT0/Mode Bits) *)"); - printf("%-3d : %02x %s\n", 50, spd->dt2n_dt2q, - " spd->dt2n_dt2q, * 50 DRAM Case Temperature Rise from " - "Ambient due to Precharge/Quiet Standby " - "(DT2N/DT2Q) *"); - printf("%-3d : %02x %s\n", 51, spd->dt2p, - " spd->dt2p, * 51 DRAM Case Temperature Rise from " - "Ambient due to Precharge Power-Down (DT2P) *"); - printf("%-3d : %02x %s\n", 52, spd->dt3n, - " spd->dt3n, * 52 DRAM Case Temperature Rise from " - "Ambient due to Active Standby (DT3N) *"); - printf("%-3d : %02x %s\n", 53, spd->dt3pfast, - " spd->dt3pfast, * 53 DRAM Case Temperature Rise from " - "Ambient due to Active Power-Down with Fast PDN Exit " - "(DT3Pfast) *"); - printf("%-3d : %02x %s\n", 54, spd->dt3pslow, - " spd->dt3pslow, * 54 DRAM Case Temperature Rise from " - "Ambient due to Active Power-Down with Slow PDN Exit " - "(DT3Pslow) *"); - printf("%-3d : %02x %s\n", 55, spd->dt4r_dt4r4w, - " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from " - "Ambient due to Page Open Burst Read/DT4R4W Mode Bit " - "(DT4R/DT4R4W Mode Bit) *"); - printf("%-3d : %02x %s\n", 56, spd->dt5b, - " spd->dt5b, * 56 DRAM Case Temperature Rise from " - "Ambient due to Burst Refresh (DT5B) *"); - printf("%-3d : %02x %s\n", 57, spd->dt7, - " spd->dt7, * 57 DRAM Case Temperature Rise from " - "Ambient due to Bank Interleave Reads with " - "Auto-Precharge (DT7) *"); - printf("%-3d : %02x %s\n", 58, spd->psi_ta_pll, - " spd->psi_ta_pll, * 58 Thermal Resistance of PLL Package form" - " Top (Case) to Ambient (Psi T-A PLL) *"); - printf("%-3d : %02x %s\n", 59, spd->psi_ta_reg, - " spd->psi_ta_reg, * 59 Thermal Reisitance of Register Package" - " from Top (Case) to Ambient (Psi T-A Register) *"); - printf("%-3d : %02x %s\n", 60, spd->dtpllactive, - " spd->dtpllactive, * 60 PLL Case Temperature Rise from " - "Ambient due to PLL Active (DT PLL Active) *"); - printf("%-3d : %02x %s\n", 61, spd->dtregact, - " spd->dtregact, " - "* 61 Register Case Temperature Rise from Ambient due to " - "Register Active/Mode Bit (DT Register Active/Mode Bit) *"); - printf("%-3d : %02x %s\n", 62, spd->spd_rev, - " spd->spd_rev, * 62 SPD Data Revision Code *"); - printf("%-3d : %02x %s\n", 63, spd->cksum, - " spd->cksum, * 63 Checksum for bytes 0-62 *"); - - printf("%-3d-%3d: ", 64, 71); - - for (i = 0; i < 8; i++) - printf("%02x", spd->mid[i]); - - printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); - - printf("%-3d : %02x %s\n", 72, spd->mloc, - " spd->mloc, * 72 Manufacturing Location *"); - - printf("%-3d-%3d: >>", 73, 90); - for (i = 0; i < 18; i++) - printf("%c", spd->mpart[i]); - - - printf("<<* 73 Manufacturer's Part Number *\n"); - - printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], - "* 91 Revision Code *"); - printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1], - "* 93 Manufacturing Date *"); - printf("%-3d-%3d: ", 95, 98); - - for (i = 0; i < 4; i++) - printf("%02x", spd->sernum[i]); - - printf("* 95 Assembly Serial Number *\n"); - - printf("%-3d-%3d: ", 99, 127); - for (i = 0; i < 27; i++) - printf("%02x", spd->mspec[i]); - - - printf("* 99 Manufacturer Specific Data *\n"); -} -#endif - -#ifdef CONFIG_FSL_DDR3 -void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd) -{ - unsigned int i; - - /* General Section: Bytes 0-59 */ - -#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y); -#define PRINT_NNXXS(n0, n1, x0, x1, s) \ - printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1); - - PRINT_NXS(0, spd->info_size_crc, - "info_size_crc bytes written into serial memory, " - "CRC coverage"); - PRINT_NXS(1, spd->spd_rev, - "spd_rev SPD Revision"); - PRINT_NXS(2, spd->mem_type, - "mem_type Key Byte / DRAM Device Type"); - PRINT_NXS(3, spd->module_type, - "module_type Key Byte / Module Type"); - PRINT_NXS(4, spd->density_banks, - "density_banks SDRAM Density and Banks"); - PRINT_NXS(5, spd->addressing, - "addressing SDRAM Addressing"); - PRINT_NXS(6, spd->module_vdd, - "module_vdd Module Nominal Voltage, VDD"); - PRINT_NXS(7, spd->organization, - "organization Module Organization"); - PRINT_NXS(8, spd->bus_width, - "bus_width Module Memory Bus Width"); - PRINT_NXS(9, spd->ftb_div, - "ftb_div Fine Timebase (FTB) Dividend / Divisor"); - PRINT_NXS(10, spd->mtb_dividend, - "mtb_dividend Medium Timebase (MTB) Dividend"); - PRINT_NXS(11, spd->mtb_divisor, - "mtb_divisor Medium Timebase (MTB) Divisor"); - PRINT_NXS(12, spd->tck_min, - "tck_min SDRAM Minimum Cycle Time"); - PRINT_NXS(13, spd->res_13, - "res_13 Reserved"); - PRINT_NXS(14, spd->caslat_lsb, - "caslat_lsb CAS Latencies Supported, LSB"); - PRINT_NXS(15, spd->caslat_msb, - "caslat_msb CAS Latencies Supported, MSB"); - PRINT_NXS(16, spd->taa_min, - "taa_min Min CAS Latency Time"); - PRINT_NXS(17, spd->twr_min, - "twr_min Min Write REcovery Time"); - PRINT_NXS(18, spd->trcd_min, - "trcd_min Min RAS# to CAS# Delay Time"); - PRINT_NXS(19, spd->trrd_min, - "trrd_min Min Row Active to Row Active Delay Time"); - PRINT_NXS(20, spd->trp_min, - "trp_min Min Row Precharge Delay Time"); - PRINT_NXS(21, spd->tras_trc_ext, - "tras_trc_ext Upper Nibbles for tRAS and tRC"); - PRINT_NXS(22, spd->tras_min_lsb, - "tras_min_lsb Min Active to Precharge Delay Time, LSB"); - PRINT_NXS(23, spd->trc_min_lsb, - "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB"); - PRINT_NXS(24, spd->trfc_min_lsb, - "trfc_min_lsb Min Refresh Recovery Delay Time LSB"); - PRINT_NXS(25, spd->trfc_min_msb, - "trfc_min_msb Min Refresh Recovery Delay Time MSB"); - PRINT_NXS(26, spd->twtr_min, - "twtr_min Min Internal Write to Read Command Delay Time"); - PRINT_NXS(27, spd->trtp_min, - "trtp_min " - "Min Internal Read to Precharge Command Delay Time"); - PRINT_NXS(28, spd->tfaw_msb, - "tfaw_msb Upper Nibble for tFAW"); - PRINT_NXS(29, spd->tfaw_min, - "tfaw_min Min Four Activate Window Delay Time"); - PRINT_NXS(30, spd->opt_features, - "opt_features SDRAM Optional Features"); - PRINT_NXS(31, spd->therm_ref_opt, - "therm_ref_opt SDRAM Thermal and Refresh Opts"); - PRINT_NXS(32, spd->therm_sensor, - "therm_sensor SDRAM Thermal Sensor"); - PRINT_NXS(33, spd->device_type, - "device_type SDRAM Device Type"); - PRINT_NXS(34, spd->fine_tck_min, - "fine_tck_min Fine offset for tCKmin"); - PRINT_NXS(35, spd->fine_taa_min, - "fine_taa_min Fine offset for tAAmin"); - PRINT_NXS(36, spd->fine_trcd_min, - "fine_trcd_min Fine offset for tRCDmin"); - PRINT_NXS(37, spd->fine_trp_min, - "fine_trp_min Fine offset for tRPmin"); - PRINT_NXS(38, spd->fine_trc_min, - "fine_trc_min Fine offset for tRCmin"); - - printf("%-3d-%3d: ", 39, 59); /* Reserved, General Section */ - - for (i = 39; i <= 59; i++) - printf("%02x ", spd->res_39_59[i - 39]); - - puts("\n"); - - switch (spd->module_type) { - case 0x02: /* UDIMM */ - case 0x03: /* SO-DIMM */ - case 0x04: /* Micro-DIMM */ - case 0x06: /* Mini-UDIMM */ - PRINT_NXS(60, spd->mod_section.unbuffered.mod_height, - "mod_height (Unbuffered) Module Nominal Height"); - PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness, - "mod_thickness (Unbuffered) Module Maximum Thickness"); - PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card, - "ref_raw_card (Unbuffered) Reference Raw Card Used"); - PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping, - "addr_mapping (Unbuffered) Address mapping from " - "Edge Connector to DRAM"); - break; - case 0x01: /* RDIMM */ - case 0x05: /* Mini-RDIMM */ - PRINT_NXS(60, spd->mod_section.registered.mod_height, - "mod_height (Registered) Module Nominal Height"); - PRINT_NXS(61, spd->mod_section.registered.mod_thickness, - "mod_thickness (Registered) Module Maximum Thickness"); - PRINT_NXS(62, spd->mod_section.registered.ref_raw_card, - "ref_raw_card (Registered) Reference Raw Card Used"); - PRINT_NXS(63, spd->mod_section.registered.modu_attr, - "modu_attr (Registered) DIMM Module Attributes"); - PRINT_NXS(64, spd->mod_section.registered.thermal, - "thermal (Registered) Thermal Heat " - "Spreader Solution"); - PRINT_NXS(65, spd->mod_section.registered.reg_id_lo, - "reg_id_lo (Registered) Register Manufacturer ID " - "Code, LSB"); - PRINT_NXS(66, spd->mod_section.registered.reg_id_hi, - "reg_id_hi (Registered) Register Manufacturer ID " - "Code, MSB"); - PRINT_NXS(67, spd->mod_section.registered.reg_rev, - "reg_rev (Registered) Register " - "Revision Number"); - PRINT_NXS(68, spd->mod_section.registered.reg_type, - "reg_type (Registered) Register Type"); - for (i = 69; i <= 76; i++) { - printf("%-3d : %02x rcw[%d]\n", i, - spd->mod_section.registered.rcw[i-69], i-69); - } - break; - default: - /* Module-specific Section, Unsupported Module Type */ - printf("%-3d-%3d: ", 60, 116); - - for (i = 60; i <= 116; i++) - printf("%02x", spd->mod_section.uc[i - 60]); - - break; - } - - /* Unique Module ID: Bytes 117-125 */ - PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106"); - PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106"); - PRINT_NXS(119, spd->mloc, "Mfg Location"); - PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date"); - - printf("%-3d-%3d: ", 122, 125); - - for (i = 122; i <= 125; i++) - printf("%02x ", spd->sernum[i - 122]); - printf(" Module Serial Number\n"); - - /* CRC: Bytes 126-127 */ - PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC"); - - /* Other Manufacturer Fields and User Space: Bytes 128-255 */ - printf("%-3d-%3d: ", 128, 145); - for (i = 128; i <= 145; i++) - printf("%02x ", spd->mpart[i - 128]); - printf(" Mfg's Module Part Number\n"); - - PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1], - "Module Revision code"); - - PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106"); - PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106"); - - printf("%-3d-%3d: ", 150, 175); - for (i = 150; i <= 175; i++) - printf("%02x ", spd->msd[i - 150]); - printf(" Mfg's Specific Data\n"); - - printf("%-3d-%3d: ", 176, 255); - for (i = 176; i <= 255; i++) - printf("%02x", spd->cust[i - 176]); - printf(" Mfg's Specific Data\n"); - -} -#endif - -static inline void generic_spd_dump(const generic_spd_eeprom_t *spd) -{ -#if defined(CONFIG_FSL_DDR1) - ddr1_spd_dump(spd); -#elif defined(CONFIG_FSL_DDR2) - ddr2_spd_dump(spd); -#elif defined(CONFIG_FSL_DDR3) - ddr3_spd_dump(spd); -#endif -} - -static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo, - unsigned int ctrl_mask, - unsigned int dimm_mask, - unsigned int do_mask) -{ - unsigned int i, j, retval; - - /* STEP 1: DIMM SPD data */ - if (do_mask & STEP_GET_SPD) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - if (!(dimm_mask & (1 << j))) - continue; - - printf("SPD info: Controller=%u " - "DIMM=%u\n", i, j); - generic_spd_dump( - &(pinfo->spd_installed_dimms[i][j])); - printf("\n"); - } - printf("\n"); - } - printf("\n"); - } - - /* STEP 2: DIMM Parameters */ - if (do_mask & STEP_COMPUTE_DIMM_PARMS) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - if (!(dimm_mask & (1 << j))) - continue; - printf("DIMM parameters: Controller=%u " - "DIMM=%u\n", i, j); - print_dimm_parameters( - &(pinfo->dimm_params[i][j])); - printf("\n"); - } - printf("\n"); - } - printf("\n"); - } - - /* STEP 3: Common Parameters */ - if (do_mask & STEP_COMPUTE_COMMON_PARMS) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - printf("\"lowest common\" DIMM parameters: " - "Controller=%u\n", i); - print_lowest_common_dimm_parameters( - &pinfo->common_timing_params[i]); - printf("\n"); - } - printf("\n"); - } - - /* STEP 4: User Configuration Options */ - if (do_mask & STEP_GATHER_OPTS) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - printf("User Config Options: Controller=%u\n", i); - print_memctl_options(&pinfo->memctl_opts[i]); - printf("\n"); - } - printf("\n"); - } - - /* STEP 5: Address assignment */ - if (do_mask & STEP_ASSIGN_ADDRESSES) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - printf("Address Assignment: Controller=%u " - "DIMM=%u\n", i, j); - printf("Don't have this functionality yet\n"); - } - printf("\n"); - } - printf("\n"); - } - - /* STEP 6: computed controller register values */ - if (do_mask & STEP_COMPUTE_REGS) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - printf("Computed Register Values: Controller=%u\n", i); - print_fsl_memctl_config_regs( - &pinfo->fsl_ddr_config_reg[i]); - retval = check_fsl_memctl_config_regs( - &pinfo->fsl_ddr_config_reg[i]); - if (retval) { - printf("check_fsl_memctl_config_regs " - "result = %u\n", retval); - } - printf("\n"); - } - printf("\n"); - } -} - -struct data_strings { - const char *data_name; - unsigned int step_mask; - unsigned int dimm_number_required; -}; - -#define DATA_OPTIONS(name, step, dimm) {#name, step, dimm} - -static unsigned int fsl_ddr_parse_interactive_cmd( - char **argv, - int argc, - unsigned int *pstep_mask, - unsigned int *pctlr_mask, - unsigned int *pdimm_mask, - unsigned int *pdimm_number_required - ) { - - static const struct data_strings options[] = { - DATA_OPTIONS(spd, STEP_GET_SPD, 1), - DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1), - DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0), - DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0), - DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0), - DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - unsigned int i, j; - unsigned int error = 0; - - for (i = 1; i < argc; i++) { - unsigned int matched = 0; - - for (j = 0; j < n_opts; j++) { - if (strcmp(options[j].data_name, argv[i]) != 0) - continue; - *pstep_mask |= options[j].step_mask; - *pdimm_number_required = - options[j].dimm_number_required; - matched = 1; - break; - } - - if (matched) - continue; - - if (argv[i][0] == 'c') { - char c = argv[i][1]; - if (isdigit(c)) - *pctlr_mask |= 1 << (c - '0'); - continue; - } - - if (argv[i][0] == 'd') { - char c = argv[i][1]; - if (isdigit(c)) - *pdimm_mask |= 1 << (c - '0'); - continue; - } - - printf("unknown arg %s\n", argv[i]); - *pstep_mask = 0; - error = 1; - break; - } - - return error; -} - -int fsl_ddr_interactive_env_var_exists(void) -{ - char buffer[CONFIG_SYS_CBSIZE]; - - if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0) - return 1; - - return 0; -} - -unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set) -{ - unsigned long long ddrsize; - const char *prompt = "FSL DDR>"; - char buffer[CONFIG_SYS_CBSIZE]; - char buffer2[CONFIG_SYS_CBSIZE]; - char *p = NULL; - char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */ - int argc; - unsigned int next_step = STEP_GET_SPD; - const char *usage = { - "commands:\n" - "print print SPD and intermediate computed data\n" - "reset reboot machine\n" - "recompute reload SPD and options to default and recompute regs\n" - "edit modify spd, parameter, or option\n" - "compute recompute registers from current next_step to end\n" - "copy copy parameters\n" - "next_step shows current next_step\n" - "help this message\n" - "go program the memory controller and continue with u-boot\n" - }; - - if (var_is_set) { - if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) { - p = buffer2; - } else { - var_is_set = 0; - } - } - - /* - * The strategy for next_step is that it points to the next - * step in the computation process that needs to be done. - */ - while (1) { - if (var_is_set) { - char *pend = strchr(p, ';'); - if (pend) { - /* found command separator, copy sub-command */ - *pend = '\0'; - strcpy(buffer, p); - p = pend + 1; - } else { - /* separator not found, copy whole string */ - strcpy(buffer, p); - p = NULL; - var_is_set = 0; - } - } else { - /* - * No need to worry for buffer overflow here in - * this function; readline() maxes out at CFG_CBSIZE - */ - readline_into_buffer(prompt, buffer, 0); - } - argc = parse_line(buffer, argv); - if (argc == 0) - continue; - - - if (strcmp(argv[0], "help") == 0) { - puts(usage); - continue; - } - - if (strcmp(argv[0], "next_step") == 0) { - printf("next_step = 0x%02X (%s)\n", - next_step, - step_to_string(next_step)); - continue; - } - - if (strcmp(argv[0], "copy") == 0) { - unsigned int error = 0; - unsigned int step_mask = 0; - unsigned int src_ctlr_mask = 0; - unsigned int src_dimm_mask = 0; - unsigned int dimm_number_required = 0; - unsigned int src_ctlr_num = 0; - unsigned int src_dimm_num = 0; - unsigned int dst_ctlr_num = -1; - unsigned int dst_dimm_num = -1; - unsigned int i, num_dest_parms; - - if (argc == 1) { - printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n"); - continue; - } - - error = fsl_ddr_parse_interactive_cmd( - argv, argc, - &step_mask, - &src_ctlr_mask, - &src_dimm_mask, - &dimm_number_required - ); - - /* XXX: only dimm_number_required and step_mask will - be used by this function. Parse the controller and - DIMM number separately because it is easier. */ - - if (error) - continue; - - /* parse source destination controller / DIMM */ - - num_dest_parms = dimm_number_required ? 2 : 1; - - for (i = 0; i < argc; i++) { - if (argv[i][0] == 'c') { - char c = argv[i][1]; - if (isdigit(c)) { - src_ctlr_num = (c - '0'); - break; - } - } - } - - for (i = 0; i < argc; i++) { - if (argv[i][0] == 'd') { - char c = argv[i][1]; - if (isdigit(c)) { - src_dimm_num = (c - '0'); - break; - } - } - } - - /* parse destination controller / DIMM */ - - for (i = argc - 1; i >= argc - num_dest_parms; i--) { - if (argv[i][0] == 'c') { - char c = argv[i][1]; - if (isdigit(c)) { - dst_ctlr_num = (c - '0'); - break; - } - } - } - - for (i = argc - 1; i >= argc - num_dest_parms; i--) { - if (argv[i][0] == 'd') { - char c = argv[i][1]; - if (isdigit(c)) { - dst_dimm_num = (c - '0'); - break; - } - } - } - - /* TODO: validate inputs */ - - debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n", - src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask); - - - switch (step_mask) { - - case STEP_GET_SPD: - memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]), - &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]), - sizeof(pinfo->spd_installed_dimms[0][0])); - break; - - case STEP_COMPUTE_DIMM_PARMS: - memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]), - &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]), - sizeof(pinfo->dimm_params[0][0])); - break; - - case STEP_COMPUTE_COMMON_PARMS: - memcpy(&(pinfo->common_timing_params[dst_ctlr_num]), - &(pinfo->common_timing_params[src_ctlr_num]), - sizeof(pinfo->common_timing_params[0])); - break; - - case STEP_GATHER_OPTS: - memcpy(&(pinfo->memctl_opts[dst_ctlr_num]), - &(pinfo->memctl_opts[src_ctlr_num]), - sizeof(pinfo->memctl_opts[0])); - break; - - /* someday be able to have addresses to copy addresses... */ - - case STEP_COMPUTE_REGS: - memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]), - &(pinfo->fsl_ddr_config_reg[src_ctlr_num]), - sizeof(pinfo->memctl_opts[0])); - break; - - default: - printf("unexpected step_mask value\n"); - } - - continue; - - } - - if (strcmp(argv[0], "edit") == 0) { - unsigned int error = 0; - unsigned int step_mask = 0; - unsigned int ctlr_mask = 0; - unsigned int dimm_mask = 0; - char *p_element = NULL; - char *p_value = NULL; - unsigned int dimm_number_required = 0; - unsigned int ctrl_num; - unsigned int dimm_num; - - if (argc == 1) { - /* Only the element and value must be last */ - printf("edit <c#> <d#> " - "<spd|dimmparms|commonparms|opts|" - "addresses|regs> <element> <value>\n"); - printf("for spd, specify byte number for " - "element\n"); - continue; - } - - error = fsl_ddr_parse_interactive_cmd( - argv, argc - 2, - &step_mask, - &ctlr_mask, - &dimm_mask, - &dimm_number_required - ); - - if (error) - continue; - - - /* Check arguments */ - - /* ERROR: If no steps were found */ - if (step_mask == 0) { - printf("Error: No valid steps were specified " - "in argument.\n"); - continue; - } - - /* ERROR: If multiple steps were found */ - if (step_mask & (step_mask - 1)) { - printf("Error: Multiple steps specified in " - "argument.\n"); - continue; - } - - /* ERROR: Controller not specified */ - if (ctlr_mask == 0) { - printf("Error: controller number not " - "specified or no element and " - "value specified\n"); - continue; - } - - if (ctlr_mask & (ctlr_mask - 1)) { - printf("Error: multiple controllers " - "specified, %X\n", ctlr_mask); - continue; - } - - /* ERROR: DIMM number not specified */ - if (dimm_number_required && dimm_mask == 0) { - printf("Error: DIMM number number not " - "specified or no element and " - "value specified\n"); - continue; - } - - if (dimm_mask & (dimm_mask - 1)) { - printf("Error: multipled DIMMs specified\n"); - continue; - } - - p_element = argv[argc - 2]; - p_value = argv[argc - 1]; - - ctrl_num = __ilog2(ctlr_mask); - dimm_num = __ilog2(dimm_mask); - - switch (step_mask) { - case STEP_GET_SPD: - { - unsigned int element_num; - unsigned int value; - - element_num = simple_strtoul(p_element, - NULL, 0); - value = simple_strtoul(p_value, - NULL, 0); - fsl_ddr_spd_edit(pinfo, - ctrl_num, - dimm_num, - element_num, - value); - next_step = STEP_COMPUTE_DIMM_PARMS; - } - break; - - case STEP_COMPUTE_DIMM_PARMS: - fsl_ddr_dimm_parameters_edit( - pinfo, ctrl_num, dimm_num, - p_element, p_value); - next_step = STEP_COMPUTE_COMMON_PARMS; - break; - - case STEP_COMPUTE_COMMON_PARMS: - lowest_common_dimm_parameters_edit(pinfo, - ctrl_num, p_element, p_value); - next_step = STEP_GATHER_OPTS; - break; - - case STEP_GATHER_OPTS: - fsl_ddr_options_edit(pinfo, ctrl_num, - p_element, p_value); - next_step = STEP_ASSIGN_ADDRESSES; - break; - - case STEP_ASSIGN_ADDRESSES: - printf("editing of address assignment " - "not yet implemented\n"); - break; - - case STEP_COMPUTE_REGS: - { - fsl_ddr_regs_edit(pinfo, - ctrl_num, - p_element, - p_value); - next_step = STEP_PROGRAM_REGS; - } - break; - - default: - printf("programming error\n"); - while (1) - ; - break; - } - continue; - } - - if (strcmp(argv[0], "reset") == 0) { - /* - * Reboot machine. - * Args don't seem to matter because this - * doesn't return - */ - do_reset(NULL, 0, 0, NULL); - printf("Reset didn't work\n"); - } - - if (strcmp(argv[0], "recompute") == 0) { - /* - * Recalculate everything, starting with - * loading SPD EEPROM from DIMMs - */ - next_step = STEP_GET_SPD; - ddrsize = fsl_ddr_compute(pinfo, next_step, 0); - continue; - } - - if (strcmp(argv[0], "compute") == 0) { - /* - * Compute rest of steps starting at - * the current next_step/ - */ - ddrsize = fsl_ddr_compute(pinfo, next_step, 0); - continue; - } - - if (strcmp(argv[0], "print") == 0) { - unsigned int error = 0; - unsigned int step_mask = 0; - unsigned int ctlr_mask = 0; - unsigned int dimm_mask = 0; - unsigned int dimm_number_required = 0; - - if (argc == 1) { - printf("print [c<n>] [d<n>] [spd] [dimmparms] " - "[commonparms] [opts] [addresses] [regs]\n"); - continue; - } - - error = fsl_ddr_parse_interactive_cmd( - argv, argc, - &step_mask, - &ctlr_mask, - &dimm_mask, - &dimm_number_required - ); - - if (error) - continue; - - /* If no particular controller was found, print all */ - if (ctlr_mask == 0) - ctlr_mask = 0xFF; - - /* If no particular dimm was found, print all dimms. */ - if (dimm_mask == 0) - dimm_mask = 0xFF; - - /* If no steps were found, print all steps. */ - if (step_mask == 0) - step_mask = STEP_ALL; - - fsl_ddr_printinfo(pinfo, ctlr_mask, - dimm_mask, step_mask); - continue; - } - - if (strcmp(argv[0], "go") == 0) { - if (next_step) - ddrsize = fsl_ddr_compute(pinfo, next_step, 0); - break; - } - - printf("unknown command %s\n", argv[0]); - } - - debug("end of memory = %llu\n", (u64)ddrsize); - - return ddrsize; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c deleted file mode 100644 index 332fe25..0000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ /dev/null @@ -1,526 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> -#include <asm/fsl_ddr_sdram.h> - -#include "ddr.h" - -#if defined(CONFIG_FSL_DDR3) -static unsigned int -compute_cas_latency_ddr3(const dimm_params_t *dimm_params, - common_timing_params_t *outpdimm, - unsigned int number_of_dimms) -{ - unsigned int i; - unsigned int taamin_ps = 0; - unsigned int tckmin_x_ps = 0; - unsigned int common_caslat; - unsigned int caslat_actual; - unsigned int retry = 16; - unsigned int tmp; - const unsigned int mclk_ps = get_memory_clk_period_ps(); - - /* compute the common CAS latency supported between slots */ - tmp = dimm_params[0].caslat_x; - for (i = 1; i < number_of_dimms; i++) { - if (dimm_params[i].n_ranks) - tmp &= dimm_params[i].caslat_x; - } - common_caslat = tmp; - - /* compute the max tAAmin tCKmin between slots */ - for (i = 0; i < number_of_dimms; i++) { - taamin_ps = max(taamin_ps, dimm_params[i].taa_ps); - tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps); - } - /* validate if the memory clk is in the range of dimms */ - if (mclk_ps < tckmin_x_ps) { - printf("DDR clock (MCLK cycle %u ps) is faster than " - "the slowest DIMM(s) (tCKmin %u ps) can support.\n", - mclk_ps, tckmin_x_ps); - } - /* determine the acutal cas latency */ - caslat_actual = (taamin_ps + mclk_ps - 1) / mclk_ps; - /* check if the dimms support the CAS latency */ - while (!(common_caslat & (1 << caslat_actual)) && retry > 0) { - caslat_actual++; - retry--; - } - /* once the caculation of caslat_actual is completed - * we must verify that this CAS latency value does not - * exceed tAAmax, which is 20 ns for all DDR3 speed grades - */ - if (caslat_actual * mclk_ps > 20000) { - printf("The choosen cas latency %d is too large\n", - caslat_actual); - } - outpdimm->lowest_common_SPD_caslat = caslat_actual; - - return 0; -} -#endif - -/* - * compute_lowest_common_dimm_parameters() - * - * Determine the worst-case DIMM timing parameters from the set of DIMMs - * whose parameters have been computed into the array pointed to - * by dimm_params. - */ -unsigned int -compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, - common_timing_params_t *outpdimm, - const unsigned int number_of_dimms) -{ - unsigned int i, j; - - unsigned int tckmin_x_ps = 0; - unsigned int tckmax_ps = 0xFFFFFFFF; - unsigned int tckmax_max_ps = 0; - unsigned int trcd_ps = 0; - unsigned int trp_ps = 0; - unsigned int tras_ps = 0; - unsigned int twr_ps = 0; - unsigned int twtr_ps = 0; - unsigned int trfc_ps = 0; - unsigned int trrd_ps = 0; - unsigned int trc_ps = 0; - unsigned int refresh_rate_ps = 0; - unsigned int extended_op_srt = 1; - unsigned int tis_ps = 0; - unsigned int tih_ps = 0; - unsigned int tds_ps = 0; - unsigned int tdh_ps = 0; - unsigned int trtp_ps = 0; - unsigned int tdqsq_max_ps = 0; - unsigned int tqhs_ps = 0; - - unsigned int temp1, temp2; - unsigned int additive_latency = 0; -#if !defined(CONFIG_FSL_DDR3) - const unsigned int mclk_ps = get_memory_clk_period_ps(); - unsigned int lowest_good_caslat; - unsigned int not_ok; - - debug("using mclk_ps = %u\n", mclk_ps); -#endif - - temp1 = 0; - for (i = 0; i < number_of_dimms; i++) { - /* - * If there are no ranks on this DIMM, - * it probably doesn't exist, so skip it. - */ - if (dimm_params[i].n_ranks == 0) { - temp1++; - continue; - } - if (dimm_params[i].n_ranks == 4 && i != 0) { - printf("Found Quad-rank DIMM in wrong bank, ignored." - " Software may not run as expected.\n"); - temp1++; - continue; - } - - /* - * check if quad-rank DIMM is plugged if - * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined - * Only the board with proper design is capable - */ -#ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - if (dimm_params[i].n_ranks == 4 && \ - CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) { - printf("Found Quad-rank DIMM, not able to support."); - temp1++; - continue; - } -#endif - /* - * Find minimum tckmax_ps to find fastest slow speed, - * i.e., this is the slowest the whole system can go. - */ - tckmax_ps = min(tckmax_ps, dimm_params[i].tckmax_ps); - - /* Either find maximum value to determine slowest - * speed, delay, time, period, etc */ - tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps); - tckmax_max_ps = max(tckmax_max_ps, dimm_params[i].tckmax_ps); - trcd_ps = max(trcd_ps, dimm_params[i].trcd_ps); - trp_ps = max(trp_ps, dimm_params[i].trp_ps); - tras_ps = max(tras_ps, dimm_params[i].tras_ps); - twr_ps = max(twr_ps, dimm_params[i].twr_ps); - twtr_ps = max(twtr_ps, dimm_params[i].twtr_ps); - trfc_ps = max(trfc_ps, dimm_params[i].trfc_ps); - trrd_ps = max(trrd_ps, dimm_params[i].trrd_ps); - trc_ps = max(trc_ps, dimm_params[i].trc_ps); - tis_ps = max(tis_ps, dimm_params[i].tis_ps); - tih_ps = max(tih_ps, dimm_params[i].tih_ps); - tds_ps = max(tds_ps, dimm_params[i].tds_ps); - tdh_ps = max(tdh_ps, dimm_params[i].tdh_ps); - trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps); - tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps); - refresh_rate_ps = max(refresh_rate_ps, - dimm_params[i].refresh_rate_ps); - /* extended_op_srt is either 0 or 1, 0 having priority */ - extended_op_srt = min(extended_op_srt, - dimm_params[i].extended_op_srt); - - /* - * Find maximum tdqsq_max_ps to find slowest. - * - * FIXME: is finding the slowest value the correct - * strategy for this parameter? - */ - tdqsq_max_ps = max(tdqsq_max_ps, dimm_params[i].tdqsq_max_ps); - } - - outpdimm->ndimms_present = number_of_dimms - temp1; - - if (temp1 == number_of_dimms) { - debug("no dimms this memory controller\n"); - return 0; - } - - outpdimm->tckmin_x_ps = tckmin_x_ps; - outpdimm->tckmax_ps = tckmax_ps; - outpdimm->tckmax_max_ps = tckmax_max_ps; - outpdimm->trcd_ps = trcd_ps; - outpdimm->trp_ps = trp_ps; - outpdimm->tras_ps = tras_ps; - outpdimm->twr_ps = twr_ps; - outpdimm->twtr_ps = twtr_ps; - outpdimm->trfc_ps = trfc_ps; - outpdimm->trrd_ps = trrd_ps; - outpdimm->trc_ps = trc_ps; - outpdimm->refresh_rate_ps = refresh_rate_ps; - outpdimm->extended_op_srt = extended_op_srt; - outpdimm->tis_ps = tis_ps; - outpdimm->tih_ps = tih_ps; - outpdimm->tds_ps = tds_ps; - outpdimm->tdh_ps = tdh_ps; - outpdimm->trtp_ps = trtp_ps; - outpdimm->tdqsq_max_ps = tdqsq_max_ps; - outpdimm->tqhs_ps = tqhs_ps; - - /* Determine common burst length for all DIMMs. */ - temp1 = 0xff; - for (i = 0; i < number_of_dimms; i++) { - if (dimm_params[i].n_ranks) { - temp1 &= dimm_params[i].burst_lengths_bitmask; - } - } - outpdimm->all_dimms_burst_lengths_bitmask = temp1; - - /* Determine if all DIMMs registered buffered. */ - temp1 = temp2 = 0; - for (i = 0; i < number_of_dimms; i++) { - if (dimm_params[i].n_ranks) { - if (dimm_params[i].registered_dimm) { - temp1 = 1; -#ifndef CONFIG_SPL_BUILD - printf("Detected RDIMM %s\n", - dimm_params[i].mpart); -#endif - } else { - temp2 = 1; -#ifndef CONFIG_SPL_BUILD - printf("Detected UDIMM %s\n", - dimm_params[i].mpart); -#endif - } - } - } - - outpdimm->all_dimms_registered = 0; - outpdimm->all_dimms_unbuffered = 0; - if (temp1 && !temp2) { - outpdimm->all_dimms_registered = 1; - } else if (!temp1 && temp2) { - outpdimm->all_dimms_unbuffered = 1; - } else { - printf("ERROR: Mix of registered buffered and unbuffered " - "DIMMs detected!\n"); - } - - temp1 = 0; - if (outpdimm->all_dimms_registered) - for (j = 0; j < 16; j++) { - outpdimm->rcw[j] = dimm_params[0].rcw[j]; - for (i = 1; i < number_of_dimms; i++) { - if (!dimm_params[i].n_ranks) - continue; - if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) { - temp1 = 1; - break; - } - } - } - - if (temp1 != 0) - printf("ERROR: Mix different RDIMM detected!\n"); - -#if defined(CONFIG_FSL_DDR3) - if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms)) - return 1; -#else - /* - * Compute a CAS latency suitable for all DIMMs - * - * Strategy for SPD-defined latencies: compute only - * CAS latency defined by all DIMMs. - */ - - /* - * Step 1: find CAS latency common to all DIMMs using bitwise - * operation. - */ - temp1 = 0xFF; - for (i = 0; i < number_of_dimms; i++) { - if (dimm_params[i].n_ranks) { - temp2 = 0; - temp2 |= 1 << dimm_params[i].caslat_x; - temp2 |= 1 << dimm_params[i].caslat_x_minus_1; - temp2 |= 1 << dimm_params[i].caslat_x_minus_2; - /* - * FIXME: If there was no entry for X-2 (X-1) in - * the SPD, then caslat_x_minus_2 - * (caslat_x_minus_1) contains either 255 or - * 0xFFFFFFFF because that's what the glorious - * __ilog2 function returns for an input of 0. - * On 32-bit PowerPC, left shift counts with bit - * 26 set (that the value of 255 or 0xFFFFFFFF - * will have), cause the destination register to - * be 0. That is why this works. - */ - temp1 &= temp2; - } - } - - /* - * Step 2: check each common CAS latency against tCK of each - * DIMM's SPD. - */ - lowest_good_caslat = 0; - temp2 = 0; - while (temp1) { - not_ok = 0; - temp2 = __ilog2(temp1); - debug("checking common caslat = %u\n", temp2); - - /* Check if this CAS latency will work on all DIMMs at tCK. */ - for (i = 0; i < number_of_dimms; i++) { - if (!dimm_params[i].n_ranks) { - continue; - } - if (dimm_params[i].caslat_x == temp2) { - if (mclk_ps >= dimm_params[i].tckmin_x_ps) { - debug("CL = %u ok on DIMM %u at tCK=%u" - " ps with its tCKmin_X_ps of %u\n", - temp2, i, mclk_ps, - dimm_params[i].tckmin_x_ps); - continue; - } else { - not_ok++; - } - } - - if (dimm_params[i].caslat_x_minus_1 == temp2) { - unsigned int tckmin_x_minus_1_ps - = dimm_params[i].tckmin_x_minus_1_ps; - if (mclk_ps >= tckmin_x_minus_1_ps) { - debug("CL = %u ok on DIMM %u at " - "tCK=%u ps with its " - "tckmin_x_minus_1_ps of %u\n", - temp2, i, mclk_ps, - tckmin_x_minus_1_ps); - continue; - } else { - not_ok++; - } - } - - if (dimm_params[i].caslat_x_minus_2 == temp2) { - unsigned int tckmin_x_minus_2_ps - = dimm_params[i].tckmin_x_minus_2_ps; - if (mclk_ps >= tckmin_x_minus_2_ps) { - debug("CL = %u ok on DIMM %u at " - "tCK=%u ps with its " - "tckmin_x_minus_2_ps of %u\n", - temp2, i, mclk_ps, - tckmin_x_minus_2_ps); - continue; - } else { - not_ok++; - } - } - } - - if (!not_ok) { - lowest_good_caslat = temp2; - } - - temp1 &= ~(1 << temp2); - } - - debug("lowest common SPD-defined CAS latency = %u\n", - lowest_good_caslat); - outpdimm->lowest_common_SPD_caslat = lowest_good_caslat; - - - /* - * Compute a common 'de-rated' CAS latency. - * - * The strategy here is to find the *highest* dereated cas latency - * with the assumption that all of the DIMMs will support a dereated - * CAS latency higher than or equal to their lowest dereated value. - */ - temp1 = 0; - for (i = 0; i < number_of_dimms; i++) { - temp1 = max(temp1, dimm_params[i].caslat_lowest_derated); - } - outpdimm->highest_common_derated_caslat = temp1; - debug("highest common dereated CAS latency = %u\n", temp1); -#endif /* #if defined(CONFIG_FSL_DDR3) */ - - /* Determine if all DIMMs ECC capable. */ - temp1 = 1; - for (i = 0; i < number_of_dimms; i++) { - if (dimm_params[i].n_ranks && - !(dimm_params[i].edc_config & EDC_ECC)) { - temp1 = 0; - break; - } - } - if (temp1) { - debug("all DIMMs ECC capable\n"); - } else { - debug("Warning: not all DIMMs ECC capable, cant enable ECC\n"); - } - outpdimm->all_dimms_ecc_capable = temp1; - -#ifndef CONFIG_FSL_DDR3 - /* FIXME: move to somewhere else to validate. */ - if (mclk_ps > tckmax_max_ps) { - printf("Warning: some of the installed DIMMs " - "can not operate this slowly.\n"); - return 1; - } -#endif - /* - * Compute additive latency. - * - * For DDR1, additive latency should be 0. - * - * For DDR2, with ODT enabled, use "a value" less than ACTTORW, - * which comes from Trcd, and also note that: - * add_lat + caslat must be >= 4 - * - * For DDR3, we use the AL=0 - * - * When to use additive latency for DDR2: - * - * I. Because you are using CL=3 and need to do ODT on writes and - * want functionality. - * 1. Are you going to use ODT? (Does your board not have - * additional termination circuitry for DQ, DQS, DQS_, - * DM, RDQS, RDQS_ for x4/x8 configs?) - * 2. If so, is your lowest supported CL going to be 3? - * 3. If so, then you must set AL=1 because - * - * WL >= 3 for ODT on writes - * RL = AL + CL - * WL = RL - 1 - * -> - * WL = AL + CL - 1 - * AL + CL - 1 >= 3 - * AL + CL >= 4 - * QED - * - * RL >= 3 for ODT on reads - * RL = AL + CL - * - * Since CL aren't usually less than 2, AL=0 is a minimum, - * so the WL-derived AL should be the -- FIXME? - * - * II. Because you are using auto-precharge globally and want to - * use additive latency (posted CAS) to get more bandwidth. - * 1. Are you going to use auto-precharge mode globally? - * - * Use addtivie latency and compute AL to be 1 cycle less than - * tRCD, i.e. the READ or WRITE command is in the cycle - * immediately following the ACTIVATE command.. - * - * III. Because you feel like it or want to do some sort of - * degraded-performance experiment. - * 1. Do you just want to use additive latency because you feel - * like it? - * - * Validation: AL is less than tRCD, and within the other - * read-to-precharge constraints. - */ - - additive_latency = 0; - -#if defined(CONFIG_FSL_DDR2) - if (lowest_good_caslat < 4) { - additive_latency = (picos_to_mclk(trcd_ps) > lowest_good_caslat) - ? picos_to_mclk(trcd_ps) - lowest_good_caslat : 0; - if (mclk_to_picos(additive_latency) > trcd_ps) { - additive_latency = picos_to_mclk(trcd_ps); - debug("setting additive_latency to %u because it was " - " greater than tRCD_ps\n", additive_latency); - } - } - -#elif defined(CONFIG_FSL_DDR3) - /* - * The system will not use the global auto-precharge mode. - * However, it uses the page mode, so we set AL=0 - */ - additive_latency = 0; -#endif - - /* - * Validate additive latency - * FIXME: move to somewhere else to validate - * - * AL <= tRCD(min) - */ - if (mclk_to_picos(additive_latency) > trcd_ps) { - printf("Error: invalid additive latency exceeds tRCD(min).\n"); - return 1; - } - - /* - * RL = CL + AL; RL >= 3 for ODT_RD_CFG to be enabled - * WL = RL - 1; WL >= 3 for ODT_WL_CFG to be enabled - * ADD_LAT (the register) must be set to a value less - * than ACTTORW if WL = 1, then AL must be set to 1 - * RD_TO_PRE (the register) must be set to a minimum - * tRTP + AL if AL is nonzero - */ - - /* - * Additive latency will be applied only if the memctl option to - * use it. - */ - outpdimm->additive_latency = additive_latency; - - debug("tCKmin_ps = %u\n", outpdimm->tckmin_x_ps); - debug("trcd_ps = %u\n", outpdimm->trcd_ps); - debug("trp_ps = %u\n", outpdimm->trp_ps); - debug("tras_ps = %u\n", outpdimm->tras_ps); - debug("twr_ps = %u\n", outpdimm->twr_ps); - debug("twtr_ps = %u\n", outpdimm->twtr_ps); - debug("trfc_ps = %u\n", outpdimm->trfc_ps); - debug("trrd_ps = %u\n", outpdimm->trrd_ps); - debug("trc_ps = %u\n", outpdimm->trc_ps); - - return 0; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c deleted file mode 100644 index 34d8bc3a..0000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ /dev/null @@ -1,718 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -/* - * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. - * Based on code from spd_sdram.c - * Author: James Yang [at freescale.com] - */ - -#include <common.h> -#include <i2c.h> -#include <asm/fsl_ddr_sdram.h> -#include <asm/fsl_law.h> - -#include "ddr.h" - -void fsl_ddr_set_lawbar( - const common_timing_params_t *memctl_common_params, - unsigned int memctl_interleaved, - unsigned int ctrl_num); -void fsl_ddr_set_intl3r(const unsigned int granule_size); - -#if defined(SPD_EEPROM_ADDRESS) || \ - defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ - defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) -#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS, -}; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ - [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ -}; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ - [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ -}; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ - [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ - [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ - [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ -}; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ - [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ - [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */ -}; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ - [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ - [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ - [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ - [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */ - [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */ -}; - -#endif - -static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) -{ - int ret; - - i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); - - ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, - sizeof(generic_spd_eeprom_t)); - - if (ret) { - if (i2c_address == -#ifdef SPD_EEPROM_ADDRESS - SPD_EEPROM_ADDRESS -#elif defined(SPD_EEPROM_ADDRESS1) - SPD_EEPROM_ADDRESS1 -#endif - ) { - printf("DDR: failed to read SPD from address %u\n", - i2c_address); - } else { - debug("DDR: failed to read SPD from address %u\n", - i2c_address); - } - memset(spd, 0, sizeof(generic_spd_eeprom_t)); - } -} - -__attribute__((weak, alias("__get_spd"))) -void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address); - -void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - i2c_address = spd_i2c_addr[ctrl_num][i]; - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} -#else -void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ -} -#endif /* SPD_EEPROM_ADDRESSx */ - -/* - * ASSUMPTIONS: - * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller - * - Same memory data bus width on all controllers - * - * NOTES: - * - * The memory controller and associated documentation use confusing - * terminology when referring to the orgranization of DRAM. - * - * Here is a terminology translation table: - * - * memory controller/documention |industry |this code |signals - * -------------------------------|-----------|-----------|----------------- - * physical bank/bank |rank |rank |chip select (CS) - * logical bank/sub-bank |bank |bank |bank address (BA) - * page/row |row |page |row address - * ??? |column |column |column address - * - * The naming confusion is further exacerbated by the descriptions of the - * memory controller interleaving feature, where accesses are interleaved - * _BETWEEN_ two seperate memory controllers. This is configured only in - * CS0_CONFIG[INTLV_CTL] of each memory controller. - * - * memory controller documentation | number of chip selects - * | per memory controller supported - * --------------------------------|----------------------------------------- - * cache line interleaving | 1 (CS0 only) - * page interleaving | 1 (CS0 only) - * bank interleaving | 1 (CS0 only) - * superbank interleraving | depends on bank (chip select) - * | interleraving [rank interleaving] - * | mode used on every memory controller - * - * Even further confusing is the existence of the interleaving feature - * _WITHIN_ each memory controller. The feature is referred to in - * documentation as chip select interleaving or bank interleaving, - * although it is configured in the DDR_SDRAM_CFG field. - * - * Name of field | documentation name | this code - * -----------------------------|-----------------------|------------------ - * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving - * | interleaving - */ - -const char *step_string_tbl[] = { - "STEP_GET_SPD", - "STEP_COMPUTE_DIMM_PARMS", - "STEP_COMPUTE_COMMON_PARMS", - "STEP_GATHER_OPTS", - "STEP_ASSIGN_ADDRESSES", - "STEP_COMPUTE_REGS", - "STEP_PROGRAM_REGS", - "STEP_ALL" -}; - -const char * step_to_string(unsigned int step) { - - unsigned int s = __ilog2(step); - - if ((1 << s) != step) - return step_string_tbl[7]; - - return step_string_tbl[s]; -} - -static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, - unsigned int dbw_cap_adj[]) -{ - int i, j; - unsigned long long total_mem, current_mem_base, total_ctlr_mem; - unsigned long long rank_density, ctlr_density = 0; - - /* - * If a reduced data width is requested, but the SPD - * specifies a physically wider device, adjust the - * computed dimm capacities accordingly before - * assigning addresses. - */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - unsigned int found = 0; - - switch (pinfo->memctl_opts[i].data_bus_width) { - case 2: - /* 16-bit */ - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - unsigned int dw; - if (!pinfo->dimm_params[i][j].n_ranks) - continue; - dw = pinfo->dimm_params[i][j].primary_sdram_width; - if ((dw == 72 || dw == 64)) { - dbw_cap_adj[i] = 2; - break; - } else if ((dw == 40 || dw == 32)) { - dbw_cap_adj[i] = 1; - break; - } - } - break; - - case 1: - /* 32-bit */ - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - unsigned int dw; - dw = pinfo->dimm_params[i][j].data_width; - if (pinfo->dimm_params[i][j].n_ranks - && (dw == 72 || dw == 64)) { - /* - * FIXME: can't really do it - * like this because this just - * further reduces the memory - */ - found = 1; - break; - } - } - if (found) { - dbw_cap_adj[i] = 1; - } - break; - - case 0: - /* 64-bit */ - break; - - default: - printf("unexpected data bus width " - "specified controller %u\n", i); - return 1; - } - debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); - } - - current_mem_base = 0ull; - total_mem = 0; - if (pinfo->memctl_opts[0].memctl_interleaving) { - rank_density = pinfo->dimm_params[0][0].rank_density >> - dbw_cap_adj[0]; - switch (pinfo->memctl_opts[0].ba_intlv_ctl & - FSL_DDR_CS0_CS1_CS2_CS3) { - case FSL_DDR_CS0_CS1_CS2_CS3: - ctlr_density = 4 * rank_density; - break; - case FSL_DDR_CS0_CS1: - case FSL_DDR_CS0_CS1_AND_CS2_CS3: - ctlr_density = 2 * rank_density; - break; - case FSL_DDR_CS2_CS3: - default: - ctlr_density = rank_density; - break; - } - debug("rank density is 0x%llx, ctlr density is 0x%llx\n", - rank_density, ctlr_density); - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (pinfo->memctl_opts[i].memctl_interleaving) { - switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { - case FSL_DDR_CACHE_LINE_INTERLEAVING: - case FSL_DDR_PAGE_INTERLEAVING: - case FSL_DDR_BANK_INTERLEAVING: - case FSL_DDR_SUPERBANK_INTERLEAVING: - total_ctlr_mem = 2 * ctlr_density; - break; - case FSL_DDR_3WAY_1KB_INTERLEAVING: - case FSL_DDR_3WAY_4KB_INTERLEAVING: - case FSL_DDR_3WAY_8KB_INTERLEAVING: - total_ctlr_mem = 3 * ctlr_density; - break; - case FSL_DDR_4WAY_1KB_INTERLEAVING: - case FSL_DDR_4WAY_4KB_INTERLEAVING: - case FSL_DDR_4WAY_8KB_INTERLEAVING: - total_ctlr_mem = 4 * ctlr_density; - break; - default: - panic("Unknown interleaving mode"); - } - pinfo->common_timing_params[i].base_address = - current_mem_base; - pinfo->common_timing_params[i].total_mem = - total_ctlr_mem; - total_mem = current_mem_base + total_ctlr_mem; - debug("ctrl %d base 0x%llx\n", i, current_mem_base); - debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); - } else { - /* when 3rd controller not interleaved */ - current_mem_base = total_mem; - total_ctlr_mem = 0; - pinfo->common_timing_params[i].base_address = - current_mem_base; - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - unsigned long long cap = - pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; - pinfo->dimm_params[i][j].base_address = - current_mem_base; - debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); - current_mem_base += cap; - total_ctlr_mem += cap; - } - debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); - pinfo->common_timing_params[i].total_mem = - total_ctlr_mem; - total_mem += total_ctlr_mem; - } - } - } else { - /* - * Simple linear assignment if memory - * controllers are not interleaved. - */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - total_ctlr_mem = 0; - pinfo->common_timing_params[i].base_address = - current_mem_base; - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - /* Compute DIMM base addresses. */ - unsigned long long cap = - pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; - pinfo->dimm_params[i][j].base_address = - current_mem_base; - debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); - current_mem_base += cap; - total_ctlr_mem += cap; - } - debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); - pinfo->common_timing_params[i].total_mem = - total_ctlr_mem; - total_mem += total_ctlr_mem; - } - } - debug("Total mem by %s is 0x%llx\n", __func__, total_mem); - - return total_mem; -} - -/* Use weak function to allow board file to override the address assignment */ -__attribute__((weak, alias("__step_assign_addresses"))) -unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, - unsigned int dbw_cap_adj[]); - -unsigned long long -fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, - unsigned int size_only) -{ - unsigned int i, j; - unsigned long long total_mem = 0; - int assert_reset; - - fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg; - common_timing_params_t *timing_params = pinfo->common_timing_params; - assert_reset = board_need_mem_reset(); - - /* data bus width capacity adjust shift amount */ - unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS]; - - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - dbw_capacity_adjust[i] = 0; - } - - debug("starting at step %u (%s)\n", - start_step, step_to_string(start_step)); - - switch (start_step) { - case STEP_GET_SPD: -#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) - /* STEP 1: Gather all DIMM SPD data */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i); - } - - case STEP_COMPUTE_DIMM_PARMS: - /* STEP 2: Compute DIMM parameters from SPD data */ - - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - unsigned int retval; - generic_spd_eeprom_t *spd = - &(pinfo->spd_installed_dimms[i][j]); - dimm_params_t *pdimm = - &(pinfo->dimm_params[i][j]); - - retval = compute_dimm_parameters(spd, pdimm, i); -#ifdef CONFIG_SYS_DDR_RAW_TIMING - if (!i && !j && retval) { - printf("SPD error on controller %d! " - "Trying fallback to raw timing " - "calculation\n", i); - fsl_ddr_get_dimm_params(pdimm, i, j); - } -#else - if (retval == 2) { - printf("Error: compute_dimm_parameters" - " non-zero returned FATAL value " - "for memctl=%u dimm=%u\n", i, j); - return 0; - } -#endif - if (retval) { - debug("Warning: compute_dimm_parameters" - " non-zero return value for memctl=%u " - "dimm=%u\n", i, j); - } - } - } - -#elif defined(CONFIG_SYS_DDR_RAW_TIMING) - case STEP_COMPUTE_DIMM_PARMS: - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - dimm_params_t *pdimm = - &(pinfo->dimm_params[i][j]); - fsl_ddr_get_dimm_params(pdimm, i, j); - } - } - debug("Filling dimm parameters from board specific file\n"); -#endif - case STEP_COMPUTE_COMMON_PARMS: - /* - * STEP 3: Compute a common set of timing parameters - * suitable for all of the DIMMs on each memory controller - */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - debug("Computing lowest common DIMM" - " parameters for memctl=%u\n", i); - compute_lowest_common_dimm_parameters( - pinfo->dimm_params[i], - &timing_params[i], - CONFIG_DIMM_SLOTS_PER_CTLR); - } - - case STEP_GATHER_OPTS: - /* STEP 4: Gather configuration requirements from user */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - debug("Reloading memory controller " - "configuration options for memctl=%u\n", i); - /* - * This "reloads" the memory controller options - * to defaults. If the user "edits" an option, - * next_step points to the step after this, - * which is currently STEP_ASSIGN_ADDRESSES. - */ - populate_memctl_options( - timing_params[i].all_dimms_registered, - &pinfo->memctl_opts[i], - pinfo->dimm_params[i], i); - /* - * For RDIMMs, JEDEC spec requires clocks to be stable - * before reset signal is deasserted. For the boards - * using fixed parameters, this function should be - * be called from board init file. - */ - if (timing_params[i].all_dimms_registered) - assert_reset = 1; - } - if (assert_reset) { - debug("Asserting mem reset\n"); - board_assert_mem_reset(); - } - - case STEP_ASSIGN_ADDRESSES: - /* STEP 5: Assign addresses to chip selects */ - check_interleaving_options(pinfo); - total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust); - - case STEP_COMPUTE_REGS: - /* STEP 6: compute controller register values */ - debug("FSL Memory ctrl register computation\n"); - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (timing_params[i].ndimms_present == 0) { - memset(&ddr_reg[i], 0, - sizeof(fsl_ddr_cfg_regs_t)); - continue; - } - - compute_fsl_memctl_config_regs( - &pinfo->memctl_opts[i], - &ddr_reg[i], &timing_params[i], - pinfo->dimm_params[i], - dbw_capacity_adjust[i], - size_only); - } - - default: - break; - } - - { - /* - * Compute the amount of memory available just by - * looking for the highest valid CSn_BNDS value. - * This allows us to also experiment with using - * only CS0 when using dual-rank DIMMs. - */ - unsigned int max_end = 0; - - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) { - fsl_ddr_cfg_regs_t *reg = &ddr_reg[i]; - if (reg->cs[j].config & 0x80000000) { - unsigned int end; - /* - * 0xfffffff is a special value we put - * for unused bnds - */ - if (reg->cs[j].bnds == 0xffffffff) - continue; - end = reg->cs[j].bnds & 0xffff; - if (end > max_end) { - max_end = end; - } - } - } - } - - total_mem = 1 + (((unsigned long long)max_end << 24ULL) - | 0xFFFFFFULL); - } - - return total_mem; -} - -/* - * fsl_ddr_sdram() -- this is the main function to be called by - * initdram() in the board file. - * - * It returns amount of memory configured in bytes. - */ -phys_size_t fsl_ddr_sdram(void) -{ - unsigned int i; - unsigned int law_memctl = LAW_TRGT_IF_DDR_1; - unsigned long long total_memory; - fsl_ddr_info_t info; - int deassert_reset; - - /* Reset info structure. */ - memset(&info, 0, sizeof(fsl_ddr_info_t)); - - /* Compute it once normally. */ -#ifdef CONFIG_FSL_DDR_INTERACTIVE - if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */ - total_memory = fsl_ddr_interactive(&info, 0); - } else if (fsl_ddr_interactive_env_var_exists()) { - total_memory = fsl_ddr_interactive(&info, 1); - } else -#endif - total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); - - /* setup 3-way interleaving before enabling DDRC */ - if (info.memctl_opts[0].memctl_interleaving) { - switch (info.memctl_opts[0].memctl_interleaving_mode) { - case FSL_DDR_3WAY_1KB_INTERLEAVING: - case FSL_DDR_3WAY_4KB_INTERLEAVING: - case FSL_DDR_3WAY_8KB_INTERLEAVING: - fsl_ddr_set_intl3r( - info.memctl_opts[0].memctl_interleaving_mode); - break; - default: - break; - } - } - - /* - * Program configuration registers. - * JEDEC specs requires clocks to be stable before deasserting reset - * for RDIMMs. Clocks start after chip select is enabled and clock - * control register is set. During step 1, all controllers have their - * registers set but not enabled. Step 2 proceeds after deasserting - * reset through board FPGA or GPIO. - * For non-registered DIMMs, initialization can go through but it is - * also OK to follow the same flow. - */ - deassert_reset = board_need_mem_reset(); - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (info.common_timing_params[i].all_dimms_registered) - deassert_reset = 1; - } - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - debug("Programming controller %u\n", i); - if (info.common_timing_params[i].ndimms_present == 0) { - debug("No dimms present on controller %u; " - "skipping programming\n", i); - continue; - } - /* - * The following call with step = 1 returns before enabling - * the controller. It has to finish with step = 2 later. - */ - fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i, - deassert_reset ? 1 : 0); - } - if (deassert_reset) { - /* Use board FPGA or GPIO to deassert reset signal */ - debug("Deasserting mem reset\n"); - board_deassert_mem_reset(); - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - /* Call with step = 2 to continue initialization */ - fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), - i, 2); - } - } - - /* program LAWs */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (info.memctl_opts[i].memctl_interleaving) { - switch (info.memctl_opts[i].memctl_interleaving_mode) { - case FSL_DDR_CACHE_LINE_INTERLEAVING: - case FSL_DDR_PAGE_INTERLEAVING: - case FSL_DDR_BANK_INTERLEAVING: - case FSL_DDR_SUPERBANK_INTERLEAVING: - if (i == 0) { - law_memctl = LAW_TRGT_IF_DDR_INTRLV; - fsl_ddr_set_lawbar(&info.common_timing_params[i], - law_memctl, i); - } else if (i == 2) { - law_memctl = LAW_TRGT_IF_DDR_INTLV_34; - fsl_ddr_set_lawbar(&info.common_timing_params[i], - law_memctl, i); - } - break; - case FSL_DDR_3WAY_1KB_INTERLEAVING: - case FSL_DDR_3WAY_4KB_INTERLEAVING: - case FSL_DDR_3WAY_8KB_INTERLEAVING: - law_memctl = LAW_TRGT_IF_DDR_INTLV_123; - if (i == 0) { - fsl_ddr_set_lawbar(&info.common_timing_params[i], - law_memctl, i); - } - break; - case FSL_DDR_4WAY_1KB_INTERLEAVING: - case FSL_DDR_4WAY_4KB_INTERLEAVING: - case FSL_DDR_4WAY_8KB_INTERLEAVING: - law_memctl = LAW_TRGT_IF_DDR_INTLV_1234; - if (i == 0) - fsl_ddr_set_lawbar(&info.common_timing_params[i], - law_memctl, i); - /* place holder for future 4-way interleaving */ - break; - default: - break; - } - } else { - switch (i) { - case 0: - law_memctl = LAW_TRGT_IF_DDR_1; - break; - case 1: - law_memctl = LAW_TRGT_IF_DDR_2; - break; - case 2: - law_memctl = LAW_TRGT_IF_DDR_3; - break; - case 3: - law_memctl = LAW_TRGT_IF_DDR_4; - break; - default: - break; - } - fsl_ddr_set_lawbar(&info.common_timing_params[i], - law_memctl, i); - } - } - - debug("total_memory by %s = %llu\n", __func__, total_memory); - -#if !defined(CONFIG_PHYS_64BIT) - /* Check for 4G or more. Bad. */ - if (total_memory >= (1ull << 32)) { - puts("Detected "); - print_size(total_memory, " of memory\n"); - printf(" This U-Boot only supports < 4G of DDR\n"); - printf(" You could rebuild it with CONFIG_PHYS_64BIT\n"); - printf(" "); /* re-align to match init_func_ram print */ - total_memory = CONFIG_MAX_MEM_MAPPED; - } -#endif - - return total_memory; -} - -/* - * fsl_ddr_sdram_size() - This function only returns the size of the total - * memory without setting ddr control registers. - */ -phys_size_t -fsl_ddr_sdram_size(void) -{ - fsl_ddr_info_t info; - unsigned long long total_memory = 0; - - memset(&info, 0 , sizeof(fsl_ddr_info_t)); - - /* Compute it once normally. */ - total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); - - return total_memory; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c deleted file mode 100644 index 1297845..0000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ /dev/null @@ -1,1147 +0,0 @@ -/* - * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <hwconfig.h> -#include <asm/fsl_ddr_sdram.h> - -#include "ddr.h" - -/* - * Use our own stack based buffer before relocation to allow accessing longer - * hwconfig strings that might be in the environment before we've relocated. - * This is pretty fragile on both the use of stack and if the buffer is big - * enough. However we will get a warning from getenv_f for the later. - */ - -/* Board-specific functions defined in each board's ddr.c */ -extern void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num); - -struct dynamic_odt { - unsigned int odt_rd_cfg; - unsigned int odt_wr_cfg; - unsigned int odt_rtt_norm; - unsigned int odt_rtt_wr; -}; - -#ifdef CONFIG_FSL_DDR3 -static const struct dynamic_odt single_Q[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS_AND_OTHER_DIMM, - DDR3_RTT_20_OHM, - DDR3_RTT_120_OHM - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, /* tied high */ - DDR3_RTT_OFF, - DDR3_RTT_120_OHM - }, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS_AND_OTHER_DIMM, - DDR3_RTT_20_OHM, - DDR3_RTT_120_OHM - }, - { /* cs3 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, /* tied high */ - DDR3_RTT_OFF, - DDR3_RTT_120_OHM - } -}; - -static const struct dynamic_odt single_D[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_ALL, - DDR3_RTT_40_OHM, - DDR3_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR3_RTT_OFF, - DDR3_RTT_OFF - }, - {0, 0, 0, 0}, - {0, 0, 0, 0} -}; - -static const struct dynamic_odt single_S[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_ALL, - DDR3_RTT_40_OHM, - DDR3_RTT_OFF - }, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0}, -}; - -static const struct dynamic_odt dual_DD[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_SAME_DIMM, - DDR3_RTT_120_OHM, - DDR3_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR3_RTT_30_OHM, - DDR3_RTT_OFF - }, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_SAME_DIMM, - DDR3_RTT_120_OHM, - DDR3_RTT_OFF - }, - { /* cs3 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR3_RTT_30_OHM, - DDR3_RTT_OFF - } -}; - -static const struct dynamic_odt dual_DS[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_SAME_DIMM, - DDR3_RTT_120_OHM, - DDR3_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR3_RTT_30_OHM, - DDR3_RTT_OFF - }, - { /* cs2 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_ALL, - DDR3_RTT_20_OHM, - DDR3_RTT_120_OHM - }, - {0, 0, 0, 0} -}; -static const struct dynamic_odt dual_SD[4] = { - { /* cs0 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_ALL, - DDR3_RTT_20_OHM, - DDR3_RTT_120_OHM - }, - {0, 0, 0, 0}, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_SAME_DIMM, - DDR3_RTT_120_OHM, - DDR3_RTT_OFF - }, - { /* cs3 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR3_RTT_20_OHM, - DDR3_RTT_OFF - } -}; - -static const struct dynamic_odt dual_SS[4] = { - { /* cs0 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_ALL, - DDR3_RTT_30_OHM, - DDR3_RTT_120_OHM - }, - {0, 0, 0, 0}, - { /* cs2 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_ALL, - DDR3_RTT_30_OHM, - DDR3_RTT_120_OHM - }, - {0, 0, 0, 0} -}; - -static const struct dynamic_odt dual_D0[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_SAME_DIMM, - DDR3_RTT_40_OHM, - DDR3_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR3_RTT_OFF, - DDR3_RTT_OFF - }, - {0, 0, 0, 0}, - {0, 0, 0, 0} -}; - -static const struct dynamic_odt dual_0D[4] = { - {0, 0, 0, 0}, - {0, 0, 0, 0}, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_SAME_DIMM, - DDR3_RTT_40_OHM, - DDR3_RTT_OFF - }, - { /* cs3 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR3_RTT_OFF, - DDR3_RTT_OFF - } -}; - -static const struct dynamic_odt dual_S0[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR3_RTT_40_OHM, - DDR3_RTT_OFF - }, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0} - -}; - -static const struct dynamic_odt dual_0S[4] = { - {0, 0, 0, 0}, - {0, 0, 0, 0}, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR3_RTT_40_OHM, - DDR3_RTT_OFF - }, - {0, 0, 0, 0} - -}; - -static const struct dynamic_odt odt_unknown[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR3_RTT_120_OHM, - DDR3_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR3_RTT_120_OHM, - DDR3_RTT_OFF - }, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR3_RTT_120_OHM, - DDR3_RTT_OFF - }, - { /* cs3 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR3_RTT_120_OHM, - DDR3_RTT_OFF - } -}; -#else /* CONFIG_FSL_DDR3 */ -static const struct dynamic_odt single_Q[4] = { - {0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0} -}; - -static const struct dynamic_odt single_D[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_ALL, - DDR2_RTT_150_OHM, - DDR2_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - }, - {0, 0, 0, 0}, - {0, 0, 0, 0} -}; - -static const struct dynamic_odt single_S[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_ALL, - DDR2_RTT_150_OHM, - DDR2_RTT_OFF - }, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0}, -}; - -static const struct dynamic_odt dual_DD[4] = { - { /* cs0 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - }, - { /* cs2 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - { /* cs3 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - } -}; - -static const struct dynamic_odt dual_DS[4] = { - { /* cs0 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - }, - { /* cs2 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - {0, 0, 0, 0} -}; - -static const struct dynamic_odt dual_SD[4] = { - { /* cs0 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - {0, 0, 0, 0}, - { /* cs2 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - { /* cs3 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - } -}; - -static const struct dynamic_odt dual_SS[4] = { - { /* cs0 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - {0, 0, 0, 0}, - { /* cs2 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - {0, 0, 0, 0} -}; - -static const struct dynamic_odt dual_D0[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_ALL, - DDR2_RTT_150_OHM, - DDR2_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - }, - {0, 0, 0, 0}, - {0, 0, 0, 0} -}; - -static const struct dynamic_odt dual_0D[4] = { - {0, 0, 0, 0}, - {0, 0, 0, 0}, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_ALL, - DDR2_RTT_150_OHM, - DDR2_RTT_OFF - }, - { /* cs3 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - } -}; - -static const struct dynamic_odt dual_S0[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR2_RTT_150_OHM, - DDR2_RTT_OFF - }, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0} - -}; - -static const struct dynamic_odt dual_0S[4] = { - {0, 0, 0, 0}, - {0, 0, 0, 0}, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR2_RTT_150_OHM, - DDR2_RTT_OFF - }, - {0, 0, 0, 0} - -}; - -static const struct dynamic_odt odt_unknown[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - }, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - { /* cs3 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - } -}; -#endif - -/* - * Automatically seleect bank interleaving mode based on DIMMs - * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null. - * This function only deal with one or two slots per controller. - */ -static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm) -{ -#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) - if (pdimm[0].n_ranks == 4) - return FSL_DDR_CS0_CS1_CS2_CS3; - else if (pdimm[0].n_ranks == 2) - return FSL_DDR_CS0_CS1; -#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) -#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - if (pdimm[0].n_ranks == 4) - return FSL_DDR_CS0_CS1_CS2_CS3; -#endif - if (pdimm[0].n_ranks == 2) { - if (pdimm[1].n_ranks == 2) - return FSL_DDR_CS0_CS1_CS2_CS3; - else - return FSL_DDR_CS0_CS1; - } -#endif - return 0; -} - -unsigned int populate_memctl_options(int all_dimms_registered, - memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - unsigned int i; - char buffer[HWCONFIG_BUFFER_SIZE]; - char *buf = NULL; -#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2) - const struct dynamic_odt *pdodt = odt_unknown; -#endif - ulong ddr_freq; - - /* - * Extract hwconfig from environment since we have not properly setup - * the environment but need it for ddr config params - */ - if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) - buf = buffer; - -#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2) - /* Chip select options. */ - if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { - switch (pdimm[0].n_ranks) { - case 1: - pdodt = single_S; - break; - case 2: - pdodt = single_D; - break; - case 4: - pdodt = single_Q; - break; - } - } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { - switch (pdimm[0].n_ranks) { -#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - case 4: - pdodt = single_Q; - if (pdimm[1].n_ranks) - printf("Error: Quad- and Dual-rank DIMMs " - "cannot be used together\n"); - break; -#endif - case 2: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_DD; - break; - case 1: - pdodt = dual_DS; - break; - case 0: - pdodt = dual_D0; - break; - } - break; - case 1: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_SD; - break; - case 1: - pdodt = dual_SS; - break; - case 0: - pdodt = dual_S0; - break; - } - break; - case 0: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_0D; - break; - case 1: - pdodt = dual_0S; - break; - } - break; - } - } -#endif - - /* Pick chip-select local options. */ - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { -#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2) - popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg; - popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg; - popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm; - popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr; -#else - popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; - popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; -#endif - popts->cs_local_opts[i].auto_precharge = 0; - } - - /* Pick interleaving mode. */ - - /* - * 0 = no interleaving - * 1 = interleaving between 2 controllers - */ - popts->memctl_interleaving = 0; - - /* - * 0 = cacheline - * 1 = page - * 2 = (logical) bank - * 3 = superbank (only if CS interleaving is enabled) - */ - popts->memctl_interleaving_mode = 0; - - /* - * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl - * 1: page: bit to the left of the column bits selects the memctl - * 2: bank: bit to the left of the bank bits selects the memctl - * 3: superbank: bit to the left of the chip select selects the memctl - * - * NOTE: ba_intlv (rank interleaving) is independent of memory - * controller interleaving; it is only within a memory controller. - * Must use superbank interleaving if rank interleaving is used and - * memory controller interleaving is enabled. - */ - - /* - * 0 = no - * 0x40 = CS0,CS1 - * 0x20 = CS2,CS3 - * 0x60 = CS0,CS1 + CS2,CS3 - * 0x04 = CS0,CS1,CS2,CS3 - */ - popts->ba_intlv_ctl = 0; - - /* Memory Organization Parameters */ - popts->registered_dimm_en = all_dimms_registered; - - /* Operational Mode Paramters */ - - /* Pick ECC modes */ - popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */ -#ifdef CONFIG_DDR_ECC - if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) { - if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf)) - popts->ecc_mode = 1; - } else - popts->ecc_mode = 1; -#endif - popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */ - - /* - * Choose DQS config - * 0 for DDR1 - * 1 for DDR2 - */ -#if defined(CONFIG_FSL_DDR1) - popts->dqs_config = 0; -#elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) - popts->dqs_config = 1; -#endif - - /* Choose self-refresh during sleep. */ - popts->self_refresh_in_sleep = 1; - - /* Choose dynamic power management mode. */ - popts->dynamic_power = 0; - - /* - * check first dimm for primary sdram width - * presuming all dimms are similar - * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit - */ -#if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2) - if (pdimm[0].n_ranks != 0) { - if ((pdimm[0].data_width >= 64) && \ - (pdimm[0].data_width <= 72)) - popts->data_bus_width = 0; - else if ((pdimm[0].data_width >= 32) || \ - (pdimm[0].data_width <= 40)) - popts->data_bus_width = 1; - else { - panic("Error: data width %u is invalid!\n", - pdimm[0].data_width); - } - } -#else - if (pdimm[0].n_ranks != 0) { - if (pdimm[0].primary_sdram_width == 64) - popts->data_bus_width = 0; - else if (pdimm[0].primary_sdram_width == 32) - popts->data_bus_width = 1; - else if (pdimm[0].primary_sdram_width == 16) - popts->data_bus_width = 2; - else { - panic("Error: primary sdram width %u is invalid!\n", - pdimm[0].primary_sdram_width); - } - } -#endif - - popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0; - - /* Choose burst length. */ -#if defined(CONFIG_FSL_DDR3) -#if defined(CONFIG_E500MC) - popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */ - popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ -#else - if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) { - /* 32-bit or 16-bit bus */ - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - } else { - popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */ - popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ - } -#endif -#else - popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */ -#endif - - /* Choose ddr controller address mirror mode */ -#if defined(CONFIG_FSL_DDR3) - popts->mirrored_dimm = pdimm[0].mirrored_dimm; -#endif - - /* Global Timing Parameters. */ - debug("mclk_ps = %u ps\n", get_memory_clk_period_ps()); - - /* Pick a caslat override. */ - popts->cas_latency_override = 0; - popts->cas_latency_override_value = 3; - if (popts->cas_latency_override) { - debug("using caslat override value = %u\n", - popts->cas_latency_override_value); - } - - /* Decide whether to use the computed derated latency */ - popts->use_derated_caslat = 0; - - /* Choose an additive latency. */ - popts->additive_latency_override = 0; - popts->additive_latency_override_value = 3; - if (popts->additive_latency_override) { - debug("using additive latency override value = %u\n", - popts->additive_latency_override_value); - } - - /* - * 2T_EN setting - * - * Factors to consider for 2T_EN: - * - number of DIMMs installed - * - number of components, number of active ranks - * - how much time you want to spend playing around - */ - popts->twot_en = 0; - popts->threet_en = 0; - - /* for RDIMM, address parity enable */ - popts->ap_en = 1; - - /* - * BSTTOPRE precharge interval - * - * Set this to 0 for global auto precharge - * - * FIXME: Should this be configured in picoseconds? - * Why it should be in ps: better understanding of this - * relative to actual DRAM timing parameters such as tRAS. - * e.g. tRAS(min) = 40 ns - */ - popts->bstopre = 0x100; - - /* Minimum CKE pulse width -- tCKE(MIN) */ - popts->tcke_clock_pulse_width_ps - = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR); - - /* - * Window for four activates -- tFAW - * - * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only - * FIXME: varies depending upon number of column addresses or data - * FIXME: width, was considering looking at pdimm->primary_sdram_width - */ -#if defined(CONFIG_FSL_DDR1) - popts->tfaw_window_four_activates_ps = mclk_to_picos(1); - -#elif defined(CONFIG_FSL_DDR2) - /* - * x4/x8; some datasheets have 35000 - * x16 wide columns only? Use 50000? - */ - popts->tfaw_window_four_activates_ps = 37500; - -#elif defined(CONFIG_FSL_DDR3) - popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps; -#endif - popts->zq_en = 0; - popts->wrlvl_en = 0; -#if defined(CONFIG_FSL_DDR3) - /* - * due to ddr3 dimm is fly-by topology - * we suggest to enable write leveling to - * meet the tQDSS under different loading. - */ - popts->wrlvl_en = 1; - popts->zq_en = 1; - popts->wrlvl_override = 0; -#endif - - /* - * Check interleaving configuration from environment. - * Please refer to doc/README.fsl-ddr for the detail. - * - * If memory controller interleaving is enabled, then the data - * bus widths must be programmed identically for all memory controllers. - * - * XXX: Attempt to set all controllers to the same chip select - * interleaving mode. It will do a best effort to get the - * requested ranks interleaved together such that the result - * should be a subset of the requested configuration. - */ -#if (CONFIG_NUM_DDR_CONTROLLERS > 1) - if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) - goto done; - - if (pdimm[0].n_ranks == 0) { - printf("There is no rank on CS0 for controller %d.\n", ctrl_num); - popts->memctl_interleaving = 0; - goto done; - } - popts->memctl_interleaving = 1; - /* - * test null first. if CONFIG_HWCONFIG is not defined - * hwconfig_arg_cmp returns non-zero - */ - if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", - "null", buf)) { - popts->memctl_interleaving = 0; - debug("memory controller interleaving disabled.\n"); - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "cacheline", buf)) { - popts->memctl_interleaving_mode = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? - 0 : FSL_DDR_CACHE_LINE_INTERLEAVING; - popts->memctl_interleaving = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? - 0 : 1; - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "page", buf)) { - popts->memctl_interleaving_mode = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? - 0 : FSL_DDR_PAGE_INTERLEAVING; - popts->memctl_interleaving = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? - 0 : 1; - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "bank", buf)) { - popts->memctl_interleaving_mode = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? - 0 : FSL_DDR_BANK_INTERLEAVING; - popts->memctl_interleaving = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? - 0 : 1; - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "superbank", buf)) { - popts->memctl_interleaving_mode = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? - 0 : FSL_DDR_SUPERBANK_INTERLEAVING; - popts->memctl_interleaving = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? - 0 : 1; -#if (CONFIG_NUM_DDR_CONTROLLERS == 3) - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "3way_1KB", buf)) { - popts->memctl_interleaving_mode = - FSL_DDR_3WAY_1KB_INTERLEAVING; - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "3way_4KB", buf)) { - popts->memctl_interleaving_mode = - FSL_DDR_3WAY_4KB_INTERLEAVING; - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "3way_8KB", buf)) { - popts->memctl_interleaving_mode = - FSL_DDR_3WAY_8KB_INTERLEAVING; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 4) - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "4way_1KB", buf)) { - popts->memctl_interleaving_mode = - FSL_DDR_4WAY_1KB_INTERLEAVING; - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "4way_4KB", buf)) { - popts->memctl_interleaving_mode = - FSL_DDR_4WAY_4KB_INTERLEAVING; - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "4way_8KB", buf)) { - popts->memctl_interleaving_mode = - FSL_DDR_4WAY_8KB_INTERLEAVING; -#endif - } else { - popts->memctl_interleaving = 0; - printf("hwconfig has unrecognized parameter for ctlr_intlv.\n"); - } -done: -#endif - if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) && - (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { - /* test null first. if CONFIG_HWCONFIG is not defined, - * hwconfig_subarg_cmp_f returns non-zero */ - if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", - "null", buf)) - debug("bank interleaving disabled.\n"); - else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", - "cs0_cs1", buf)) - popts->ba_intlv_ctl = FSL_DDR_CS0_CS1; - else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", - "cs2_cs3", buf)) - popts->ba_intlv_ctl = FSL_DDR_CS2_CS3; - else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", - "cs0_cs1_and_cs2_cs3", buf)) - popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3; - else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", - "cs0_cs1_cs2_cs3", buf)) - popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; - else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", - "auto", buf)) - popts->ba_intlv_ctl = auto_bank_intlv(pdimm); - else - printf("hwconfig has unrecognized parameter for bank_intlv.\n"); - switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { - case FSL_DDR_CS0_CS1_CS2_CS3: -#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) - if (pdimm[0].n_ranks < 4) { - popts->ba_intlv_ctl = 0; - printf("Not enough bank(chip-select) for " - "CS0+CS1+CS2+CS3 on controller %d, " - "interleaving disabled!\n", ctrl_num); - } -#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) -#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - if (pdimm[0].n_ranks == 4) - break; -#endif - if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) { - popts->ba_intlv_ctl = 0; - printf("Not enough bank(chip-select) for " - "CS0+CS1+CS2+CS3 on controller %d, " - "interleaving disabled!\n", ctrl_num); - } - if (pdimm[0].capacity != pdimm[1].capacity) { - popts->ba_intlv_ctl = 0; - printf("Not identical DIMM size for " - "CS0+CS1+CS2+CS3 on controller %d, " - "interleaving disabled!\n", ctrl_num); - } -#endif - break; - case FSL_DDR_CS0_CS1: - if (pdimm[0].n_ranks < 2) { - popts->ba_intlv_ctl = 0; - printf("Not enough bank(chip-select) for " - "CS0+CS1 on controller %d, " - "interleaving disabled!\n", ctrl_num); - } - break; - case FSL_DDR_CS2_CS3: -#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) - if (pdimm[0].n_ranks < 4) { - popts->ba_intlv_ctl = 0; - printf("Not enough bank(chip-select) for CS2+CS3 " - "on controller %d, interleaving disabled!\n", ctrl_num); - } -#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) - if (pdimm[1].n_ranks < 2) { - popts->ba_intlv_ctl = 0; - printf("Not enough bank(chip-select) for CS2+CS3 " - "on controller %d, interleaving disabled!\n", ctrl_num); - } -#endif - break; - case FSL_DDR_CS0_CS1_AND_CS2_CS3: -#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) - if (pdimm[0].n_ranks < 4) { - popts->ba_intlv_ctl = 0; - printf("Not enough bank(CS) for CS0+CS1 and " - "CS2+CS3 on controller %d, " - "interleaving disabled!\n", ctrl_num); - } -#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) - if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) { - popts->ba_intlv_ctl = 0; - printf("Not enough bank(CS) for CS0+CS1 and " - "CS2+CS3 on controller %d, " - "interleaving disabled!\n", ctrl_num); - } -#endif - break; - default: - popts->ba_intlv_ctl = 0; - break; - } - } - - if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) { - if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf)) - popts->addr_hash = 0; - else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", - "true", buf)) - popts->addr_hash = 1; - } - - if (pdimm[0].n_ranks == 4) - popts->quad_rank_present = 1; - - ddr_freq = get_ddr_freq(0) / 1000000; - if (popts->registered_dimm_en) { - popts->rcw_override = 1; - popts->rcw_1 = 0x000a5a00; - if (ddr_freq <= 800) - popts->rcw_2 = 0x00000000; - else if (ddr_freq <= 1066) - popts->rcw_2 = 0x00100000; - else if (ddr_freq <= 1333) - popts->rcw_2 = 0x00200000; - else - popts->rcw_2 = 0x00300000; - } - - fsl_ddr_board_options(popts, pdimm, ctrl_num); - - return 0; -} - -void check_interleaving_options(fsl_ddr_info_t *pinfo) -{ - int i, j, k, check_n_ranks, intlv_invalid = 0; - unsigned int check_intlv, check_n_row_addr, check_n_col_addr; - unsigned long long check_rank_density; - struct dimm_params_s *dimm; - /* - * Check if all controllers are configured for memory - * controller interleaving. Identical dimms are recommended. At least - * the size, row and col address should be checked. - */ - j = 0; - check_n_ranks = pinfo->dimm_params[0][0].n_ranks; - check_rank_density = pinfo->dimm_params[0][0].rank_density; - check_n_row_addr = pinfo->dimm_params[0][0].n_row_addr; - check_n_col_addr = pinfo->dimm_params[0][0].n_col_addr; - check_intlv = pinfo->memctl_opts[0].memctl_interleaving_mode; - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - dimm = &pinfo->dimm_params[i][0]; - if (!pinfo->memctl_opts[i].memctl_interleaving) { - continue; - } else if (((check_rank_density != dimm->rank_density) || - (check_n_ranks != dimm->n_ranks) || - (check_n_row_addr != dimm->n_row_addr) || - (check_n_col_addr != dimm->n_col_addr) || - (check_intlv != - pinfo->memctl_opts[i].memctl_interleaving_mode))){ - intlv_invalid = 1; - break; - } else { - j++; - } - - } - if (intlv_invalid) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) - pinfo->memctl_opts[i].memctl_interleaving = 0; - printf("Not all DIMMs are identical. " - "Memory controller interleaving disabled.\n"); - } else { - switch (check_intlv) { - case FSL_DDR_CACHE_LINE_INTERLEAVING: - case FSL_DDR_PAGE_INTERLEAVING: - case FSL_DDR_BANK_INTERLEAVING: - case FSL_DDR_SUPERBANK_INTERLEAVING: - if (3 == CONFIG_NUM_DDR_CONTROLLERS) - k = 2; - else - k = CONFIG_NUM_DDR_CONTROLLERS; - break; - case FSL_DDR_3WAY_1KB_INTERLEAVING: - case FSL_DDR_3WAY_4KB_INTERLEAVING: - case FSL_DDR_3WAY_8KB_INTERLEAVING: - case FSL_DDR_4WAY_1KB_INTERLEAVING: - case FSL_DDR_4WAY_4KB_INTERLEAVING: - case FSL_DDR_4WAY_8KB_INTERLEAVING: - default: - k = CONFIG_NUM_DDR_CONTROLLERS; - break; - } - debug("%d of %d controllers are interleaving.\n", j, k); - if (j && (j != k)) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) - pinfo->memctl_opts[i].memctl_interleaving = 0; - printf("Not all controllers have compatible " - "interleaving mode. All disabled.\n"); - } - } - debug("Checking interleaving options completed\n"); -} - -int fsl_use_spd(void) -{ - int use_spd = 0; - -#ifdef CONFIG_DDR_SPD - char buffer[HWCONFIG_BUFFER_SIZE]; - char *buf = NULL; - - /* - * Extract hwconfig from environment since we have not properly setup - * the environment but need it for ddr config params - */ - if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) - buf = buffer; - - /* if hwconfig is not enabled, or "sdram" is not defined, use spd */ - if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) { - if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf)) - use_spd = 1; - else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", - "fixed", buf)) - use_spd = 0; - else - use_spd = 1; - } else - use_spd = 1; -#endif - - return use_spd; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c deleted file mode 100644 index acfe1f0..0000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <div64.h> - -#include "ddr.h" - -/* To avoid 64-bit full-divides, we factor this here */ -#define ULL_2E12 2000000000000ULL -#define UL_5POW12 244140625UL -#define UL_2POW13 (1UL << 13) - -#define ULL_8FS 0xFFFFFFFFULL - -/* - * Round up mclk_ps to nearest 1 ps in memory controller code - * if the error is 0.5ps or more. - * - * If an imprecise data rate is too high due to rounding error - * propagation, compute a suitably rounded mclk_ps to compute - * a working memory controller configuration. - */ -unsigned int get_memory_clk_period_ps(void) -{ - unsigned int data_rate = get_ddr_freq(0); - unsigned int result; - - /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ - unsigned long long rem, mclk_ps = ULL_2E12; - - /* Now perform the big divide, the result fits in 32-bits */ - rem = do_div(mclk_ps, data_rate); - result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; - - return result; -} - -/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ -unsigned int picos_to_mclk(unsigned int picos) -{ - unsigned long long clks, clks_rem; - unsigned long data_rate = get_ddr_freq(0); - - /* Short circuit for zero picos */ - if (!picos) - return 0; - - /* First multiply the time by the data rate (32x32 => 64) */ - clks = picos * (unsigned long long)data_rate; - /* - * Now divide by 5^12 and track the 32-bit remainder, then divide - * by 2*(2^12) using shifts (and updating the remainder). - */ - clks_rem = do_div(clks, UL_5POW12); - clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; - clks >>= 13; - - /* If we had a remainder greater than the 1ps error, then round up */ - if (clks_rem > data_rate) - clks++; - - /* Clamp to the maximum representable value */ - if (clks > ULL_8FS) - clks = ULL_8FS; - return (unsigned int) clks; -} - -unsigned int mclk_to_picos(unsigned int mclk) -{ - return get_memory_clk_period_ps() * mclk; -} - -void -__fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, - unsigned int law_memctl, - unsigned int ctrl_num) -{ - unsigned long long base = memctl_common_params->base_address; - unsigned long long size = memctl_common_params->total_mem; - - /* - * If no DIMMs on this controller, do not proceed any further. - */ - if (!memctl_common_params->ndimms_present) { - return; - } - -#if !defined(CONFIG_PHYS_64BIT) - if (base >= CONFIG_MAX_MEM_MAPPED) - return; - if ((base + size) >= CONFIG_MAX_MEM_MAPPED) - size = CONFIG_MAX_MEM_MAPPED - base; -#endif - if (set_ddr_laws(base, size, law_memctl) < 0) { - printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, - law_memctl); - return ; - } - debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", - base, size, law_memctl); -} - -__attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void -fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, - unsigned int memctl_interleaved, - unsigned int ctrl_num); - -void fsl_ddr_set_intl3r(const unsigned int granule_size) -{ -#ifdef CONFIG_E6500 - u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); - *mcintl3r = 0x80000000 | (granule_size & 0x1f); - debug("Enable MCINTL3R with granule size 0x%x\n", granule_size); -#endif -} - -u32 fsl_ddr_get_intl3r(void) -{ - u32 val = 0; -#ifdef CONFIG_E6500 - u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); - val = *mcintl3r; -#endif - return val; -} - -void board_add_ram_info(int use_default) -{ - ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); - -#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) - u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); -#endif -#if (CONFIG_NUM_DDR_CONTROLLERS > 1) - uint32_t cs0_config = in_be32(&ddr->cs0_config); -#endif - uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg); - int cas_lat; - -#if CONFIG_NUM_DDR_CONTROLLERS >= 2 - if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { - ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR2_ADDR; - sdram_cfg = in_be32(&ddr->sdram_cfg); - } -#endif -#if CONFIG_NUM_DDR_CONTROLLERS >= 3 - if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { - ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR3_ADDR; - sdram_cfg = in_be32(&ddr->sdram_cfg); - } -#endif - puts(" (DDR"); - switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> - SDRAM_CFG_SDRAM_TYPE_SHIFT) { - case SDRAM_TYPE_DDR1: - puts("1"); - break; - case SDRAM_TYPE_DDR2: - puts("2"); - break; - case SDRAM_TYPE_DDR3: - puts("3"); - break; - default: - puts("?"); - break; - } - - if (sdram_cfg & SDRAM_CFG_32_BE) - puts(", 32-bit"); - else if (sdram_cfg & SDRAM_CFG_16_BE) - puts(", 16-bit"); - else - puts(", 64-bit"); - - /* Calculate CAS latency based on timing cfg values */ - cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; - if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1) - cas_lat += (8 << 1); - printf(", CL=%d", cas_lat >> 1); - if (cas_lat & 0x1) - puts(".5"); - - if (sdram_cfg & SDRAM_CFG_ECC_EN) - puts(", ECC on)"); - else - puts(", ECC off)"); - -#if (CONFIG_NUM_DDR_CONTROLLERS == 3) -#ifdef CONFIG_E6500 - if (*mcintl3r & 0x80000000) { - puts("\n"); - puts(" DDR Controller Interleaving Mode: "); - switch (*mcintl3r & 0x1f) { - case FSL_DDR_3WAY_1KB_INTERLEAVING: - puts("3-way 1KB"); - break; - case FSL_DDR_3WAY_4KB_INTERLEAVING: - puts("3-way 4KB"); - break; - case FSL_DDR_3WAY_8KB_INTERLEAVING: - puts("3-way 8KB"); - break; - default: - puts("3-way UNKNOWN"); - break; - } - } -#endif -#endif -#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) - if (cs0_config & 0x20000000) { - puts("\n"); - puts(" DDR Controller Interleaving Mode: "); - - switch ((cs0_config >> 24) & 0xf) { - case FSL_DDR_CACHE_LINE_INTERLEAVING: - puts("cache line"); - break; - case FSL_DDR_PAGE_INTERLEAVING: - puts("page"); - break; - case FSL_DDR_BANK_INTERLEAVING: - puts("bank"); - break; - case FSL_DDR_SUPERBANK_INTERLEAVING: - puts("super-bank"); - break; - default: - puts("invalid"); - break; - } - } -#endif - - if ((sdram_cfg >> 8) & 0x7f) { - puts("\n"); - puts(" DDR Chip-Select Interleaving Mode: "); - switch(sdram_cfg >> 8 & 0x7f) { - case FSL_DDR_CS0_CS1_CS2_CS3: - puts("CS0+CS1+CS2+CS3"); - break; - case FSL_DDR_CS0_CS1: - puts("CS0+CS1"); - break; - case FSL_DDR_CS2_CS3: - puts("CS2+CS3"); - break; - case FSL_DDR_CS0_CS1_AND_CS2_CS3: - puts("CS0+CS1 and CS2+CS3"); - break; - default: - puts("invalid"); - break; - } - } -} diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c deleted file mode 100644 index 2d0fb43..0000000 --- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * Author: Dipen Dudhat <dipen.dudhat@freescale.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_ifc.h> - -void print_ifc_regs(void) -{ - int i, j; - - printf("IFC Controller Registers\n"); - for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) { - printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n", - i, get_ifc_cspr(i), i, get_ifc_amask(i), - i, get_ifc_csor(i)); - for (j = 0; j < 4; j++) - printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j)); - } -} - -void init_early_memctl_regs(void) -{ -#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) - set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0); - set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1); - set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); - set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); - -#ifndef CONFIG_A003399_NOR_WORKAROUND -#ifdef CONFIG_SYS_CSPR0_EXT - set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT); -#endif - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); - set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); -#endif -#endif - -#ifdef CONFIG_SYS_CSPR1_EXT - set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT); -#endif -#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) - set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); - set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); - set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2); - set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3); - - set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1); - set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1); - set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); -#endif - -#ifdef CONFIG_SYS_CSPR2_EXT - set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT); -#endif -#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) - set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); - set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); - set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2); - set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3); - - set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2); - set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); - set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); -#endif - -#ifdef CONFIG_SYS_CSPR3_EXT - set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT); -#endif -#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) - set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); - set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); - set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2); - set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3); - - set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3); - set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); - set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); -#endif - -#ifdef CONFIG_SYS_CSPR4_EXT - set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); -#endif -#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) - set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0); - set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1); - set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2); - set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3); - - set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4); - set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4); - set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4); -#endif - -#ifdef CONFIG_SYS_CSPR5_EXT - set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT); -#endif -#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5) - set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0); - set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1); - set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2); - set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3); - - set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5); - set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5); - set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5); -#endif - -#ifdef CONFIG_SYS_CSPR6_EXT - set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); -#endif -#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) - set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0); - set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1); - set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2); - set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3); - - set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6); - set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6); - set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6); -#endif - -#ifdef CONFIG_SYS_CSPR7_EXT - set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); -#endif -#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) - set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0); - set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1); - set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2); - set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3); - - set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7); - set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7); - set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7); -#endif -} diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 3c17c99..423a6fb 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -9,10 +9,16 @@ #ifdef CONFIG_MPC85xx #include <asm/config_mpc85xx.h> +#define CONFIG_SYS_FSL_DDR #endif #ifdef CONFIG_MPC86xx #include <asm/config_mpc86xx.h> +#define CONFIG_SYS_FSL_DDR +#endif + +#ifdef CONFIG_MPC83xx +#define CONFIG_SYS_FSL_DDR #endif #ifndef HWCONFIG_BUFFER_SIZE diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 4cc12ee..99e16bd 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -40,17 +40,20 @@ #elif defined(CONFIG_MPC8540) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8541) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8544) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 @@ -59,6 +62,7 @@ #elif defined(CONFIG_MPC8548) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 @@ -77,17 +81,20 @@ #elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8560) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8568) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define QE_MURAM_SIZE 0x10000UL #define MAX_QE_RISC 2 @@ -674,7 +681,8 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #endif -#elif defined(CONFIG_PPC_T1040) +#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ +defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ @@ -710,6 +718,50 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#define CONFIG_E6500 +#define CONFIG_SYS_PPC64 /* 64-bit core */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 +#define CONFIG_SYS_FSL_QMAN_V3 +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_PCI_VER_3_X +#if defined(CONFIG_PPC_T2080) +#define CONFIG_SYS_NUM_FM1_DTSEC 8 +#define CONFIG_SYS_NUM_FM1_10GEC 4 +#define CONFIG_SYS_FSL_SRDS_2 +#define CONFIG_SYS_FSL_SRIO_LIODN +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#elif defined(CONFIG_PPC_T2081) +#define CONFIG_SYS_NUM_FM1_DTSEC 6 +#define CONFIG_SYS_NUM_FM1_10GEC 2 +#endif +#define CONFIG_SYS_FSL_NUM_USB_CTRLS 2 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_PME_PLAT_CLK_DIV 1 +#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CONFIG_SYS_FM1_CLK 0 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" +#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_SFP_VER_3_0 +#define CONFIG_SYS_FSL_ISBC_VER 2 + #elif defined(CONFIG_PPC_C29X) #define CONFIG_MAX_CPUS 1 #define CONFIG_FSL_SDHC_V2_3 @@ -737,4 +789,10 @@ #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 #endif +#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ + !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ + !defined(CONFIG_SYS_FSL_DDRC_GEN3) +#define CONFIG_SYS_FSL_DDRC_GEN3 +#endif + #endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h index 694b110..4f9b225 100644 --- a/arch/powerpc/include/asm/config_mpc86xx.h +++ b/arch/powerpc/include/asm/config_mpc86xx.h @@ -7,6 +7,8 @@ #ifndef _ASM_MPC86xx_CONFIG_H_ #define _ASM_MPC86xx_CONFIG_H_ +#define CONFIG_SYS_FSL_DDR_86XX + /* SoC specific defines for Freescale MPC86xx processors */ #if defined(CONFIG_MPC8610) diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h deleted file mode 100644 index 99a72bc..0000000 --- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#ifndef DDR2_DIMM_PARAMS_H -#define DDR2_DIMM_PARAMS_H - -#define EDC_DATA_PARITY 1 -#define EDC_ECC 2 -#define EDC_AC_PARITY 4 - -/* Parameters for a DDR2 dimm computed from the SPD */ -typedef struct dimm_params_s { - - /* DIMM organization parameters */ - char mpart[19]; /* guaranteed null terminated */ - - unsigned int n_ranks; - unsigned long long rank_density; - unsigned long long capacity; - unsigned int data_width; - unsigned int primary_sdram_width; - unsigned int ec_sdram_width; - unsigned int registered_dimm; - unsigned int device_width; /* x4, x8, x16 components */ - - /* SDRAM device parameters */ - unsigned int n_row_addr; - unsigned int n_col_addr; - unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ - unsigned int n_banks_per_sdram_device; - unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ - unsigned int row_density; - - /* used in computing base address of DIMMs */ - unsigned long long base_address; - /* mirrored DIMMs */ - unsigned int mirrored_dimm; /* only for ddr3 */ - - /* DIMM timing parameters */ - - unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */ - unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */ - unsigned int taa_ps; /* minimum CAS latency time, only for ddr3 */ - unsigned int tfaw_ps; /* four active window delay, only for ddr3 */ - - /* - * SDRAM clock periods - * The range for these are 1000-10000 so a short should be sufficient - */ - unsigned int tckmin_x_ps; - unsigned int tckmin_x_minus_1_ps; - unsigned int tckmin_x_minus_2_ps; - unsigned int tckmax_ps; - - /* SPD-defined CAS latencies */ - unsigned int caslat_x; - unsigned int caslat_x_minus_1; - unsigned int caslat_x_minus_2; - - unsigned int caslat_lowest_derated; /* Derated CAS latency */ - - /* basic timing parameters */ - unsigned int trcd_ps; - unsigned int trp_ps; - unsigned int tras_ps; - - unsigned int twr_ps; /* maximum = 63750 ps */ - unsigned int twtr_ps; /* maximum = 63750 ps */ - unsigned int trfc_ps; /* max = 255 ns + 256 ns + .75 ns - = 511750 ps */ - - unsigned int trrd_ps; /* maximum = 63750 ps */ - unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ - - unsigned int refresh_rate_ps; - unsigned int extended_op_srt; - - /* DDR3 doesn't need these as below */ - unsigned int tis_ps; /* byte 32, spd->ca_setup */ - unsigned int tih_ps; /* byte 33, spd->ca_hold */ - unsigned int tds_ps; /* byte 34, spd->data_setup */ - unsigned int tdh_ps; /* byte 35, spd->data_hold */ - unsigned int trtp_ps; /* byte 38, spd->trtp */ - unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ - unsigned int tqhs_ps; /* byte 45, spd->tqhs */ - - /* DDR3 RDIMM */ - unsigned char rcw[16]; /* Register Control Word 0-15 */ -} dimm_params_t; - -extern unsigned int ddr_compute_dimm_parameters( - const generic_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number); - -#endif diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h deleted file mode 100644 index 2c3c514..0000000 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ /dev/null @@ -1,377 +0,0 @@ -/* - * Copyright 2008-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#ifndef FSL_DDR_MEMCTL_H -#define FSL_DDR_MEMCTL_H - -/* - * Pick a basic DDR Technology. - */ -#include <ddr_spd.h> - -#define SDRAM_TYPE_DDR1 2 -#define SDRAM_TYPE_DDR2 3 -#define SDRAM_TYPE_LPDDR1 6 -#define SDRAM_TYPE_DDR3 7 - -#define DDR_BL4 4 /* burst length 4 */ -#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ -#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ -#define DDR_BL8 8 /* burst length 8 */ - -#define DDR3_RTT_OFF 0 -#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ -#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ -#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ -#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ -#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ - -#define DDR2_RTT_OFF 0 -#define DDR2_RTT_75_OHM 1 -#define DDR2_RTT_150_OHM 2 -#define DDR2_RTT_50_OHM 3 - -#if defined(CONFIG_FSL_DDR1) -#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) -typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; -#ifndef CONFIG_FSL_SDRAM_TYPE -#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1 -#endif -#elif defined(CONFIG_FSL_DDR2) -#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) -typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; -#ifndef CONFIG_FSL_SDRAM_TYPE -#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 -#endif -#elif defined(CONFIG_FSL_DDR3) -#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ -typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; -#ifndef CONFIG_FSL_SDRAM_TYPE -#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 -#endif -#endif /* #if defined(CONFIG_FSL_DDR1) */ - -#define FSL_DDR_ODT_NEVER 0x0 -#define FSL_DDR_ODT_CS 0x1 -#define FSL_DDR_ODT_ALL_OTHER_CS 0x2 -#define FSL_DDR_ODT_OTHER_DIMM 0x3 -#define FSL_DDR_ODT_ALL 0x4 -#define FSL_DDR_ODT_SAME_DIMM 0x5 -#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6 -#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 - -/* define bank(chip select) interleaving mode */ -#define FSL_DDR_CS0_CS1 0x40 -#define FSL_DDR_CS2_CS3 0x20 -#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) -#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) - -/* define memory controller interleaving mode */ -#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 -#define FSL_DDR_PAGE_INTERLEAVING 0x1 -#define FSL_DDR_BANK_INTERLEAVING 0x2 -#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 -#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA -#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC -#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD -/* placeholder for 4-way interleaving */ -#define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A -#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C -#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D - -#define SDRAM_CS_CONFIG_EN 0x80000000 - -/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration - */ -#define SDRAM_CFG_MEM_EN 0x80000000 -#define SDRAM_CFG_SREN 0x40000000 -#define SDRAM_CFG_ECC_EN 0x20000000 -#define SDRAM_CFG_RD_EN 0x10000000 -#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 -#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 -#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 -#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 -#define SDRAM_CFG_DYN_PWR 0x00200000 -#define SDRAM_CFG_DBW_MASK 0x00180000 -#define SDRAM_CFG_DBW_SHIFT 19 -#define SDRAM_CFG_32_BE 0x00080000 -#define SDRAM_CFG_16_BE 0x00100000 -#define SDRAM_CFG_8_BE 0x00040000 -#define SDRAM_CFG_NCAP 0x00020000 -#define SDRAM_CFG_2T_EN 0x00008000 -#define SDRAM_CFG_BI 0x00000001 - -#define SDRAM_CFG2_D_INIT 0x00000010 -#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 -#define SDRAM_CFG2_ODT_NEVER 0 -#define SDRAM_CFG2_ODT_ONLY_WRITE 1 -#define SDRAM_CFG2_ODT_ONLY_READ 2 -#define SDRAM_CFG2_ODT_ALWAYS 3 - -#define TIMING_CFG_2_CPO_MASK 0x0F800000 - -#if defined(CONFIG_P4080) -#define RD_TO_PRE_MASK 0xf -#define RD_TO_PRE_SHIFT 13 -#define WR_DATA_DELAY_MASK 0xf -#define WR_DATA_DELAY_SHIFT 9 -#else -#define RD_TO_PRE_MASK 0x7 -#define RD_TO_PRE_SHIFT 13 -#define WR_DATA_DELAY_MASK 0x7 -#define WR_DATA_DELAY_SHIFT 10 -#endif - -/* DDR_MD_CNTL */ -#define MD_CNTL_MD_EN 0x80000000 -#define MD_CNTL_CS_SEL_CS0 0x00000000 -#define MD_CNTL_CS_SEL_CS1 0x10000000 -#define MD_CNTL_CS_SEL_CS2 0x20000000 -#define MD_CNTL_CS_SEL_CS3 0x30000000 -#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000 -#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000 -#define MD_CNTL_MD_SEL_MR 0x00000000 -#define MD_CNTL_MD_SEL_EMR 0x01000000 -#define MD_CNTL_MD_SEL_EMR2 0x02000000 -#define MD_CNTL_MD_SEL_EMR3 0x03000000 -#define MD_CNTL_SET_REF 0x00800000 -#define MD_CNTL_SET_PRE 0x00400000 -#define MD_CNTL_CKE_CNTL_LOW 0x00100000 -#define MD_CNTL_CKE_CNTL_HIGH 0x00200000 -#define MD_CNTL_WRCW 0x00080000 -#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) - -/* DDR_CDR1 */ -#define DDR_CDR1_DHC_EN 0x80000000 -#define DDR_CDR1_ODT_SHIFT 17 -#define DDR_CDR1_ODT_MASK 0x6 -#define DDR_CDR2_ODT_MASK 0x1 -#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) -#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) - -#if (defined(CONFIG_SYS_FSL_DDR_VER) && \ - (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) -#define DDR_CDR_ODT_OFF 0x0 -#define DDR_CDR_ODT_120ohm 0x1 -#define DDR_CDR_ODT_180ohm 0x2 -#define DDR_CDR_ODT_75ohm 0x3 -#define DDR_CDR_ODT_110ohm 0x4 -#define DDR_CDR_ODT_60hm 0x5 -#define DDR_CDR_ODT_70ohm 0x6 -#define DDR_CDR_ODT_47ohm 0x7 -#else -#define DDR_CDR_ODT_75ohm 0x0 -#define DDR_CDR_ODT_55ohm 0x1 -#define DDR_CDR_ODT_60ohm 0x2 -#define DDR_CDR_ODT_50ohm 0x3 -#define DDR_CDR_ODT_150ohm 0x4 -#define DDR_CDR_ODT_43ohm 0x5 -#define DDR_CDR_ODT_120ohm 0x6 -#endif - -/* Record of register values computed */ -typedef struct fsl_ddr_cfg_regs_s { - struct { - unsigned int bnds; - unsigned int config; - unsigned int config_2; - } cs[CONFIG_CHIP_SELECTS_PER_CTRL]; - unsigned int timing_cfg_3; - unsigned int timing_cfg_0; - unsigned int timing_cfg_1; - unsigned int timing_cfg_2; - unsigned int ddr_sdram_cfg; - unsigned int ddr_sdram_cfg_2; - unsigned int ddr_sdram_mode; - unsigned int ddr_sdram_mode_2; - unsigned int ddr_sdram_mode_3; - unsigned int ddr_sdram_mode_4; - unsigned int ddr_sdram_mode_5; - unsigned int ddr_sdram_mode_6; - unsigned int ddr_sdram_mode_7; - unsigned int ddr_sdram_mode_8; - unsigned int ddr_sdram_md_cntl; - unsigned int ddr_sdram_interval; - unsigned int ddr_data_init; - unsigned int ddr_sdram_clk_cntl; - unsigned int ddr_init_addr; - unsigned int ddr_init_ext_addr; - unsigned int timing_cfg_4; - unsigned int timing_cfg_5; - unsigned int ddr_zq_cntl; - unsigned int ddr_wrlvl_cntl; - unsigned int ddr_wrlvl_cntl_2; - unsigned int ddr_wrlvl_cntl_3; - unsigned int ddr_sr_cntr; - unsigned int ddr_sdram_rcw_1; - unsigned int ddr_sdram_rcw_2; - unsigned int ddr_eor; - unsigned int ddr_cdr1; - unsigned int ddr_cdr2; - unsigned int err_disable; - unsigned int err_int_en; - unsigned int debug[32]; -} fsl_ddr_cfg_regs_t; - -typedef struct memctl_options_partial_s { - unsigned int all_dimms_ecc_capable; - unsigned int all_dimms_tckmax_ps; - unsigned int all_dimms_burst_lengths_bitmask; - unsigned int all_dimms_registered; - unsigned int all_dimms_unbuffered; - /* unsigned int lowest_common_SPD_caslat; */ - unsigned int all_dimms_minimum_trcd_ps; -} memctl_options_partial_t; - -#define DDR_DATA_BUS_WIDTH_64 0 -#define DDR_DATA_BUS_WIDTH_32 1 -#define DDR_DATA_BUS_WIDTH_16 2 -/* - * Generalized parameters for memory controller configuration, - * might be a little specific to the FSL memory controller - */ -typedef struct memctl_options_s { - /* - * Memory organization parameters - * - * if DIMM is present in the system - * where DIMMs are with respect to chip select - * where chip selects are with respect to memory boundaries - */ - unsigned int registered_dimm_en; /* use registered DIMM support */ - - /* Options local to a Chip Select */ - struct cs_local_opts_s { - unsigned int auto_precharge; - unsigned int odt_rd_cfg; - unsigned int odt_wr_cfg; - unsigned int odt_rtt_norm; - unsigned int odt_rtt_wr; - } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; - - /* Special configurations for chip select */ - unsigned int memctl_interleaving; - unsigned int memctl_interleaving_mode; - unsigned int ba_intlv_ctl; - unsigned int addr_hash; - - /* Operational mode parameters */ - unsigned int ecc_mode; /* Use ECC? */ - /* Initialize ECC using memory controller? */ - unsigned int ecc_init_using_memctl; - unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ - /* SREN - self-refresh during sleep */ - unsigned int self_refresh_in_sleep; - unsigned int dynamic_power; /* DYN_PWR */ - /* memory data width to use (16-bit, 32-bit, 64-bit) */ - unsigned int data_bus_width; - unsigned int burst_length; /* BL4, OTF and BL8 */ - /* On-The-Fly Burst Chop enable */ - unsigned int otf_burst_chop_en; - /* mirrior DIMMs for DDR3 */ - unsigned int mirrored_dimm; - unsigned int quad_rank_present; - unsigned int ap_en; /* address parity enable for RDIMM */ - unsigned int x4_en; /* enable x4 devices */ - - /* Global Timing Parameters */ - unsigned int cas_latency_override; - unsigned int cas_latency_override_value; - unsigned int use_derated_caslat; - unsigned int additive_latency_override; - unsigned int additive_latency_override_value; - - unsigned int clk_adjust; /* */ - unsigned int cpo_override; - unsigned int write_data_delay; /* DQS adjust */ - - unsigned int wrlvl_override; - unsigned int wrlvl_sample; /* Write leveling */ - unsigned int wrlvl_start; - unsigned int wrlvl_ctl_2; - unsigned int wrlvl_ctl_3; - - unsigned int half_strength_driver_enable; - unsigned int twot_en; - unsigned int threet_en; - unsigned int bstopre; - unsigned int tcke_clock_pulse_width_ps; /* tCKE */ - unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */ - - /* Rtt impedance */ - unsigned int rtt_override; /* rtt_override enable */ - unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ - unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ - - /* Automatic self refresh */ - unsigned int auto_self_refresh_en; - unsigned int sr_it; - /* ZQ calibration */ - unsigned int zq_en; - /* Write leveling */ - unsigned int wrlvl_en; - /* RCW override for RDIMM */ - unsigned int rcw_override; - unsigned int rcw_1; - unsigned int rcw_2; - /* control register 1 */ - unsigned int ddr_cdr1; - unsigned int ddr_cdr2; - - unsigned int trwt_override; - unsigned int trwt; /* read-to-write turnaround */ -} memctl_options_t; - -extern phys_size_t fsl_ddr_sdram(void); -extern phys_size_t fsl_ddr_sdram_size(void); -extern int fsl_use_spd(void); -extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num, int step); -u32 fsl_ddr_get_intl3r(void); - -static void __board_assert_mem_reset(void) -{ -} - -static void __board_deassert_mem_reset(void) -{ -} - -void board_assert_mem_reset(void) - __attribute__((weak, alias("__board_assert_mem_reset"))); - -void board_deassert_mem_reset(void) - __attribute__((weak, alias("__board_deassert_mem_reset"))); - -static int __board_need_mem_reset(void) -{ - return 0; -} - -int board_need_mem_reset(void) - __attribute__((weak, alias("__board_need_mem_reset"))); - -/* - * The 85xx boards have a common prototype for fixed_sdram so put the - * declaration here. - */ -#ifdef CONFIG_MPC85xx -extern phys_size_t fixed_sdram(void); -#endif - -#if defined(CONFIG_DDR_ECC) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - - -typedef struct fixed_ddr_parm{ - int min_freq; - int max_freq; - fsl_ddr_cfg_regs_t *ddr_settings; -} fixed_ddr_parm_t; -#endif diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h deleted file mode 100644 index a945e4b..0000000 --- a/arch/powerpc/include/asm/fsl_ifc.h +++ /dev/null @@ -1,986 +0,0 @@ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * Author: Dipen Dudhat <dipen.dudhat@freescale.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_PPC_FSL_IFC_H -#define __ASM_PPC_FSL_IFC_H - -#ifdef CONFIG_FSL_IFC -#include <config.h> -#include <common.h> - -/* - * CSPR - Chip Select Property Register - */ -#define CSPR_BA 0xFFFF0000 -#define CSPR_BA_SHIFT 16 -#define CSPR_PORT_SIZE 0x00000180 -#define CSPR_PORT_SIZE_SHIFT 7 -/* Port Size 8 bit */ -#define CSPR_PORT_SIZE_8 0x00000080 -/* Port Size 16 bit */ -#define CSPR_PORT_SIZE_16 0x00000100 -/* Port Size 32 bit */ -#define CSPR_PORT_SIZE_32 0x00000180 -/* Write Protect */ -#define CSPR_WP 0x00000040 -#define CSPR_WP_SHIFT 6 -/* Machine Select */ -#define CSPR_MSEL 0x00000006 -#define CSPR_MSEL_SHIFT 1 -/* NOR */ -#define CSPR_MSEL_NOR 0x00000000 -/* NAND */ -#define CSPR_MSEL_NAND 0x00000002 -/* GPCM */ -#define CSPR_MSEL_GPCM 0x00000004 -/* Bank Valid */ -#define CSPR_V 0x00000001 -#define CSPR_V_SHIFT 0 - -/* Convert an address into the right format for the CSPR Registers */ -#define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000) - -/* - * Address Mask Register - */ -#define IFC_AMASK_MASK 0xFFFF0000 -#define IFC_AMASK_SHIFT 16 -#define IFC_AMASK(n) (IFC_AMASK_MASK << \ - (__ilog2(n) - IFC_AMASK_SHIFT)) - -/* - * Chip Select Option Register IFC_NAND Machine - */ -/* Enable ECC Encoder */ -#define CSOR_NAND_ECC_ENC_EN 0x80000000 -#define CSOR_NAND_ECC_MODE_MASK 0x30000000 -/* 4 bit correction per 520 Byte sector */ -#define CSOR_NAND_ECC_MODE_4 0x00000000 -/* 8 bit correction per 528 Byte sector */ -#define CSOR_NAND_ECC_MODE_8 0x10000000 -/* Enable ECC Decoder */ -#define CSOR_NAND_ECC_DEC_EN 0x04000000 -/* Row Address Length */ -#define CSOR_NAND_RAL_MASK 0x01800000 -#define CSOR_NAND_RAL_SHIFT 20 -#define CSOR_NAND_RAL_1 0x00000000 -#define CSOR_NAND_RAL_2 0x00800000 -#define CSOR_NAND_RAL_3 0x01000000 -#define CSOR_NAND_RAL_4 0x01800000 -/* Page Size 512b, 2k, 4k */ -#define CSOR_NAND_PGS_MASK 0x00180000 -#define CSOR_NAND_PGS_SHIFT 16 -#define CSOR_NAND_PGS_512 0x00000000 -#define CSOR_NAND_PGS_2K 0x00080000 -#define CSOR_NAND_PGS_4K 0x00100000 -/* Spare region Size */ -#define CSOR_NAND_SPRZ_MASK 0x0000E000 -#define CSOR_NAND_SPRZ_SHIFT 13 -#define CSOR_NAND_SPRZ_16 0x00000000 -#define CSOR_NAND_SPRZ_64 0x00002000 -#define CSOR_NAND_SPRZ_128 0x00004000 -#define CSOR_NAND_SPRZ_210 0x00006000 -#define CSOR_NAND_SPRZ_218 0x00008000 -#define CSOR_NAND_SPRZ_224 0x0000A000 -/* Pages Per Block */ -#define CSOR_NAND_PB_MASK 0x00000700 -#define CSOR_NAND_PB_SHIFT 8 -#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) -/* Time for Read Enable High to Output High Impedance */ -#define CSOR_NAND_TRHZ_MASK 0x0000001C -#define CSOR_NAND_TRHZ_SHIFT 2 -#define CSOR_NAND_TRHZ_20 0x00000000 -#define CSOR_NAND_TRHZ_40 0x00000004 -#define CSOR_NAND_TRHZ_60 0x00000008 -#define CSOR_NAND_TRHZ_80 0x0000000C -#define CSOR_NAND_TRHZ_100 0x00000010 -/* Buffer control disable */ -#define CSOR_NAND_BCTLD 0x00000001 - -/* - * Chip Select Option Register - NOR Flash Mode - */ -/* Enable Address shift Mode */ -#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 -/* Page Read Enable from NOR device */ -#define CSOR_NOR_PGRD_EN 0x10000000 -/* AVD Toggle Enable during Burst Program */ -#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 -/* Address Data Multiplexing Shift */ -#define CSOR_NOR_ADM_MASK 0x0003E000 -#define CSOR_NOR_ADM_SHIFT_SHIFT 13 -#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) -/* Type of the NOR device hooked */ -#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 -#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 -/* Time for Read Enable High to Output High Impedance */ -#define CSOR_NOR_TRHZ_MASK 0x0000001C -#define CSOR_NOR_TRHZ_SHIFT 2 -#define CSOR_NOR_TRHZ_20 0x00000000 -#define CSOR_NOR_TRHZ_40 0x00000004 -#define CSOR_NOR_TRHZ_60 0x00000008 -#define CSOR_NOR_TRHZ_80 0x0000000C -#define CSOR_NOR_TRHZ_100 0x00000010 -/* Buffer control disable */ -#define CSOR_NOR_BCTLD 0x00000001 - -/* - * Chip Select Option Register - GPCM Mode - */ -/* GPCM Mode - Normal */ -#define CSOR_GPCM_GPMODE_NORMAL 0x00000000 -/* GPCM Mode - GenericASIC */ -#define CSOR_GPCM_GPMODE_ASIC 0x80000000 -/* Parity Mode odd/even */ -#define CSOR_GPCM_PARITY_EVEN 0x40000000 -/* Parity Checking enable/disable */ -#define CSOR_GPCM_PAR_EN 0x20000000 -/* GPCM Timeout Count */ -#define CSOR_GPCM_GPTO_MASK 0x0F000000 -#define CSOR_GPCM_GPTO_SHIFT 24 -#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) -/* GPCM External Access Termination mode for read access */ -#define CSOR_GPCM_RGETA_EXT 0x00080000 -/* GPCM External Access Termination mode for write access */ -#define CSOR_GPCM_WGETA_EXT 0x00040000 -/* Address Data Multiplexing Shift */ -#define CSOR_GPCM_ADM_MASK 0x0003E000 -#define CSOR_GPCM_ADM_SHIFT_SHIFT 13 -#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) -/* Generic ASIC Parity error indication delay */ -#define CSOR_GPCM_GAPERRD_MASK 0x00000180 -#define CSOR_GPCM_GAPERRD_SHIFT 7 -#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) -/* Time for Read Enable High to Output High Impedance */ -#define CSOR_GPCM_TRHZ_MASK 0x0000001C -#define CSOR_GPCM_TRHZ_20 0x00000000 -#define CSOR_GPCM_TRHZ_40 0x00000004 -#define CSOR_GPCM_TRHZ_60 0x00000008 -#define CSOR_GPCM_TRHZ_80 0x0000000C -#define CSOR_GPCM_TRHZ_100 0x00000010 -/* Buffer control disable */ -#define CSOR_GPCM_BCTLD 0x00000001 - -/* - * Flash Timing Registers (FTIM0 - FTIM2_CSn) - */ -/* - * FTIM0 - NAND Flash Mode - */ -#define FTIM0_NAND 0x7EFF3F3F -#define FTIM0_NAND_TCCST_SHIFT 25 -#define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) -#define FTIM0_NAND_TWP_SHIFT 16 -#define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) -#define FTIM0_NAND_TWCHT_SHIFT 8 -#define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) -#define FTIM0_NAND_TWH_SHIFT 0 -#define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) -/* - * FTIM1 - NAND Flash Mode - */ -#define FTIM1_NAND 0xFFFF3FFF -#define FTIM1_NAND_TADLE_SHIFT 24 -#define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT) -#define FTIM1_NAND_TWBE_SHIFT 16 -#define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT) -#define FTIM1_NAND_TRR_SHIFT 8 -#define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) -#define FTIM1_NAND_TRP_SHIFT 0 -#define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) -/* - * FTIM2 - NAND Flash Mode - */ -#define FTIM2_NAND 0x1FE1F8FF -#define FTIM2_NAND_TRAD_SHIFT 21 -#define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT) -#define FTIM2_NAND_TREH_SHIFT 11 -#define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT) -#define FTIM2_NAND_TWHRE_SHIFT 0 -#define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT) -/* - * FTIM3 - NAND Flash Mode - */ -#define FTIM3_NAND 0xFF000000 -#define FTIM3_NAND_TWW_SHIFT 24 -#define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) - -/* - * FTIM0 - NOR Flash Mode - */ -#define FTIM0_NOR 0xF03F3F3F -#define FTIM0_NOR_TACSE_SHIFT 28 -#define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) -#define FTIM0_NOR_TEADC_SHIFT 16 -#define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) -#define FTIM0_NOR_TAVDS_SHIFT 8 -#define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) -#define FTIM0_NOR_TEAHC_SHIFT 0 -#define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) -/* - * FTIM1 - NOR Flash Mode - */ -#define FTIM1_NOR 0xFF003F3F -#define FTIM1_NOR_TACO_SHIFT 24 -#define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) -#define FTIM1_NOR_TRAD_NOR_SHIFT 8 -#define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) -#define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 -#define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) -/* - * FTIM2 - NOR Flash Mode - */ -#define FTIM2_NOR 0x0F3CFCFF -#define FTIM2_NOR_TCS_SHIFT 24 -#define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) -#define FTIM2_NOR_TCH_SHIFT 18 -#define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) -#define FTIM2_NOR_TWPH_SHIFT 10 -#define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) -#define FTIM2_NOR_TWP_SHIFT 0 -#define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) - -/* - * FTIM0 - Normal GPCM Mode - */ -#define FTIM0_GPCM 0xF03F3F3F -#define FTIM0_GPCM_TACSE_SHIFT 28 -#define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) -#define FTIM0_GPCM_TEADC_SHIFT 16 -#define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) -#define FTIM0_GPCM_TAVDS_SHIFT 8 -#define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) -#define FTIM0_GPCM_TEAHC_SHIFT 0 -#define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) -/* - * FTIM1 - Normal GPCM Mode - */ -#define FTIM1_GPCM 0xFF003F00 -#define FTIM1_GPCM_TACO_SHIFT 24 -#define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) -#define FTIM1_GPCM_TRAD_SHIFT 8 -#define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) -/* - * FTIM2 - Normal GPCM Mode - */ -#define FTIM2_GPCM 0x0F3C00FF -#define FTIM2_GPCM_TCS_SHIFT 24 -#define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) -#define FTIM2_GPCM_TCH_SHIFT 18 -#define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) -#define FTIM2_GPCM_TWP_SHIFT 0 -#define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) - -/* - * Ready Busy Status Register (RB_STAT) - */ -/* CSn is READY */ -#define IFC_RB_STAT_READY_CS0 0x80000000 -#define IFC_RB_STAT_READY_CS1 0x40000000 -#define IFC_RB_STAT_READY_CS2 0x20000000 -#define IFC_RB_STAT_READY_CS3 0x10000000 - -/* - * General Control Register (GCR) - */ -#define IFC_GCR_MASK 0x8000F800 -/* reset all IFC hardware */ -#define IFC_GCR_SOFT_RST_ALL 0x80000000 -/* Turnaroud Time of external buffer */ -#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 -#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 - -/* - * Common Event and Error Status Register (CM_EVTER_STAT) - */ -/* Chip select error */ -#define IFC_CM_EVTER_STAT_CSER 0x80000000 - -/* - * Common Event and Error Enable Register (CM_EVTER_EN) - */ -/* Chip select error checking enable */ -#define IFC_CM_EVTER_EN_CSEREN 0x80000000 - -/* - * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) - */ -/* Chip select error interrupt enable */ -#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 - -/* - * Common Transfer Error Attribute Register-0 (CM_ERATTR0) - */ -/* transaction type of error Read/Write */ -#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 -#define IFC_CM_ERATTR0_ERAID 0x0FF00000 -#define IFC_CM_ERATTR0_ESRCID 0x0000FF00 - -/* - * Clock Control Register (CCR) - */ -#define IFC_CCR_MASK 0x0F0F8800 -/* Clock division ratio */ -#define IFC_CCR_CLK_DIV_MASK 0x0F000000 -#define IFC_CCR_CLK_DIV_SHIFT 24 -#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) -/* IFC Clock Delay */ -#define IFC_CCR_CLK_DLY_MASK 0x000F0000 -#define IFC_CCR_CLK_DLY_SHIFT 16 -#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) -/* Invert IFC clock before sending out */ -#define IFC_CCR_INV_CLK_EN 0x00008000 -/* Fedback IFC Clock */ -#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 - -/* - * Clock Status Register (CSR) - */ -/* Clk is stable */ -#define IFC_CSR_CLK_STAT_STABLE 0x80000000 - -/* - * IFC_NAND Machine Specific Registers - */ -/* - * NAND Configuration Register (NCFGR) - */ -/* Auto Boot Mode */ -#define IFC_NAND_NCFGR_BOOT 0x80000000 -/* Addressing Mode-ROW0+n/COL0 */ -#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 -/* Addressing Mode-ROW0+n/COL0+n */ -#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 -/* Number of loop iterations of FIR sequences for multi page operations */ -#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 -#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 -#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) -/* Number of wait cycles */ -#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF -#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 - -/* - * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) - */ -/* General purpose FCM flash command bytes CMD0-CMD7 */ -#define IFC_NAND_FCR0_CMD0 0xFF000000 -#define IFC_NAND_FCR0_CMD0_SHIFT 24 -#define IFC_NAND_FCR0_CMD1 0x00FF0000 -#define IFC_NAND_FCR0_CMD1_SHIFT 16 -#define IFC_NAND_FCR0_CMD2 0x0000FF00 -#define IFC_NAND_FCR0_CMD2_SHIFT 8 -#define IFC_NAND_FCR0_CMD3 0x000000FF -#define IFC_NAND_FCR0_CMD3_SHIFT 0 -#define IFC_NAND_FCR1_CMD4 0xFF000000 -#define IFC_NAND_FCR1_CMD4_SHIFT 24 -#define IFC_NAND_FCR1_CMD5 0x00FF0000 -#define IFC_NAND_FCR1_CMD5_SHIFT 16 -#define IFC_NAND_FCR1_CMD6 0x0000FF00 -#define IFC_NAND_FCR1_CMD6_SHIFT 8 -#define IFC_NAND_FCR1_CMD7 0x000000FF -#define IFC_NAND_FCR1_CMD7_SHIFT 0 - -/* - * Flash ROW and COL Address Register (ROWn, COLn) - */ -/* Main/spare region locator */ -#define IFC_NAND_COL_MS 0x80000000 -/* Column Address */ -#define IFC_NAND_COL_CA_MASK 0x00000FFF - -/* - * NAND Flash Byte Count Register (NAND_BC) - */ -/* Byte Count for read/Write */ -#define IFC_NAND_BC 0x000001FF - -/* - * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) - */ -/* NAND Machine specific opcodes OP0-OP14*/ -#define IFC_NAND_FIR0_OP0 0xFC000000 -#define IFC_NAND_FIR0_OP0_SHIFT 26 -#define IFC_NAND_FIR0_OP1 0x03F00000 -#define IFC_NAND_FIR0_OP1_SHIFT 20 -#define IFC_NAND_FIR0_OP2 0x000FC000 -#define IFC_NAND_FIR0_OP2_SHIFT 14 -#define IFC_NAND_FIR0_OP3 0x00003F00 -#define IFC_NAND_FIR0_OP3_SHIFT 8 -#define IFC_NAND_FIR0_OP4 0x000000FC -#define IFC_NAND_FIR0_OP4_SHIFT 2 -#define IFC_NAND_FIR1_OP5 0xFC000000 -#define IFC_NAND_FIR1_OP5_SHIFT 26 -#define IFC_NAND_FIR1_OP6 0x03F00000 -#define IFC_NAND_FIR1_OP6_SHIFT 20 -#define IFC_NAND_FIR1_OP7 0x000FC000 -#define IFC_NAND_FIR1_OP7_SHIFT 14 -#define IFC_NAND_FIR1_OP8 0x00003F00 -#define IFC_NAND_FIR1_OP8_SHIFT 8 -#define IFC_NAND_FIR1_OP9 0x000000FC -#define IFC_NAND_FIR1_OP9_SHIFT 2 -#define IFC_NAND_FIR2_OP10 0xFC000000 -#define IFC_NAND_FIR2_OP10_SHIFT 26 -#define IFC_NAND_FIR2_OP11 0x03F00000 -#define IFC_NAND_FIR2_OP11_SHIFT 20 -#define IFC_NAND_FIR2_OP12 0x000FC000 -#define IFC_NAND_FIR2_OP12_SHIFT 14 -#define IFC_NAND_FIR2_OP13 0x00003F00 -#define IFC_NAND_FIR2_OP13_SHIFT 8 -#define IFC_NAND_FIR2_OP14 0x000000FC -#define IFC_NAND_FIR2_OP14_SHIFT 2 - -/* - * Instruction opcodes to be programmed - * in FIR registers- 6bits - */ -enum ifc_nand_fir_opcodes { - IFC_FIR_OP_NOP, - IFC_FIR_OP_CA0, - IFC_FIR_OP_CA1, - IFC_FIR_OP_CA2, - IFC_FIR_OP_CA3, - IFC_FIR_OP_RA0, - IFC_FIR_OP_RA1, - IFC_FIR_OP_RA2, - IFC_FIR_OP_RA3, - IFC_FIR_OP_CMD0, - IFC_FIR_OP_CMD1, - IFC_FIR_OP_CMD2, - IFC_FIR_OP_CMD3, - IFC_FIR_OP_CMD4, - IFC_FIR_OP_CMD5, - IFC_FIR_OP_CMD6, - IFC_FIR_OP_CMD7, - IFC_FIR_OP_CW0, - IFC_FIR_OP_CW1, - IFC_FIR_OP_CW2, - IFC_FIR_OP_CW3, - IFC_FIR_OP_CW4, - IFC_FIR_OP_CW5, - IFC_FIR_OP_CW6, - IFC_FIR_OP_CW7, - IFC_FIR_OP_WBCD, - IFC_FIR_OP_RBCD, - IFC_FIR_OP_BTRD, - IFC_FIR_OP_RDSTAT, - IFC_FIR_OP_NWAIT, - IFC_FIR_OP_WFR, - IFC_FIR_OP_SBRD, - IFC_FIR_OP_UA, - IFC_FIR_OP_RB, -}; - -/* - * NAND Chip Select Register (NAND_CSEL) - */ -#define IFC_NAND_CSEL 0x0C000000 -#define IFC_NAND_CSEL_SHIFT 26 -#define IFC_NAND_CSEL_CS0 0x00000000 -#define IFC_NAND_CSEL_CS1 0x04000000 -#define IFC_NAND_CSEL_CS2 0x08000000 -#define IFC_NAND_CSEL_CS3 0x0C000000 - -/* - * NAND Operation Sequence Start (NANDSEQ_STRT) - */ -/* NAND Flash Operation Start */ -#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 -/* Automatic Erase */ -#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 -/* Automatic Program */ -#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 -/* Automatic Copyback */ -#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 -/* Automatic Read Operation */ -#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 -/* Automatic Status Read */ -#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 - -/* - * NAND Event and Error Status Register (NAND_EVTER_STAT) - */ -/* Operation Complete */ -#define IFC_NAND_EVTER_STAT_OPC 0x80000000 -/* Flash Timeout Error */ -#define IFC_NAND_EVTER_STAT_FTOER 0x08000000 -/* Write Protect Error */ -#define IFC_NAND_EVTER_STAT_WPER 0x04000000 -/* ECC Error */ -#define IFC_NAND_EVTER_STAT_ECCER 0x02000000 -/* RCW Load Done */ -#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 -/* Boot Loadr Done */ -#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 -/* Bad Block Indicator search select */ -#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 - -/* - * NAND Flash Page Read Completion Event Status Register - * (PGRDCMPL_EVT_STAT) - */ -#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 -/* Small Page 0-15 Done */ -#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) -/* Large Page(2K) 0-3 Done */ -#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) -/* Large Page(4K) 0-1 Done */ -#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) - -/* - * NAND Event and Error Enable Register (NAND_EVTER_EN) - */ -/* Operation complete event enable */ -#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 -/* Page read complete event enable */ -#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 -/* Flash Timeout error enable */ -#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 -/* Write Protect error enable */ -#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 -/* ECC error logging enable */ -#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 - -/* - * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) - */ -/* Enable interrupt for operation complete */ -#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 -/* Enable interrupt for Page read complete */ -#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 -/* Enable interrupt for Flash timeout error */ -#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 -/* Enable interrupt for Write protect error */ -#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 -/* Enable interrupt for ECC error*/ -#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 - -/* - * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) - */ -#define IFC_NAND_ERATTR0_MASK 0x0C080000 -/* Error on CS0-3 for NAND */ -#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 -#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 -#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 -#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 -/* Transaction type of error Read/Write */ -#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 - -/* - * NAND Flash Status Register (NAND_FSR) - */ -/* First byte of data read from read status op */ -#define IFC_NAND_NFSR_RS0 0xFF000000 -/* Second byte of data read from read status op */ -#define IFC_NAND_NFSR_RS1 0x00FF0000 - -/* - * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) - */ -/* Number of ECC errors on sector n (n = 0-15) */ -#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 -#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 -#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 -#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 -#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 -#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 -#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F -#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 -#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 -#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 -#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 -#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 -#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 -#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 -#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F -#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 -#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 -#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 -#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 -#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 -#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 -#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 -#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F -#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 -#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 -#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 -#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 -#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 -#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 -#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 -#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F -#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 - -/* - * NAND Control Register (NANDCR) - */ -#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 -#define IFC_NAND_NCR_FTOCNT_SHIFT 25 -#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) - -/* - * NAND_AUTOBOOT_TRGR - */ -/* Trigger RCW load */ -#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 -/* Trigget Auto Boot */ -#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 - -/* - * NAND_MDR - */ -/* 1st read data byte when opcode SBRD */ -#define IFC_NAND_MDR_RDATA0 0xFF000000 -/* 2nd read data byte when opcode SBRD */ -#define IFC_NAND_MDR_RDATA1 0x00FF0000 - -/* - * NOR Machine Specific Registers - */ -/* - * NOR Event and Error Status Register (NOR_EVTER_STAT) - */ -/* NOR Command Sequence Operation Complete */ -#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 -/* Write Protect Error */ -#define IFC_NOR_EVTER_STAT_WPER 0x04000000 -/* Command Sequence Timeout Error */ -#define IFC_NOR_EVTER_STAT_STOER 0x01000000 - -/* - * NOR Event and Error Enable Register (NOR_EVTER_EN) - */ -/* NOR Command Seq complete event enable */ -#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 -/* Write Protect Error Checking Enable */ -#define IFC_NOR_EVTER_EN_WPEREN 0x04000000 -/* Timeout Error Enable */ -#define IFC_NOR_EVTER_EN_STOEREN 0x01000000 - -/* - * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) - */ -/* Enable interrupt for OPC complete */ -#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 -/* Enable interrupt for write protect error */ -#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 -/* Enable interrupt for timeout error */ -#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 - -/* - * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) - */ -/* Source ID for error transaction */ -#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 -/* AXI ID for error transation */ -#define IFC_NOR_ERATTR0_ERAID 0x000FF000 -/* Chip select corresponds to NOR error */ -#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 -#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 -#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 -#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 -/* Type of transaction read/write */ -#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 - -/* - * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) - */ -#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 -#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 - -/* - * NOR Control Register (NORCR) - */ -#define IFC_NORCR_MASK 0x0F0F0000 -/* No. of Address/Data Phase */ -#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 -#define IFC_NORCR_NUM_PHASE_SHIFT 24 -#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) -/* Sequence Timeout Count */ -#define IFC_NORCR_STOCNT_MASK 0x000F0000 -#define IFC_NORCR_STOCNT_SHIFT 16 -#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) - -/* - * GPCM Machine specific registers - */ -/* - * GPCM Event and Error Status Register (GPCM_EVTER_STAT) - */ -/* Timeout error */ -#define IFC_GPCM_EVTER_STAT_TOER 0x04000000 -/* Parity error */ -#define IFC_GPCM_EVTER_STAT_PER 0x01000000 - -/* - * GPCM Event and Error Enable Register (GPCM_EVTER_EN) - */ -/* Timeout error enable */ -#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 -/* Parity error enable */ -#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 - -/* - * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) - */ -/* Enable Interrupt for timeout error */ -#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 -/* Enable Interrupt for Parity error */ -#define IFC_GPCM_EEIER_PERIR_EN 0x01000000 - -/* - * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) - */ -/* Source ID for error transaction */ -#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 -/* AXI ID for error transaction */ -#define IFC_GPCM_ERATTR0_ERAID 0x000FF000 -/* Chip select corresponds to GPCM error */ -#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 -#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 -#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 -#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 -/* Type of transaction read/Write */ -#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 - -/* - * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) - */ -/* On which beat of address/data parity error is observed */ -#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 -/* Parity Error on byte */ -#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 -/* Parity Error reported in addr or data phase */ -#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 - -/* - * GPCM Status Register (GPCM_STAT) - */ -#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ - - -#ifndef __ASSEMBLY__ -#include <asm/io.h> - -extern void print_ifc_regs(void); -extern void init_early_memctl_regs(void); - -#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) - -#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) -#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) -#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) -#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) -#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) -#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) - -#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) -#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) -#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) -#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) -#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) -#define set_ifc_ftim(i, j, v) \ - (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) - -enum ifc_chip_sel { - IFC_CS0, - IFC_CS1, - IFC_CS2, - IFC_CS3, - IFC_CS4, - IFC_CS5, - IFC_CS6, - IFC_CS7, -}; - -enum ifc_ftims { - IFC_FTIM0, - IFC_FTIM1, - IFC_FTIM2, - IFC_FTIM3, -}; - -/* - * IFC Controller NAND Machine registers - */ -struct fsl_ifc_nand { - u32 ncfgr; - u32 res1[0x4]; - u32 nand_fcr0; - u32 nand_fcr1; - u32 res2[0x8]; - u32 row0; - u32 res3; - u32 col0; - u32 res4; - u32 row1; - u32 res5; - u32 col1; - u32 res6; - u32 row2; - u32 res7; - u32 col2; - u32 res8; - u32 row3; - u32 res9; - u32 col3; - u32 res10[0x24]; - u32 nand_fbcr; - u32 res11; - u32 nand_fir0; - u32 nand_fir1; - u32 nand_fir2; - u32 res12[0x10]; - u32 nand_csel; - u32 res13; - u32 nandseq_strt; - u32 res14; - u32 nand_evter_stat; - u32 res15; - u32 pgrdcmpl_evt_stat; - u32 res16[0x2]; - u32 nand_evter_en; - u32 res17[0x2]; - u32 nand_evter_intr_en; - u32 res18[0x2]; - u32 nand_erattr0; - u32 nand_erattr1; - u32 res19[0x10]; - u32 nand_fsr; - u32 res20; - u32 nand_eccstat[4]; - u32 res21[0x20]; - u32 nanndcr; - u32 res22[0x2]; - u32 nand_autoboot_trgr; - u32 res23; - u32 nand_mdr; - u32 res24[0x5C]; -}; - -/* - * IFC controller NOR Machine registers - */ -struct fsl_ifc_nor { - u32 nor_evter_stat; - u32 res1[0x2]; - u32 nor_evter_en; - u32 res2[0x2]; - u32 nor_evter_intr_en; - u32 res3[0x2]; - u32 nor_erattr0; - u32 nor_erattr1; - u32 nor_erattr2; - u32 res4[0x4]; - u32 norcr; - u32 res5[0xEF]; -}; - -/* - * IFC controller GPCM Machine registers - */ -struct fsl_ifc_gpcm { - u32 gpcm_evter_stat; - u32 res1[0x2]; - u32 gpcm_evter_en; - u32 res2[0x2]; - u32 gpcm_evter_intr_en; - u32 res3[0x2]; - u32 gpcm_erattr0; - u32 gpcm_erattr1; - u32 gpcm_erattr2; - u32 gpcm_stat; - u32 res4[0x1F3]; -}; - -#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT -#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8) -#define IFC_CSPR_REG_LEN 148 -#define IFC_AMASK_REG_LEN 144 -#define IFC_CSOR_REG_LEN 144 -#define IFC_FTIM_REG_LEN 576 - -#define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \ - CONFIG_SYS_FSL_IFC_BANK_COUNT -#define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \ - CONFIG_SYS_FSL_IFC_BANK_COUNT -#define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \ - CONFIG_SYS_FSL_IFC_BANK_COUNT -#define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \ - CONFIG_SYS_FSL_IFC_BANK_COUNT -#else -#error IFC BANK count not vaild -#endif -#else -#error IFC BANK count not defined -#endif - -struct fsl_ifc_cspr { - u32 cspr_ext; - u32 cspr; - u32 res; -}; - -struct fsl_ifc_amask { - u32 amask; - u32 res[0x2]; -}; - -struct fsl_ifc_csor { - u32 csor; - u32 csor_ext; - u32 res; -}; - -struct fsl_ifc_ftim { - u32 ftim[4]; - u32 res[0x8]; -}; - -/* - * IFC Controller Registers - */ -struct fsl_ifc { - u32 ifc_rev; - u32 res1[0x2]; - struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; - u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN]; - struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; - u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN]; - struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; - u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN]; - struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; - u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN]; - u32 rb_stat; - u32 res6[0x2]; - u32 ifc_gcr; - u32 res7[0x2]; - u32 cm_evter_stat; - u32 res8[0x2]; - u32 cm_evter_en; - u32 res9[0x2]; - u32 cm_evter_intr_en; - u32 res10[0x2]; - u32 cm_erattr0; - u32 cm_erattr1; - u32 res11[0x2]; - u32 ifc_ccr; - u32 ifc_csr; - u32 res12[0x2EB]; - struct fsl_ifc_nand ifc_nand; - struct fsl_ifc_nor ifc_nor; - struct fsl_ifc_gpcm ifc_gpcm; -}; - -#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 -#undef CSPR_MSEL_NOR -#define CSPR_MSEL_NOR CSPR_MSEL_GPCM -#endif -#endif /* CONFIG_FSL_IFC */ - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_PPC_FSL_IFC_H */ diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index cce892c..404ded4 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -62,6 +62,8 @@ enum srds_prtcl { QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */ QSGMII_FM2_A, QSGMII_FM2_B, + XFI_FM1_MAC1, + XFI_FM1_MAC2, XFI_FM1_MAC9, XFI_FM1_MAC10, XFI_FM2_MAC9, diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 3c86ff6..2518402 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -14,6 +14,7 @@ #ifndef __IMMAP_83xx__ #define __IMMAP_83xx__ +#include <fsl_immap.h> #include <asm/types.h> #include <asm/fsl_i2c.h> #include <asm/mpc8xxx_spi.h> @@ -277,107 +278,10 @@ typedef struct qesba83xx { } qesba83xx_t; /* - * DDR Memory Controller Memory Map + * DDR Memory Controller Memory Map for DDR1 + * The structure of DDR2, or DDR3 is defined in fsl_immap.h */ -#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) -typedef struct ccsr_ddr { - u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ - u8 res1[4]; - u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ - u8 res2[4]; - u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ - u8 res3[4]; - u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ - u8 res4[100]; - u32 cs0_config; /* Chip Select Configuration */ - u32 cs1_config; /* Chip Select Configuration */ - u32 cs2_config; /* Chip Select Configuration */ - u32 cs3_config; /* Chip Select Configuration */ - u8 res4a[48]; - u32 cs0_config_2; /* Chip Select Configuration 2 */ - u32 cs1_config_2; /* Chip Select Configuration 2 */ - u32 cs2_config_2; /* Chip Select Configuration 2 */ - u32 cs3_config_2; /* Chip Select Configuration 2 */ - u8 res5[48]; - u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ - u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ - u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ - u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ - u32 sdram_cfg; /* SDRAM Control Configuration */ - u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ - u32 sdram_mode; /* SDRAM Mode Configuration */ - u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ - u32 sdram_md_cntl; /* SDRAM Mode Control */ - u32 sdram_interval; /* SDRAM Interval Configuration */ - u32 sdram_data_init; /* SDRAM Data initialization */ - u8 res6[4]; - u32 sdram_clk_cntl; /* SDRAM Clock Control */ - u8 res7[20]; - u32 init_addr; /* training init addr */ - u32 init_ext_addr; /* training init extended addr */ - u8 res8_1[16]; - u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ - u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ - u8 reg8_1a[8]; - u32 ddr_zq_cntl; /* ZQ calibration control*/ - u32 ddr_wrlvl_cntl; /* write leveling control*/ - u8 reg8_1aa[4]; - u32 ddr_sr_cntr; /* self refresh counter */ - u32 ddr_sdram_rcw_1; /* Control Words 1 */ - u32 ddr_sdram_rcw_2; /* Control Words 2 */ - u8 reg_1ab[8]; - u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ - u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ - u8 res8_1b[104]; - u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ - u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ - u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ - u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ - u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ - u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ - u8 res8_1ba[0x908]; - u32 ddr_dsr1; /* Debug Status 1 */ - u32 ddr_dsr2; /* Debug Status 2 */ - u32 ddr_cdr1; /* Control Driver 1 */ - u32 ddr_cdr2; /* Control Driver 2 */ - u8 res8_1c[200]; - u32 ip_rev1; /* IP Block Revision 1 */ - u32 ip_rev2; /* IP Block Revision 2 */ - u32 eor; /* Enhanced Optimization Register */ - u8 res8_2[252]; - u32 mtcr; /* Memory Test Control Register */ - u8 res8_3[28]; - u32 mtp1; /* Memory Test Pattern 1 */ - u32 mtp2; /* Memory Test Pattern 2 */ - u32 mtp3; /* Memory Test Pattern 3 */ - u32 mtp4; /* Memory Test Pattern 4 */ - u32 mtp5; /* Memory Test Pattern 5 */ - u32 mtp6; /* Memory Test Pattern 6 */ - u32 mtp7; /* Memory Test Pattern 7 */ - u32 mtp8; /* Memory Test Pattern 8 */ - u32 mtp9; /* Memory Test Pattern 9 */ - u32 mtp10; /* Memory Test Pattern 10 */ - u8 res8_4[184]; - u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ - u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ - u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ - u8 res9[20]; - u32 capture_data_hi; /* Data Path Read Capture High */ - u32 capture_data_lo; /* Data Path Read Capture Low */ - u32 capture_ecc; /* Data Path Read Capture ECC */ - u8 res10[20]; - u32 err_detect; /* Error Detect */ - u32 err_disable; /* Error Disable */ - u32 err_int_en; - u32 capture_attributes; /* Error Attrs Capture */ - u32 capture_address; /* Error Addr Capture */ - u32 capture_ext_address; /* Error Extended Addr Capture */ - u32 err_sbe; /* Single-Bit ECC Error Management */ - u8 res11[164]; - u32 debug[32]; /* debug_1 to debug_32 */ - u8 res12[128]; -} ccsr_ddr_t; -#else +#if !defined(CONFIG_SYS_FSL_DDR2) && !defined(CONFIG_SYS_FSL_DDR3) typedef struct ddr_cs_bnds { u32 csbnds; u8 res0[4]; @@ -739,8 +643,8 @@ typedef struct immap { u8 dll_ddr[0x100]; u8 dll_lbc[0x100]; u8 res1[0xE00]; -#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) - ccsr_ddr_t ddr; /* DDR Memory Controller Memory */ +#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3) + struct ccsr_ddr ddr; /* DDR Memory Controller Memory */ #else ddr83xx_t ddr; /* DDR Memory Controller Memory */ #endif @@ -763,6 +667,7 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; +#ifndef CONFIG_MPC834x #ifdef CONFIG_HAS_FSL_MPH_USB #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */ #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0 @@ -770,6 +675,10 @@ typedef struct immap { #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0 #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */ #endif +#else +#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 +#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 +#endif #elif defined(CONFIG_MPC8313) typedef struct immap { @@ -1024,7 +933,7 @@ typedef struct immap { #endif #define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000) -#define CONFIG_SYS_MPC8xxx_DDR_ADDR \ +#define CONFIG_SYS_FSL_DDR_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) #define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000) #define CONFIG_SYS_MPC83xx_DMA_ADDR \ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 060e0d7..672e8c6 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -15,9 +15,10 @@ #include <asm/types.h> #include <asm/fsl_dma.h> #include <asm/fsl_i2c.h> -#include <asm/fsl_ifc.h> +#include <fsl_ifc.h> #include <asm/fsl_lbc.h> #include <asm/fsl_fman.h> +#include <fsl_immap.h> typedef struct ccsr_local { u32 ccsrbarh; /* CCSR Base Addr High */ @@ -112,105 +113,6 @@ typedef struct ccsr_local_ecm { u8 res24[492]; } ccsr_local_ecm_t; -/* DDR memory controller registers */ -typedef struct ccsr_ddr { - u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ - u8 res1[4]; - u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ - u8 res2[4]; - u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ - u8 res3[4]; - u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ - u8 res4[100]; - u32 cs0_config; /* Chip Select Configuration */ - u32 cs1_config; /* Chip Select Configuration */ - u32 cs2_config; /* Chip Select Configuration */ - u32 cs3_config; /* Chip Select Configuration */ - u8 res4a[48]; - u32 cs0_config_2; /* Chip Select Configuration 2 */ - u32 cs1_config_2; /* Chip Select Configuration 2 */ - u32 cs2_config_2; /* Chip Select Configuration 2 */ - u32 cs3_config_2; /* Chip Select Configuration 2 */ - u8 res5[48]; - u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ - u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ - u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ - u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ - u32 sdram_cfg; /* SDRAM Control Configuration */ - u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ - u32 sdram_mode; /* SDRAM Mode Configuration */ - u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ - u32 sdram_md_cntl; /* SDRAM Mode Control */ - u32 sdram_interval; /* SDRAM Interval Configuration */ - u32 sdram_data_init; /* SDRAM Data initialization */ - u8 res6[4]; - u32 sdram_clk_cntl; /* SDRAM Clock Control */ - u8 res7[20]; - u32 init_addr; /* training init addr */ - u32 init_ext_addr; /* training init extended addr */ - u8 res8_1[16]; - u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ - u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ - u8 reg8_1a[8]; - u32 ddr_zq_cntl; /* ZQ calibration control*/ - u32 ddr_wrlvl_cntl; /* write leveling control*/ - u8 reg8_1aa[4]; - u32 ddr_sr_cntr; /* self refresh counter */ - u32 ddr_sdram_rcw_1; /* Control Words 1 */ - u32 ddr_sdram_rcw_2; /* Control Words 2 */ - u8 reg_1ab[8]; - u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ - u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ - u8 res8_1b[104]; - u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ - u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ - u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ - u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ - u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ - u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ - u8 res8_1ba[0x908]; - u32 ddr_dsr1; /* Debug Status 1 */ - u32 ddr_dsr2; /* Debug Status 2 */ - u32 ddr_cdr1; /* Control Driver 1 */ - u32 ddr_cdr2; /* Control Driver 2 */ - u8 res8_1c[200]; - u32 ip_rev1; /* IP Block Revision 1 */ - u32 ip_rev2; /* IP Block Revision 2 */ - u32 eor; /* Enhanced Optimization Register */ - u8 res8_2[252]; - u32 mtcr; /* Memory Test Control Register */ - u8 res8_3[28]; - u32 mtp1; /* Memory Test Pattern 1 */ - u32 mtp2; /* Memory Test Pattern 2 */ - u32 mtp3; /* Memory Test Pattern 3 */ - u32 mtp4; /* Memory Test Pattern 4 */ - u32 mtp5; /* Memory Test Pattern 5 */ - u32 mtp6; /* Memory Test Pattern 6 */ - u32 mtp7; /* Memory Test Pattern 7 */ - u32 mtp8; /* Memory Test Pattern 8 */ - u32 mtp9; /* Memory Test Pattern 9 */ - u32 mtp10; /* Memory Test Pattern 10 */ - u8 res8_4[184]; - u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ - u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ - u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ - u8 res9[20]; - u32 capture_data_hi; /* Data Path Read Capture High */ - u32 capture_data_lo; /* Data Path Read Capture Low */ - u32 capture_ecc; /* Data Path Read Capture ECC */ - u8 res10[20]; - u32 err_detect; /* Error Detect */ - u32 err_disable; /* Error Disable */ - u32 err_int_en; - u32 capture_attributes; /* Error Attrs Capture */ - u32 capture_address; /* Error Addr Capture */ - u32 capture_ext_address; /* Error Extended Addr Capture */ - u32 err_sbe; /* Single-Bit ECC Error Management */ - u8 res11[164]; - u32 debug[32]; /* debug_1 to debug_32 */ - u8 res12[128]; -} ccsr_ddr_t; - #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */ #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */ @@ -282,7 +184,9 @@ typedef struct ccsr_pcix { u32 int_ack; /* PCIX IRQ Acknowledge */ u8 res000c[52]; u32 liodn_base; /* PCIX LIODN base register */ - u8 res0044[3004]; + u8 res0044[2996]; + u32 ipver1; /* PCIX IP block revision register 1 */ + u32 ipver2; /* PCIX IP block revision register 2 */ u32 potar0; /* PCIX Outbound Transaction Addr 0 */ u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */ u32 powbar0; /* PCIX Outbound Window Base Addr 0 */ @@ -1717,6 +1621,8 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000 #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000 +#define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000 +#define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000 @@ -1847,11 +1753,18 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 -#elif defined(CONFIG_PPC_T1040) +#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ +defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 +#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 +#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 +#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 +#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 #endif #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000 @@ -1915,6 +1828,15 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 #endif +#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ +#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000 +#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ +#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000 +#define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000 +#endif u8 res18[192]; u32 scratchrw[4]; /* Scratch Read/Write */ u8 res19[240]; @@ -2911,6 +2833,7 @@ struct ccsr_pman { #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 +#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 @@ -3045,11 +2968,11 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) #define CONFIG_SYS_MPC85xx_ECM_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) -#define CONFIG_SYS_MPC8xxx_DDR_ADDR \ +#define CONFIG_SYS_FSL_DDR_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) -#define CONFIG_SYS_MPC8xxx_DDR2_ADDR \ +#define CONFIG_SYS_FSL_DDR2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET) -#define CONFIG_SYS_MPC8xxx_DDR3_ADDR \ +#define CONFIG_SYS_FSL_DDR3_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET) #define CONFIG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index 2a704fe..177918b 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -10,6 +10,7 @@ #ifndef __IMMAP_86xx__ #define __IMMAP_86xx__ +#include <fsl_immap.h> #include <asm/types.h> #include <asm/fsl_dma.h> #include <asm/fsl_lbc.h> @@ -89,75 +90,6 @@ typedef struct ccsr_local_mcm { char res31[488]; } ccsr_local_mcm_t; -/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */ - -typedef struct ccsr_ddr { - uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ - char res1[4]; - uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */ - char res2[4]; - uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */ - char res3[4]; - uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */ - char res4[4]; - uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */ - char res5[4]; - uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */ - char res6[84]; - uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */ - uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */ - uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */ - uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ - uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ - uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ - char res7[104]; - uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ - uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ - uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ - uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ - uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration 1 */ - uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ - uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration 1 */ - uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ - uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ - uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ - uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ - char res8[4]; - uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ - char res9[12]; - uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ - uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ - uint init_addr; /* 0x2148 - DDR training initialzation address */ - uint init_ext_addr; /* 0x214C - DDR training initialzation extended address */ - char res10[2728]; - uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ - uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ - char res11[512]; - uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ - uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ - uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */ - char res12[20]; - uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */ - uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */ - uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */ - char res13[20]; - uint err_detect; /* 0x2e40 - DDR Memory Error Detect */ - uint err_disable; /* 0x2e44 - DDR Memory Error Disable */ - uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */ - uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */ - uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */ - uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ - uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */ - char res14[164]; - uint debug_1; /* 0x2f00 */ - uint debug_2; - uint debug_3; - uint debug_4; - uint debug_5; - char res15[236]; -} ccsr_ddr_t; - - /* Daul I2C Registers(0x3000-0x4000) */ typedef struct ccsr_i2c { struct fsl_i2c i2c[2]; @@ -1225,11 +1157,11 @@ typedef struct ccsr_wdt { typedef struct immap { ccsr_local_mcm_t im_local_mcm; - ccsr_ddr_t im_ddr1; + struct ccsr_ddr im_ddr1; ccsr_i2c_t im_i2c; ccsr_duart_t im_duart; fsl_lbc_t im_lbc; - ccsr_ddr_t im_ddr2; + struct ccsr_ddr im_ddr2; char res1[4096]; ccsr_pex_t im_pex1; ccsr_pex_t im_pex2; @@ -1253,9 +1185,9 @@ typedef struct immap { extern immap_t *immr; #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000 -#define CONFIG_SYS_MPC8xxx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) +#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000 -#define CONFIG_SYS_MPC8xxx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET) +#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET) #define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000 #define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET) #define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000 diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h index 3d11884..87bb4a0 100644 --- a/arch/powerpc/include/asm/mpc85xx_gpio.h +++ b/arch/powerpc/include/asm/mpc85xx_gpio.h @@ -20,7 +20,7 @@ static inline void mpc85xx_gpio_set(unsigned int mask, unsigned int dir, unsigned int val) { - ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); + ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); /* First mask off the unwanted parts of "dir" and "val" */ dir &= mask; @@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned int gpios) static inline unsigned int mpc85xx_gpio_get(unsigned int mask) { - ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); + ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); /* Read the requested values */ return in_be32(&gpio->gpdat) & mask; diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 81f9d38..831804c 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1127,6 +1127,8 @@ #define SVR_T1020 0x852100 #define SVR_T1021 0x852101 #define SVR_T1022 0x852102 +#define SVR_T2080 0x853000 +#define SVR_T2081 0x853100 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index 404ff67..58c2537 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -10,5 +10,7 @@ obj-y := cpu.o os.o start.o state.o # os.c is build in the system environment, so needs standard includes -$(obj)os.o: ALL_CFLAGS := $(filter-out -nostdinc,$(ALL_CFLAGS)) -$(obj).depend.os: CPPFLAGS := $(filter-out -nostdinc,$(CPPFLAGS)) +$(obj)os.o: ALL_CFLAGS := $(BASE_CPPFLAGS) \ + $(patsubst %, -idirafter %, $(BASE_INCLUDE_DIRS)) +$(obj).depend.os: CPPFLAGS := $(BASE_CPPFLAGS) \ + $(patsubst %, -idirafter %, $(BASE_INCLUDE_DIRS)) diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index c2e5f57..26f44cb 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -8,6 +8,7 @@ #include <fcntl.h> #include <getopt.h> #include <stdio.h> +#include <stdint.h> #include <stdlib.h> #include <string.h> #include <termios.h> @@ -136,7 +137,7 @@ void os_usleep(unsigned long usec) usleep(usec); } -u64 __attribute__((no_instrument_function)) os_get_nsec(void) +uint64_t __attribute__((no_instrument_function)) os_get_nsec(void) { #if defined(CLOCK_MONOTONIC) && defined(_POSIX_MONOTONIC_CLOCK) struct timespec tp; @@ -160,7 +161,7 @@ static struct option *long_opts; int os_parse_args(struct sandbox_state *state, int argc, char *argv[]) { - struct sb_cmdline_option **sb_opt = __u_boot_sandbox_option_start; + struct sandbox_cmdline_option **sb_opt = __u_boot_sandbox_option_start; size_t num_options = __u_boot_sandbox_option_count(); size_t i; diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index f1cb793..1b15454 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -13,7 +13,7 @@ int sandbox_early_getopt_check(void) { struct sandbox_state *state = state_get_current(); - struct sb_cmdline_option **sb_opt = __u_boot_sandbox_option_start; + struct sandbox_cmdline_option **sb_opt = __u_boot_sandbox_option_start; size_t num_options = __u_boot_sandbox_option_count(); size_t i; int max_arg_len, max_noarg_len; @@ -40,7 +40,7 @@ int sandbox_early_getopt_check(void) max_noarg_len = max_arg_len + 7; for (i = 0; i < num_options; ++i) { - struct sb_cmdline_option *opt = sb_opt[i]; + struct sandbox_cmdline_option *opt = sb_opt[i]; /* first output the short flag if it has one */ if (opt->flag_short >= 0x100) @@ -61,12 +61,12 @@ int sandbox_early_getopt_check(void) os_exit(0); } -static int sb_cmdline_cb_help(struct sandbox_state *state, const char *arg) +static int sandbox_cmdline_cb_help(struct sandbox_state *state, const char *arg) { /* just flag to sandbox_early_getopt_check to show usage */ return 1; } -SB_CMDLINE_OPT_SHORT(help, 'h', 0, "Display help"); +SANDBOX_CMDLINE_OPT_SHORT(help, 'h', 0, "Display help"); int sandbox_main_loop_init(void) { @@ -81,19 +81,20 @@ int sandbox_main_loop_init(void) return 0; } -static int sb_cmdline_cb_command(struct sandbox_state *state, const char *arg) +static int sandbox_cmdline_cb_command(struct sandbox_state *state, + const char *arg) { state->cmd = arg; return 0; } -SB_CMDLINE_OPT_SHORT(command, 'c', 1, "Execute U-Boot command"); +SANDBOX_CMDLINE_OPT_SHORT(command, 'c', 1, "Execute U-Boot command"); -static int sb_cmdline_cb_fdt(struct sandbox_state *state, const char *arg) +static int sandbox_cmdline_cb_fdt(struct sandbox_state *state, const char *arg) { state->fdt_fname = arg; return 0; } -SB_CMDLINE_OPT_SHORT(fdt, 'd', 1, "Specify U-Boot's control FDT"); +SANDBOX_CMDLINE_OPT_SHORT(fdt, 'd', 1, "Specify U-Boot's control FDT"); int main(int argc, char *argv[]) { diff --git a/arch/sandbox/include/asm/config.h b/arch/sandbox/include/asm/config.h index 7755a4d..ec7729e 100644 --- a/arch/sandbox/include/asm/config.h +++ b/arch/sandbox/include/asm/config.h @@ -9,4 +9,12 @@ #define CONFIG_SANDBOX_ARCH +/* Used by drivers/spi/sandbox_spi.c and arch/sandbox/include/asm/state.h */ +#ifndef CONFIG_SANDBOX_SPI_MAX_BUS +#define CONFIG_SANDBOX_SPI_MAX_BUS 1 +#endif +#ifndef CONFIG_SANDBOX_SPI_MAX_CS +#define CONFIG_SANDBOX_SPI_MAX_CS 10 +#endif + #endif diff --git a/arch/sandbox/include/asm/getopt.h b/arch/sandbox/include/asm/getopt.h index 685883c..3048c2c 100644 --- a/arch/sandbox/include/asm/getopt.h +++ b/arch/sandbox/include/asm/getopt.h @@ -18,7 +18,7 @@ struct sandbox_state; * consumer code should focus on the macros below and * the callback function. */ -struct sb_cmdline_option { +struct sandbox_cmdline_option { /* The long flag name: "help" for "--help" */ const char *flag; /* The (optional) short flag name: "h" for "-h" */ @@ -35,18 +35,19 @@ struct sb_cmdline_option { * Internal macro to expand the lower macros into the necessary * magic junk that makes this all work. */ -#define _SB_CMDLINE_OPT(f, s, ha, h) \ - static struct sb_cmdline_option sb_cmdline_option_##f = { \ +#define _SANDBOX_CMDLINE_OPT(f, s, ha, h) \ + static struct sandbox_cmdline_option sandbox_cmdline_option_##f = { \ .flag = #f, \ .flag_short = s, \ .help = h, \ .has_arg = ha, \ - .callback = sb_cmdline_cb_##f, \ + .callback = sandbox_cmdline_cb_##f, \ }; \ /* Ppointer to the struct in a special section for the linker script */ \ static __attribute__((section(".u_boot_sandbox_getopt"), used)) \ - struct sb_cmdline_option *sb_cmdline_option_##f##_ptr = \ - &sb_cmdline_option_##f + struct sandbox_cmdline_option \ + *sandbox_cmdline_option_##f##_ptr = \ + &sandbox_cmdline_option_##f /** * Macros for end code to declare new command line flags. @@ -56,16 +57,16 @@ struct sb_cmdline_option { * @param h The help string displayed when showing --help * * This invocation: - * SB_CMDLINE_OPT(foo, 0, "The foo arg"); + * SANDBOX_CMDLINE_OPT(foo, 0, "The foo arg"); * Will create a new flag named "--foo" (no short option) that takes * no argument. If the user specifies "--foo", then the callback func - * sb_cmdline_cb_foo() will automatically be called. + * sandbox_cmdline_cb_foo() will automatically be called. */ -#define SB_CMDLINE_OPT(f, ha, h) _SB_CMDLINE_OPT(f, 0, ha, h) +#define SANDBOX_CMDLINE_OPT(f, ha, h) _SANDBOX_CMDLINE_OPT(f, 0, ha, h) /* * Same as above, but @s is used to specify a short flag e.g. - * SB_CMDLINE_OPT(foo, 'f', 0, "The foo arg"); + * SANDBOX_CMDLINE_OPT(foo, 'f', 0, "The foo arg"); */ -#define SB_CMDLINE_OPT_SHORT(f, s, ha, h) _SB_CMDLINE_OPT(f, s, ha, h) +#define SANDBOX_CMDLINE_OPT_SHORT(f, s, ha, h) _SANDBOX_CMDLINE_OPT(f, s, ha, h) #endif diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h index 9ac6a5f..7956041 100644 --- a/arch/sandbox/include/asm/io.h +++ b/arch/sandbox/include/asm/io.h @@ -38,6 +38,6 @@ static inline void unmap_sysmem(const void *vaddr) } /* Map from a pointer to our RAM buffer */ -phys_addr_t map_to_sysmem(void *ptr); +phys_addr_t map_to_sysmem(const void *ptr); #endif diff --git a/arch/sandbox/include/asm/sections.h b/arch/sandbox/include/asm/sections.h index 4c37860..fbc1bd1 100644 --- a/arch/sandbox/include/asm/sections.h +++ b/arch/sandbox/include/asm/sections.h @@ -11,9 +11,9 @@ #include <asm-generic/sections.h> -struct sb_cmdline_option; +struct sandbox_cmdline_option; -extern struct sb_cmdline_option *__u_boot_sandbox_option_start[], +extern struct sandbox_cmdline_option *__u_boot_sandbox_option_start[], *__u_boot_sandbox_option_end[]; static inline size_t __u_boot_sandbox_option_count(void) diff --git a/arch/sandbox/include/asm/spi.h b/arch/sandbox/include/asm/spi.h new file mode 100644 index 0000000..49b4a0f --- /dev/null +++ b/arch/sandbox/include/asm/spi.h @@ -0,0 +1,58 @@ +/* + * Simulate a SPI port and clients (see README.sandbox for details) + * + * Copyright (c) 2011-2013 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_SPI_H__ +#define __ASM_SPI_H__ + +#include <linux/types.h> + +/* + * The interface between the SPI bus and the SPI client. The bus will + * instantiate a client, and that then call into it via these entry + * points. These should be enough for the client to emulate the SPI + * device just like the real hardware. + */ +struct sandbox_spi_emu_ops { + /* The bus wants to instantiate a new client, so setup everything */ + int (*setup)(void **priv, const char *spec); + /* The bus is done with us, so break things down */ + void (*free)(void *priv); + /* The CS has been "activated" -- we won't worry about low/high */ + void (*cs_activate)(void *priv); + /* The CS has been "deactivated" -- we won't worry about low/high */ + void (*cs_deactivate)(void *priv); + /* The client is rx-ing bytes from the bus, so it should tx some */ + int (*xfer)(void *priv, const u8 *rx, u8 *tx, uint bytes); +}; + +/* + * There are times when the data lines are allowed to tristate. What + * is actually sensed on the line depends on the hardware. It could + * always be 0xFF/0x00 (if there are pull ups/downs), or things could + * float and so we'd get garbage back. This func encapsulates that + * scenario so we can worry about the details here. + */ +static inline void sandbox_spi_tristate(u8 *buf, uint len) +{ + /* XXX: make this into a user config option ? */ + memset(buf, 0xff, len); +} + +/* + * Extract the bus/cs from the spi spec and return the start of the spi + * client spec. If the bus/cs are invalid for the current config, then + * it returns NULL. + * + * Example: arg="0:1:foo" will set bus to 0, cs to 1, and return "foo" + */ +const char *sandbox_spi_parse_spec(const char *arg, unsigned long *bus, + unsigned long *cs); + +#endif diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index 093c81d..a38820b 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -15,6 +15,11 @@ enum exit_type_id { STATE_EXIT_POWER_OFF, }; +struct sandbox_spi_info { + const char *spec; + const struct sandbox_spi_emu_ops *ops; +}; + /* The complete state of the test system */ struct sandbox_state { const char *cmd; /* Command to execute */ @@ -23,6 +28,10 @@ struct sandbox_state { const char *parse_err; /* Error to report from parsing */ int argc; /* Program arguments */ char **argv; + + /* Pointer to information for each SPI bus/cs */ + struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS] + [CONFIG_SANDBOX_SPI_MAX_CS]; }; /** diff --git a/arch/sandbox/include/asm/types.h b/arch/sandbox/include/asm/types.h index 88c84ba..6d3eb1f 100644 --- a/arch/sandbox/include/asm/types.h +++ b/arch/sandbox/include/asm/types.h @@ -48,8 +48,8 @@ typedef unsigned long long u64; #define BITS_PER_LONG CONFIG_SANDBOX_BITS_PER_LONG typedef unsigned long dma_addr_t; -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; +typedef u32 phys_addr_t; +typedef u32 phys_size_t; #endif /* __KERNEL__ */ diff --git a/arch/sparc/cpu/leon3/start.S b/arch/sparc/cpu/leon3/start.S index bbc1b34..cf897f6 100644 --- a/arch/sparc/cpu/leon3/start.S +++ b/arch/sparc/cpu/leon3/start.S @@ -1,33 +1,41 @@ -#include <config.h> - -TRAP ta 0; nop; nop; nop; - -/* Software trap. Treat as BAD_TRAP for the time being... */ -#define SOFT_TRAP TRAP(_hwerr) - -#define PSR_INIT 0x1FC0 /* Disable traps, set s and ps */ -#define WIM_INIT 2 - -/* All traps low-level code here must end with this macro. */ -#define RESTORE_ALL b ret_trap_entry; clr %l6; - -#define WRITE_PAUSE nop;nop;nop - -WINDOWSIZE = (16 * 4) -ARGPUSHSIZE = (6 * 4) -ARGPUSH = (WINDOWSIZE + 4) -MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4) - -/* Number of register windows */ -#ifndef CONFIG_SYS_SPARC_NWINDOWS -#error Must define number of SPARC register windows, default is 8 -#endif - -#define STACK_ALIGN 8 -#define SA(X) (((X)+(STACK_ALIGN-1)) & ~(STACK_ALIGN-1)) +/* This is where the SPARC/LEON3 starts + * Copyright (C) 2007, + * Daniel Hellstrom, daniel@gaisler.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * SPDX-License-Identifier: GPL-2.0+ + */ - .section ".start", "ax" - .globl _starttate */ +#include <asm-offsets.h> +#include <config.h> +#include <asm/asmmacro.h> +#include <asm/winmacro.h> +#include <asm/psr.h> +#include <asm/stack.h> +#include <asm/leon.h> +#include <version.h> + +/* Entry for traps which jump to a programmer-specified trap handler. */ +#define TRAPR(H) \ + wr %g0, 0xfe0, %psr; \ + mov %g0, %tbr; \ + ba (H); \ + mov %g0, %wim; + +#define TRAP(H) \ + mov %psr, %l0; \ + ba (H); \ + nop; nop; + +#define TRAPI(ilevel) \ + mov ilevel, %l7; \ + mov %psr, %l0; \ + b _irq_entry; \ + mov %wim, %l3 + +/* Unexcpected trap will halt the processor by forcing it to error state */ #undef BAD_TRAP #define BAD_TRAP ta 0; nop; nop; nop; |