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-rw-r--r--arch/arm/cpu/armv7/exynos/clock.c33
-rw-r--r--arch/arm/include/asm/arch-exynos/clk.h1
2 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 330bd75..f7829b2 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -578,6 +578,29 @@ void exynos4_set_mipi_clk(void)
writel(cfg, &clk->div_lcd0);
}
+/*
+ * I2C
+ *
+ * exynos5: obtaining the I2C clock
+ */
+static unsigned long exynos5_get_i2c_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long aclk_66, aclk_66_pre, sclk;
+ unsigned int ratio;
+
+ sclk = get_pll_clk(MPLL);
+
+ ratio = (readl(&clk->div_top1)) >> 24;
+ ratio &= 0x7;
+ aclk_66_pre = sclk / (ratio + 1);
+ ratio = readl(&clk->div_top0);
+ ratio &= 0x7;
+ aclk_66 = aclk_66_pre / (ratio + 1);
+ return aclk_66;
+}
+
unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5())
@@ -594,6 +617,16 @@ unsigned long get_arm_clk(void)
return exynos4_get_arm_clk();
}
+unsigned long get_i2c_clk(void)
+{
+ if (cpu_is_exynos5()) {
+ return exynos5_get_i2c_clk();
+ } else {
+ debug("I2C clock is not set for this CPU\n");
+ return 0;
+ }
+}
+
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5())
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index 637fb4b..72dc655 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -30,6 +30,7 @@
unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
+unsigned long get_i2c_clk(void);
unsigned long get_pwm_clk(void);
unsigned long get_uart_clk(int dev_index);
void set_mmc_clk(int dev_index, unsigned int div);