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-rw-r--r--arch/x86/cpu/baytrail/fsp_configs.c162
-rw-r--r--arch/x86/cpu/baytrail/valleyview.c11
-rw-r--r--arch/x86/cpu/cpu.c11
-rw-r--r--arch/x86/cpu/interrupts.c2
-rw-r--r--arch/x86/cpu/irq.c58
-rw-r--r--arch/x86/cpu/mp_init.c7
-rw-r--r--arch/x86/cpu/pci.c9
-rw-r--r--arch/x86/cpu/qemu/qemu.c4
-rw-r--r--arch/x86/cpu/quark/quark.c4
-rw-r--r--arch/x86/cpu/queensbay/tnc.c4
-rw-r--r--arch/x86/cpu/start.S95
-rw-r--r--arch/x86/dts/bayleybay.dts38
-rw-r--r--arch/x86/dts/minnowmax.dts125
-rw-r--r--arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h1
-rw-r--r--arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h1
-rw-r--r--arch/x86/include/asm/fsp/fsp_support.h7
-rw-r--r--arch/x86/include/asm/fsp/fsp_types.h11
-rw-r--r--arch/x86/include/asm/global_data.h4
-rw-r--r--arch/x86/include/asm/irq.h4
-rw-r--r--arch/x86/include/asm/u-boot-x86.h1
-rw-r--r--arch/x86/lib/fsp/fsp_common.c13
-rw-r--r--arch/x86/lib/fsp/fsp_support.c3
22 files changed, 386 insertions, 189 deletions
diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
index 86b6926..a72d615 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -1,14 +1,18 @@
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2015, Kodak Alaris, Inc
*
* SPDX-License-Identifier: Intel
*/
#include <common.h>
+#include <fdtdec.h>
#include <asm/arch/fsp/azalia.h>
#include <asm/fsp/fsp_support.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* ALC262 Verb Table - 10EC0262 */
static const uint32_t verb_table_data13[] = {
/* Pin Complex (NID 0x11) */
@@ -116,41 +120,139 @@ const struct pch_azalia_config azalia_config = {
.reset_wait_timer_us = 300
};
+/**
+ * Override the FSP's UPD.
+ * If the device tree does not specify an integer setting, use the default
+ * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file.
+ */
void update_fsp_upd(struct upd_region *fsp_upd)
{
struct memory_down_data *mem;
+ const void *blob = gd->fdt_blob;
+ int node;
- /*
- * Configure everything here to avoid the poor hard-pressed user
- * needing to run Intel's binary configuration tool. It may also allow
- * us to support the 1GB single core variant easily.
- *
- * TODO(sjg@chromium.org): Move to device tree
- */
- fsp_upd->mrc_init_tseg_size = 8;
- fsp_upd->mrc_init_mmio_size = 0x800;
- fsp_upd->emmc_boot_mode = 0xff;
- fsp_upd->enable_sdio = 1;
- fsp_upd->enable_sdcard = 1;
- fsp_upd->enable_hsuart0 = 1;
fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
- fsp_upd->enable_i2_c0 = 0;
- fsp_upd->enable_i2_c2 = 0;
- fsp_upd->enable_i2_c3 = 0;
- fsp_upd->enable_i2_c4 = 0;
- fsp_upd->enable_xhci = 0;
- fsp_upd->igd_render_standby = 1;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP);
+ if (node < 0) {
+ debug("%s: Cannot find FSP node\n", __func__);
+ return;
+ }
+
+ fsp_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node,
+ "fsp,mrc-init-tseg-size",
+ 0);
+ fsp_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node,
+ "fsp,mrc-init-mmio-size",
+ 0x800);
+ fsp_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node,
+ "fsp,mrc-init-spd-addr1",
+ 0xa0);
+ fsp_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node,
+ "fsp,mrc-init-spd-addr2",
+ 0xa2);
+ fsp_upd->emmc_boot_mode = fdtdec_get_int(blob, node,
+ "fsp,emmc-boot-mode", 2);
+ fsp_upd->enable_sdio = fdtdec_get_bool(blob, node, "fsp,enable-sdio");
+ fsp_upd->enable_sdcard = fdtdec_get_bool(blob, node,
+ "fsp,enable-sdcard");
+ fsp_upd->enable_hsuart0 = fdtdec_get_bool(blob, node,
+ "fsp,enable-hsuart0");
+ fsp_upd->enable_hsuart1 = fdtdec_get_bool(blob, node,
+ "fsp,enable-hsuart1");
+ fsp_upd->enable_spi = fdtdec_get_bool(blob, node, "fsp,enable-spi");
+ fsp_upd->enable_sata = fdtdec_get_bool(blob, node, "fsp,enable-sata");
+ fsp_upd->sata_mode = fdtdec_get_int(blob, node, "fsp,sata-mode", 1);
+ fsp_upd->enable_azalia = fdtdec_get_bool(blob, node,
+ "fsp,enable-azalia");
+ fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci");
+ fsp_upd->enable_lpe = fdtdec_get_bool(blob, node, "fsp,enable-lpe");
+ fsp_upd->lpss_sio_enable_pci_mode = fdtdec_get_bool(blob, node,
+ "fsp,lpss-sio-enable-pci-mode");
+ fsp_upd->enable_dma0 = fdtdec_get_bool(blob, node, "fsp,enable-dma0");
+ fsp_upd->enable_dma1 = fdtdec_get_bool(blob, node, "fsp,enable-dma1");
+ fsp_upd->enable_i2_c0 = fdtdec_get_bool(blob, node, "fsp,enable-i2c0");
+ fsp_upd->enable_i2_c1 = fdtdec_get_bool(blob, node, "fsp,enable-i2c1");
+ fsp_upd->enable_i2_c2 = fdtdec_get_bool(blob, node, "fsp,enable-i2c2");
+ fsp_upd->enable_i2_c3 = fdtdec_get_bool(blob, node, "fsp,enable-i2c3");
+ fsp_upd->enable_i2_c4 = fdtdec_get_bool(blob, node, "fsp,enable-i2c4");
+ fsp_upd->enable_i2_c5 = fdtdec_get_bool(blob, node, "fsp,enable-i2c5");
+ fsp_upd->enable_i2_c6 = fdtdec_get_bool(blob, node, "fsp,enable-i2c6");
+ fsp_upd->enable_pwm0 = fdtdec_get_bool(blob, node, "fsp,enable-pwm0");
+ fsp_upd->enable_pwm1 = fdtdec_get_bool(blob, node, "fsp,enable-pwm1");
+ fsp_upd->enable_hsi = fdtdec_get_bool(blob, node, "fsp,enable-hsi");
+ fsp_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node,
+ "fsp,igd-dvmt50-pre-alloc", 2);
+ fsp_upd->aperture_size = fdtdec_get_int(blob, node, "fsp,aperture-size",
+ 2);
+ fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size", 2);
+ fsp_upd->serial_debug_port_address = fdtdec_get_int(blob, node,
+ "fsp,serial-debug-port-address", 0x3f8);
+ fsp_upd->serial_debug_port_type = fdtdec_get_int(blob, node,
+ "fsp,serial-debug-port-type", 1);
+ fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node,
+ "fsp,mrc-debug-msg");
+ fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable");
+ fsp_upd->scc_enable_pci_mode = fdtdec_get_bool(blob, node,
+ "fsp,scc-enable-pci-mode");
+ fsp_upd->igd_render_standby = fdtdec_get_bool(blob, node,
+ "fsp,igd-render-standby");
+ fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node,
+ "fsp,txe-uma-enable");
+ fsp_upd->os_selection = fdtdec_get_int(blob, node, "fsp,os-selection",
+ 4);
+ fsp_upd->emmc45_ddr50_enabled = fdtdec_get_bool(blob, node,
+ "fsp,emmc45-ddr50-enabled");
+ fsp_upd->emmc45_hs200_enabled = fdtdec_get_bool(blob, node,
+ "fsp,emmc45-hs200-enabled");
+ fsp_upd->emmc45_retune_timer_value = fdtdec_get_int(blob, node,
+ "fsp,emmc45-retune-timer-value", 8);
+ fsp_upd->enable_igd = fdtdec_get_bool(blob, node, "fsp,enable-igd");
mem = &fsp_upd->memory_params;
- mem->enable_memory_down = 1;
- mem->dram_speed = 1;
- mem->dimm_width = 1;
- mem->dimm_density = 2;
- mem->dimm_tcl = 0xb;
- mem->dimm_trpt_rcd = 0xb;
- mem->dimm_twr = 0xc;
- mem->dimm_twtr = 6;
- mem->dimm_trrd = 6;
- mem->dimm_trtp = 6;
- mem->dimm_tfaw = 0x14;
+ mem->enable_memory_down = fdtdec_get_bool(blob, node,
+ "fsp,enable-memory-down");
+ if (mem->enable_memory_down) {
+ node = fdtdec_next_compatible(blob, node,
+ COMPAT_INTEL_BAYTRAIL_FSP_MDP);
+ if (node < 0) {
+ debug("%s: Cannot find FSP memory-down-params node\n",
+ __func__);
+ } else {
+ mem->dram_speed = fdtdec_get_int(blob, node,
+ "fsp,dram-speed",
+ 0x02);
+ mem->dram_type = fdtdec_get_int(blob, node,
+ "fsp,dram-type", 0x01);
+ mem->dimm_0_enable = fdtdec_get_bool(blob, node,
+ "fsp,dimm-0-enable");
+ mem->dimm_1_enable = fdtdec_get_bool(blob, node,
+ "fsp,dimm-1-enable");
+ mem->dimm_width = fdtdec_get_int(blob, node,
+ "fsp,dimm-width",
+ 0x00);
+ mem->dimm_density = fdtdec_get_int(blob, node,
+ "fsp,dimm-density",
+ 0x01);
+ mem->dimm_bus_width = fdtdec_get_int(blob, node,
+ "fsp,dimm-bus-width", 0x03);
+ mem->dimm_sides = fdtdec_get_int(blob, node,
+ "fsp,dimm-sides",
+ 0x00);
+ mem->dimm_tcl = fdtdec_get_int(blob, node,
+ "fsp,dimm-tcl", 0x09);
+ mem->dimm_trpt_rcd = fdtdec_get_int(blob, node,
+ "fsp,dimm-trpt-rcd", 0x09);
+ mem->dimm_twr = fdtdec_get_int(blob, node,
+ "fsp,dimm-twr", 0x0A);
+ mem->dimm_twtr = fdtdec_get_int(blob, node,
+ "fsp,dimm-twtr", 0x05);
+ mem->dimm_trrd = fdtdec_get_int(blob, node,
+ "fsp,dimm-trrd", 0x04);
+ mem->dimm_trtp = fdtdec_get_int(blob, node,
+ "fsp,dimm-trtp", 0x05);
+ mem->dimm_tfaw = fdtdec_get_int(blob, node,
+ "fsp,dimm-tfaw", 0x14);
+ }
+ }
}
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
index 610e9d9..6c3dfe8 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -9,6 +9,7 @@
#include <pci_ids.h>
#include <asm/irq.h>
#include <asm/post.h>
+#include <asm/fsp/fsp_support.h>
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
@@ -40,8 +41,14 @@ int arch_cpu_init(void)
int arch_misc_init(void)
{
- pirq_init();
+ int ret;
- return 0;
+ if (!ll_boot_init())
+ return 0;
+ ret = pirq_init();
+ if (ret)
+ return ret;
+
+ return fsp_init_phase_pci();
}
#endif
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 129777c..1b76ca1 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -136,9 +136,12 @@ static void load_gdt(const u64 *boot_gdt, u16 num_entries)
asm volatile("lgdtl %0\n" : : "m" (gdt));
}
-void setup_gdt(gd_t *id, u64 *gdt_addr)
+void arch_setup_gd(gd_t *new_gd)
{
- id->arch.gdt = gdt_addr;
+ u64 *gdt_addr;
+
+ gdt_addr = new_gd->arch.gdt;
+
/* CS: code, read/execute, 4 GB, base 0 */
gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
@@ -146,9 +149,9 @@ void setup_gdt(gd_t *id, u64 *gdt_addr)
gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
/* FS: data, read/write, 4 GB, base (Global Data Pointer) */
- id->arch.gd_addr = id;
+ new_gd->arch.gd_addr = new_gd;
gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
- (ulong)&id->arch.gd_addr, 0xfffff);
+ (ulong)&new_gd->arch.gd_addr, 0xfffff);
/* 16-bit CS: code, read/execute, 64 kB, base 0 */
gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index 9217307..addd26e 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -103,6 +103,8 @@ static void dump_regs(struct irq_regs *regs)
printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
(u16)cs, eip, eflags);
+ if (gd->flags & GD_FLG_RELOC)
+ printf("Original EIP :[<%08lx>]\n", eip - gd->reloc_off);
printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
regs->eax, regs->ebx, regs->ecx, regs->edx);
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 97dd000..35b29f6 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -125,10 +125,10 @@ static int create_pirq_routing_table(void)
return -EINVAL;
}
- ret = fdtdec_get_int_array(blob, node, "intel,pirq-link",
- &irq_router.link_base, 1);
- if (ret)
+ ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1);
+ if (ret == -1)
return ret;
+ irq_router.link_base = ret;
irq_router.irq_mask = fdtdec_get_int(blob, node,
"intel,pirq-mask", PIRQ_BITMAP);
@@ -156,18 +156,13 @@ static int create_pirq_routing_table(void)
}
cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
- if (!cell)
- return -EINVAL;
-
- if ((len % sizeof(struct pirq_routing)) == 0)
- count = len / sizeof(struct pirq_routing);
- else
+ if (!cell || len % sizeof(struct pirq_routing))
return -EINVAL;
+ count = len / sizeof(struct pirq_routing);
- rt = malloc(sizeof(struct irq_routing_table));
+ rt = calloc(1, sizeof(struct irq_routing_table));
if (!rt)
return -ENOMEM;
- memset((char *)rt, 0, sizeof(struct irq_routing_table));
/* Populate the PIRQ table fields */
rt->signature = PIRQ_SIGNATURE;
@@ -181,7 +176,8 @@ static int create_pirq_routing_table(void)
slot_base = rt->slots;
/* Now fill in the irq_info entries in the PIRQ table */
- for (i = 0; i < count; i++) {
+ for (i = 0; i < count;
+ i++, cell += sizeof(struct pirq_routing) / sizeof(u32)) {
struct pirq_routing pr;
pr.bdf = fdt_addr_to_cpu(cell[0]);
@@ -212,25 +208,14 @@ static int create_pirq_routing_table(void)
if (slot->irq[pr.pin - 1].link !=
LINK_N2V(pr.pirq, irq_router.link_base))
debug("WARNING: Inconsistent PIRQ routing information\n");
-
- cell += sizeof(struct pirq_routing) /
- sizeof(u32);
- continue;
- } else {
- debug("writing INT%c\n", 'A' + pr.pin - 1);
- fill_irq_info(slot, PCI_BUS(pr.bdf),
- PCI_DEV(pr.bdf), pr.pin, pr.pirq);
- cell += sizeof(struct pirq_routing) /
- sizeof(u32);
continue;
}
+ } else {
+ slot = slot_base + irq_entries++;
}
-
- slot = slot_base + irq_entries;
- fill_irq_info(slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
- pr.pin, pr.pirq);
- irq_entries++;
- cell += sizeof(struct pirq_routing) / sizeof(u32);
+ debug("writing INT%c\n", 'A' + pr.pin - 1);
+ fill_irq_info(slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), pr.pin,
+ pr.pirq);
}
rt->size = irq_entries * sizeof(struct irq_info) + 32;
@@ -240,17 +225,22 @@ static int create_pirq_routing_table(void)
return 0;
}
-void pirq_init(void)
+int pirq_init(void)
{
+ int ret;
+
cpu_irq_init();
- if (create_pirq_routing_table()) {
+ ret = create_pirq_routing_table();
+ if (ret) {
debug("Failed to create pirq routing table\n");
- } else {
- /* Route PIRQ */
- pirq_route_irqs(pirq_routing_table->slots,
- get_irq_slot_count(pirq_routing_table));
+ return ret;
}
+ /* Route PIRQ */
+ pirq_route_irqs(pirq_routing_table->slots,
+ get_irq_slot_count(pirq_routing_table));
+
+ return 0;
}
u32 write_pirq_routing_table(u32 addr)
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 3294a50..4334f5b 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -515,5 +515,12 @@ int mp_init(struct mp_params *p)
int mp_init_cpu(struct udevice *cpu, void *unused)
{
+ /*
+ * Multiple APs are brought up simultaneously and they may get the same
+ * seq num in the uclass_resolve_seq() during device_probe(). To avoid
+ * this, set req_seq to the reg number in the device tree in advance.
+ */
+ cpu->req_seq = fdtdec_get_int(gd->fdt_blob, cpu->of_offset, "reg", -1);
+
return device_probe(cpu);
}
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index f8da080..d2ec45a 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -76,7 +76,8 @@ unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where)
{
uint8_t value;
- pci_hose_read_config_byte(get_hose(), dev, where, &value);
+ if (pci_hose_read_config_byte(get_hose(), dev, where, &value))
+ return -1U;
return value;
}
@@ -85,7 +86,8 @@ unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where)
{
uint16_t value;
- pci_hose_read_config_word(get_hose(), dev, where, &value);
+ if (pci_hose_read_config_word(get_hose(), dev, where, &value))
+ return -1U;
return value;
}
@@ -94,7 +96,8 @@ unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where)
{
uint32_t value;
- pci_hose_read_config_dword(get_hose(), dev, where, &value);
+ if (pci_hose_read_config_dword(get_hose(), dev, where, &value))
+ return -1U;
return value;
}
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 64634a9..7c03e02 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -41,7 +41,5 @@ void reset_cpu(ulong addr)
int arch_misc_init(void)
{
- pirq_init();
-
- return 0;
+ return pirq_init();
}
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 20cc09e..12ac376 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -174,7 +174,5 @@ void cpu_irq_init(void)
int arch_misc_init(void)
{
- pirq_init();
-
- return 0;
+ return pirq_init();
}
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index de50893..c465642 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -80,7 +80,5 @@ void cpu_irq_init(void)
int arch_misc_init(void)
{
- pirq_init();
-
- return 0;
+ return pirq_init();
}
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 313fa3f..e94ddc4 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -104,8 +104,7 @@ car_init_ret:
*
* top-> CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE
* MRC area
- * global_data
- * x86 global descriptor table
+ * global_data with x86 global descriptor table
* early malloc area
* stack
* bottom-> CONFIG_SYS_CAR_ADDR
@@ -120,13 +119,10 @@ car_init_ret:
* and esi holds the HOB list address returned by the FSP.
*/
#endif
-
- /* Reserve space on stack for global data */
- subl $GENERATED_GBL_DATA_SIZE, %esp
-
- /* Align global data to 16-byte boundary */
- andl $0xfffffff0, %esp
- post_code(POST_START_STACK)
+ /* Set up global data */
+ mov %esp, %eax
+ call board_init_f_mem
+ mov %eax, %esp
/*
* Debug UART is available here although it may not be plumbed out
@@ -137,56 +133,21 @@ car_init_ret:
* call printch
*/
- /* Zero the global data since it won't happen later */
- xorl %eax, %eax
- movl $GENERATED_GBL_DATA_SIZE, %ecx
- movl %esp, %edi
- rep stosb
-
+ /* Get address of global_data */
+ mov %fs:0, %edx
#ifdef CONFIG_HAVE_FSP
+ /* Store the HOB list if we have one */
test %esi, %esi
jz skip_hob
-
- /* Store HOB list */
- movl %esp, %edx
- addl $GD_HOB_LIST, %edx
- movl %esi, (%edx)
+ movl %esi, GD_HOB_LIST(%edx)
skip_hob:
#else
/* Store table pointer */
- movl %esp, %edx
- addl $GD_TABLE, %edx
- movl %esi, (%edx)
+ movl %esi, GD_TABLE(%edx)
#endif
-
- /* Setup first parameter to setup_gdt, pointer to global_data */
- movl %esp, %eax
-
- /* Reserve space for global descriptor table */
- subl $X86_GDT_SIZE, %esp
-
- /* Align temporary global descriptor table to 16-byte boundary */
- andl $0xfffffff0, %esp
- movl %esp, %ecx
-
-#if defined(CONFIG_SYS_MALLOC_F_LEN)
- /* Set up the pre-relocation malloc pool */
- subl $CONFIG_SYS_MALLOC_F_LEN, %esp
- movl %eax, %edx
- addl $GD_MALLOC_BASE, %edx
- movl %esp, (%edx)
-#endif
- /* Store BIST into global_data */
- movl %eax, %edx
- addl $GD_BIST, %edx
- movl %ebp, (%edx)
-
- /* Set second parameter to setup_gdt() */
- movl %ecx, %edx
-
- /* Setup global descriptor table so gd->xyz works */
- call setup_gdt
+ /* Store BIST */
+ movl %ebp, GD_BIST(%edx)
/* Set parameter to board_init_f() to boot flags */
post_code(POST_START_DONE)
@@ -213,37 +174,7 @@ board_init_f_r_trampoline:
/* Stack grows down from top of SDRAM */
movl %eax, %esp
- /* Reserve space on stack for global data */
- subl $GENERATED_GBL_DATA_SIZE, %esp
-
- /* Align global data to 16-byte boundary */
- andl $0xfffffff0, %esp
-
- /* Setup first parameter to memcpy() and setup_gdt() */
- movl %esp, %eax
-
- /* Setup second parameter to memcpy() */
- fs movl 0, %edx
-
- /* Set third parameter to memcpy() */
- movl $GENERATED_GBL_DATA_SIZE, %ecx
-
- /* Copy global data from CAR to SDRAM stack */
- call memcpy
-
- /* Reserve space for global descriptor table */
- subl $X86_GDT_SIZE, %esp
-
- /* Align global descriptor table to 16-byte boundary */
- andl $0xfffffff0, %esp
-
- /* Set second parameter to setup_gdt() */
- movl %esp, %edx
-
- /* Setup global descriptor table so gd->xyz works */
- call setup_gdt
-
- /* Set if we need to disable CAR */
+ /* See if we need to disable CAR */
.weak car_uninit
movl $car_uninit, %eax
cmpl $0, %eax
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 9f8fa70..8f0e192 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -188,6 +188,44 @@
};
};
+ fsp {
+ compatible = "intel,baytrail-fsp";
+ fsp,mrc-init-tseg-size = <0>;
+ fsp,mrc-init-mmio-size = <0x800>;
+ fsp,mrc-init-spd-addr1 = <0xa0>;
+ fsp,mrc-init-spd-addr2 = <0xa2>;
+ fsp,emmc-boot-mode = <2>;
+ fsp,enable-sdio;
+ fsp,enable-sdcard;
+ fsp,enable-hsuart1;
+ fsp,enable-spi;
+ fsp,enable-sata;
+ fsp,sata-mode = <1>;
+ fsp,enable-lpe;
+ fsp,lpss-sio-enable-pci-mode;
+ fsp,enable-dma0;
+ fsp,enable-dma1;
+ fsp,enable-i2c0;
+ fsp,enable-i2c1;
+ fsp,enable-i2c2;
+ fsp,enable-i2c3;
+ fsp,enable-i2c4;
+ fsp,enable-i2c5;
+ fsp,enable-i2c6;
+ fsp,enable-pwm0;
+ fsp,enable-pwm1;
+ fsp,igd-dvmt50-pre-alloc = <2>;
+ fsp,aperture-size = <2>;
+ fsp,gtt-size = <2>;
+ fsp,serial-debug-port-address = <0x3f8>;
+ fsp,serial-debug-port-type = <1>;
+ fsp,scc-enable-pci-mode;
+ fsp,os-selection = <4>;
+ fsp,emmc45-ddr50-enabled;
+ fsp,emmc45-retune-timer-value = <8>;
+ fsp,enable-igd;
+ };
+
microcode {
update@0 {
#include "microcode/m0230671117.dtsi"
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 9527233..daac24e 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/gpio/x86-gpio.h>
+#include <dt-bindings/interrupt-router/intel-irq.h>
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
@@ -117,9 +118,127 @@
#address-cells = <3>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
- ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0 0x10000000
- 0x42000000 0x0 0xc0000000 0xc0000000 0 0x10000000
- 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+ ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
+ 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
+ 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+ irq-router@1f,0 {
+ reg = <0x0000f800 0 0 0 0>;
+ compatible = "intel,irq-router";
+ intel,pirq-config = "ibase";
+ intel,ibase-offset = <0x50>;
+ intel,pirq-link = <8 8>;
+ intel,pirq-mask = <0xdee0>;
+ intel,pirq-routing = <
+ /* BayTrail PCI devices */
+ PCI_BDF(0, 2, 0) INTA PIRQA
+ PCI_BDF(0, 3, 0) INTA PIRQA
+ PCI_BDF(0, 16, 0) INTA PIRQA
+ PCI_BDF(0, 17, 0) INTA PIRQA
+ PCI_BDF(0, 18, 0) INTA PIRQA
+ PCI_BDF(0, 19, 0) INTA PIRQA
+ PCI_BDF(0, 20, 0) INTA PIRQA
+ PCI_BDF(0, 21, 0) INTA PIRQA
+ PCI_BDF(0, 22, 0) INTA PIRQA
+ PCI_BDF(0, 23, 0) INTA PIRQA
+ PCI_BDF(0, 24, 0) INTA PIRQA
+ PCI_BDF(0, 24, 1) INTC PIRQC
+ PCI_BDF(0, 24, 2) INTD PIRQD
+ PCI_BDF(0, 24, 3) INTB PIRQB
+ PCI_BDF(0, 24, 4) INTA PIRQA
+ PCI_BDF(0, 24, 5) INTC PIRQC
+ PCI_BDF(0, 24, 6) INTD PIRQD
+ PCI_BDF(0, 24, 7) INTB PIRQB
+ PCI_BDF(0, 26, 0) INTA PIRQA
+ PCI_BDF(0, 27, 0) INTA PIRQA
+ PCI_BDF(0, 28, 0) INTA PIRQA
+ PCI_BDF(0, 28, 1) INTB PIRQB
+ PCI_BDF(0, 28, 2) INTC PIRQC
+ PCI_BDF(0, 28, 3) INTD PIRQD
+ PCI_BDF(0, 29, 0) INTA PIRQA
+ PCI_BDF(0, 30, 0) INTA PIRQA
+ PCI_BDF(0, 30, 1) INTD PIRQD
+ PCI_BDF(0, 30, 2) INTB PIRQB
+ PCI_BDF(0, 30, 3) INTC PIRQC
+ PCI_BDF(0, 30, 4) INTD PIRQD
+ PCI_BDF(0, 30, 5) INTB PIRQB
+ PCI_BDF(0, 31, 3) INTB PIRQB
+
+ /* PCIe root ports downstream interrupts */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(1, 0, 0) INTB PIRQB
+ PCI_BDF(1, 0, 0) INTC PIRQC
+ PCI_BDF(1, 0, 0) INTD PIRQD
+ PCI_BDF(2, 0, 0) INTA PIRQB
+ PCI_BDF(2, 0, 0) INTB PIRQC
+ PCI_BDF(2, 0, 0) INTC PIRQD
+ PCI_BDF(2, 0, 0) INTD PIRQA
+ PCI_BDF(3, 0, 0) INTA PIRQC
+ PCI_BDF(3, 0, 0) INTB PIRQD
+ PCI_BDF(3, 0, 0) INTC PIRQA
+ PCI_BDF(3, 0, 0) INTD PIRQB
+ PCI_BDF(4, 0, 0) INTA PIRQD
+ PCI_BDF(4, 0, 0) INTB PIRQA
+ PCI_BDF(4, 0, 0) INTC PIRQB
+ PCI_BDF(4, 0, 0) INTD PIRQC
+ >;
+ };
+ };
+
+ fsp {
+ compatible = "intel,baytrail-fsp";
+ fsp,mrc-init-tseg-size = <0>;
+ fsp,mrc-init-mmio-size = <0x800>;
+ fsp,mrc-init-spd-addr1 = <0xa0>;
+ fsp,mrc-init-spd-addr2 = <0xa2>;
+ fsp,emmc-boot-mode = <2>;
+ fsp,enable-sdio;
+ fsp,enable-sdcard;
+ fsp,enable-hsuart1;
+ fsp,enable-spi;
+ fsp,enable-sata;
+ fsp,sata-mode = <1>;
+ fsp,enable-lpe;
+ fsp,lpss-sio-enable-pci-mode;
+ fsp,enable-dma0;
+ fsp,enable-dma1;
+ fsp,enable-i2c0;
+ fsp,enable-i2c1;
+ fsp,enable-i2c2;
+ fsp,enable-i2c3;
+ fsp,enable-i2c4;
+ fsp,enable-i2c5;
+ fsp,enable-i2c6;
+ fsp,enable-pwm0;
+ fsp,enable-pwm1;
+ fsp,igd-dvmt50-pre-alloc = <2>;
+ fsp,aperture-size = <2>;
+ fsp,gtt-size = <2>;
+ fsp,serial-debug-port-address = <0x3f8>;
+ fsp,serial-debug-port-type = <1>;
+ fsp,scc-enable-pci-mode;
+ fsp,os-selection = <4>;
+ fsp,emmc45-ddr50-enabled;
+ fsp,emmc45-retune-timer-value = <8>;
+ fsp,enable-igd;
+ fsp,enable-memory-down;
+ fsp,memory-down-params {
+ compatible = "intel,baytrail-fsp-mdp";
+ fsp,dram-speed = <1>;
+ fsp,dram-type = <1>;
+ fsp,dimm-0-enable;
+ fsp,dimm-width = <1>;
+ fsp,dimm-density = <2>;
+ fsp,dimm-bus-width = <3>;
+ fsp,dimm-sides = <0>;
+ fsp,dimm-tcl = <0xb>;
+ fsp,dimm-trpt-rcd = <0xb>;
+ fsp,dimm-twr = <0xc>;
+ fsp,dimm-twtr = <6>;
+ fsp,dimm-trrd = <6>;
+ fsp,dimm-trtp = <6>;
+ fsp,dimm-tfaw = <0x14>;
+ };
};
spi {
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
index eb0d506..3c782a8 100644
--- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
+++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
@@ -82,7 +82,6 @@ struct __packed upd_region {
};
#define VPD_IMAGE_ID 0x3157454956594C56 /* 'VLYVIEW1' */
-#define VPD_IMAGE_REV 0x00000303
struct __packed vpd_region {
uint64_t sign; /* Offset 0x0000 */
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
index 3c57558..9c54ecc 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
@@ -35,7 +35,6 @@ struct __packed upd_region {
};
#define VPD_IMAGE_ID 0x445056574F4E4E4D /* 'MNNOWVPD' */
-#define VPD_IMAGE_REV 0x00000301
struct __packed vpd_region {
u64 sign; /* Offset 0x0000 */
diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h
index c6c7dc0..7317dda 100644
--- a/arch/x86/include/asm/fsp/fsp_support.h
+++ b/arch/x86/include/asm/fsp/fsp_support.h
@@ -207,4 +207,11 @@ void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len);
*/
void update_fsp_upd(struct upd_region *fsp_upd);
+/**
+ * fsp_init_phase_pci() - Tell the FSP that we have completed PCI init
+ *
+ * @return 0 if OK, -EPERM if the FSP gave an error.
+ */
+int fsp_init_phase_pci(void);
+
#endif
diff --git a/arch/x86/include/asm/fsp/fsp_types.h b/arch/x86/include/asm/fsp/fsp_types.h
index f32d827..4fe69f2 100644
--- a/arch/x86/include/asm/fsp/fsp_types.h
+++ b/arch/x86/include/asm/fsp/fsp_types.h
@@ -68,15 +68,4 @@ struct efi_guid {
#define SIGNATURE_64(A, B, C, D, E, F, G, H) \
(SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32))
-/*
- * Define FSP API return status code.
- * Compatiable with EFI_STATUS defined in PI Spec.
- */
-#define FSP_SUCCESS 0
-#define FSP_INVALID_PARAM 0x80000002
-#define FSP_UNSUPPORTED 0x80000003
-#define FSP_DEVICE_ERROR 0x80000007
-#define FSP_NOT_FOUND 0x8000000E
-#define FSP_ALREADY_STARTED 0x80000014
-
#endif
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index f7e3889..35148ab 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -10,6 +10,8 @@
#ifndef __ASSEMBLY__
+#include <asm/processor.h>
+
enum pei_boot_mode_t {
PEI_BOOT_NONE = 0,
PEI_BOOT_SOFT_RESET,
@@ -44,6 +46,7 @@ struct mtrr_request {
/* Architecture-specific global data */
struct arch_global_data {
+ u64 gdt[X86_GDT_NUM_ENTRIES] __aligned(16);
struct global_data *gd_addr; /* Location of Global Data */
uint8_t x86; /* CPU family */
uint8_t x86_vendor; /* CPU vendor */
@@ -68,7 +71,6 @@ struct arch_global_data {
/* MRC training data to save for the next boot */
char *mrc_output;
unsigned int mrc_output_len;
- void *gdt; /* Global descriptor table */
ulong table; /* Table pointer from previous loader */
};
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index 4de5512..6697da3 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -70,7 +70,9 @@ void cpu_irq_init(void);
*
* This initializes the PIRQ routing on the platform and configures all PCI
* devices' interrupt line register to a working IRQ number on the 8259 PIC.
+ *
+ * @return 0 if OK, -ve on error
*/
-void pirq_init(void);
+int pirq_init(void);
#endif /* _ARCH_IRQ_H_ */
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 4dae365..1c459d5 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -14,7 +14,6 @@ extern char gdt_rom[];
int arch_cpu_init(void);
int x86_cpu_init_f(void);
int cpu_init_f(void);
-void init_gd(gd_t *id, u64 *gdt_addr);
void setup_gdt(gd_t *id, u64 *gdt_addr);
/*
* Setup FSP execution environment GDT to use the one we used in
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index c585710..d564cb9 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -19,19 +19,24 @@ int print_cpuinfo(void)
return default_print_cpuinfo();
}
-int board_pci_post_scan(struct pci_controller *hose)
+int fsp_init_phase_pci(void)
{
u32 status;
/* call into FspNotify */
debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
status = fsp_notify(NULL, INIT_PHASE_PCI);
- if (status != FSP_SUCCESS)
+ if (status)
debug("fail, error code %x\n", status);
else
debug("OK\n");
- return 0;
+ return status ? -EPERM : 0;
+}
+
+int board_pci_post_scan(struct pci_controller *hose)
+{
+ return fsp_init_phase_pci();
}
void board_final_cleanup(void)
@@ -41,7 +46,7 @@ void board_final_cleanup(void)
/* call into FspNotify */
debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
status = fsp_notify(NULL, INIT_PHASE_BOOT);
- if (status != FSP_SUCCESS)
+ if (status)
debug("fail, error code %x\n", status);
else
debug("OK\n");
diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index 4585166..1d48ff4 100644
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -147,8 +147,7 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
fsp_hdr->cfg_region_off);
/* Verify the VPD data region is valid */
- assert((fsp_vpd->img_rev == VPD_IMAGE_REV) &&
- (fsp_vpd->sign == VPD_IMAGE_ID));
+ assert(fsp_vpd->sign == VPD_IMAGE_ID);
/* Copy default data from Flash */
memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
generated by cgit v1.1 at 2025-01-04 20:40:34 +0000