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-rw-r--r--arch/x86/include/asm/i8254.h43
-rw-r--r--arch/x86/include/asm/i8259.h31
-rw-r--r--arch/x86/lib/pcat_interrupts.c21
-rw-r--r--arch/x86/lib/pcat_timer.c10
4 files changed, 52 insertions, 53 deletions
diff --git a/arch/x86/include/asm/i8254.h b/arch/x86/include/asm/i8254.h
index 4116de1..48e4df2 100644
--- a/arch/x86/include/asm/i8254.h
+++ b/arch/x86/include/asm/i8254.h
@@ -5,38 +5,35 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-
/* i8254.h Intel 8254 PIT registers */
-
#ifndef _ASMI386_I8254_H_
-#define _ASMI386_I8954_H_ 1
-
+#define _ASMI386_I8954_H_
-#define PIT_T0 0x00 /* PIT channel 0 count/status */
-#define PIT_T1 0x01 /* PIT channel 1 count/status */
-#define PIT_T2 0x02 /* PIT channel 2 count/status */
-#define PIT_COMMAND 0x03 /* PIT mode control, latch and read back */
+#define PIT_T0 0x00 /* PIT channel 0 count/status */
+#define PIT_T1 0x01 /* PIT channel 1 count/status */
+#define PIT_T2 0x02 /* PIT channel 2 count/status */
+#define PIT_COMMAND 0x03 /* PIT mode control, latch and read back */
/* PIT Command Register Bit Definitions */
-#define PIT_CMD_CTR0 0x00 /* Select PIT counter 0 */
-#define PIT_CMD_CTR1 0x40 /* Select PIT counter 1 */
-#define PIT_CMD_CTR2 0x80 /* Select PIT counter 2 */
+#define PIT_CMD_CTR0 0x00 /* Select PIT counter 0 */
+#define PIT_CMD_CTR1 0x40 /* Select PIT counter 1 */
+#define PIT_CMD_CTR2 0x80 /* Select PIT counter 2 */
-#define PIT_CMD_LATCH 0x00 /* Counter Latch Command */
-#define PIT_CMD_LOW 0x10 /* Access counter bits 7-0 */
-#define PIT_CMD_HIGH 0x20 /* Access counter bits 15-8 */
-#define PIT_CMD_BOTH 0x30 /* Access counter bits 15-0 in two accesses */
+#define PIT_CMD_LATCH 0x00 /* Counter Latch Command */
+#define PIT_CMD_LOW 0x10 /* Access counter bits 7-0 */
+#define PIT_CMD_HIGH 0x20 /* Access counter bits 15-8 */
+#define PIT_CMD_BOTH 0x30 /* Access counter bits 15-0 in two accesses */
-#define PIT_CMD_MODE0 0x00 /* Select mode 0 */
-#define PIT_CMD_MODE1 0x02 /* Select mode 1 */
-#define PIT_CMD_MODE2 0x04 /* Select mode 2 */
-#define PIT_CMD_MODE3 0x06 /* Select mode 3 */
-#define PIT_CMD_MODE4 0x08 /* Select mode 4 */
-#define PIT_CMD_MODE5 0x0A /* Select mode 5 */
+#define PIT_CMD_MODE0 0x00 /* Select mode 0 */
+#define PIT_CMD_MODE1 0x02 /* Select mode 1 */
+#define PIT_CMD_MODE2 0x04 /* Select mode 2 */
+#define PIT_CMD_MODE3 0x06 /* Select mode 3 */
+#define PIT_CMD_MODE4 0x08 /* Select mode 4 */
+#define PIT_CMD_MODE5 0x0a /* Select mode 5 */
/* The clock frequency of the i8253/i8254 PIT */
-#define PIT_TICK_RATE 1193182ul
+#define PIT_TICK_RATE 1193182
-#endif
+#endif /* _ASMI386_I8954_H_ */
diff --git a/arch/x86/include/asm/i8259.h b/arch/x86/include/asm/i8259.h
index bc4033b..f216c23 100644
--- a/arch/x86/include/asm/i8259.h
+++ b/arch/x86/include/asm/i8259.h
@@ -8,11 +8,9 @@
/* i8259.h i8259 PIC Registers */
#ifndef _ASMI386_I8259_H_
-#define _ASMI386_I8959_H_ 1
-
+#define _ASMI386_I8959_H_
/* PIC I/O mapped registers */
-
#define IRR 0x0 /* Interrupt Request Register */
#define ISR 0x0 /* In-Service Register */
#define ICW1 0x0 /* Initialization Control Word 1 */
@@ -23,7 +21,7 @@
#define ICW4 0x1 /* Initialization Control Word 4 */
#define IMR 0x1 /* Interrupt Mask Register */
-/* bits for IRR, IMR, ISR and ICW3 */
+/* IRR, IMR, ISR and ICW3 bits */
#define IR7 0x80 /* IR7 */
#define IR6 0x40 /* IR6 */
#define IR5 0x20 /* IR5 */
@@ -33,7 +31,7 @@
#define IR1 0x02 /* IR1 */
#define IR0 0x01 /* IR0 */
-/* bits for SEOI */
+/* SEOI bits */
#define SEOI_IR7 0x07 /* IR7 */
#define SEOI_IR6 0x06 /* IR6 */
#define SEOI_IR5 0x05 /* IR5 */
@@ -49,9 +47,9 @@
#define OCW2_NOP 0x40 /* NOP */
#define OCW2_SEOI 0x60 /* Specific EOI */
#define OCW2_RSET 0x80 /* Rotate/set */
-#define OCW2_REOI 0xA0 /* Rotate on non specific EOI */
-#define OCW2_PSET 0xC0 /* Priority Set Command */
-#define OCW2_RSEOI 0xE0 /* Rotate on specific EOI */
+#define OCW2_REOI 0xa0 /* Rotate on non specific EOI */
+#define OCW2_PSET 0xc0 /* Priority Set Command */
+#define OCW2_RSEOI 0xe0 /* Rotate on specific EOI */
/* ICW1 bits */
#define ICW1_SEL 0x10 /* Select ICW1 */
@@ -60,15 +58,20 @@
#define ICW1_SNGL 0x02 /* Single PIC */
#define ICW1_EICW4 0x01 /* Expect initilization ICW4 */
-/* ICW2 is the starting vector number */
-
-/* ICW2 is bit-mask of present slaves for a master device,
- * or the slave ID for a slave device */
+/*
+ * ICW2 is the starting vector number
+ *
+ * ICW2 is bit-mask of present slaves for a master device,
+ * or the slave ID for a slave device
+ */
/* ICW4 bits */
-#define ICW4_AEOI 0x02 /* Automatic EOI Mode */
+#define ICW4_AEOI 0x02 /* Automatic EOI Mode */
#define ICW4_PM 0x01 /* Microprocessor Mode */
+#define ELCR1 0x4d0
+#define ELCR2 0x4d1
+
int i8259_init(void);
-#endif
+#endif /* _ASMI386_I8959_H_ */
diff --git a/arch/x86/lib/pcat_interrupts.c b/arch/x86/lib/pcat_interrupts.c
index 9780f46..b9d0614 100644
--- a/arch/x86/lib/pcat_interrupts.c
+++ b/arch/x86/lib/pcat_interrupts.c
@@ -28,10 +28,11 @@ int i8259_init(void)
outb(0xff, MASTER_PIC + IMR);
outb(0xff, SLAVE_PIC + IMR);
- /* Master PIC */
- /* Place master PIC interrupts at INT20 */
- /* ICW3, One slave PIC is present */
- outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1);
+ /*
+ * Master PIC
+ * Place master PIC interrupts at INT20
+ */
+ outb(ICW1_SEL | ICW1_EICW4, MASTER_PIC + ICW1);
outb(0x20, MASTER_PIC + ICW2);
outb(IR2, MASTER_PIC + ICW3);
outb(ICW4_PM, MASTER_PIC + ICW4);
@@ -39,10 +40,11 @@ int i8259_init(void)
for (i = 0; i < 8; i++)
outb(OCW2_SEOI | i, MASTER_PIC + OCW2);
- /* Slave PIC */
- /* Place slave PIC interrupts at INT28 */
- /* Slave ID */
- outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1);
+ /*
+ * Slave PIC
+ * Place slave PIC interrupts at INT28
+ */
+ outb(ICW1_SEL | ICW1_EICW4, SLAVE_PIC + ICW1);
outb(0x28, SLAVE_PIC + ICW2);
outb(0x02, SLAVE_PIC + ICW3);
outb(ICW4_PM, SLAVE_PIC + ICW4);
@@ -110,9 +112,6 @@ void specific_eoi(int irq)
outb(OCW2_SEOI | irq, MASTER_PIC + OCW2);
}
-#define ELCR1 0x4d0
-#define ELCR2 0x4d1
-
void configure_irq_trigger(int int_num, bool is_level_triggered)
{
u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
diff --git a/arch/x86/lib/pcat_timer.c b/arch/x86/lib/pcat_timer.c
index 3545a50..ce15818 100644
--- a/arch/x86/lib/pcat_timer.c
+++ b/arch/x86/lib/pcat_timer.c
@@ -9,17 +9,17 @@
#include <asm/io.h>
#include <asm/i8254.h>
-#define TIMER2_VALUE 0x0a8e /* 440Hz */
+#define TIMER2_VALUE 0x0a8e /* 440Hz */
int pcat_timer_init(void)
{
/*
- * initialize 2, used to drive the speaker
- * (to start a beep: write 3 to port 0x61,
- * to stop it again: write 0)
+ * Initialize counter 2, used to drive the speaker.
+ * To start a beep, set both bit0 and bit1 of port 0x61.
+ * To stop it, clear both bit0 and bit1 of port 0x61.
*/
outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3,
- PIT_BASE + PIT_COMMAND);
+ PIT_BASE + PIT_COMMAND);
outb(TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2);
outb(TIMER2_VALUE >> 8, PIT_BASE + PIT_T2);
generated by cgit v1.1 at 2024-12-20 14:06:17 +0000