diff options
Diffstat (limited to 'arch/x86/cpu/quark/smc.c')
| -rw-r--r-- | arch/x86/cpu/quark/smc.c | 1205 |
1 files changed, 531 insertions, 674 deletions
diff --git a/arch/x86/cpu/quark/smc.c b/arch/x86/cpu/quark/smc.c index e34bec4..3ffe92b 100644 --- a/arch/x86/cpu/quark/smc.c +++ b/arch/x86/cpu/quark/smc.c @@ -60,7 +60,7 @@ void clear_self_refresh(struct mrc_params *mrc_params) ENTERFN(); /* clear the PMSTS Channel Self Refresh bits */ - mrc_write_mask(MEM_CTLR, PMSTS, BIT0, BIT0); + mrc_write_mask(MEM_CTLR, PMSTS, PMSTS_DISR, PMSTS_DISR); LEAVEFN(); } @@ -101,47 +101,47 @@ void prog_ddr_timing_control(struct mrc_params *mrc_params) wl = 5 + mrc_params->ddr_speed; - dtr0 &= ~(BIT0 | BIT1); + dtr0 &= ~DTR0_DFREQ_MASK; dtr0 |= mrc_params->ddr_speed; - dtr0 &= ~(BIT12 | BIT13 | BIT14); + dtr0 &= ~DTR0_TCL_MASK; tmp1 = tcl - 5; dtr0 |= ((tcl - 5) << 12); - dtr0 &= ~(BIT4 | BIT5 | BIT6 | BIT7); + dtr0 &= ~DTR0_TRP_MASK; dtr0 |= ((trp - 5) << 4); /* 5 bit DRAM Clock */ - dtr0 &= ~(BIT8 | BIT9 | BIT10 | BIT11); + dtr0 &= ~DTR0_TRCD_MASK; dtr0 |= ((trcd - 5) << 8); /* 5 bit DRAM Clock */ - dtr1 &= ~(BIT0 | BIT1 | BIT2); + dtr1 &= ~DTR1_TWCL_MASK; tmp2 = wl - 3; dtr1 |= (wl - 3); - dtr1 &= ~(BIT8 | BIT9 | BIT10 | BIT11); + dtr1 &= ~DTR1_TWTP_MASK; dtr1 |= ((wl + 4 + twr - 14) << 8); /* Change to tWTP */ - dtr1 &= ~(BIT28 | BIT29 | BIT30); + dtr1 &= ~DTR1_TRTP_MASK; dtr1 |= ((MMAX(trtp, 4) - 3) << 28); /* 4 bit DRAM Clock */ - dtr1 &= ~(BIT24 | BIT25); + dtr1 &= ~DTR1_TRRD_MASK; dtr1 |= ((trrd - 4) << 24); /* 4 bit DRAM Clock */ - dtr1 &= ~(BIT4 | BIT5); + dtr1 &= ~DTR1_TCMD_MASK; dtr1 |= (1 << 4); - dtr1 &= ~(BIT20 | BIT21 | BIT22 | BIT23); + dtr1 &= ~DTR1_TRAS_MASK; dtr1 |= ((tras - 14) << 20); /* 6 bit DRAM Clock */ - dtr1 &= ~(BIT16 | BIT17 | BIT18 | BIT19); + dtr1 &= ~DTR1_TFAW_MASK; dtr1 |= ((((tfaw + 1) >> 1) - 5) << 16);/* 4 bit DRAM Clock */ /* Set 4 Clock CAS to CAS delay (multi-burst) */ - dtr1 &= ~(BIT12 | BIT13); + dtr1 &= ~DTR1_TCCD_MASK; - dtr2 &= ~(BIT0 | BIT1 | BIT2); + dtr2 &= ~DTR2_TRRDR_MASK; dtr2 |= 1; - dtr2 &= ~(BIT8 | BIT9 | BIT10); + dtr2 &= ~DTR2_TWWDR_MASK; dtr2 |= (2 << 8); - dtr2 &= ~(BIT16 | BIT17 | BIT18 | BIT19); + dtr2 &= ~DTR2_TRWDR_MASK; dtr2 |= (2 << 16); - dtr3 &= ~(BIT0 | BIT1 | BIT2); + dtr3 &= ~DTR3_TWRDR_MASK; dtr3 |= 2; - dtr3 &= ~(BIT4 | BIT5 | BIT6); + dtr3 &= ~DTR3_TXXXX_MASK; dtr3 |= (2 << 4); - dtr3 &= ~(BIT8 | BIT9 | BIT10 | BIT11); + dtr3 &= ~DTR3_TRWSR_MASK; if (mrc_params->ddr_speed == DDRFREQ_800) { /* Extended RW delay (+1) */ dtr3 |= ((tcl - 5 + 1) << 8); @@ -150,24 +150,24 @@ void prog_ddr_timing_control(struct mrc_params *mrc_params) dtr3 |= ((tcl - 5 + 1) << 8); } - dtr3 &= ~(BIT13 | BIT14 | BIT15 | BIT16); + dtr3 &= ~DTR3_TWRSR_MASK; dtr3 |= ((4 + wl + twtr - 11) << 13); - dtr3 &= ~(BIT22 | BIT23); + dtr3 &= ~DTR3_TXP_MASK; if (mrc_params->ddr_speed == DDRFREQ_800) dtr3 |= ((MMAX(0, 1 - 1)) << 22); else dtr3 |= ((MMAX(0, 2 - 1)) << 22); - dtr4 &= ~(BIT0 | BIT1); + dtr4 &= ~DTR4_WRODTSTRT_MASK; dtr4 |= 1; - dtr4 &= ~(BIT4 | BIT5 | BIT6); + dtr4 &= ~DTR4_WRODTSTOP_MASK; dtr4 |= (1 << 4); - dtr4 &= ~(BIT8 | BIT9 | BIT10); + dtr4 &= ~DTR4_XXXX1_MASK; dtr4 |= ((1 + tmp1 - tmp2 + 2) << 8); - dtr4 &= ~(BIT12 | BIT13 | BIT14); + dtr4 &= ~DTR4_XXXX2_MASK; dtr4 |= ((1 + tmp1 - tmp2 + 2) << 12); - dtr4 &= ~(BIT15 | BIT16); + dtr4 &= ~(DTR4_ODTDIS | DTR4_TRGSTRDIS); msg_port_write(MEM_CTLR, DTR0, dtr0); msg_port_write(MEM_CTLR, DTR1, dtr1); @@ -191,25 +191,25 @@ void prog_decode_before_jedec(struct mrc_params *mrc_params) /* Disable power saving features */ dpmc0 = msg_port_read(MEM_CTLR, DPMC0); - dpmc0 |= (BIT24 | BIT25); - dpmc0 &= ~(BIT16 | BIT17 | BIT18); - dpmc0 &= ~BIT23; + dpmc0 |= (DPMC0_CLKGTDIS | DPMC0_DISPWRDN); + dpmc0 &= ~DPMC0_PCLSTO_MASK; + dpmc0 &= ~DPMC0_DYNSREN; msg_port_write(MEM_CTLR, DPMC0, dpmc0); /* Disable out of order transactions */ dsch = msg_port_read(MEM_CTLR, DSCH); - dsch |= (BIT8 | BIT12); + dsch |= (DSCH_OOODIS | DSCH_NEWBYPDIS); msg_port_write(MEM_CTLR, DSCH, dsch); /* Disable issuing the REF command */ drfc = msg_port_read(MEM_CTLR, DRFC); - drfc &= ~(BIT12 | BIT13 | BIT14); + drfc &= ~DRFC_TREFI_MASK; msg_port_write(MEM_CTLR, DRFC, drfc); /* Disable ZQ calibration short */ dcal = msg_port_read(MEM_CTLR, DCAL); - dcal &= ~(BIT8 | BIT9 | BIT10); - dcal &= ~(BIT12 | BIT13); + dcal &= ~DCAL_ZQCINT_MASK; + dcal &= ~DCAL_SRXZQCL_MASK; msg_port_write(MEM_CTLR, DCAL, dcal); /* @@ -218,9 +218,9 @@ void prog_decode_before_jedec(struct mrc_params *mrc_params) */ drp = 0; if (mrc_params->rank_enables & 1) - drp |= BIT0; + drp |= DRP_RKEN0; if (mrc_params->rank_enables & 2) - drp |= BIT1; + drp |= DRP_RKEN1; msg_port_write(MEM_CTLR, DRP, drp); LEAVEFN(); @@ -238,14 +238,14 @@ void perform_ddr_reset(struct mrc_params *mrc_params) ENTERFN(); /* Set COLDWAKE bit before sending the WAKE message */ - mrc_write_mask(MEM_CTLR, DRMC, BIT16, BIT16); + mrc_write_mask(MEM_CTLR, DRMC, DRMC_COLDWAKE, DRMC_COLDWAKE); /* Send wake command to DUNIT (MUST be done before JEDEC) */ dram_wake_command(); /* Set default value */ msg_port_write(MEM_CTLR, DRMC, - (mrc_params->rd_odt_value == 0 ? BIT12 : 0)); + mrc_params->rd_odt_value == 0 ? DRMC_ODTMODE : 0); LEAVEFN(); } @@ -263,7 +263,7 @@ void ddrphy_init(struct mrc_params *mrc_params) uint8_t bl_grp; /* byte lane group counter (2 BLs per module) */ uint8_t bl_divisor = 1; /* byte lane divisor */ /* For DDR3 --> 0 == 800, 1 == 1066, 2 == 1333 */ - uint8_t speed = mrc_params->ddr_speed & (BIT1 | BIT0); + uint8_t speed = mrc_params->ddr_speed & 3; uint8_t cas; uint8_t cwl; @@ -286,21 +286,21 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* Deassert DDRPHY Initialization Complete */ mrc_alt_write_mask(DDRPHY, - (CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)), - ~BIT20, BIT20); /* SPID_INIT_COMPLETE=0 */ + CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, + ~(1 << 20), 1 << 20); /* SPID_INIT_COMPLETE=0 */ /* Deassert IOBUFACT */ mrc_alt_write_mask(DDRPHY, - (CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)), - ~BIT2, BIT2); /* IOBUFACTRST_N=0 */ + CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, + ~(1 << 2), 1 << 2); /* IOBUFACTRST_N=0 */ /* Disable WRPTR */ mrc_alt_write_mask(DDRPHY, - (CMDPTRREG + (ch * DDRIOCCC_CH_OFFSET)), - ~BIT0, BIT0); /* WRPTRENABLE=0 */ + CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, + ~(1 << 0), 1 << 0); /* WRPTRENABLE=0 */ } } /* Put PHY in reset */ - mrc_alt_write_mask(DDRPHY, MASTERRSTN, 0, BIT0); + mrc_alt_write_mask(DDRPHY, MASTERRSTN, 0, 1); /* Initialize DQ01, DQ23, CMD, CLK-CTL, COMP modules */ @@ -310,14 +310,14 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* DQ01-DQ23 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { /* Analog MUX select - IO2xCLKSEL */ mrc_alt_write_mask(DDRPHY, - (DQOBSCKEBBCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((bl_grp) ? (0x00) : (BIT22)), (BIT22)); + DQOBSCKEBBCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + bl_grp ? 0 : (1 << 22), 1 << 22); /* ODT Strength */ switch (mrc_params->rd_odt_value) { @@ -337,20 +337,20 @@ void ddrphy_init(struct mrc_params *mrc_params) /* ODT strength */ mrc_alt_write_mask(DDRPHY, - (B0RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (temp << 5), (BIT6 | BIT5)); + B0RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp << 5, 0x60); /* ODT strength */ mrc_alt_write_mask(DDRPHY, - (B1RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (temp << 5), (BIT6 | BIT5)); + B1RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp << 5, 0x60); /* Dynamic ODT/DIFFAMP */ - temp = (((cas) << 24) | ((cas) << 16) | - ((cas) << 8) | ((cas) << 0)); + temp = (cas << 24) | (cas << 16) | + (cas << 8) | (cas << 0); switch (speed) { case 0: temp -= 0x01010101; @@ -368,247 +368,199 @@ void ddrphy_init(struct mrc_params *mrc_params) /* Launch Time: ODT, DIFFAMP, ODT, DIFFAMP */ mrc_alt_write_mask(DDRPHY, - (B01LATCTL1 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT28 | BIT27 | BIT26 | BIT25 | BIT24 | - BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | - BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + B01LATCTL1 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x1f1f1f1f); switch (speed) { /* HSD#234715 */ case 0: - temp = ((0x06 << 16) | (0x07 << 8)); + temp = (0x06 << 16) | (0x07 << 8); break; /* 800 */ case 1: - temp = ((0x07 << 16) | (0x08 << 8)); + temp = (0x07 << 16) | (0x08 << 8); break; /* 1066 */ case 2: - temp = ((0x09 << 16) | (0x0A << 8)); + temp = (0x09 << 16) | (0x0a << 8); break; /* 1333 */ case 3: - temp = ((0x0A << 16) | (0x0B << 8)); + temp = (0x0a << 16) | (0x0b << 8); break; /* 1600 */ } /* On Duration: ODT, DIFFAMP */ mrc_alt_write_mask(DDRPHY, - (B0ONDURCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8)); + B0ONDURCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x003f3f00); /* On Duration: ODT, DIFFAMP */ mrc_alt_write_mask(DDRPHY, - (B1ONDURCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8)); + B1ONDURCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x003f3f00); switch (mrc_params->rd_odt_value) { case 0: /* override DIFFAMP=on, ODT=off */ - temp = ((0x3F << 16) | (0x3f << 10)); + temp = (0x3f << 16) | (0x3f << 10); break; default: /* override DIFFAMP=on, ODT=on */ - temp = ((0x3F << 16) | (0x2A << 10)); + temp = (0x3f << 16) | (0x2a << 10); break; } /* Override: DIFFAMP, ODT */ mrc_alt_write_mask(DDRPHY, - (B0OVRCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT15 | BIT14 | BIT13 | BIT12 | - BIT11 | BIT10)); + B0OVRCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x003ffc00); /* Override: DIFFAMP, ODT */ mrc_alt_write_mask(DDRPHY, - (B1OVRCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT15 | BIT14 | BIT13 | BIT12 | - BIT11 | BIT10)); + B1OVRCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x003ffc00); /* DLL Setup */ /* 1xCLK Domain Timings: tEDP,RCVEN,WDQS (PO) */ mrc_alt_write_mask(DDRPHY, - (B0LATCTL0 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (((cas + 7) << 16) | ((cas - 4) << 8) | - ((cwl - 2) << 0)), - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT12 | BIT11 | BIT10 | BIT9 | - BIT8 | BIT4 | BIT3 | BIT2 | BIT1 | - BIT0)); + B0LATCTL0 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + ((cas + 7) << 16) | ((cas - 4) << 8) | + ((cwl - 2) << 0), 0x003f1f1f); mrc_alt_write_mask(DDRPHY, - (B1LATCTL0 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (((cas + 7) << 16) | ((cas - 4) << 8) | - ((cwl - 2) << 0)), - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT12 | BIT11 | BIT10 | BIT9 | - BIT8 | BIT4 | BIT3 | BIT2 | BIT1 | - BIT0)); + B1LATCTL0 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + ((cas + 7) << 16) | ((cas - 4) << 8) | + ((cwl - 2) << 0), 0x003f1f1f); /* RCVEN Bypass (PO) */ mrc_alt_write_mask(DDRPHY, - (B0RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((0x0 << 7) | (0x0 << 0)), - (BIT7 | BIT0)); + B0RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 0x81); mrc_alt_write_mask(DDRPHY, - (B1RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((0x0 << 7) | (0x0 << 0)), - (BIT7 | BIT0)); + B1RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 0x81); /* TX */ mrc_alt_write_mask(DDRPHY, - (DQCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT16), (BIT16)); + DQCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 16, 1 << 16); mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT8), (BIT8)); + B01PTRCTL1 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 8, 1 << 8); /* RX (PO) */ /* Internal Vref Code, Enable#, Ext_or_Int (1=Ext) */ mrc_alt_write_mask(DDRPHY, - (B0VREFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((0x03 << 2) | (0x0 << 1) | (0x0 << 0)), - (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | - BIT2 | BIT1 | BIT0)); + B0VREFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + (0x03 << 2) | (0x0 << 1) | (0x0 << 0), + 0xff); /* Internal Vref Code, Enable#, Ext_or_Int (1=Ext) */ mrc_alt_write_mask(DDRPHY, - (B1VREFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((0x03 << 2) | (0x0 << 1) | (0x0 << 0)), - (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | - BIT2 | BIT1 | BIT0)); + B1VREFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + (0x03 << 2) | (0x0 << 1) | (0x0 << 0), + 0xff); /* Per-Bit De-Skew Enable */ mrc_alt_write_mask(DDRPHY, - (B0RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (0), (BIT4)); + B0RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 0x10); /* Per-Bit De-Skew Enable */ mrc_alt_write_mask(DDRPHY, - (B1RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (0), (BIT4)); + B1RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 0x10); } /* CLKEBB */ mrc_alt_write_mask(DDRPHY, - (CMDOBSCKEBBCTL + (ch * DDRIOCCC_CH_OFFSET)), - 0, (BIT23)); + CMDOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET, + 0, 1 << 23); /* Enable tristate control of cmd/address bus */ mrc_alt_write_mask(DDRPHY, - (CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)), - 0, (BIT1 | BIT0)); + CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, + 0, 0x03); /* ODT RCOMP */ mrc_alt_write_mask(DDRPHY, - (CMDRCOMPODT + (ch * DDRIOCCC_CH_OFFSET)), - ((0x03 << 5) | (0x03 << 0)), - (BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | - BIT3 | BIT2 | BIT1 | BIT0)); + CMDRCOMPODT + ch * DDRIOCCC_CH_OFFSET, + (0x03 << 5) | (0x03 << 0), 0x3ff); /* CMDPM* registers must be programmed in this order */ /* Turn On Delays: SFR (regulator), MPLL */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG4 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFFFFU << 16) | (0xFFFF << 0)), - 0xFFFFFFFF); + CMDPMDLYREG4 + ch * DDRIOCCC_CH_OFFSET, + 0xffffffff, 0xffffffff); /* * Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, * VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT * for_PM_MSG_gt0, MDLL Turn On */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG3 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFU << 28) | (0xFFF << 16) | (0xF << 12) | - (0x616 << 0)), 0xFFFFFFFF); + CMDPMDLYREG3 + ch * DDRIOCCC_CH_OFFSET, + 0xfffff616, 0xffffffff); /* MPLL Divider Reset Delays */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG2 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) | - (0xFF << 0)), 0xFFFFFFFF); + CMDPMDLYREG2 + ch * DDRIOCCC_CH_OFFSET, + 0xffffffff, 0xffffffff); /* Turn Off Delays: VREG, Staggered MDLL, MDLL, PI */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG1 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) | - (0xFF << 0)), 0xFFFFFFFF); + CMDPMDLYREG1 + ch * DDRIOCCC_CH_OFFSET, + 0xffffffff, 0xffffffff); /* Turn On Delays: MPLL, Staggered MDLL, PI, IOBUFACT */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG0 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) | - (0xFF << 0)), 0xFFFFFFFF); + CMDPMDLYREG0 + ch * DDRIOCCC_CH_OFFSET, + 0xffffffff, 0xffffffff); /* Allow PUnit signals */ mrc_alt_write_mask(DDRPHY, - (CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)), - ((0x6 << 8) | BIT6 | (0x4 << 0)), - (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 | - BIT25 | BIT24 | BIT23 | BIT22 | BIT21 | BIT11 | - BIT10 | BIT9 | BIT8 | BIT6 | BIT3 | BIT2 | - BIT1 | BIT0)); + CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, + (0x6 << 8) | (0x1 << 6) | (0x4 << 0), + 0xffe00f4f); /* DLL_VREG Bias Trim, VREF Tuning for DLL_VREG */ mrc_alt_write_mask(DDRPHY, - (CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - ((0x3 << 4) | (0x7 << 0)), - (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | - BIT0)); + CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + (0x3 << 4) | (0x7 << 0), 0x7f); /* CLK-CTL */ mrc_alt_write_mask(DDRPHY, - (CCOBSCKEBBCTL + (ch * DDRIOCCC_CH_OFFSET)), - 0, BIT24); /* CLKEBB */ + CCOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET, + 0, 1 << 24); /* CLKEBB */ /* Buffer Enable: CS,CKE,ODT,CLK */ mrc_alt_write_mask(DDRPHY, - (CCCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)), - ((0x0 << 16) | (0x0 << 12) | (0x0 << 8) | - (0xF << 4) | BIT0), - (BIT19 | BIT18 | BIT17 | BIT16 | BIT15 | BIT14 | - BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT7 | BIT6 | BIT5 | BIT4 | BIT0)); + CCCFGREG0 + ch * DDRIOCCC_CH_OFFSET, + 0x1f, 0x000ffff1); /* ODT RCOMP */ mrc_alt_write_mask(DDRPHY, - (CCRCOMPODT + (ch * DDRIOCCC_CH_OFFSET)), - ((0x03 << 8) | (0x03 << 0)), - (BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | BIT4 | - BIT3 | BIT2 | BIT1 | BIT0)); + CCRCOMPODT + ch * DDRIOCCC_CH_OFFSET, + (0x03 << 8) | (0x03 << 0), 0x00001f1f); /* DLL_VREG Bias Trim, VREF Tuning for DLL_VREG */ mrc_alt_write_mask(DDRPHY, - (CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - ((0x3 << 4) | (0x7 << 0)), - (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | - BIT0)); + CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + (0x3 << 4) | (0x7 << 0), 0x7f); /* * COMP (RON channel specific) @@ -618,66 +570,43 @@ void ddrphy_init(struct mrc_params *mrc_params) */ /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (DQVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x08 << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + DQVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x08 << 24) | (0x03 << 16), 0x3f3f0000); /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (CMDVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x0C << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + CMDVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x0C << 24) | (0x03 << 16), 0x3f3f0000); /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (CLKVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x0F << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x0F << 24) | (0x03 << 16), 0x3f3f0000); /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (DQSVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x08 << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x08 << 24) | (0x03 << 16), 0x3f3f0000); /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (CTLVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x0C << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + CTLVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x0C << 24) | (0x03 << 16), 0x3f3f0000); /* DQS Swapped Input Enable */ mrc_alt_write_mask(DDRPHY, - (COMPEN1CH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT19 | BIT17), - (BIT31 | BIT30 | BIT19 | BIT17 | - BIT15 | BIT14)); + COMPEN1CH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 19) | (1 << 17), 0xc00ac000); /* ODT VREF = 1.5 x 274/360+274 = 0.65V (code of ~50) */ /* ODT Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (DQVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x32 << 8) | (0x03 << 0)), - (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + DQVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x32 << 8) | (0x03 << 0), 0x00003f3f); /* ODT Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (DQSVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x32 << 8) | (0x03 << 0)), - (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x32 << 8) | (0x03 << 0), 0x00003f3f); /* ODT Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (CLKVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x0E << 8) | (0x05 << 0)), - (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x0E << 8) | (0x05 << 0), 0x00003f3f); /* * Slew rate settings are frequency specific, @@ -685,273 +614,227 @@ void ddrphy_init(struct mrc_params *mrc_params) * - DQ/DQS/DM/CLK SR: 4V/ns, * - CTRL/CMD SR: 1.5V/ns */ - temp = (0x0E << 16) | (0x0E << 12) | (0x08 << 8) | - (0x0B << 4) | (0x0B << 0); + temp = (0x0e << 16) | (0x0e << 12) | (0x08 << 8) | + (0x0b << 4) | (0x0b << 0); /* DCOMP Delay Select: CTL,CMD,CLK,DQS,DQ */ mrc_alt_write_mask(DDRPHY, - (DLYSELCH0 + (ch * DDRCOMP_CH_OFFSET)), - temp, - (BIT19 | BIT18 | BIT17 | BIT16 | BIT15 | - BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | - BIT3 | BIT2 | BIT1 | BIT0)); + DLYSELCH0 + ch * DDRCOMP_CH_OFFSET, + temp, 0x000fffff); /* TCO Vref CLK,DQS,DQ */ mrc_alt_write_mask(DDRPHY, - (TCOVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x05 << 16) | (0x05 << 8) | (0x05 << 0)), - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8 | BIT5 | BIT4 | BIT3 | BIT2 | - BIT1 | BIT0)); + TCOVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x05 << 16) | (0x05 << 8) | (0x05 << 0), + 0x003f3f3f); /* ODTCOMP CMD/CTL PU/PD */ mrc_alt_write_mask(DDRPHY, - (CCBUFODTCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x03 << 8) | (0x03 << 0)), - (BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + CCBUFODTCH0 + ch * DDRCOMP_CH_OFFSET, + (0x03 << 8) | (0x03 << 0), + 0x00001f1f); /* COMP */ mrc_alt_write_mask(DDRPHY, - (COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)), - 0, (BIT31 | BIT30 | BIT8)); + COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, + 0, 0xc0000100); #ifdef BACKUP_COMPS /* DQ COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x10 << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x10 << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x10 << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x10 << 16), + 0x801f0000); /* ODTCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* ODTCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* DQS COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x10 << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x10 << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x10 << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x10 << 16), + 0x801f0000); /* ODTCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* ODTCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* CLK COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0C << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0c << 16), + 0x801f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0C << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0c << 16), + 0x801f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x07 << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x07 << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x07 << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x07 << 16), + 0x801f0000); /* ODTCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* ODTCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* CMD COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CMDDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0D << 16)), - (BIT31 | BIT21 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CMDDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0d << 16), + 0x803f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CMDDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0D << 16)), - (BIT31 | BIT21 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CMDDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0d << 16), + 0x803f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CMDDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CMDDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CMDDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CMDDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* CTL COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CTLDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0D << 16)), - (BIT31 | BIT21 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CTLDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0d << 16), + 0x803f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CTLDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0D << 16)), - (BIT31 | BIT21 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CTLDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0d << 16), + 0x803f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CTLDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CTLDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CTLDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CTLDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); #else /* DQ TCOCOMP Overrides */ /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* DQS TCOCOMP Overrides */ /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* CLK TCOCOMP Overrides */ /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); #endif /* program STATIC delays */ @@ -962,7 +845,7 @@ void ddrphy_init(struct mrc_params *mrc_params) #endif for (rk = 0; rk < NUM_RANKS; rk++) { - if (mrc_params->rank_enables & (1<<rk)) { + if (mrc_params->rank_enables & (1 << rk)) { set_wclk(ch, rk, ddr_wclk[PLATFORM_ID]); #ifdef BACKUP_WCTL set_wctl(ch, rk, ddr_wctl[PLATFORM_ID]); @@ -976,86 +859,80 @@ void ddrphy_init(struct mrc_params *mrc_params) /* COMP (non channel specific) */ /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANADRVPDCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CMDANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CMDANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CMDANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CMDANADRVPDCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANADRVPDCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANADRVPDCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CTLANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CTLANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CTLANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CTLANADRVPDCTL, 1 << 30, 1 << 30); /* ODT: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQANAODTPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANAODTPUCTL, 1 << 30, 1 << 30); /* ODT: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQANAODTPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANAODTPDCTL, 1 << 30, 1 << 30); /* ODT: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANAODTPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANAODTPUCTL, 1 << 30, 1 << 30); /* ODT: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANAODTPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANAODTPDCTL, 1 << 30, 1 << 30); /* ODT: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANAODTPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANAODTPUCTL, 1 << 30, 1 << 30); /* ODT: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANAODTPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANAODTPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANADLYPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CMDANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CMDANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CMDANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CMDANADLYPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANADLYPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANADLYPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CTLANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CTLANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CTLANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CTLANADLYPDCTL, 1 << 30, 1 << 30); /* TCO: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQANATCOPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANATCOPUCTL, 1 << 30, 1 << 30); /* TCO: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQANATCOPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANATCOPDCTL, 1 << 30, 1 << 30); /* TCO: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANATCOPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANATCOPUCTL, 1 << 30, 1 << 30); /* TCO: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANATCOPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANATCOPDCTL, 1 << 30, 1 << 30); /* TCO: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANATCOPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANATCOPUCTL, 1 << 30, 1 << 30); /* TCO: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANATCOPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANATCOPDCTL, 1 << 30, 1 << 30); /* TCOCOMP: Pulse Count */ - mrc_alt_write_mask(DDRPHY, (TCOCNTCTRL), (0x1 << 0), (BIT1 | BIT0)); + mrc_alt_write_mask(DDRPHY, TCOCNTCTRL, 1, 3); /* ODT: CMD/CTL PD/PU */ - mrc_alt_write_mask(DDRPHY, - (CHNLBUFSTATIC), ((0x03 << 24) | (0x03 << 16)), - (BIT28 | BIT27 | BIT26 | BIT25 | BIT24 | - BIT20 | BIT19 | BIT18 | BIT17 | BIT16)); + mrc_alt_write_mask(DDRPHY, CHNLBUFSTATIC, + (0x03 << 24) | (0x03 << 16), 0x1f1f0000); /* Set 1us counter */ - mrc_alt_write_mask(DDRPHY, - (MSCNTR), (0x64 << 0), - (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); - mrc_alt_write_mask(DDRPHY, - (LATCH1CTL), (0x1 << 28), - (BIT30 | BIT29 | BIT28)); + mrc_alt_write_mask(DDRPHY, MSCNTR, 0x64, 0xff); + mrc_alt_write_mask(DDRPHY, LATCH1CTL, 0x1 << 28, 0x70000000); /* Release PHY from reset */ - mrc_alt_write_mask(DDRPHY, MASTERRSTN, BIT0, BIT0); + mrc_alt_write_mask(DDRPHY, MASTERRSTN, 1, 1); /* STEP1 */ mrc_post_code(0x03, 0x11); @@ -1064,30 +941,30 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* DQ01-DQ23 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { mrc_alt_write_mask(DDRPHY, - (DQMDLLCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT13), - (BIT13)); /* Enable VREG */ + DQMDLLCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 13, + 1 << 13); /* Enable VREG */ delay_n(3); } /* ECC */ - mrc_alt_write_mask(DDRPHY, (ECCMDLLCTL), - (BIT13), (BIT13)); /* Enable VREG */ + mrc_alt_write_mask(DDRPHY, ECCMDLLCTL, + 1 << 13, 1 << 13); /* Enable VREG */ delay_n(3); /* CMD */ mrc_alt_write_mask(DDRPHY, - (CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - (BIT13), (BIT13)); /* Enable VREG */ + CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + 1 << 13, 1 << 13); /* Enable VREG */ delay_n(3); /* CLK-CTL */ mrc_alt_write_mask(DDRPHY, - (CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - (BIT13), (BIT13)); /* Enable VREG */ + CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + 1 << 13, 1 << 13); /* Enable VREG */ delay_n(3); } } @@ -1100,30 +977,30 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* DQ01-DQ23 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { mrc_alt_write_mask(DDRPHY, - (DQMDLLCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT17), - (BIT17)); /* Enable MCDLL */ + DQMDLLCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 17, + 1 << 17); /* Enable MCDLL */ delay_n(50); } /* ECC */ - mrc_alt_write_mask(DDRPHY, (ECCMDLLCTL), - (BIT17), (BIT17)); /* Enable MCDLL */ + mrc_alt_write_mask(DDRPHY, ECCMDLLCTL, + 1 << 17, 1 << 17); /* Enable MCDLL */ delay_n(50); /* CMD */ mrc_alt_write_mask(DDRPHY, - (CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - (BIT18), (BIT18)); /* Enable MCDLL */ + CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + 1 << 18, 1 << 18); /* Enable MCDLL */ delay_n(50); /* CLK-CTL */ mrc_alt_write_mask(DDRPHY, - (CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - (BIT18), (BIT18)); /* Enable MCDLL */ + CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + 1 << 18, 1 << 18); /* Enable MCDLL */ delay_n(50); } } @@ -1136,54 +1013,47 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* DQ01-DQ23 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { #ifdef FORCE_16BIT_DDRIO - temp = ((bl_grp) && + temp = (bl_grp && (mrc_params->channel_width == X16)) ? - ((0x1 << 12) | (0x1 << 8) | - (0xF << 4) | (0xF << 0)) : - ((0xF << 12) | (0xF << 8) | - (0xF << 4) | (0xF << 0)); + 0x11ff : 0xffff; #else - temp = ((0xF << 12) | (0xF << 8) | - (0xF << 4) | (0xF << 0)); + temp = 0xffff; #endif /* Enable TXDLL */ mrc_alt_write_mask(DDRPHY, - (DQDLLTXCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, 0xFFFF); + DQDLLTXCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0xffff); delay_n(3); /* Enable RXDLL */ mrc_alt_write_mask(DDRPHY, - (DQDLLRXCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT3 | BIT2 | BIT1 | BIT0), - (BIT3 | BIT2 | BIT1 | BIT0)); + DQDLLRXCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0xf, 0xf); delay_n(3); /* Enable RXDLL Overrides BL0 */ mrc_alt_write_mask(DDRPHY, - (B0OVRCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT3 | BIT2 | BIT1 | BIT0), - (BIT3 | BIT2 | BIT1 | BIT0)); + B0OVRCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0xf, 0xf); } /* ECC */ - temp = ((0xF << 12) | (0xF << 8) | - (0xF << 4) | (0xF << 0)); - mrc_alt_write_mask(DDRPHY, (ECCDLLTXCTL), - temp, 0xFFFF); + temp = 0xffff; + mrc_alt_write_mask(DDRPHY, ECCDLLTXCTL, + temp, 0xffff); delay_n(3); /* CMD (PO) */ mrc_alt_write_mask(DDRPHY, - (CMDDLLTXCTL + (ch * DDRIOCCC_CH_OFFSET)), - temp, 0xFFFF); + CMDDLLTXCTL + ch * DDRIOCCC_CH_OFFSET, + temp, 0xffff); delay_n(3); } } @@ -1195,94 +1065,85 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* Host To Memory Clock Alignment (HMC) for 800/1066 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { /* CLK_ALIGN_MOD_ID */ mrc_alt_write_mask(DDRPHY, - (DQCLKALIGNREG2 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (bl_grp) ? (0x3) : (0x1), - (BIT3 | BIT2 | BIT1 | BIT0)); + DQCLKALIGNREG2 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + bl_grp ? 3 : 1, + 0xf); } mrc_alt_write_mask(DDRPHY, - (ECCCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)), - 0x2, - (BIT3 | BIT2 | BIT1 | BIT0)); + ECCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, + 0x2, 0xf); mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)), - 0x0, - (BIT3 | BIT2 | BIT1 | BIT0)); + CMDCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, + 0x0, 0xf); mrc_alt_write_mask(DDRPHY, - (CCCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)), - 0x2, - (BIT3 | BIT2 | BIT1 | BIT0)); + CCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, + 0x2, 0xf); mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET)), - (0x2 << 4), (BIT5 | BIT4)); + CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET, + 0x20, 0x30); /* * NUM_SAMPLES, MAX_SAMPLES, * MACRO_PI_STEP, MICRO_PI_STEP */ mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG1 + (ch * DDRIOCCC_CH_OFFSET)), - ((0x18 << 16) | (0x10 << 8) | - (0x8 << 2) | (0x1 << 0)), - (BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | - BIT2 | BIT1 | BIT0)); + CMDCLKALIGNREG1 + ch * DDRIOCCC_CH_OFFSET, + (0x18 << 16) | (0x10 << 8) | + (0x8 << 2) | (0x1 << 0), + 0x007f7fff); /* TOTAL_NUM_MODULES, FIRST_U_PARTITION */ mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG2 + (ch * DDRIOCCC_CH_OFFSET)), - ((0x10 << 16) | (0x4 << 8) | (0x2 << 4)), - (BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | - BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | - BIT5 | BIT4)); + CMDCLKALIGNREG2 + ch * DDRIOCCC_CH_OFFSET, + (0x10 << 16) | (0x4 << 8) | (0x2 << 4), + 0x001f0ff0); #ifdef HMC_TEST /* START_CLK_ALIGN=1 */ mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET)), - BIT24, BIT24); + CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET, + 1 << 24, 1 << 24); while (msg_port_alt_read(DDRPHY, - (CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET))) & - BIT24) + CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET) & + (1 << 24)) ; /* wait for START_CLK_ALIGN=0 */ #endif /* Set RD/WR Pointer Seperation & COUNTEN & FIFOPTREN */ mrc_alt_write_mask(DDRPHY, - (CMDPTRREG + (ch * DDRIOCCC_CH_OFFSET)), - BIT0, BIT0); /* WRPTRENABLE=1 */ + CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, + 1, 1); /* WRPTRENABLE=1 */ /* COMP initial */ /* enable bypass for CLK buffer (PO) */ mrc_alt_write_mask(DDRPHY, - (COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)), - BIT5, BIT5); + COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 5, 1 << 5); /* Initial COMP Enable */ - mrc_alt_write_mask(DDRPHY, (CMPCTRL), - (BIT0), (BIT0)); + mrc_alt_write_mask(DDRPHY, CMPCTRL, 1, 1); /* wait for Initial COMP Enable = 0 */ - while (msg_port_alt_read(DDRPHY, (CMPCTRL)) & BIT0) + while (msg_port_alt_read(DDRPHY, CMPCTRL) & 1) ; /* disable bypass for CLK buffer (PO) */ mrc_alt_write_mask(DDRPHY, - (COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)), - ~BIT5, BIT5); + COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, + ~(1 << 5), 1 << 5); /* IOBUFACT */ /* STEP4a */ mrc_alt_write_mask(DDRPHY, - (CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)), - BIT2, BIT2); /* IOBUFACTRST_N=1 */ + CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, + 1 << 2, 1 << 2); /* IOBUFACTRST_N=1 */ /* DDRPHY initialization complete */ mrc_alt_write_mask(DDRPHY, - (CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)), - BIT20, BIT20); /* SPID_INIT_COMPLETE=1 */ + CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, + 1 << 20, 1 << 20); /* SPID_INIT_COMPLETE=1 */ } } @@ -1308,13 +1169,13 @@ void perform_jedec_init(struct mrc_params *mrc_params) mrc_post_code(0x04, 0x00); /* DDR3_RESET_SET=0, DDR3_RESET_RESET=1 */ - mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, BIT1, (BIT8 | BIT1)); + mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, 2, 0x102); /* Assert RESET# for 200us */ delay_u(200); /* DDR3_RESET_SET=1, DDR3_RESET_RESET=0 */ - mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, BIT8, (BIT8 | BIT1)); + mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, 0x100, 0x102); dtr0 = msg_port_read(MEM_CTLR, DTR0); @@ -1327,8 +1188,8 @@ void perform_jedec_init(struct mrc_params *mrc_params) drp &= 0x3; drmc = msg_port_read(MEM_CTLR, DRMC); - drmc &= 0xFFFFFFFC; - drmc |= (BIT4 | drp); + drmc &= 0xfffffffc; + drmc |= (DRMC_CKEMODE | drp); msg_port_write(MEM_CTLR, DRMC, drmc); @@ -1341,7 +1202,7 @@ void perform_jedec_init(struct mrc_params *mrc_params) } msg_port_write(MEM_CTLR, DRMC, - (mrc_params->rd_odt_value == 0 ? BIT12 : 0)); + (mrc_params->rd_odt_value == 0 ? DRMC_ODTMODE : 0)); /* * setup for emrs 2 @@ -1392,12 +1253,12 @@ void perform_jedec_init(struct mrc_params *mrc_params) * 1** --> RESERVED */ emrs1_cmd |= (1 << 3); - emrs1_cmd &= ~BIT6; + emrs1_cmd &= ~(1 << 6); if (mrc_params->ron_value == 0) - emrs1_cmd |= BIT7; + emrs1_cmd |= (1 << 7); else - emrs1_cmd &= ~BIT7; + emrs1_cmd &= ~(1 << 7); if (mrc_params->rtt_nom_value == 0) emrs1_cmd |= (DDR3_EMRS1_RTTNOM_40 << 6); @@ -1432,8 +1293,8 @@ void perform_jedec_init(struct mrc_params *mrc_params) * BIT[02:02] "0" if oem_tCAS <= 11 (1866?) * BIT[06:04] use oem_tCAS-4 */ - mrs0_cmd |= BIT14; - mrs0_cmd |= BIT18; + mrs0_cmd |= (1 << 14); + mrs0_cmd |= (1 << 18); mrs0_cmd |= ((((dtr0 >> 12) & 7) + 1) << 10); tck = t_ck[mrc_params->ddr_speed]; @@ -1480,8 +1341,8 @@ void set_ddr_init_complete(struct mrc_params *mrc_params) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco &= ~BIT28; - dco |= BIT31; + dco &= ~DCO_PMICTL; + dco |= DCO_IC; msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); @@ -1577,7 +1438,7 @@ void rcvn_cal(struct mrc_params *mrc_params) /* need separate burst to sample DQS preamble */ dtr1 = msg_port_read(MEM_CTLR, DTR1); dtr1_save = dtr1; - dtr1 |= BIT12; + dtr1 |= DTR1_TCCD_12CLK; msg_port_write(MEM_CTLR, DTR1, dtr1); #endif @@ -1596,7 +1457,7 @@ void rcvn_cal(struct mrc_params *mrc_params) * POST_CODE here indicates the current * channel and rank being calibrated */ - mrc_post_code(0x05, (0x10 + ((ch << 4) | rk))); + mrc_post_code(0x05, 0x10 + ((ch << 4) | rk)); #ifdef BACKUP_RCVN /* et hard-coded timing values */ @@ -1606,10 +1467,10 @@ void rcvn_cal(struct mrc_params *mrc_params) /* enable FIFORST */ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl += 2) { mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - ((bl >> 1) * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - 0, BIT8); + B01PTRCTL1 + + (bl >> 1) * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 1 << 8); } /* initialize the starting delay to 128 PI (cas +1 CLK) */ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { @@ -1638,11 +1499,11 @@ void rcvn_cal(struct mrc_params *mrc_params) } else { /* not enough delay */ training_message(ch, rk, bl); - mrc_post_code(0xEE, 0x50); + mrc_post_code(0xee, 0x50); } } } - } while (temp & 0xFF); + } while (temp & 0xff); #ifdef R2R_SHARING /* increment "num_ranks_enabled" */ @@ -1653,7 +1514,7 @@ void rcvn_cal(struct mrc_params *mrc_params) /* add "delay[]" values to "final_delay[][]" for rolling average */ final_delay[ch][bl] += delay[bl]; /* set timing based on rolling average values */ - set_rcvn(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled)); + set_rcvn(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); } #else /* Finally increment delay by 32 PI (1/4 CLK) to place in center of preamble */ @@ -1666,10 +1527,10 @@ void rcvn_cal(struct mrc_params *mrc_params) /* disable FIFORST */ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl += 2) { mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - ((bl >> 1) * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - BIT8, BIT8); + B01PTRCTL1 + + (bl >> 1) * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 8, 1 << 8); } #endif } @@ -1742,12 +1603,12 @@ void wr_level(struct mrc_params *mrc_params) * POST_CODE here indicates the current * rank and channel being calibrated */ - mrc_post_code(0x06, (0x10 + ((ch << 4) | rk))); + mrc_post_code(0x06, 0x10 + ((ch << 4) | rk)); #ifdef BACKUP_WDQS for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { set_wdqs(ch, rk, bl, ddr_wdqs[PLATFORM_ID]); - set_wdq(ch, rk, bl, (ddr_wdqs[PLATFORM_ID] - QRTR_CLK)); + set_wdq(ch, rk, bl, ddr_wdqs[PLATFORM_ID] - QRTR_CLK); } #else /* @@ -1760,7 +1621,7 @@ void wr_level(struct mrc_params *mrc_params) * enable Write Levelling Mode * (EMRS1 w/ Write Levelling Mode Enable) */ - dram_init_command(DCMD_MRS1(rk, 0x0082)); + dram_init_command(DCMD_MRS1(rk, 0x82)); /* * set ODT DRAM Full Time Termination @@ -1769,24 +1630,24 @@ void wr_level(struct mrc_params *mrc_params) dtr4 = msg_port_read(MEM_CTLR, DTR4); dtr4_save = dtr4; - dtr4 |= BIT15; + dtr4 |= DTR4_ODTDIS; msg_port_write(MEM_CTLR, DTR4, dtr4); - for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) { + for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) { /* * Enable Sandy Bridge Mode (WDQ Tri-State) & * Ensure 5 WDQS pulses during Write Leveling */ mrc_alt_write_mask(DDRPHY, - DQCTL + (DDRIODQ_BL_OFFSET * bl) + (DDRIODQ_CH_OFFSET * ch), - (BIT28 | BIT8 | BIT6 | BIT4 | BIT2), - (BIT28 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2)); + DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, + 0x10000154, + 0x100003fc); } /* Write Leveling Mode enabled in IO */ mrc_alt_write_mask(DDRPHY, - CCDDR3RESETCTL + (DDRIOCCC_CH_OFFSET * ch), - BIT16, BIT16); + CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch, + 1 << 16, 1 << 16); /* Initialize the starting delay to WCLK */ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { @@ -1804,15 +1665,15 @@ void wr_level(struct mrc_params *mrc_params) /* disable Write Levelling Mode */ mrc_alt_write_mask(DDRPHY, - CCDDR3RESETCTL + (DDRIOCCC_CH_OFFSET * ch), - 0, BIT16); + CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch, + 0, 1 << 16); - for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) { + for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) { /* Disable Sandy Bridge Mode & Ensure 4 WDQS pulses during normal operation */ mrc_alt_write_mask(DDRPHY, - DQCTL + (DDRIODQ_BL_OFFSET * bl) + (DDRIODQ_CH_OFFSET * ch), - (BIT8 | BIT6 | BIT4 | BIT2), - (BIT28 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2)); + DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, + 0x00000154, + 0x100003fc); } /* restore original DTR4 */ @@ -1830,7 +1691,7 @@ void wr_level(struct mrc_params *mrc_params) */ dram_init_command(DCMD_PREA(rk)); - mrc_post_code(0x06, (0x30 + ((ch << 4) | rk))); + mrc_post_code(0x06, 0x30 + ((ch << 4) | rk)); /* * COARSE WRITE LEVEL: @@ -1863,13 +1724,13 @@ void wr_level(struct mrc_params *mrc_params) coarse_result = check_rw_coarse(mrc_params, address); /* check for failures and margin the byte lane back 128 PI (1 CLK) */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (coarse_result & (coarse_result_mask << bl)) { all_edges_found = false; delay[bl] -= FULL_CLK; set_wdqs(ch, rk, bl, delay[bl]); /* program WDQ timings based on WDQS (WDQ = WDQS - 32 PI) */ - set_wdq(ch, rk, bl, (delay[bl] - QRTR_CLK)); + set_wdq(ch, rk, bl, delay[bl] - QRTR_CLK); } } } while (!all_edges_found); @@ -1878,11 +1739,11 @@ void wr_level(struct mrc_params *mrc_params) /* increment "num_ranks_enabled" */ num_ranks_enabled++; /* accumulate "final_delay[][]" values from "delay[]" values for rolling average */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { final_delay[ch][bl] += delay[bl]; - set_wdqs(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled)); + set_wdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); /* program WDQ timings based on WDQS (WDQ = WDQS - 32 PI) */ - set_wdq(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled) - QRTR_CLK); + set_wdq(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled - QRTR_CLK); } #endif #endif @@ -1901,9 +1762,9 @@ void prog_page_ctrl(struct mrc_params *mrc_params) ENTERFN(); dpmc0 = msg_port_read(MEM_CTLR, DPMC0); - dpmc0 &= ~(BIT16 | BIT17 | BIT18); + dpmc0 &= ~DPMC0_PCLSTO_MASK; dpmc0 |= (4 << 16); - dpmc0 |= BIT21; + dpmc0 |= DPMC0_PREAPWDEN; msg_port_write(MEM_CTLR, DPMC0, dpmc0); } @@ -1966,7 +1827,7 @@ void rd_train(struct mrc_params *mrc_params) for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { set_rdqs(ch, rk, bl, ddr_rdqs[PLATFORM_ID]); } @@ -1981,7 +1842,7 @@ void rd_train(struct mrc_params *mrc_params) for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { /* x_coordinate */ x_coordinate[L][B][ch][rk][bl] = RDQS_MIN; @@ -2011,7 +1872,7 @@ void rd_train(struct mrc_params *mrc_params) /* look for passing coordinates */ for (side_y = B; side_y <= T; side_y++) { for (side_x = L; side_x <= R; side_x++) { - mrc_post_code(0x07, (0x10 + (side_y * 2) + (side_x))); + mrc_post_code(0x07, 0x10 + side_y * 2 + side_x); /* find passing values */ for (ch = 0; ch < NUM_CHANNELS; ch++) { @@ -2021,7 +1882,7 @@ void rd_train(struct mrc_params *mrc_params) (0x1 << rk)) { /* set x/y_coordinate search starting settings */ for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { set_rdqs(ch, rk, bl, x_coordinate[side_x][side_y][ch][rk][bl]); @@ -2041,9 +1902,9 @@ void rd_train(struct mrc_params *mrc_params) result = check_bls_ex(mrc_params, address); /* check for failures */ - if (result & 0xFF) { + if (result & 0xff) { /* at least 1 byte lane failed */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (result & (bl_mask << bl)) { /* adjust the RDQS values accordingly */ @@ -2072,13 +1933,13 @@ void rd_train(struct mrc_params *mrc_params) (y_coordinate[side_x][B][ch][bl] == y_coordinate[side_x][T][ch][bl])) { /* VREF_EYE collapsed below MIN_VREF_EYE */ training_message(ch, rk, bl); - mrc_post_code(0xEE, (0x70 + (side_y * 2) + (side_x))); + mrc_post_code(0xEE, 0x70 + side_y * 2 + side_x); } else { /* update the VREF setting */ set_vref(ch, bl, y_coordinate[side_x][side_y][ch][bl]); /* reset the X coordinate to begin the search at the new VREF */ x_coordinate[side_x][side_y][ch][rk][bl] = - (side_x == L) ? (RDQS_MIN) : (RDQS_MAX); + (side_x == L) ? RDQS_MIN : RDQS_MAX; } } @@ -2087,7 +1948,7 @@ void rd_train(struct mrc_params *mrc_params) } } } - } while (result & 0xFF); + } while (result & 0xff); } } } @@ -2147,23 +2008,23 @@ void rd_train(struct mrc_params *mrc_params) /* perform an eye check */ for (side_y = B; side_y <= T; side_y++) { for (side_x = L; side_x <= R; side_x++) { - mrc_post_code(0x07, (0x30 + (side_y * 2) + (side_x))); + mrc_post_code(0x07, 0x30 + side_y * 2 + side_x); /* update the settings for the eye check */ for (ch = 0; ch < NUM_CHANNELS; ch++) { if (mrc_params->channel_enables & (1 << ch)) { for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (side_x == L) - set_rdqs(ch, rk, bl, (x_center[ch][rk][bl] - (MIN_RDQS_EYE / 2))); + set_rdqs(ch, rk, bl, x_center[ch][rk][bl] - (MIN_RDQS_EYE / 2)); else - set_rdqs(ch, rk, bl, (x_center[ch][rk][bl] + (MIN_RDQS_EYE / 2))); + set_rdqs(ch, rk, bl, x_center[ch][rk][bl] + (MIN_RDQS_EYE / 2)); if (side_y == B) - set_vref(ch, bl, (y_center[ch][bl] - (MIN_VREF_EYE / 2))); + set_vref(ch, bl, y_center[ch][bl] - (MIN_VREF_EYE / 2)); else - set_vref(ch, bl, (y_center[ch][bl] + (MIN_VREF_EYE / 2))); + set_vref(ch, bl, y_center[ch][bl] + (MIN_VREF_EYE / 2)); } } } @@ -2174,9 +2035,9 @@ void rd_train(struct mrc_params *mrc_params) mrc_params->hte_setup = 1; /* check the eye */ - if (check_bls_ex(mrc_params, address) & 0xFF) { + if (check_bls_ex(mrc_params, address) & 0xff) { /* one or more byte lanes failed */ - mrc_post_code(0xEE, (0x74 + (side_x * 2) + (side_y))); + mrc_post_code(0xee, 0x74 + side_x * 2 + side_y); } } } @@ -2197,7 +2058,7 @@ void rd_train(struct mrc_params *mrc_params) /* x_coordinate */ #ifdef R2R_SHARING final_delay[ch][bl] += x_center[ch][rk][bl]; - set_rdqs(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled)); + set_rdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); #else set_rdqs(ch, rk, bl, x_center[ch][rk][bl]); #endif @@ -2258,7 +2119,7 @@ void wr_train(struct mrc_params *mrc_params) for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { set_wdq(ch, rk, bl, ddr_wdq[PLATFORM_ID]); } @@ -2273,7 +2134,7 @@ void wr_train(struct mrc_params *mrc_params) for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { /* * want to start with @@ -2303,7 +2164,7 @@ void wr_train(struct mrc_params *mrc_params) * until no failures are observed, then repeat for the RIGHT side. */ for (side = L; side <= R; side++) { - mrc_post_code(0x08, (0x10 + (side))); + mrc_post_code(0x08, 0x10 + side); /* set starting values */ for (ch = 0; ch < NUM_CHANNELS; ch++) { @@ -2312,7 +2173,7 @@ void wr_train(struct mrc_params *mrc_params) if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { set_wdq(ch, rk, bl, delay[side][ch][rk][bl]); } @@ -2338,9 +2199,9 @@ void wr_train(struct mrc_params *mrc_params) /* result[07:00] == failing byte lane (MAX 8) */ result = check_bls_ex(mrc_params, address); /* check for failures */ - if (result & 0xFF) { + if (result & 0xff) { /* at least 1 byte lane failed */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (result & (bl_mask << bl)) { if (side == L) @@ -2362,13 +2223,13 @@ void wr_train(struct mrc_params *mrc_params) * notify the user and halt */ training_message(ch, rk, bl); - mrc_post_code(0xEE, (0x80 + side)); + mrc_post_code(0xee, 0x80 + side); } } } } /* stop when all byte lanes pass */ - } while (result & 0xFF); + } while (result & 0xff); } } } @@ -2384,7 +2245,7 @@ void wr_train(struct mrc_params *mrc_params) /* increment "num_ranks_enabled" */ num_ranks_enabled++; #endif - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { DPF(D_INFO, "WDQ eye rank%d lane%d : %d-%d\n", rk, bl, @@ -2396,7 +2257,7 @@ void wr_train(struct mrc_params *mrc_params) #ifdef R2R_SHARING final_delay[ch][bl] += temp; set_wdq(ch, rk, bl, - ((final_delay[ch][bl]) / num_ranks_enabled)); + final_delay[ch][bl] / num_ranks_enabled); #else set_wdq(ch, rk, bl, temp); #endif @@ -2470,7 +2331,7 @@ void enable_scrambling(struct mrc_params *mrc_params) * get seed from system clock * and make sure it is not all 1's */ - lfsr = rdtsc() & 0x0FFFFFFF; + lfsr = rdtsc() & 0x0fffffff; } else { /* * Need to replace scrambler @@ -2491,10 +2352,10 @@ void enable_scrambling(struct mrc_params *mrc_params) * In cold boot, we have the last 32bit LFSR which is the new seed. */ lfsr32(&lfsr); /* shift to next value */ - msg_port_write(MEM_CTLR, SCRMSEED, (lfsr & 0x0003FFFF)); + msg_port_write(MEM_CTLR, SCRMSEED, (lfsr & 0x0003ffff)); for (i = 0; i < 2; i++) - msg_port_write(MEM_CTLR, SCRMLO + i, (lfsr & 0xAAAAAAAA)); + msg_port_write(MEM_CTLR, SCRMLO + i, (lfsr & 0xaaaaaaaa)); LEAVEFN(); } @@ -2511,20 +2372,20 @@ void prog_ddr_control(struct mrc_params *mrc_params) ENTERFN(); dsch = msg_port_read(MEM_CTLR, DSCH); - dsch &= ~(BIT8 | BIT9 | BIT12); + dsch &= ~(DSCH_OOODIS | DSCH_OOOST3DIS | DSCH_NEWBYPDIS); msg_port_write(MEM_CTLR, DSCH, dsch); dpmc0 = msg_port_read(MEM_CTLR, DPMC0); - dpmc0 &= ~BIT25; + dpmc0 &= ~DPMC0_DISPWRDN; dpmc0 |= (mrc_params->power_down_disable << 25); - dpmc0 &= ~BIT24; - dpmc0 &= ~(BIT16 | BIT17 | BIT18); + dpmc0 &= ~DPMC0_CLKGTDIS; + dpmc0 &= ~DPMC0_PCLSTO_MASK; dpmc0 |= (4 << 16); - dpmc0 |= BIT21; + dpmc0 |= DPMC0_PREAPWDEN; msg_port_write(MEM_CTLR, DPMC0, dpmc0); /* CMDTRIST = 2h - CMD/ADDR are tristated when no valid command */ - mrc_write_mask(MEM_CTLR, DPMC1, 2 << 4, BIT4 | BIT5); + mrc_write_mask(MEM_CTLR, DPMC1, 0x20, 0x30); LEAVEFN(); } @@ -2542,14 +2403,14 @@ void prog_dra_drb(struct mrc_params *mrc_params) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco &= ~BIT31; + dco &= ~DCO_IC; msg_port_write(MEM_CTLR, DCO, dco); drp = 0; if (mrc_params->rank_enables & 1) - drp |= BIT0; + drp |= DRP_RKEN0; if (mrc_params->rank_enables & 2) - drp |= BIT1; + drp |= DRP_RKEN1; if (mrc_params->dram_width == X16) { drp |= (1 << 4); drp |= (1 << 9); @@ -2570,8 +2431,8 @@ void prog_dra_drb(struct mrc_params *mrc_params) msg_port_write(MEM_CTLR, DRP, drp); - dco &= ~BIT28; - dco |= BIT31; + dco &= ~DCO_PMICTL; + dco |= DCO_IC; msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); @@ -2600,18 +2461,18 @@ void change_refresh_period(struct mrc_params *mrc_params) ENTERFN(); drfc = msg_port_read(MEM_CTLR, DRFC); - drfc &= ~(BIT12 | BIT13 | BIT14); + drfc &= ~DRFC_TREFI_MASK; drfc |= (mrc_params->refresh_rate << 12); - drfc |= BIT21; + drfc |= DRFC_REFDBTCLR; msg_port_write(MEM_CTLR, DRFC, drfc); dcal = msg_port_read(MEM_CTLR, DCAL); - dcal &= ~(BIT8 | BIT9 | BIT10); + dcal &= ~DCAL_ZQCINT_MASK; dcal |= (3 << 8); /* 63ms */ msg_port_write(MEM_CTLR, DCAL, dcal); dpmc0 = msg_port_read(MEM_CTLR, DPMC0); - dpmc0 |= (BIT23 | BIT29); + dpmc0 |= (DPMC0_DYNSREN | DPMC0_ENPHYCLKGATE); msg_port_write(MEM_CTLR, DPMC0, dpmc0); LEAVEFN(); @@ -2638,36 +2499,32 @@ void set_auto_refresh(struct mrc_params *mrc_params) for (channel = 0; channel < NUM_CHANNELS; channel++) { if (mrc_params->channel_enables & (1 << channel)) { /* Enable Periodic RCOMPS */ - mrc_alt_write_mask(DDRPHY, CMPCTRL, BIT1, BIT1); + mrc_alt_write_mask(DDRPHY, CMPCTRL, 2, 2); /* Enable Dynamic DiffAmp & Set Read ODT Value */ switch (mrc_params->rd_odt_value) { case 0: - temp = 0x3F; /* OFF */ + temp = 0x3f; /* OFF */ break; default: temp = 0x00; /* Auto */ break; } - for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) { + for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) { /* Override: DIFFAMP, ODT */ mrc_alt_write_mask(DDRPHY, - (B0OVRCTL + (bl * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)), - (0x00 << 16) | (temp << 10), - (BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16 | BIT15 | BIT14 | - BIT13 | BIT12 | BIT11 | BIT10)); + B0OVRCTL + bl * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET, + temp << 10, + 0x003ffc00); /* Override: DIFFAMP, ODT */ mrc_alt_write_mask(DDRPHY, - (B1OVRCTL + (bl * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)), - (0x00 << 16) | (temp << 10), - (BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16 | BIT15 | BIT14 | - BIT13 | BIT12 | BIT11 | BIT10)); + B1OVRCTL + bl * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET, + temp << 10, + 0x003ffc00); } /* Issue ZQCS command */ @@ -2702,18 +2559,18 @@ void ecc_enable(struct mrc_params *mrc_params) /* Configuration required in ECC mode */ drp = msg_port_read(MEM_CTLR, DRP); - drp &= ~(BIT14 | BIT15); - drp |= BIT15; - drp |= BIT13; + drp &= ~DRP_ADDRMAP_MASK; + drp |= DRP_ADDRMAP_MAP1; + drp |= DRP_PRI64BSPLITEN; msg_port_write(MEM_CTLR, DRP, drp); /* Disable new request bypass */ dsch = msg_port_read(MEM_CTLR, DSCH); - dsch |= BIT12; + dsch |= DSCH_NEWBYPDIS; msg_port_write(MEM_CTLR, DSCH, dsch); /* Enable ECC */ - ecc_ctrl = (BIT0 | BIT1 | BIT17); + ecc_ctrl = (DECCCTRL_SBEEN | DECCCTRL_DBEEN | DECCCTRL_ENCBGEN); msg_port_write(MEM_CTLR, DECCCTRL, ecc_ctrl); /* Assume 8 bank memory, one bank is gone for ECC */ @@ -2756,8 +2613,8 @@ void lock_registers(struct mrc_params *mrc_params) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco &= ~(BIT28 | BIT29); - dco |= (BIT0 | BIT8); + dco &= ~(DCO_PMICTL | DCO_PMIDIS); + dco |= (DCO_DRPLOCK | DCO_CPGCLOCK); msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); |