diff options
Diffstat (limited to 'arch/x86/cpu/ivybridge/bd82x6x.c')
| -rw-r--r-- | arch/x86/cpu/ivybridge/bd82x6x.c | 256 |
1 files changed, 176 insertions, 80 deletions
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 434dfd6..2b172d4 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -3,12 +3,15 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> #include <dm.h> #include <errno.h> #include <fdtdec.h> #include <malloc.h> +#include <pch.h> +#include <syscon.h> +#include <asm/cpu.h> +#include <asm/io.h> #include <asm/lapic.h> #include <asm/pci.h> #include <asm/arch/bd82x6x.h> @@ -16,106 +19,198 @@ #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h> -void bd82x6x_pci_init(pci_dev_t dev) +#define BIOS_CTRL 0xdc + +static int pch_revision_id = -1; +static int pch_type = -1; + +/** + * pch_silicon_revision() - Read silicon revision ID from the PCH + * + * @dev: PCH device + * @return silicon revision ID + */ +static int pch_silicon_revision(struct udevice *dev) { - u16 reg16; - u8 reg8; - - debug("bd82x6x PCI init.\n"); - /* Enable Bus Master */ - reg16 = x86_pci_read_config16(dev, PCI_COMMAND); - reg16 |= PCI_COMMAND_MASTER; - x86_pci_write_config16(dev, PCI_COMMAND, reg16); - - /* This device has no interrupt */ - x86_pci_write_config8(dev, INTR, 0xff); - - /* disable parity error response and SERR */ - reg16 = x86_pci_read_config16(dev, BCTRL); - reg16 &= ~(1 << 0); - reg16 &= ~(1 << 1); - x86_pci_write_config16(dev, BCTRL, reg16); - - /* Master Latency Count must be set to 0x04! */ - reg8 = x86_pci_read_config8(dev, SMLT); - reg8 &= 0x07; - reg8 |= (0x04 << 3); - x86_pci_write_config8(dev, SMLT, reg8); - - /* Will this improve throughput of bus masters? */ - x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06); - - /* Clear errors in status registers */ - reg16 = x86_pci_read_config16(dev, PSTS); - /* reg16 |= 0xf900; */ - x86_pci_write_config16(dev, PSTS, reg16); - - reg16 = x86_pci_read_config16(dev, SECSTS); - /* reg16 |= 0xf900; */ - x86_pci_write_config16(dev, SECSTS, reg16); + u8 val; + + if (pch_revision_id < 0) { + dm_pci_read_config8(dev, PCI_REVISION_ID, &val); + pch_revision_id = val; + } + + return pch_revision_id; } -static int bd82x6x_probe(struct udevice *dev) +int pch_silicon_type(struct udevice *dev) { - const void *blob = gd->fdt_blob; - struct pci_controller *hose; - struct x86_cpu_priv *cpu; - int sata_node, gma_node; - int ret; + u8 val; - hose = pci_bus_to_hose(0); - lpc_enable(PCH_LPC_DEV); - lpc_init(hose, PCH_LPC_DEV); - sata_node = fdtdec_next_compatible(blob, 0, - COMPAT_INTEL_PANTHERPOINT_AHCI); - if (sata_node < 0) { - debug("%s: Cannot find SATA node\n", __func__); - return -EINVAL; + if (pch_type < 0) { + dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val); + pch_type = val; } - bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node); - bd82x6x_usb_ehci_init(PCH_EHCI1_DEV); - bd82x6x_usb_ehci_init(PCH_EHCI2_DEV); - - cpu = calloc(1, sizeof(*cpu)); - if (!cpu) - return -ENOMEM; - model_206ax_init(cpu); - - gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA); - if (gma_node < 0) { - debug("%s: Cannot find GMA node\n", __func__); - return -EINVAL; + + return pch_type; +} + +/** + * pch_silicon_supported() - Check if a certain revision is supported + * + * @dev: PCH device + * @type: PCH type + * @rev: Minimum required resion + * @return 0 if not supported, 1 if supported + */ +static int pch_silicon_supported(struct udevice *dev, int type, int rev) +{ + int cur_type = pch_silicon_type(dev); + int cur_rev = pch_silicon_revision(dev); + + switch (type) { + case PCH_TYPE_CPT: + /* CougarPoint minimum revision */ + if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) + return 1; + /* PantherPoint any revision */ + if (cur_type == PCH_TYPE_PPT) + return 1; + break; + + case PCH_TYPE_PPT: + /* PantherPoint minimum revision */ + if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) + return 1; + break; + } + + return 0; +} + +#define IOBP_RETRY 1000 +static inline int iobp_poll(void) +{ + unsigned try = IOBP_RETRY; + u32 data; + + while (try--) { + data = readl(RCB_REG(IOBPS)); + if ((data & 1) == 0) + return 1; + udelay(10); } - ret = dm_pci_bus_find_bdf(PCH_VIDEO_DEV, &dev); + + printf("IOBP timeout\n"); + return 0; +} + +void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, + u32 orvalue) +{ + u32 data; + + /* Set the address */ + writel(address, RCB_REG(IOBPIRI)); + + /* READ OPCODE */ + if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) + writel(IOBPS_RW_BX, RCB_REG(IOBPS)); + else + writel(IOBPS_READ_AX, RCB_REG(IOBPS)); + if (!iobp_poll()) + return; + + /* Read IOBP data */ + data = readl(RCB_REG(IOBPD)); + if (!iobp_poll()) + return; + + /* Check for successful transaction */ + if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) { + printf("IOBP read 0x%08x failed\n", address); + return; + } + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + /* WRITE OPCODE */ + if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) + writel(IOBPS_RW_BX, RCB_REG(IOBPS)); + else + writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); + if (!iobp_poll()) + return; + + /* Write IOBP data */ + writel(data, RCB_REG(IOBPD)); + if (!iobp_poll()) + return; +} + +static int bd82x6x_probe(struct udevice *dev) +{ + struct udevice *gma_dev; + int ret; + + if (!(gd->flags & GD_FLG_RELOC)) + return 0; + + /* Cause the SATA device to do its init */ + uclass_first_device(UCLASS_DISK, &dev); + + ret = syscon_get_by_driver_data(X86_SYSCON_GMA, &gma_dev); if (ret) return ret; - ret = gma_func0_init(dev, blob, gma_node); + ret = gma_func0_init(gma_dev); if (ret) return ret; return 0; } -int bd82x6x_init(void) +static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep) { - const void *blob = gd->fdt_blob; - int sata_node; - - sata_node = fdtdec_next_compatible(blob, 0, - COMPAT_INTEL_PANTHERPOINT_AHCI); - if (sata_node < 0) { - debug("%s: Cannot find SATA node\n", __func__); - return -EINVAL; - } + u32 rcba; + + dm_pci_read_config32(dev, PCH_RCBA, &rcba); + /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ + rcba = rcba & 0xffffc000; + *sbasep = rcba + 0x3800; + + return 0; +} + +static enum pch_version bd82x6x_pch_get_version(struct udevice *dev) +{ + return PCHV_9; +} - bd82x6x_pci_init(PCH_DEV); - bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node); - northbridge_enable(PCH_DEV); - northbridge_init(PCH_DEV); +static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect) +{ + uint8_t bios_cntl; + + /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */ + dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl); + if (protect) { + bios_cntl &= ~BIOS_CTRL_BIOSWE; + bios_cntl |= BIT(5); + } else { + bios_cntl |= BIOS_CTRL_BIOSWE; + bios_cntl &= ~BIT(5); + } + dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl); return 0; } +static const struct pch_ops bd82x6x_pch_ops = { + .get_sbase = bd82x6x_pch_get_sbase, + .get_version = bd82x6x_pch_get_version, + .set_spi_protect = bd82x6x_set_spi_protect, +}; + static const struct udevice_id bd82x6x_ids[] = { { .compatible = "intel,bd82x6x" }, { } @@ -126,4 +221,5 @@ U_BOOT_DRIVER(bd82x6x_drv) = { .id = UCLASS_PCH, .of_match = bd82x6x_ids, .probe = bd82x6x_probe, + .ops = &bd82x6x_pch_ops, }; |