diff options
Diffstat (limited to 'arch/powerpc')
59 files changed, 2401 insertions, 388 deletions
diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 31e4416..a307154 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -23,23 +23,12 @@ CROSS_COMPILE ?= ppc_8xx- -STANDALONE_LOAD_ADDR = 0x40000 +CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 LDFLAGS_FINAL += --gc-sections -PLATFORM_RELFLAGS += -mrelocatable -ffunction-sections -fdata-sections +PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ PLATFORM_LDFLAGS += -n -ifdef CONFIG_SYS_LDSCRIPT -# need to strip off double quotes -LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT)) -else ifdef CONFIG_NAND_SPL -LDSCRIPT := $(SRCTREE)/$(CONFIG_BOARDDIR)/u-boot-nand.lds -else -ifneq ($(wildcard $(SRCTREE)/arch/powerpc/cpu/$(CPU)/u-boot.lds),) -LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/$(CPU)/u-boot.lds -endif -endif - # # When cross-compiling on NetBSD, we have to define __PPC__ or else we # will pick up a va_list declaration that is incompatible with the diff --git a/arch/powerpc/cpu/74xx_7xx/config.mk b/arch/powerpc/cpu/74xx_7xx/config.mk index df1f6ac..fb0c715 100644 --- a/arch/powerpc/cpu/74xx_7xx/config.mk +++ b/arch/powerpc/cpu/74xx_7xx/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -mstring diff --git a/arch/powerpc/cpu/mpc512x/config.mk b/arch/powerpc/cpu/mpc512x/config.mk index baf55cc..8fceded 100644 --- a/arch/powerpc/cpu/mpc512x/config.mk +++ b/arch/powerpc/cpu/mpc512x/config.mk @@ -20,7 +20,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \ -ffixed-r2 -msoft-float -mcpu=603e diff --git a/arch/powerpc/cpu/mpc512x/diu.c b/arch/powerpc/cpu/mpc512x/diu.c index c4108af..9dc1e48 100644 --- a/arch/powerpc/cpu/mpc512x/diu.c +++ b/arch/powerpc/cpu/mpc512x/diu.c @@ -51,20 +51,10 @@ void diu_set_pixel_clock(unsigned int pixclock) debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr)); } -int platform_diu_init(unsigned int *xres, unsigned int *yres) +int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) { - unsigned int pixel_format; - -#if defined(CONFIG_VIDEO_XRES) & defined(CONFIG_VIDEO_YRES) - *xres = CONFIG_VIDEO_XRES; - *yres = CONFIG_VIDEO_YRES; -#else - *xres = 1024; - *yres = 768; -#endif - pixel_format = 0x88883316; + unsigned int pixel_format = 0x88883316; debug("mpc5121_diu_init\n"); - - return fsl_diu_init(*xres, pixel_format, 0); + return fsl_diu_init(xres, pixel_format, 0); } diff --git a/arch/powerpc/cpu/mpc5xx/config.mk b/arch/powerpc/cpu/mpc5xx/config.mk index 1c7df00..ab55040 100644 --- a/arch/powerpc/cpu/mpc5xx/config.mk +++ b/arch/powerpc/cpu/mpc5xx/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float diff --git a/arch/powerpc/cpu/mpc5xxx/config.mk b/arch/powerpc/cpu/mpc5xxx/config.mk index 832909f..fb87980 100644 --- a/arch/powerpc/cpu/mpc5xxx/config.mk +++ b/arch/powerpc/cpu/mpc5xxx/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 \ -mstring -mcpu=603e -mmultiple diff --git a/arch/powerpc/cpu/mpc8220/config.mk b/arch/powerpc/cpu/mpc8220/config.mk index 9142b91..2c638b5 100644 --- a/arch/powerpc/cpu/mpc8220/config.mk +++ b/arch/powerpc/cpu/mpc8220/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 \ -mstring -mcpu=603e -mmultiple diff --git a/arch/powerpc/cpu/mpc824x/config.mk b/arch/powerpc/cpu/mpc824x/config.mk index 65a1771..82b8cc6 100644 --- a/arch/powerpc/cpu/mpc824x/config.mk +++ b/arch/powerpc/cpu/mpc824x/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float diff --git a/arch/powerpc/cpu/mpc8260/config.mk b/arch/powerpc/cpu/mpc8260/config.mk index 5e4645a..f091fa9 100644 --- a/arch/powerpc/cpu/mpc8260/config.mk +++ b/arch/powerpc/cpu/mpc8260/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 \ -mstring -mcpu=603e -mmultiple diff --git a/arch/powerpc/cpu/mpc83xx/config.mk b/arch/powerpc/cpu/mpc83xx/config.mk index 0dced88..a79729e 100644 --- a/arch/powerpc/cpu/mpc83xx/config.mk +++ b/arch/powerpc/cpu/mpc83xx/config.mk @@ -20,7 +20,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC83xx -DCONFIG_E300 \ -ffixed-r2 -msoft-float diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index daf73a6..028c8f0 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -32,7 +32,8 @@ extern void ft_qe_setup(void *blob); DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_BOOTCOUNT_LIMIT) && defined(CONFIG_MPC8360) +#if defined(CONFIG_BOOTCOUNT_LIMIT) && \ + (defined(CONFIG_QE)) #include <asm/immap_qe.h> void fdt_fixup_muram (void *blob) diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index cbb0fc6..d61d34c 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -55,9 +55,13 @@ COBJS-$(CONFIG_P1011) += ddr-gen3.o COBJS-$(CONFIG_P1012) += ddr-gen3.o COBJS-$(CONFIG_P1013) += ddr-gen3.o COBJS-$(CONFIG_P1014) += ddr-gen3.o +COBJS-$(CONFIG_P1015) += ddr-gen3.o +COBJS-$(CONFIG_P1016) += ddr-gen3.o COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_P1021) += ddr-gen3.o COBJS-$(CONFIG_P1022) += ddr-gen3.o +COBJS-$(CONFIG_P1024) += ddr-gen3.o +COBJS-$(CONFIG_P1025) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o @@ -69,7 +73,7 @@ COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_FSL_CORENET) += liodn.o COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_PCI) += pci.o -COBJS-$(CONFIG_FSL_CORENET) += portals.o +COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o # various SoC specific assignments COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o @@ -87,12 +91,20 @@ COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o +COBJS-$(CONFIG_P1010) += p1010_serdes.o COBJS-$(CONFIG_P1011) += p1021_serdes.o COBJS-$(CONFIG_P1012) += p1021_serdes.o COBJS-$(CONFIG_P1013) += p1022_serdes.o +COBJS-$(CONFIG_P1014) += p1010_serdes.o +COBJS-$(CONFIG_P1015) += p1021_serdes.o +COBJS-$(CONFIG_P1016) += p1021_serdes.o +COBJS-$(CONFIG_P1017) += p1023_serdes.o COBJS-$(CONFIG_P1020) += p1021_serdes.o COBJS-$(CONFIG_P1021) += p1021_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o +COBJS-$(CONFIG_P1023) += p1023_serdes.o +COBJS-$(CONFIG_P1024) += p1021_serdes.o +COBJS-$(CONFIG_P1025) += p1021_serdes.o COBJS-$(CONFIG_P2010) += p2020_serdes.o COBJS-$(CONFIG_P2020) += p2020_serdes.o COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index e94975a..7b9f773 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -44,6 +44,12 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) puts("Work-around for Erratum SERDES8 enabled\n"); #endif +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) + puts("Work-around for Erratum SERDES9 enabled\n"); +#endif +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005) + puts("Work-around for Erratum SERDES-A005 enabled\n"); +#endif #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) puts("Work-around for Erratum CPU22 enabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/config.mk b/arch/powerpc/cpu/mpc85xx/config.mk index 66d1741..68ac57d 100644 --- a/arch/powerpc/cpu/mpc85xx/config.mk +++ b/arch/powerpc/cpu/mpc85xx/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 1aad2ba..f863f4a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -33,6 +33,7 @@ #include <asm/cache.h> #include <asm/io.h> #include <asm/mmu.h> +#include <asm/fsl_ifc.h> #include <asm/fsl_law.h> #include <asm/fsl_lbc.h> #include <post.h> @@ -233,13 +234,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* * Get timebase clock frequency */ +#ifndef CONFIG_SYS_FSL_TBCLK_DIV +#define CONFIG_SYS_FSL_TBCLK_DIV 8 +#endif unsigned long get_tbclk (void) { -#ifdef CONFIG_FSL_CORENET - return (gd->bus_clk + 8) / 16; -#else - return (gd->bus_clk + 4UL)/8UL; -#endif + unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; + + return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; } @@ -280,7 +282,8 @@ int cpu_mmc_init(bd_t *bis) /* * Print out the state of various machine registers. - * Currently prints out LAWs, BR0/OR0, and TLBs + * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing + * parameters for IFC and TLBs */ void mpc85xx_reginfo(void) { @@ -289,11 +292,24 @@ void mpc85xx_reginfo(void) #if defined(CONFIG_FSL_LBC) print_lbc_regs(); #endif +#ifdef CONFIG_FSL_IFC + print_ifc_regs(); +#endif } /* Common ddr init for non-corenet fsl 85xx platforms */ #ifndef CONFIG_FSL_CORENET +#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR) +phys_size_t initdram(int board_type) +{ +#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) + return fsl_ddr_sdram_size(); +#else + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +#endif +} +#else /* CONFIG_SYS_RAMBOOT */ phys_size_t initdram(int board_type) { phys_size_t dram_size = 0; @@ -343,6 +359,7 @@ phys_size_t initdram(int board_type) puts("DDR: "); return dram_size; } +#endif /* CONFIG_SYS_RAMBOOT */ #endif #if CONFIG_POST & CONFIG_SYS_POST_MEMORY diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 8ece970..b3da970 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -37,6 +37,10 @@ #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include "mp.h" +#ifdef CONFIG_SYS_QE_FW_IN_NAND +#include <nand.h> +#include <errno.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -141,6 +145,22 @@ static void enable_cpc(void) for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { u32 cpccfg0 = in_be32(&cpc->cpccfg0); size += CPC_CFG0_SZ_K(cpccfg0); +#ifdef CONFIG_RAMBOOT_PBL + if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { + /* find and disable LAW of SRAM */ + struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); + + if (law.index == -1) { + printf("\nFatal error happened\n"); + return; + } + disable_law(law.index); + + clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); + out_be32(&cpc->cpccsr0, 0); + out_be32(&cpc->cpcsrcr0, 0); + } +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); @@ -164,6 +184,9 @@ void invalidate_cpc(void) cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + /* skip CPC when it used as all SRAM */ + if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) + continue; /* Flash invalidate the CPC and clear all the locks */ out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) @@ -384,12 +407,6 @@ int cpu_init_r(void) enable_cpc(); -#ifdef CONFIG_QE - uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ - qe_init(qe_base); - qe_reset(); -#endif - /* needs to be in ram since code uses global static vars */ fsl_serdes_init(); @@ -419,6 +436,23 @@ int cpu_init_r(void) isync(); #endif +#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE + { + ccsr_usb_phy_t *usb_phy1 = + (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; + out_be32(&usb_phy1->usb_enable_override, + CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); + } +#endif +#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE + { + ccsr_usb_phy_t *usb_phy2 = + (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; + out_be32(&usb_phy2->usb_enable_override, + CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); + } +#endif + return 0; } @@ -449,3 +483,25 @@ int sata_initialize(void) return 1; } #endif + +void cpu_secondary_init_r(void) +{ +#ifdef CONFIG_QE + uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ +#ifdef CONFIG_SYS_QE_FW_IN_NAND + int ret; + size_t fw_length = CONFIG_SYS_QE_FW_LENGTH; + + /* load QE firmware from NAND flash to DDR first */ + ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND, + &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR); + + if (ret && ret == -EUCLEAN) { + printf ("NAND read for QE firmware at offset %x failed %d\n", + CONFIG_SYS_QE_FW_IN_NAND, ret); + } +#endif + qe_init(qe_base); + qe_reset(); +#endif +} diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c index 8fb27ab..796d398 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c @@ -33,17 +33,15 @@ void cpu_init_f(void) */ out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8); -#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM) - set_lbc_br(0, CONFIG_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_NAND_OR_PRELIM); +#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); #else -#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined +#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined #endif #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; - char *l2srbar; - int i; out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); @@ -54,10 +52,5 @@ void cpu_init_f(void) /* set L2E=1 & L2SRAM=001 */ out_be32(&l2cache->l2ctl, (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); - - /* Initialize L2 SRAM to zero */ - l2srbar = (char *)CONFIG_SYS_INIT_L2_ADDR; - for (i = 0; i < CONFIG_SYS_L2_SIZE; i++) - l2srbar[i] = 0; #endif } diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 00fa752..6e909b5 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -338,6 +338,9 @@ void fdt_add_enet_stashing(void *fdt) do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); + do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1); + do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1); + do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1); } #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) @@ -470,6 +473,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_portal(blob, "fsl,bman-portal", "bman-portals", (u64)CONFIG_SYS_BMAN_MEM_PHYS, CONFIG_SYS_BMAN_MEM_SIZE); + fdt_fixup_bportals(blob); #endif #if defined(CONFIG_SYS_QMAN_MEM_PHYS) @@ -483,4 +487,13 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_SRIO ft_srio_setup(blob); #endif + + /* + * system-clock = CCB clock/2 + * Here gd->bus_clk = CCB clock + * We are using the system clock as 1588 Timer reference + * clock source select + */ + do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", + "timer-frequency", gd->bus_clk/2, 1); } diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 7fc00d8..741a0f8 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -29,6 +29,7 @@ #include <asm/io.h> #include <asm/processor.h> #include <asm/fsl_law.h> +#include <asm/errno.h> #include "fsl_corenet_serdes.h" static u32 serdes_prtcl_map; @@ -91,7 +92,7 @@ int serdes_get_lane_idx(int lane) return lanes[lane].idx; } -int serdes_get_bank(int lane) +int serdes_get_bank_by_lane(int lane) { return lanes[lane].bank; } @@ -109,10 +110,13 @@ int serdes_lane_enabled(int lane) return 0; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 - if (!IS_SVR_REV(get_svr(), 1, 0)) - if (bank > 0) - return !(srds_lpd_b[bank] & - (8 >> (lane - (6 + 4 * bank)))); + /* + * For banks two and three, use the srds_lpd_b[] array instead of the + * RCW, because this array contains the real values of SRDS_LPD_B2 and + * SRDS_LPD_B3. + */ + if (bank > 0) + return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank)))); #endif return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit)); @@ -129,6 +133,125 @@ int is_serdes_configured(enum srds_prtcl device) return (1 << device) & serdes_prtcl_map; } +static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device) +{ + int i; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_get_prtcl(prtcl, i) == device) + return i; + } + + return -ENODEV; +} + +/* + * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given + * device. This depends on the current SERDES protocol, as defined in the RCW. + * + * Returns a negative error code if SERDES is disabled or the given device is + * not supported in the current SERDES protocol. + */ +int serdes_get_first_lane(enum srds_prtcl device) +{ + u32 prtcl; + const ccsr_gur_t *gur; + + gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Is serdes enabled at all? */ + if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) + return -ENODEV; + + prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + return __serdes_get_first_lane(prtcl, device); +} + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 +/* + * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given + * SERDES protocol. + * + * Returns a negative error code if the given device is not supported for the + * given SERDES protocol. + */ +static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device) +{ + int lane; + + lane = __serdes_get_first_lane(prtcl, device); + if (unlikely(lane < 0)) + return lane; + + return serdes_get_bank_by_lane(lane); +} + +static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device, + int first) +{ + int lane; + + for (lane = first; lane < SRDS_MAX_LANES; lane++) { + if (serdes_get_prtcl(prtcl, lane) != device) + break; + } + + return lane - first; +} + +static void __serdes_reset_rx(serdes_corenet_t *regs, + uint32_t prtcl, + enum srds_prtcl device) +{ + int lane, idx, first, last; + + lane = __serdes_get_first_lane(prtcl, device); + if (unlikely(lane < 0)) + return; + first = serdes_get_lane_idx(lane); + last = first + __serdes_get_lane_count(prtcl, device, lane); + + /* + * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is + * selected as XAUI to place the lane into reset. + */ + for (idx = first; idx < last; idx++) + clrbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST); + + /* Wait at least 250 ns */ + udelay(1); + + /* + * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is + * selected as XAUI to bring the lane out of reset. + */ + for (idx = first; idx < last; idx++) + setbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST); +} + +void serdes_reset_rx(enum srds_prtcl device) +{ + u32 prtcl; + const ccsr_gur_t *gur; + serdes_corenet_t *regs; + + if (unlikely(device == NONE)) + return; + + gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Is serdes enabled at all? */ + if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) + return; + + regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + __serdes_reset_rx(regs, prtcl, device); +} +#endif + #ifndef CONFIG_SYS_DCSRBAR_PHYS #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ #define CONFIG_SYS_DCSRBAR 0x80000000 @@ -263,6 +386,74 @@ static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur, } #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 +/* + * If PCIe is not selected as a protocol for any lanes driven by a given PLL, + * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0. + */ +static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg) +{ + enum srds_prtcl device; + + switch (cfg) { + case 0x13: + case 0x16: + /* + * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL] + * to 0. + */ + clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + break; + case 0x19: + /* + * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and + * SRDSB3PLLCR1[PLLBW_SEL] to 1. + */ + clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + break; + } + + /* + * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI + * before XAUI is initialized. + */ + for (device = XAUI_FM1; device <= XAUI_FM2; device++) { + if (is_serdes_configured(device)) { + int bank = serdes_get_bank_by_device(cfg, device); + + clrbits_be32(®s->bank[bank].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + } + } +} +#endif + +/* + * Wait for the RSTDONE bit to get set, or a one-second timeout. + */ +static void wait_for_rstdone(unsigned int bank) +{ + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + unsigned long long end_tick; + u32 rstctl; + + /* wait for reset complete or 1-second timeout */ + end_tick = usec2ticks(1000000) + get_ticks(); + do { + rstctl = in_be32(&srds_regs->bank[bank].rstctl); + if (rstctl & SRDS_RSTCTL_RSTDONE) + break; + } while (end_tick > get_ticks()); + + if (!(rstctl & SRDS_RSTCTL_RSTDONE)) + printf("SERDES: timeout resetting bank %u\n", bank); +} + void fsl_serdes_init(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -270,7 +461,6 @@ void fsl_serdes_init(void) serdes_corenet_t *srds_regs; int lane, bank, idx; enum srds_prtcl lane_prtcl; - long long end_tick; int have_bank[SRDS_MAX_BANK] = {}; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 u32 serdes8_devdisr = 0; @@ -279,6 +469,12 @@ void fsl_serdes_init(void) const char *srds_lpd_arg; size_t arglen; #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 + enum srds_prtcl device; +#endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */ +#endif char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; @@ -303,60 +499,76 @@ void fsl_serdes_init(void) } #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 - if (!IS_SVR_REV(get_svr(), 1, 0)) - for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) { - sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1); - srds_lpd_arg = hwconfig_subarg_f("serdes", srds_lpd_opt, - &arglen, buf); - if (srds_lpd_arg) - srds_lpd_b[bank] = simple_strtoul(srds_lpd_arg, - NULL, 0); - } + /* + * Display a warning if banks two and three are not disabled in the RCW, + * since our work-around for SERDES8 depends on these banks being + * disabled at power-on. + */ +#define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3) + if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) { + printf("Warning: SERDES8 requires banks two and " + "three to be disabled in the RCW\n"); + } + + /* + * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3 + * hwconfig options into the srds_lpd_b[] array. See README.p4080ds + * for a description of these options. + */ + for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) { + sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1); + srds_lpd_arg = + hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf); + if (srds_lpd_arg) + srds_lpd_b[bank] = + simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf; + } #endif /* Look for banks with all lanes disabled, and power down the bank. */ for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane); if (serdes_lane_enabled(lane)) { - have_bank[serdes_get_bank(lane)] = 1; + have_bank[serdes_get_bank_by_lane(lane)] = 1; serdes_prtcl_map |= (1 << lane_prtcl); } } #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 - if (IS_SVR_REV(get_svr(), 1, 0)) { - /* At least one bank must be disabled due to SERDES8. If - * no bank is found to be disabled based on lane - * disables, disable bank 3 because we can't turn off its - * lanes in the RCW without disabling MDIO due to erratum - * GEN8. - * - * This means that if you are relying on bank 3 being - * disabled to avoid SERDES8, in some cases you cannot - * also disable all lanes of another bank, or else bank - * 3 won't be disabled, leaving you with a configuration - * that isn't valid according to SERDES8 (e.g. if banks - * 2 and 3 have the same clock, and bank 1 is disabled - * instead of 3). - */ - for (bank = 0; bank < SRDS_MAX_BANK; bank++) { - if (!have_bank[bank]) - break; - } + /* + * Bank two uses the clock from bank three, so if bank two is enabled, + * then bank three must also be enabled. + */ + if (have_bank[FSL_SRDS_BANK_2]) + have_bank[FSL_SRDS_BANK_3] = 1; +#endif - if (bank == SRDS_MAX_BANK) - have_bank[FSL_SRDS_BANK_3] = 0; - } else { - if (have_bank[FSL_SRDS_BANK_2]) - have_bank[FSL_SRDS_BANK_3] = 1; - } +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + /* + * The work-aroud for erratum SERDES-A001 is needed only if bank two + * is disabled and bank three is enabled. + */ + need_serdes_a001 = + !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3]; #endif + /* Power down the banks we're not interested in */ for (bank = 0; bank < SRDS_MAX_BANK; bank++) { if (!have_bank[bank]) { printf("SERDES: bank %d disabled\n", bank + 1); +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + /* + * Erratum SERDES-A001 says bank two needs to be powered + * down after bank three is powered up, so don't power + * down bank two here. + */ + if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2)) + setbits_be32(&srds_regs->bank[bank].rstctl, + SRDS_RSTCTL_SDPD); +#else setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_SDPD); +#endif } } @@ -382,6 +594,35 @@ void fsl_serdes_init(void) printf("%s ", serdes_prtcl_str[lane_prtcl]); #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 + /* + * Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for + * each of the SerDes lanes selected as SGMII, XAUI, SRIO, or + * AURORA before the device is initialized. + */ + switch (lane_prtcl) { + case SGMII_FM1_DTSEC1: + case SGMII_FM1_DTSEC2: + case SGMII_FM1_DTSEC3: + case SGMII_FM1_DTSEC4: + case SGMII_FM2_DTSEC1: + case SGMII_FM2_DTSEC2: + case SGMII_FM2_DTSEC3: + case SGMII_FM2_DTSEC4: + case XAUI_FM1: + case XAUI_FM2: + case SRIO1: + case SRIO2: + case AURORA: + clrsetbits_be32(&srds_regs->lane[idx].ttlcr0, + SRDS_TTLCR0_FLT_SEL_MASK, + SRDS_TTLCR0_FLT_SEL_750PPM | + SRDS_TTLCR0_PM_DIS); + default: + break; + } +#endif + #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 switch (lane_prtcl) { case PCIE1: @@ -428,13 +669,12 @@ void fsl_serdes_init(void) FSL_CORENET_DEVDISR2_DTSEC2_4; break; case XAUI_FM1: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | + FSL_CORENET_DEVDISR2_10GEC1; + break; case XAUI_FM2: - if (lane_prtcl == XAUI_FM1) - serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | - FSL_CORENET_DEVDISR2_10GEC1; - else - serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | - FSL_CORENET_DEVDISR2_10GEC2; + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_10GEC2; break; case AURORA: break; @@ -449,25 +689,24 @@ void fsl_serdes_init(void) puts("\n"); #endif - for (idx = 0; idx < SRDS_MAX_BANK; idx++) { - u32 rstctl; +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 + p4080_erratum_serdes_a005(srds_regs, cfg); +#endif + for (idx = 0; idx < SRDS_MAX_BANK; idx++) { bank = idx; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 - if (!IS_SVR_REV(get_svr(), 1, 0)) { - /* - * Change bank init order to 0, 2, 1, so that the - * third bank's PLL is established before we - * start the second bank which shares the third - * bank's PLL. - */ + /* + * Change bank init order to 0, 2, 1, so that the third bank's + * PLL is established before we start the second bank. The + * second bank uses the third bank's PLL. + */ - if (idx == 1) - bank = FSL_SRDS_BANK_3; - else if (idx == 2) - bank = FSL_SRDS_BANK_2; - } + if (idx == 1) + bank = FSL_SRDS_BANK_3; + else if (idx == 2) + bank = FSL_SRDS_BANK_2; #endif /* Skip disabled banks */ @@ -475,32 +714,48 @@ void fsl_serdes_init(void) continue; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 - if (!IS_SVR_REV(get_svr(), 1, 0)) { - if (idx == 1) { - p4080_erratum_serdes8(srds_regs, gur, - serdes8_devdisr, - serdes8_devdisr2, cfg); - } else if (idx == 2) { - enable_bank(gur, FSL_SRDS_BANK_2); - } + if (idx == 1) { + /* + * Re-enable devices on banks two and three that were + * disabled by the RCW, and then enable bank three. The + * devices need to be enabled before either bank is + * powered up. + */ + p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr, + serdes8_devdisr2, cfg); + } else if (idx == 2) { + /* Eable bank two now that bank three is enabled. */ + enable_bank(gur, FSL_SRDS_BANK_2); } #endif /* reset banks for errata */ setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST); - /* wait for reset complete or 1-second timeout */ - end_tick = usec2ticks(1000000) + get_ticks(); - do { - rstctl = in_be32(&srds_regs->bank[bank].rstctl); - if (rstctl & SRDS_RSTCTL_RSTDONE) - break; - } while (end_tick > get_ticks()); - - if (!(rstctl & SRDS_RSTCTL_RSTDONE)) { - printf("SERDES: timeout resetting bank %d\n", - bank + 1); - continue; - } + wait_for_rstdone(bank); } + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + if (need_serdes_a001) { + /* + * Bank three has been enabled, so enable bank two and then + * disable it. + */ + srds_lpd_b[FSL_SRDS_BANK_2] = 0; + enable_bank(gur, FSL_SRDS_BANK_2); + + wait_for_rstdone(FSL_SRDS_BANK_2); + + /* Disable bank 2 */ + setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl, + SRDS_RSTCTL_SDPD); + } +#endif + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 + for (device = XAUI_FM1; device <= XAUI_FM2; device++) { + if (is_serdes_configured(device)) + __serdes_reset_rx(srds_regs, cfg, device); + } +#endif } diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h index 42d771e..f261351 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h @@ -33,7 +33,7 @@ enum srds_bank { int is_serdes_prtcl_valid(u32 prtcl); int serdes_get_lane_idx(int lane); -int serdes_get_bank(int lane); +int serdes_get_bank_by_lane(int lane); int serdes_lane_enabled(int lane); enum srds_prtcl serdes_get_prtcl(int cfg, int lane); diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c new file mode 100644 index 0000000..e8a0387 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c @@ -0,0 +1,75 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Author: Prabhakar Kushwaha <prabhakar@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 +#define SRDS2_MAX_LANES 2 + +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + +static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x00] = {NONE, NONE, NONE, NONE}, + [0x01] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3}, + [0x02] = {PCIE1, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3}, + [0x03] = {NONE, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3}, +}; + +static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x00] = {NONE, NONE}, + [0x01] = {SATA1, SATA2}, + [0x02] = {SATA1, SATA2}, + [0x03] = {PCIE1, PCIE2}, +}; + + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + + if (ret) + return ret; + + return (1 << device) & serdes2_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c new file mode 100644 index 0000000..c8ab5d6 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c @@ -0,0 +1,53 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Roy Zang <tie-fei.zang@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x00] = {PCIE1, PCIE2, NONE, NONE}, + [0x01] = {PCIE1, PCIE2, PCIE3, NONE}, + [0x02] = {PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC2}, + [0x03] = {PCIE1, PCIE2, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + return ret; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + +} diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index febbee9..1255898 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -52,10 +52,10 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 127), SET_SATA_LIODN(2, 128), - SET_PCI_LIODN(1, 193), - SET_PCI_LIODN(2, 194), - SET_PCI_LIODN(3, 195), - SET_PCI_LIODN(4, 196), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196), SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index df25048..fd155c8 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -44,9 +44,9 @@ struct liodn_id_table liodn_tbl[] = { SET_SDHC_LIODN(1, 156), - SET_PCI_LIODN(1, 193), - SET_PCI_LIODN(2, 194), - SET_PCI_LIODN(3, 195), + SET_PCI_LIODN("fsl,p4080-pcie", 1, 193), + SET_PCI_LIODN("fsl,p4080-pcie", 2, 194), + SET_PCI_LIODN("fsl,p4080-pcie", 3, 195), SET_DMA_LIODN(1, 196), SET_DMA_LIODN(2, 197), diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index febbee9..1255898 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -52,10 +52,10 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 127), SET_SATA_LIODN(2, 128), - SET_PCI_LIODN(1, 193), - SET_PCI_LIODN(2, 194), - SET_PCI_LIODN(3, 195), - SET_PCI_LIODN(4, 196), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196), SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index 01aec6e..c014163 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -30,18 +30,14 @@ #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> -static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_CORENET_QMAN_ADDR; +static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; +static ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR; void setup_portals(void) { +#ifdef CONFIG_FSL_CORENET int i; - /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ -#ifdef CONFIG_PHYS_64BIT - out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); -#endif - out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); - for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { u8 sdest = qp_info[i].sdest; u16 fliodn = qp_info[i].fliodn; @@ -53,6 +49,13 @@ void setup_portals(void) /* set frame liodn */ out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn); } +#endif + + /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ +#ifdef CONFIG_PHYS_64BIT + out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); +#endif + out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); } /* Update portal containter to match LAW setup of portal in phy map */ @@ -118,9 +121,12 @@ void fdt_portal(void *blob, const char *compat, const char *container, static int fdt_qportal(void *blob, int off, int id, char *name, enum fsl_dpaa_dev dev, int create) { - int childoff, dev_off, num, ret = 0; + int childoff, dev_off, ret = 0; uint32_t dev_handle; +#ifdef CONFIG_FSL_CORENET + int num; u32 liodns[2]; +#endif childoff = fdt_subnode_offset(blob, off, name); if (create) { @@ -154,9 +160,11 @@ static int fdt_qportal(void *blob, int off, int id, char *name, if (ret < 0) return ret; +#ifdef CONFIG_FSL_CORENET num = get_dpaa_liodn(dev, &liodns[0], id); ret = fdt_setprop(blob, childoff, "fsl,liodn", &liodns[0], sizeof(u32) * num); +#endif } else { return childoff; } @@ -184,7 +192,9 @@ void fdt_fixup_qportals(void *blob) off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal"); while (off != -FDT_ERR_NOTFOUND) { +#ifdef CONFIG_FSL_CORENET u32 liodns[2]; +#endif const int *ci = fdt_getprop(blob, off, "cell-index", NULL); int j, i = *ci; @@ -192,6 +202,7 @@ void fdt_fixup_qportals(void *blob) if (err < 0) goto err; +#ifdef CONFIG_FSL_CORENET liodns[0] = qp_info[i].dliodn; liodns[1] = qp_info[i].fliodn; @@ -199,6 +210,7 @@ void fdt_fixup_qportals(void *blob) &liodns, sizeof(u32) * 2); if (err < 0) goto err; +#endif i++; @@ -207,6 +219,7 @@ void fdt_fixup_qportals(void *blob) if (err < 0) goto err; +#ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_DPAA_PME err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1); if (err < 0) @@ -214,6 +227,8 @@ void fdt_fixup_qportals(void *blob) #else fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0); #endif +#endif + #ifdef CONFIG_SYS_DPAA_FMAN for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) { char name[] = "fman@0"; @@ -236,3 +251,32 @@ err: off = fdt_node_offset_by_compatible(blob, off, "fsl,qman-portal"); } } + +void fdt_fixup_bportals(void *blob) +{ + int off, err; + unsigned int maj, min; + u32 rev_1 = in_be32(&bman->ip_rev_1); + char compat[64]; + int compat_len; + + maj = (rev_1 >> 8) & 0xff; + min = rev_1 & 0xff; + + compat_len = sprintf(compat, "fsl,bman-portal-%u.%u", maj, min) + 1; + compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1; + + off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal"); + while (off != -FDT_ERR_NOTFOUND) { + err = fdt_setprop(blob, off, "compatible", compat, compat_len); + if (err < 0) { + printf("ERROR: unable to create props for %s: %s\n", + fdt_get_name(blob, off, NULL), + fdt_strerror(err)); + return; + } + + off = fdt_node_offset_by_compatible(blob, off, "fsl,bman-portal"); + } + +} diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index f2aa8d0..c4c156d 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -28,6 +28,7 @@ #include <common.h> #include <ppc_asm.tmpl> +#include <linux/compiler.h> #include <asm/processor.h> #include <asm/io.h> @@ -107,25 +108,45 @@ void get_sys_info (sys_info_t * sysInfo) #define PME_CLK_SEL 0x80000000 #define FM1_CLK_SEL 0x40000000 #define FM2_CLK_SEL 0x20000000 +#define HWA_ASYNC_DIV 0x04000000 +#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) +#define HWA_CC_PLL 1 +#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) +#define HWA_CC_PLL 2 +#else +#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case +#endif rcw_tmp = in_be32(&gur->rcwsr[7]); #ifdef CONFIG_SYS_DPAA_PME - if (rcw_tmp & PME_CLK_SEL) - sysInfo->freqPME = freqCC_PLL[2] / 2; - else + if (rcw_tmp & PME_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqPME = sysInfo->freqSystemBus / 2; + } #endif #ifdef CONFIG_SYS_DPAA_FMAN - if (rcw_tmp & FM1_CLK_SEL) - sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; - else + if (rcw_tmp & FM1_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; + } #if (CONFIG_SYS_NUM_FMAN) == 2 - if (rcw_tmp & FM2_CLK_SEL) - sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; - else + if (rcw_tmp & FM2_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; + } #endif #endif @@ -136,7 +157,7 @@ void get_sys_info (sys_info_t * sysInfo) #endif int i; #ifdef CONFIG_QE - u32 qe_ratio; + __maybe_unused u32 qe_ratio; #endif plat_ratio = (gur->porpllsr) & 0x0000003e; @@ -162,13 +183,23 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; } #endif -#endif #ifdef CONFIG_QE +#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ + defined(CONFIG_P1021) || defined(CONFIG_P1025) + sysInfo->freqQE = sysInfo->freqSystemBus; +#else qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; #endif +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + sysInfo->freqFMan[0] = sysInfo->freqSystemBus; +#endif + +#endif /* CONFIG_FSL_CORENET */ #if defined(CONFIG_FSL_LBC) #if defined(CONFIG_SYS_LBC_LCRR) @@ -254,7 +285,8 @@ int get_clocks (void) gd->i2c2_clk = gd->i2c1_clk; #if defined(CONFIG_FSL_ESDHC) -#ifdef CONFIG_MPC8569 +#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ + defined(CONFIG_P1014) gd->sdhc_clk = gd->bus_clk; #else gd->sdhc_clk = gd->bus_clk / 2; diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 31143ba..295f175 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -55,6 +55,7 @@ void init_tlbs(void) return ; } +#ifndef CONFIG_NAND_SPL void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, phys_addr_t *rpn) { @@ -73,7 +74,6 @@ void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, #endif } -#ifndef CONFIG_NAND_SPL void print_tlbcam(void) { int i; diff --git a/arch/powerpc/cpu/mpc86xx/config.mk b/arch/powerpc/cpu/mpc86xx/config.mk index ca2f837..92ff7bf 100644 --- a/arch/powerpc/cpu/mpc86xx/config.mk +++ b/arch/powerpc/cpu/mpc86xx/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -ffixed-r2 -mstring PLATFORM_CPPFLAGS += -maltivec -mabi=altivec -msoft-float diff --git a/arch/powerpc/cpu/mpc8xx/config.mk b/arch/powerpc/cpu/mpc8xx/config.mk index f5e08a5..aa61980 100644 --- a/arch/powerpc/cpu/mpc8xx/config.mk +++ b/arch/powerpc/cpu/mpc8xx/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -mstring -mcpu=860 -msoft-float diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 5dfd65b..4ae26e4 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -15,6 +15,7 @@ COBJS-y += cpu.o endif COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o COBJS-$(CONFIG_SYS_SRIO) += srio.o diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 4335fb4..39b304a 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -71,15 +71,27 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P1012, P1012, 1), CPU_TYPE_ENTRY(P1012, P1012_E, 1), CPU_TYPE_ENTRY(P1013, P1013, 1), + CPU_TYPE_ENTRY(P1013, P1013_E, 1), CPU_TYPE_ENTRY(P1014, P1014_E, 1), CPU_TYPE_ENTRY(P1014, P1014, 1), - CPU_TYPE_ENTRY(P1013, P1013_E, 1), + CPU_TYPE_ENTRY(P1015, P1015_E, 1), + CPU_TYPE_ENTRY(P1015, P1015, 1), + CPU_TYPE_ENTRY(P1016, P1016_E, 1), + CPU_TYPE_ENTRY(P1016, P1016, 1), + CPU_TYPE_ENTRY(P1017, P1017, 1), + CPU_TYPE_ENTRY(P1017, P1017, 1), CPU_TYPE_ENTRY(P1020, P1020, 2), CPU_TYPE_ENTRY(P1020, P1020_E, 2), CPU_TYPE_ENTRY(P1021, P1021, 2), CPU_TYPE_ENTRY(P1021, P1021_E, 2), CPU_TYPE_ENTRY(P1022, P1022, 2), CPU_TYPE_ENTRY(P1022, P1022_E, 2), + CPU_TYPE_ENTRY(P1023, P1023, 2), + CPU_TYPE_ENTRY(P1023, P1023_E, 2), + CPU_TYPE_ENTRY(P1024, P1024, 2), + CPU_TYPE_ENTRY(P1024, P1024_E, 2), + CPU_TYPE_ENTRY(P1025, P1025, 2), + CPU_TYPE_ENTRY(P1025, P1025_E, 2), CPU_TYPE_ENTRY(P2010, P2010, 1), CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index cefabe7..02d069c 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -236,7 +236,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, * tAXPD=1, need design to confirm. */ int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ - unsigned int data_rate = fsl_ddr_get_mem_data_rate(); + unsigned int data_rate = get_ddr_freq(0); tmrd_mclk = 4; /* set the turnaround time */ trwt_mclk = 1; @@ -1305,7 +1305,7 @@ static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) { if (popts->addr_hash) { ddr->ddr_eor = 0x40000000; /* address hash enable */ - puts("Addess hashing enabled.\n"); + puts("Address hashing enabled.\n"); } } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index c7c12c1..1e866fe 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -80,5 +80,4 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo); extern unsigned int mclk_to_picos(unsigned int mclk); extern unsigned int get_memory_clk_period_ps(void); extern unsigned int picos_to_mclk(unsigned int picos); -extern unsigned int fsl_ddr_get_mem_data_rate(void); #endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c index dcb37ce..b565e33 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c @@ -250,24 +250,27 @@ ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd, pdimm->primary_sdram_width = spd->primw; pdimm->ec_sdram_width = spd->ecw; - /* FIXME: what about registered SO-DIMM? */ + /* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */ switch (spd->dimm_type) { - case 0x01: /* RDIMM */ - case 0x10: /* Mini-RDIMM */ - pdimm->registered_dimm = 1; /* register buffered */ + case DDR2_SPD_DIMMTYPE_RDIMM: + case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM: + case DDR2_SPD_DIMMTYPE_MINI_RDIMM: + /* Registered/buffered DIMMs */ + pdimm->registered_dimm = 1; break; - case 0x02: /* UDIMM */ - case 0x04: /* SO-DIMM */ - case 0x08: /* Micro-DIMM */ - case 0x20: /* Mini-UDIMM */ - pdimm->registered_dimm = 0; /* unbuffered */ + case DDR2_SPD_DIMMTYPE_UDIMM: + case DDR2_SPD_DIMMTYPE_SO_DIMM: + case DDR2_SPD_DIMMTYPE_MICRO_DIMM: + case DDR2_SPD_DIMMTYPE_MINI_UDIMM: + /* Unbuffered DIMMs */ + pdimm->registered_dimm = 0; break; + case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM: default: printf("unknown dimm_type 0x%02X\n", spd->dimm_type); return 1; - break; } /* SDRAM device parameters */ diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index 29cea53..756b15f 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -128,24 +128,32 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, pdimm->data_width = pdimm->primary_sdram_width + pdimm->ec_sdram_width; - switch (spd->module_type & 0xf) { - case 0x01: /* RDIMM */ - case 0x05: /* Mini-RDIMM */ - pdimm->registered_dimm = 1; /* register buffered */ + /* These are the types defined by the JEDEC DDR3 SPD spec */ + pdimm->mirrored_dimm = 0; + pdimm->registered_dimm = 0; + switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) { + case DDR3_SPD_MODULETYPE_RDIMM: + case DDR3_SPD_MODULETYPE_MINI_RDIMM: + /* Registered/buffered DIMMs */ + pdimm->registered_dimm = 1; for (i = 0; i < 16; i += 2) { - pdimm->rcw[i] = spd->mod_section.registered.rcw[i/2] & 0x0F; - pdimm->rcw[i+1] = (spd->mod_section.registered.rcw[i/2] >> 4) & 0x0F; + u8 rcw = spd->mod_section.registered.rcw[i/2]; + pdimm->rcw[i] = (rcw >> 0) & 0x0F; + pdimm->rcw[i+1] = (rcw >> 4) & 0x0F; } break; - case 0x02: /* UDIMM */ - case 0x03: /* SO-DIMM */ - case 0x04: /* Micro-DIMM */ - case 0x06: /* Mini-UDIMM */ - pdimm->registered_dimm = 0; /* unbuffered */ + + case DDR3_SPD_MODULETYPE_UDIMM: + case DDR3_SPD_MODULETYPE_SO_DIMM: + case DDR3_SPD_MODULETYPE_MICRO_DIMM: + case DDR3_SPD_MODULETYPE_MINI_UDIMM: + /* Unbuffered DIMMs */ + if (spd->mod_section.unbuffered.addr_mapping & 0x1) + pdimm->mirrored_dimm = 1; break; default: - printf("unknown dimm_type 0x%02X\n", spd->module_type); + printf("unknown module_type 0x%02X\n", spd->module_type); return 1; } @@ -303,16 +311,5 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, pdimm->tFAW_ps = (((spd->tFAW_msb & 0xf) << 8) | spd->tFAW_min) * mtb_ps; - /* - * We need check the address mirror for unbuffered DIMM - * If SPD indicate the address map mirror, The DDR controller - * need care it. - */ - if ((spd->module_type == SPD_MODULETYPE_UDIMM) || - (spd->module_type == SPD_MODULETYPE_SODIMM) || - (spd->module_type == SPD_MODULETYPE_MICRODIMM) || - (spd->module_type == SPD_MODULETYPE_MINIUDIMM)) - pdimm->mirrored_dimm = spd->mod_section.unbuffered.addr_mapping & 0x1; - return 0; } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c index 8b31ec0..00f3d6c 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c @@ -207,10 +207,15 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, temp1 = temp2 = 0; for (i = 0; i < number_of_dimms; i++) { if (dimm_params[i].n_ranks) { - if (dimm_params[i].registered_dimm) + if (dimm_params[i].registered_dimm) { temp1 = 1; - if (!dimm_params[i].registered_dimm) + printf("Detected RDIMM %s\n", + dimm_params[i].mpart); + } else { temp2 = 1; + printf("Detected UDIMM %s\n", + dimm_params[i].mpart); + } } } @@ -218,10 +223,8 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, outpdimm->all_DIMMs_unbuffered = 0; if (temp1 && !temp2) { outpdimm->all_DIMMs_registered = 1; - printf("Detected RDIMM(s)\n"); } else if (!temp1 && temp2) { outpdimm->all_DIMMs_unbuffered = 1; - printf("Detected UDIMM(s)\n"); } else { printf("ERROR: Mix of registered buffered and unbuffered " "DIMMs detected!\n"); diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index bb96d66..c8fa123 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -13,6 +13,7 @@ */ #include <common.h> +#include <i2c.h> #include <asm/fsl_ddr_sdram.h> #include "ddr.h" @@ -26,9 +27,65 @@ extern void fsl_ddr_set_lawbar( extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num); -/* Board-specific functions defined in each board's ddr.c */ -extern void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num); +#if defined(SPD_EEPROM_ADDRESS) || \ + defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ + defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) +#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS, +}; +#endif +#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ +}; +#endif +#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ + [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ +}; +#endif + +static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); + + if (ret) { + printf("DDR: failed to read SPD from address %u\n", i2c_address); + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +} + +__attribute__((weak, alias("__get_spd"))) +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address); + +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + i2c_address = spd_i2c_addr[ctrl_num][i]; + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} +#else +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ +} +#endif /* SPD_EEPROM_ADDRESSx */ /* * ASSUMPTIONS: diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c index 1e2d921..104d360 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -8,10 +8,16 @@ #include <common.h> #include <asm/fsl_law.h> +#include <div64.h> #include "ddr.h" -unsigned int fsl_ddr_get_mem_data_rate(void); +/* To avoid 64-bit full-divides, we factor this here */ +#define ULL_2E12 2000000000000ULL +#define UL_5POW12 244140625UL +#define UL_2POW13 (1UL << 13) + +#define ULL_8FS 0xFFFFFFFFULL /* * Round mclk_ps to nearest 10 ps in memory controller code. @@ -22,35 +28,51 @@ unsigned int fsl_ddr_get_mem_data_rate(void); */ unsigned int get_memory_clk_period_ps(void) { - unsigned int mclk_ps; + unsigned int data_rate = get_ddr_freq(0); + unsigned int result; + + /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ + unsigned long long mclk_ps = ULL_2E12; + + /* Add 5*data_rate, for rounding */ + mclk_ps += 5*(unsigned long long)data_rate; - mclk_ps = 2000000000000ULL / fsl_ddr_get_mem_data_rate(); - /* round to nearest 10 ps */ - return 10 * ((mclk_ps + 5) / 10); + /* Now perform the big divide, the result fits in 32-bits */ + do_div(mclk_ps, data_rate); + result = mclk_ps; + + /* We still need to round to 10ps */ + return 10 * (result/10); } /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ unsigned int picos_to_mclk(unsigned int picos) { - const unsigned long long ULL_2e12 = 2000000000000ULL; - const unsigned long long ULL_8Fs = 0xFFFFFFFFULL; - unsigned long long clks; - unsigned long long clks_temp; + unsigned long long clks, clks_rem; + /* Short circuit for zero picos */ if (!picos) return 0; - clks = fsl_ddr_get_mem_data_rate() * (unsigned long long) picos; - clks_temp = clks; - clks = clks / ULL_2e12; - if (clks_temp % ULL_2e12) { - clks++; - } + /* First multiply the time by the data rate (32x32 => 64) */ + clks = picos * (unsigned long long)get_ddr_freq(0); - if (clks > ULL_8Fs) { - clks = ULL_8Fs; - } + /* + * Now divide by 5^12 and track the 32-bit remainder, then divide + * by 2*(2^12) using shifts (and updating the remainder). + */ + clks_rem = do_div(clks, UL_5POW12); + clks_rem <<= 13; + clks_rem |= clks & (UL_2POW13-1); + clks >>= 13; + + /* If we had a remainder, then round up */ + if (clks_rem) + clks++; + /* Clamp to the maximum representable value */ + if (clks > ULL_8FS) + clks = ULL_8FS; return (unsigned int) clks; } @@ -141,6 +163,8 @@ void board_add_ram_info(int use_default) if (sdram_cfg & SDRAM_CFG_32_BE) puts(", 32-bit"); + else if (sdram_cfg & SDRAM_CFG_16_BE) + puts(", 16-bit"); else puts(", 64-bit"); diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 0c166fd..520cb90 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -27,8 +27,8 @@ #include <libfdt.h> #include <fdt_support.h> #include <asm/mp.h> -#include <asm/fsl_enet.h> #include <asm/fsl_serdes.h> +#include <phy.h> #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) @@ -218,27 +218,10 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev) } #endif -int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc) +int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { - static const char *fsl_phy_enet_if_str[] = { - [MII] = "mii", - [RMII] = "rmii", - [GMII] = "gmii", - [RGMII] = "rgmii", - [RGMII_ID] = "rgmii-id", - [RGMII_RXID] = "rgmii-rxid", - [SGMII] = "sgmii", - [TBI] = "tbi", - [RTBI] = "rtbi", - [XAUI] = "xgmii", - [FSL_ETH_IF_NONE] = "", - }; - - if (phyc > ARRAY_SIZE(fsl_phy_enet_if_str)) - return fdt_setprop_string(blob, offset, "phy-connection-type", ""); - return fdt_setprop_string(blob, offset, "phy-connection-type", - fsl_phy_enet_if_str[phyc]); + phy_string_for_interface(phyc)); } #ifdef CONFIG_SYS_SRIO diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c new file mode 100644 index 0000000..e794821 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c @@ -0,0 +1,83 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Dipen Dudhat <dipen.dudhat@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_ifc.h> + +void print_ifc_regs(void) +{ + int i, j; + + printf("IFC Controller Registers\n"); + for (i = 0; i < FSL_IFC_BANK_COUNT; i++) { + printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n", + i, get_ifc_cspr(i), i, get_ifc_amask(i), + i, get_ifc_csor(i)); + for (j = 0; j < 4; j++) + printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j)); + } +} + +void init_early_memctl_regs(void) +{ +#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) + set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0); + set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1); + set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); + set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); + + set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); + set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); + set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); +#endif + +#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) + set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); + set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); + set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2); + set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3); + + set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1); + set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1); + set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); +#endif + +#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) + set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); + set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); + set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2); + set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3); + + set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2); + set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); + set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); +#endif + +#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) + set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); + set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); + set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2); + set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3); + + set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3); + set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); + set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); +#endif +} diff --git a/arch/powerpc/cpu/ppc4xx/config.mk b/arch/powerpc/cpu/ppc4xx/config.mk index d862bb4..f5cbbbd 100644 --- a/arch/powerpc/cpu/ppc4xx/config.mk +++ b/arch/powerpc/cpu/ppc4xx/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -msoft-float cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 2b6b233..9aad9be 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -29,6 +29,13 @@ #include <asm/config_mpc86xx.h> #endif +/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ +#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) +# ifndef CONFIG_HARD_SPI +# define CONFIG_HARD_SPI +# endif +#endif + #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH #define CONFIG_SYS_BOOT_GET_CMDLINE @@ -75,8 +82,19 @@ /* Since so many PPC SOCs have a semi-common LBC, define this here */ #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ defined(CONFIG_MPC83xx) +#if !defined(CONFIG_FSL_IFC) #define CONFIG_FSL_LBC #endif +#endif + +/* The TSEC driver uses the PHYLIB infrastructure */ +#ifndef CONFIG_PHYLIB +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_PHYLIB + +#include <config_phylib_all_drivers.h> +#endif /* TSEC_ENET */ +#endif /* !CONFIG_PHYLIB */ /* All PPC boards must swap IDE bytes */ #define CONFIG_IDE_SWAP_IO diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 6c16681..41c2d20 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -67,11 +67,17 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define QE_MURAM_SIZE 0x10000UL +#define MAX_QE_RISC 2 +#define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_MPC8569) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define QE_MURAM_SIZE 0x20000UL +#define MAX_QE_RISC 4 +#define QE_NUM_OF_SNUM 46 #elif defined(CONFIG_MPC8572) #define CONFIG_MAX_CPUS 2 @@ -82,24 +88,39 @@ #elif defined(CONFIG_P1010) #define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +/* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +/* P1012 is single core version of P1021 */ #elif defined(CONFIG_P1012) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 +/* P1013 is single core version of P1022 */ #elif defined(CONFIG_P1013) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 @@ -111,9 +132,49 @@ #elif defined(CONFIG_P1014) #define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 + +/* P1015 is single core version of P1024 */ +#elif defined(CONFIG_P1015) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +/* P1016 is single core version of P1025 */ +#elif defined(CONFIG_P1016) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 + +/* P1017 is single core version of P1023 */ +#elif defined(CONFIG_P1017) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 2 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_QMAN_NUM_PORTALS 3 +#define CONFIG_SYS_BMAN_NUM_PORTALS 3 +#define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #elif defined(CONFIG_P1020) #define CONFIG_MAX_CPUS 2 @@ -121,6 +182,8 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_P1021) #define CONFIG_MAX_CPUS 2 @@ -128,6 +191,11 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_P1022) #define CONFIG_MAX_CPUS 2 @@ -138,6 +206,41 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 +#elif defined(CONFIG_P1023) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 2 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_QMAN_NUM_PORTALS 3 +#define CONFIG_SYS_BMAN_NUM_PORTALS 3 +#define CONFIG_SYS_FM_MURAM_SIZE 0x10000 + +/* P1024 is lower end variant of P1020 */ +#elif defined(CONFIG_P1024) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +/* P1025 is lower end variant of P1021 */ +#elif defined(CONFIG_P1025) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 + +/* P2010 is single core version of P2020 */ #elif defined(CONFIG_P2010) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 @@ -154,21 +257,44 @@ #elif defined(CONFIG_PPC_P2040) #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 @@ -177,6 +303,8 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 @@ -186,16 +314,40 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 +#define CONFIG_SYS_P4080_ERRATUM_SERDES9 +#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 +#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 +/* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) #define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #else #error Processor type not defined for this platform diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 02a1f5d..127a840 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -84,6 +84,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 #define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_16_BE 0x00100000 #define SDRAM_CFG_8_BE 0x00040000 #define SDRAM_CFG_NCAP 0x00020000 #define SDRAM_CFG_2T_EN 0x00008000 @@ -270,7 +271,10 @@ typedef struct memctl_options_s { } memctl_options_t; extern phys_size_t fsl_ddr_sdram(void); +extern phys_size_t fsl_ddr_sdram_size(void); extern int fsl_use_spd(void); +extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num); /* * The 85xx boards have a common prototype for fixed_sdram so put the diff --git a/arch/powerpc/include/asm/fsl_enet.h b/arch/powerpc/include/asm/fsl_enet.h index 4fb2857..8227b66 100644 --- a/arch/powerpc/include/asm/fsl_enet.h +++ b/arch/powerpc/include/asm/fsl_enet.h @@ -13,21 +13,18 @@ #ifndef __ASM_PPC_FSL_ENET_H #define __ASM_PPC_FSL_ENET_H -enum fsl_phy_enet_if { - MII, - RMII, - GMII, - RGMII, - RGMII_ID, - RGMII_RXID, - RGMII_TXID, - SGMII, - TBI, - RTBI, - XAUI, - FSL_ETH_IF_NONE, -}; +#include <phy.h> -int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc); +struct tsec_mii_mng { + u32 miimcfg; /* MII management configuration reg */ + u32 miimcom; /* MII management command reg */ + u32 miimadd; /* MII management address reg */ + u32 miimcon; /* MII management control reg */ + u32 miimstat; /* MII management status reg */ + u32 miimind; /* MII management indication reg */ + u32 ifstat; /* Interface Status Register */ +} __attribute__ ((packed)); + +int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc); #endif /* __ASM_PPC_FSL_ENET_H */ diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h new file mode 100644 index 0000000..d4d9809 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_ifc.h @@ -0,0 +1,957 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Dipen Dudhat <dipen.dudhat@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_PPC_FSL_IFC_H +#define __ASM_PPC_FSL_IFC_H + +#include <config.h> +#include <common.h> + +/* + * CSPR - Chip Select Property Register + */ +#define CSPR_BA 0xFFFF0000 +#define CSPR_BA_SHIFT 16 +#define CSPR_PORT_SIZE 0x00000180 +#define CSPR_PORT_SIZE_SHIFT 7 +/* Port Size 8 bit */ +#define CSPR_PORT_SIZE_8 0x00000080 +/* Port Size 16 bit */ +#define CSPR_PORT_SIZE_16 0x00000100 +/* Port Size 32 bit */ +#define CSPR_PORT_SIZE_32 0x00000180 +/* Write Protect */ +#define CSPR_WP 0x00000040 +#define CSPR_WP_SHIFT 6 +/* Machine Select */ +#define CSPR_MSEL 0x00000006 +#define CSPR_MSEL_SHIFT 1 +/* NOR */ +#define CSPR_MSEL_NOR 0x00000000 +/* NAND */ +#define CSPR_MSEL_NAND 0x00000002 +/* GPCM */ +#define CSPR_MSEL_GPCM 0x00000004 +/* Bank Valid */ +#define CSPR_V 0x00000001 +#define CSPR_V_SHIFT 0 + +/* Convert an address into the right format for the CSPR Registers */ +#define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000) + +/* + * Address Mask Register + */ +#define IFC_AMASK_MASK 0xFFFF0000 +#define IFC_AMASK_SHIFT 16 +#define IFC_AMASK(n) (IFC_AMASK_MASK << \ + (__ilog2(n) - IFC_AMASK_SHIFT)) + +/* + * Chip Select Option Register IFC_NAND Machine + */ +/* Enable ECC Encoder */ +#define CSOR_NAND_ECC_ENC_EN 0x80000000 +/* 4 bit correction per 520 Byte sector */ +#define CSOR_NAND_ECC_MODE_4 0x00000000 +/* 8 bit correction per 528 Byte sector */ +#define CSOR_NAND_ECC_MODE_8 0x10000000 +/* Enable ECC Decoder */ +#define CSOR_NAND_ECC_DEC_EN 0x04000000 +/* Row Address Length */ +#define CSOR_NAND_RAL_MASK 0x01800000 +#define CSOR_NAND_RAL_SHIFT 20 +#define CSOR_NAND_RAL_1 0x00000000 +#define CSOR_NAND_RAL_2 0x00800000 +#define CSOR_NAND_RAL_3 0x01000000 +#define CSOR_NAND_RAL_4 0x01800000 +/* Page Size 512b, 2k, 4k */ +#define CSOR_NAND_PGS_MASK 0x00180000 +#define CSOR_NAND_PGS_SHIFT 16 +#define CSOR_NAND_PGS_512 0x00000000 +#define CSOR_NAND_PGS_2K 0x00080000 +#define CSOR_NAND_PGS_4K 0x00100000 +/* Spare region Size */ +#define CSOR_NAND_SPRZ_MASK 0x0000E000 +#define CSOR_NAND_SPRZ_SHIFT 13 +#define CSOR_NAND_SPRZ_16 0x00000000 +#define CSOR_NAND_SPRZ_64 0x00002000 +#define CSOR_NAND_SPRZ_128 0x00004000 +#define CSOR_NAND_SPRZ_210 0x00006000 +#define CSOR_NAND_SPRZ_218 0x00008000 +#define CSOR_NAND_SPRZ_224 0x0000A000 +/* Pages Per Block */ +#define CSOR_NAND_PB_MASK 0x00000700 +#define CSOR_NAND_PB_SHIFT 8 +#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_NAND_TRHZ_MASK 0x0000001C +#define CSOR_NAND_TRHZ_SHIFT 2 +#define CSOR_NAND_TRHZ_20 0x00000000 +#define CSOR_NAND_TRHZ_40 0x00000004 +#define CSOR_NAND_TRHZ_60 0x00000008 +#define CSOR_NAND_TRHZ_80 0x0000000C +#define CSOR_NAND_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_NAND_BCTLD 0x00000001 + +/* + * Chip Select Option Register - NOR Flash Mode + */ +/* Enable Address shift Mode */ +#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 +/* Page Read Enable from NOR device */ +#define CSOR_NOR_PGRD_EN 0x10000000 +/* AVD Toggle Enable during Burst Program */ +#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 +/* Address Data Multiplexing Shift */ +#define CSOR_NOR_ADM_MASK 0x0003E000 +#define CSOR_NOR_ADM_SHIFT_SHIFT 13 +#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) +/* Type of the NOR device hooked */ +#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 +#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_NOR_TRHZ_MASK 0x0000001C +#define CSOR_NOR_TRHZ_SHIFT 2 +#define CSOR_NOR_TRHZ_20 0x00000000 +#define CSOR_NOR_TRHZ_40 0x00000004 +#define CSOR_NOR_TRHZ_60 0x00000008 +#define CSOR_NOR_TRHZ_80 0x0000000C +#define CSOR_NOR_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_NOR_BCTLD 0x00000001 + +/* + * Chip Select Option Register - GPCM Mode + */ +/* GPCM Mode - Normal */ +#define CSOR_GPCM_GPMODE_NORMAL 0x00000000 +/* GPCM Mode - GenericASIC */ +#define CSOR_GPCM_GPMODE_ASIC 0x80000000 +/* Parity Mode odd/even */ +#define CSOR_GPCM_PARITY_EVEN 0x40000000 +/* Parity Checking enable/disable */ +#define CSOR_GPCM_PAR_EN 0x20000000 +/* GPCM Timeout Count */ +#define CSOR_GPCM_GPTO_MASK 0x0F000000 +#define CSOR_GPCM_GPTO_SHIFT 24 +#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) +/* GPCM External Access Termination mode for read access */ +#define CSOR_GPCM_RGETA_EXT 0x00080000 +/* GPCM External Access Termination mode for write access */ +#define CSOR_GPCM_WGETA_EXT 0x00040000 +/* Address Data Multiplexing Shift */ +#define CSOR_GPCM_ADM_MASK 0x0003E000 +#define CSOR_GPCM_ADM_SHIFT_SHIFT 13 +#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) +/* Generic ASIC Parity error indication delay */ +#define CSOR_GPCM_GAPERRD_MASK 0x00000180 +#define CSOR_GPCM_GAPERRD_SHIFT 7 +#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_GPCM_TRHZ_MASK 0x0000001C +#define CSOR_GPCM_TRHZ_20 0x00000000 +#define CSOR_GPCM_TRHZ_40 0x00000004 +#define CSOR_GPCM_TRHZ_60 0x00000008 +#define CSOR_GPCM_TRHZ_80 0x0000000C +#define CSOR_GPCM_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_GPCM_BCTLD 0x00000001 + +/* + * Flash Timing Registers (FTIM0 - FTIM2_CSn) + */ +/* + * FTIM0 - NAND Flash Mode + */ +#define FTIM0_NAND 0x7EFF3F3F +#define FTIM0_NAND_TCCST_SHIFT 25 +#define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) +#define FTIM0_NAND_TWP_SHIFT 16 +#define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) +#define FTIM0_NAND_TWCHT_SHIFT 8 +#define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) +#define FTIM0_NAND_TWH_SHIFT 0 +#define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) +/* + * FTIM1 - NAND Flash Mode + */ +#define FTIM1_NAND 0xFFFF3FFF +#define FTIM1_NAND_TADLE_SHIFT 24 +#define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT) +#define FTIM1_NAND_TWBE_SHIFT 16 +#define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT) +#define FTIM1_NAND_TRR_SHIFT 8 +#define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) +#define FTIM1_NAND_TRP_SHIFT 0 +#define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) +/* + * FTIM2 - NAND Flash Mode + */ +#define FTIM2_NAND 0x1FE1F8FF +#define FTIM2_NAND_TRAD_SHIFT 21 +#define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT) +#define FTIM2_NAND_TREH_SHIFT 11 +#define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT) +#define FTIM2_NAND_TWHRE_SHIFT 0 +#define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT) +/* + * FTIM3 - NAND Flash Mode + */ +#define FTIM3_NAND 0xFF000000 +#define FTIM3_NAND_TWW_SHIFT 24 +#define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) + +/* + * FTIM0 - NOR Flash Mode + */ +#define FTIM0_NOR 0xF03F3F3F +#define FTIM0_NOR_TACSE_SHIFT 28 +#define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) +#define FTIM0_NOR_TEADC_SHIFT 16 +#define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) +#define FTIM0_NOR_TAVDS_SHIFT 8 +#define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) +#define FTIM0_NOR_TEAHC_SHIFT 0 +#define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) +/* + * FTIM1 - NOR Flash Mode + */ +#define FTIM1_NOR 0xFF003F3F +#define FTIM1_NOR_TACO_SHIFT 24 +#define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) +#define FTIM1_NOR_TRAD_NOR_SHIFT 8 +#define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) +#define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 +#define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) +/* + * FTIM2 - NOR Flash Mode + */ +#define FTIM2_NOR 0x0F3CFCFF +#define FTIM2_NOR_TCS_SHIFT 24 +#define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) +#define FTIM2_NOR_TCH_SHIFT 18 +#define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) +#define FTIM2_NOR_TWPH_SHIFT 10 +#define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) +#define FTIM2_NOR_TWP_SHIFT 0 +#define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) + +/* + * FTIM0 - Normal GPCM Mode + */ +#define FTIM0_GPCM 0xF03F3F3F +#define FTIM0_GPCM_TACSE_SHIFT 28 +#define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) +#define FTIM0_GPCM_TEADC_SHIFT 16 +#define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) +#define FTIM0_GPCM_TAVDS_SHIFT 8 +#define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) +#define FTIM0_GPCM_TEAHC_SHIFT 0 +#define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) +/* + * FTIM1 - Normal GPCM Mode + */ +#define FTIM1_GPCM 0xFF003F00 +#define FTIM1_GPCM_TACO_SHIFT 24 +#define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) +#define FTIM1_GPCM_TRAD_SHIFT 8 +#define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) +/* + * FTIM2 - Normal GPCM Mode + */ +#define FTIM2_GPCM 0x0F3C00FF +#define FTIM2_GPCM_TCS_SHIFT 24 +#define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) +#define FTIM2_GPCM_TCH_SHIFT 18 +#define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) +#define FTIM2_GPCM_TWP_SHIFT 0 +#define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) + +/* + * Ready Busy Status Register (RB_STAT) + */ +/* CSn is READY */ +#define IFC_RB_STAT_READY_CS0 0x80000000 +#define IFC_RB_STAT_READY_CS1 0x40000000 +#define IFC_RB_STAT_READY_CS2 0x20000000 +#define IFC_RB_STAT_READY_CS3 0x10000000 + +/* + * General Control Register (GCR) + */ +#define IFC_GCR_MASK 0x8000F800 +/* reset all IFC hardware */ +#define IFC_GCR_SOFT_RST_ALL 0x80000000 +/* Turnaroud Time of external buffer */ +#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 +#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 + +/* + * Common Event and Error Status Register (CM_EVTER_STAT) + */ +/* Chip select error */ +#define IFC_CM_EVTER_STAT_CSER 0x80000000 + +/* + * Common Event and Error Enable Register (CM_EVTER_EN) + */ +/* Chip select error checking enable */ +#define IFC_CM_EVTER_EN_CSEREN 0x80000000 + +/* + * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) + */ +/* Chip select error interrupt enable */ +#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 + +/* + * Common Transfer Error Attribute Register-0 (CM_ERATTR0) + */ +/* transaction type of error Read/Write */ +#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 +#define IFC_CM_ERATTR0_ERAID 0x0FF00000 +#define IFC_CM_ERATTR0_ESRCID 0x0000FF00 + +/* + * Clock Control Register (CCR) + */ +#define IFC_CCR_MASK 0x0F0F8800 +/* Clock division ratio */ +#define IFC_CCR_CLK_DIV_MASK 0x0F000000 +#define IFC_CCR_CLK_DIV_SHIFT 24 +#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) +/* IFC Clock Delay */ +#define IFC_CCR_CLK_DLY_MASK 0x000F0000 +#define IFC_CCR_CLK_DLY_SHIFT 16 +#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) +/* Invert IFC clock before sending out */ +#define IFC_CCR_INV_CLK_EN 0x00008000 +/* Fedback IFC Clock */ +#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 + +/* + * Clock Status Register (CSR) + */ +/* Clk is stable */ +#define IFC_CSR_CLK_STAT_STABLE 0x80000000 + +/* + * IFC_NAND Machine Specific Registers + */ +/* + * NAND Configuration Register (NCFGR) + */ +/* Auto Boot Mode */ +#define IFC_NAND_NCFGR_BOOT 0x80000000 +/* Addressing Mode-ROW0+n/COL0 */ +#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 +/* Addressing Mode-ROW0+n/COL0+n */ +#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 +/* Number of loop iterations of FIR sequences for multi page operations */ +#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 +#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 +#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) +/* Number of wait cycles */ +#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF +#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 + +/* + * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) + */ +/* General purpose FCM flash command bytes CMD0-CMD7 */ +#define IFC_NAND_FCR0_CMD0 0xFF000000 +#define IFC_NAND_FCR0_CMD0_SHIFT 24 +#define IFC_NAND_FCR0_CMD1 0x00FF0000 +#define IFC_NAND_FCR0_CMD1_SHIFT 16 +#define IFC_NAND_FCR0_CMD2 0x0000FF00 +#define IFC_NAND_FCR0_CMD2_SHIFT 8 +#define IFC_NAND_FCR0_CMD3 0x000000FF +#define IFC_NAND_FCR0_CMD3_SHIFT 0 +#define IFC_NAND_FCR1_CMD4 0xFF000000 +#define IFC_NAND_FCR1_CMD4_SHIFT 24 +#define IFC_NAND_FCR1_CMD5 0x00FF0000 +#define IFC_NAND_FCR1_CMD5_SHIFT 16 +#define IFC_NAND_FCR1_CMD6 0x0000FF00 +#define IFC_NAND_FCR1_CMD6_SHIFT 8 +#define IFC_NAND_FCR1_CMD7 0x000000FF +#define IFC_NAND_FCR1_CMD7_SHIFT 0 + +/* + * Flash ROW and COL Address Register (ROWn, COLn) + */ +/* Main/spare region locator */ +#define IFC_NAND_COL_MS 0x80000000 +/* Column Address */ +#define IFC_NAND_COL_CA_MASK 0x00000FFF + +/* + * NAND Flash Byte Count Register (NAND_BC) + */ +/* Byte Count for read/Write */ +#define IFC_NAND_BC 0x000001FF + +/* + * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) + */ +/* NAND Machine specific opcodes OP0-OP14*/ +#define IFC_NAND_FIR0_OP0 0xFC000000 +#define IFC_NAND_FIR0_OP0_SHIFT 26 +#define IFC_NAND_FIR0_OP1 0x03F00000 +#define IFC_NAND_FIR0_OP1_SHIFT 20 +#define IFC_NAND_FIR0_OP2 0x000FC000 +#define IFC_NAND_FIR0_OP2_SHIFT 14 +#define IFC_NAND_FIR0_OP3 0x00003F00 +#define IFC_NAND_FIR0_OP3_SHIFT 8 +#define IFC_NAND_FIR0_OP4 0x000000FC +#define IFC_NAND_FIR0_OP4_SHIFT 2 +#define IFC_NAND_FIR1_OP5 0xFC000000 +#define IFC_NAND_FIR1_OP5_SHIFT 26 +#define IFC_NAND_FIR1_OP6 0x03F00000 +#define IFC_NAND_FIR1_OP6_SHIFT 20 +#define IFC_NAND_FIR1_OP7 0x000FC000 +#define IFC_NAND_FIR1_OP7_SHIFT 14 +#define IFC_NAND_FIR1_OP8 0x00003F00 +#define IFC_NAND_FIR1_OP8_SHIFT 8 +#define IFC_NAND_FIR1_OP9 0x000000FC +#define IFC_NAND_FIR1_OP9_SHIFT 2 +#define IFC_NAND_FIR2_OP10 0xFC000000 +#define IFC_NAND_FIR2_OP10_SHIFT 26 +#define IFC_NAND_FIR2_OP11 0x03F00000 +#define IFC_NAND_FIR2_OP11_SHIFT 20 +#define IFC_NAND_FIR2_OP12 0x000FC000 +#define IFC_NAND_FIR2_OP12_SHIFT 14 +#define IFC_NAND_FIR2_OP13 0x00003F00 +#define IFC_NAND_FIR2_OP13_SHIFT 8 +#define IFC_NAND_FIR2_OP14 0x000000FC +#define IFC_NAND_FIR2_OP14_SHIFT 2 + +/* + * Instruction opcodes to be programmed + * in FIR registers- 6bits + */ +enum ifc_nand_fir_opcodes { + IFC_FIR_OP_NOP, + IFC_FIR_OP_CA0, + IFC_FIR_OP_CA1, + IFC_FIR_OP_CA2, + IFC_FIR_OP_CA3, + IFC_FIR_OP_RA0, + IFC_FIR_OP_RA1, + IFC_FIR_OP_RA2, + IFC_FIR_OP_RA3, + IFC_FIR_OP_CMD0, + IFC_FIR_OP_CMD1, + IFC_FIR_OP_CMD2, + IFC_FIR_OP_CMD3, + IFC_FIR_OP_CMD4, + IFC_FIR_OP_CMD5, + IFC_FIR_OP_CMD6, + IFC_FIR_OP_CMD7, + IFC_FIR_OP_CW0, + IFC_FIR_OP_CW1, + IFC_FIR_OP_CW2, + IFC_FIR_OP_CW3, + IFC_FIR_OP_CW4, + IFC_FIR_OP_CW5, + IFC_FIR_OP_CW6, + IFC_FIR_OP_CW7, + IFC_FIR_OP_WBCD, + IFC_FIR_OP_RBCD, + IFC_FIR_OP_BTRD, + IFC_FIR_OP_RDSTAT, + IFC_FIR_OP_NWAIT, + IFC_FIR_OP_WFR, + IFC_FIR_OP_SBRD, + IFC_FIR_OP_UA, + IFC_FIR_OP_RB, +}; + +/* + * NAND Chip Select Register (NAND_CSEL) + */ +#define IFC_NAND_CSEL 0x0C000000 +#define IFC_NAND_CSEL_SHIFT 26 +#define IFC_NAND_CSEL_CS0 0x00000000 +#define IFC_NAND_CSEL_CS1 0x04000000 +#define IFC_NAND_CSEL_CS2 0x08000000 +#define IFC_NAND_CSEL_CS3 0x0C000000 + +/* + * NAND Operation Sequence Start (NANDSEQ_STRT) + */ +/* NAND Flash Operation Start */ +#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 +/* Automatic Erase */ +#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 +/* Automatic Program */ +#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 +/* Automatic Copyback */ +#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 +/* Automatic Read Operation */ +#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 +/* Automatic Status Read */ +#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 + +/* + * NAND Event and Error Status Register (NAND_EVTER_STAT) + */ +/* Operation Complete */ +#define IFC_NAND_EVTER_STAT_OPC 0x80000000 +/* Flash Timeout Error */ +#define IFC_NAND_EVTER_STAT_FTOER 0x08000000 +/* Write Protect Error */ +#define IFC_NAND_EVTER_STAT_WPER 0x04000000 +/* ECC Error */ +#define IFC_NAND_EVTER_STAT_ECCER 0x02000000 +/* RCW Load Done */ +#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 +/* Boot Loadr Done */ +#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 +/* Bad Block Indicator search select */ +#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 + +/* + * NAND Flash Page Read Completion Event Status Register + * (PGRDCMPL_EVT_STAT) + */ +#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 +/* Small Page 0-15 Done */ +#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) +/* Large Page(2K) 0-3 Done */ +#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) +/* Large Page(4K) 0-1 Done */ +#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) + +/* + * NAND Event and Error Enable Register (NAND_EVTER_EN) + */ +/* Operation complete event enable */ +#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 +/* Page read complete event enable */ +#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 +/* Flash Timeout error enable */ +#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 +/* Write Protect error enable */ +#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 +/* ECC error logging enable */ +#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 + +/* + * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) + */ +/* Enable interrupt for operation complete */ +#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 +/* Enable interrupt for Page read complete */ +#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 +/* Enable interrupt for Flash timeout error */ +#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 +/* Enable interrupt for Write protect error */ +#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 +/* Enable interrupt for ECC error*/ +#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 + +/* + * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) + */ +#define IFC_NAND_ERATTR0_MASK 0x0C080000 +/* Error on CS0-3 for NAND */ +#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 +#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 +#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 +/* Transaction type of error Read/Write */ +#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 + +/* + * NAND Flash Status Register (NAND_FSR) + */ +/* First byte of data read from read status op */ +#define IFC_NAND_NFSR_RS0 0xFF000000 +/* Second byte of data read from read status op */ +#define IFC_NAND_NFSR_RS1 0x00FF0000 + +/* + * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) + */ +/* Number of ECC errors on sector n (n = 0-15) */ +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 + +/* + * NAND Control Register (NANDCR) + */ +#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 +#define IFC_NAND_NCR_FTOCNT_SHIFT 25 +#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) + +/* + * NAND_AUTOBOOT_TRGR + */ +/* Trigger RCW load */ +#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 +/* Trigget Auto Boot */ +#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 + +/* + * NAND_MDR + */ +/* 1st read data byte when opcode SBRD */ +#define IFC_NAND_MDR_RDATA0 0xFF000000 +/* 2nd read data byte when opcode SBRD */ +#define IFC_NAND_MDR_RDATA1 0x00FF0000 + +/* + * NOR Machine Specific Registers + */ +/* + * NOR Event and Error Status Register (NOR_EVTER_STAT) + */ +/* NOR Command Sequence Operation Complete */ +#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 +/* Write Protect Error */ +#define IFC_NOR_EVTER_STAT_WPER 0x04000000 +/* Command Sequence Timeout Error */ +#define IFC_NOR_EVTER_STAT_STOER 0x01000000 + +/* + * NOR Event and Error Enable Register (NOR_EVTER_EN) + */ +/* NOR Command Seq complete event enable */ +#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 +/* Write Protect Error Checking Enable */ +#define IFC_NOR_EVTER_EN_WPEREN 0x04000000 +/* Timeout Error Enable */ +#define IFC_NOR_EVTER_EN_STOEREN 0x01000000 + +/* + * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) + */ +/* Enable interrupt for OPC complete */ +#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 +/* Enable interrupt for write protect error */ +#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 +/* Enable interrupt for timeout error */ +#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 + +/* + * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) + */ +/* Source ID for error transaction */ +#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 +/* AXI ID for error transation */ +#define IFC_NOR_ERATTR0_ERAID 0x000FF000 +/* Chip select corresponds to NOR error */ +#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 +#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 +#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 +/* Type of transaction read/write */ +#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 + +/* + * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) + */ +#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 +#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 + +/* + * NOR Control Register (NORCR) + */ +#define IFC_NORCR_MASK 0x0F0F0000 +/* No. of Address/Data Phase */ +#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 +#define IFC_NORCR_NUM_PHASE_SHIFT 24 +#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) +/* Sequence Timeout Count */ +#define IFC_NORCR_STOCNT_MASK 0x000F0000 +#define IFC_NORCR_STOCNT_SHIFT 16 +#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) + +/* + * GPCM Machine specific registers + */ +/* + * GPCM Event and Error Status Register (GPCM_EVTER_STAT) + */ +/* Timeout error */ +#define IFC_GPCM_EVTER_STAT_TOER 0x04000000 +/* Parity error */ +#define IFC_GPCM_EVTER_STAT_PER 0x01000000 + +/* + * GPCM Event and Error Enable Register (GPCM_EVTER_EN) + */ +/* Timeout error enable */ +#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 +/* Parity error enable */ +#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 + +/* + * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) + */ +/* Enable Interrupt for timeout error */ +#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 +/* Enable Interrupt for Parity error */ +#define IFC_GPCM_EEIER_PERIR_EN 0x01000000 + +/* + * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) + */ +/* Source ID for error transaction */ +#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 +/* AXI ID for error transaction */ +#define IFC_GPCM_ERATTR0_ERAID 0x000FF000 +/* Chip select corresponds to GPCM error */ +#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 +#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 +#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 +/* Type of transaction read/Write */ +#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 + +/* + * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) + */ +/* On which beat of address/data parity error is observed */ +#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 +/* Parity Error on byte */ +#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 +/* Parity Error reported in addr or data phase */ +#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 + +/* + * GPCM Status Register (GPCM_STAT) + */ +#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ + + +#ifndef __ASSEMBLY__ +#include <asm/io.h> + +extern void print_ifc_regs(void); +extern void init_early_memctl_regs(void); + +#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) + +#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) +#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) +#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) +#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) + +#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) +#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) +#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) +#define set_ifc_ftim(i, j, v) \ + (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) + +#define FSL_IFC_BANK_COUNT 4 + +enum ifc_chip_sel { + IFC_CS0, + IFC_CS1, + IFC_CS2, + IFC_CS3, +}; + +enum ifc_ftims { + IFC_FTIM0, + IFC_FTIM1, + IFC_FTIM2, + IFC_FTIM3, +}; + +/* + * IFC Controller NAND Machine registers + */ +struct fsl_ifc_nand { + u32 ncfgr; + u32 res1[0x4]; + u32 nand_fcr0; + u32 nand_fcr1; + u32 res2[0x8]; + u32 row0; + u32 res3; + u32 col0; + u32 res4; + u32 row1; + u32 res5; + u32 col1; + u32 res6; + u32 row2; + u32 res7; + u32 col2; + u32 res8; + u32 row3; + u32 res9; + u32 col3; + u32 res10[0x24]; + u32 nand_fbcr; + u32 res11; + u32 nand_fir0; + u32 nand_fir1; + u32 nand_fir2; + u32 res12[0x10]; + u32 nand_csel; + u32 res13; + u32 nandseq_strt; + u32 res14; + u32 nand_evter_stat; + u32 res15; + u32 pgrdcmpl_evt_stat; + u32 res16[0x2]; + u32 nand_evter_en; + u32 res17[0x2]; + u32 nand_evter_intr_en; + u32 res18[0x2]; + u32 nand_erattr0; + u32 nand_erattr1; + u32 res19[0x10]; + u32 nand_fsr; + u32 res20; + u32 nand_eccstat0; + u32 nand_eccstat1; + u32 nand_eccstat2; + u32 nand_eccstat3; + u32 res21[0x20]; + u32 nanndcr; + u32 res22[0x2]; + u32 nand_autoboot_trgr; + u32 res23; + u32 nand_mdr; + u32 res24[0x5C]; +}; + +/* + * IFC controller NOR Machine registers + */ +struct fsl_ifc_nor { + u32 nor_evter_stat; + u32 res1[0x2]; + u32 nor_evter_en; + u32 res2[0x2]; + u32 nor_evter_intr_en; + u32 res3[0x2]; + u32 nor_erattr0; + u32 nor_erattr1; + u32 nor_erattr2; + u32 res4[0x4]; + u32 norcr; + u32 res5[0xEF]; +}; + +/* + * IFC controller GPCM Machine registers + */ +struct fsl_ifc_gpcm { + u32 gpcm_evter_stat; + u32 res1[0x2]; + u32 gpcm_evter_en; + u32 res2[0x2]; + u32 gpcm_evter_intr_en; + u32 res3[0x2]; + u32 gpcm_erattr0; + u32 gpcm_erattr1; + u32 gpcm_erattr2; + u32 gpcm_stat; + u32 res4[0x1F3]; +}; + + +/* + * IFC Controller Registers + */ +struct fsl_ifc { + u32 ifc_rev; + u32 res1[0x3]; + struct { + u32 cspr; + u32 res2[0x2]; + } cspr_cs[FSL_IFC_BANK_COUNT]; + u32 res3[0x18]; + struct { + u32 amask; + u32 res4[0x2]; + } amask_cs[FSL_IFC_BANK_COUNT]; + u32 res5[0x18]; + struct { + u32 csor; + u32 res6[0x2]; + } csor_cs[FSL_IFC_BANK_COUNT]; + u32 res7[0x18]; + struct { + u32 ftim[4]; + u32 res8[0x8]; + } ftim_cs[FSL_IFC_BANK_COUNT]; + u32 res9[0x60]; + u32 rb_stat; + u32 res10[0x2]; + u32 ifc_gcr; + u32 res11[0x2]; + u32 cm_evter_stat; + u32 res12[0x2]; + u32 cm_evter_en; + u32 res13[0x2]; + u32 cm_evter_intr_en; + u32 res14[0x2]; + u32 cm_erattr0; + u32 cm_erattr1; + u32 res15[0x2]; + u32 ifc_ccr; + u32 ifc_csr; + u32 res16[0x2EB]; + struct fsl_ifc_nand ifc_nand; + struct fsl_ifc_nor ifc_nor; + struct fsl_ifc_gpcm ifc_gpcm; +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_PPC_FSL_IFC_H */ diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 6a4279c..13caffd 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -83,6 +83,7 @@ enum law_trgt_if { LAW_TRGT_IF_DDR_INTRLV = 0x0b, LAW_TRGT_IF_RIO = 0x0c, LAW_TRGT_IF_RIO_2 = 0x0d, + LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e, LAW_TRGT_IF_DDR = 0x0f, LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ }; @@ -91,6 +92,7 @@ enum law_trgt_if { #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 #define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO +#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC #ifdef CONFIG_MPC8641 #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 4c17fe2..801571f 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -70,8 +70,8 @@ extern void fdt_fixup_liodn(void *blob); SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\ CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET) -#define SET_PCI_LIODN(pciNum, liodn) \ - SET_GUTS_LIODN("fsl,p4080-pcie", liodn, pex##pciNum##liodnr,\ +#define SET_PCI_LIODN(compat, pciNum, liodn) \ + SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\ CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) /* reg nodes for DMA start @ 0x300 */ @@ -85,13 +85,13 @@ extern void fdt_fixup_liodn(void *blob); #define SET_QMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \ - CONFIG_SYS_FSL_CORENET_QMAN_OFFSET, \ - CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) + CONFIG_SYS_FSL_QMAN_OFFSET, \ + CONFIG_SYS_FSL_QMAN_OFFSET) #define SET_BMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \ - CONFIG_SYS_FSL_CORENET_BMAN_OFFSET, \ - CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) + CONFIG_SYS_FSL_BMAN_OFFSET, \ + CONFIG_SYS_FSL_BMAN_OFFSET) #define SET_PME_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \ @@ -115,10 +115,18 @@ extern void fdt_fixup_liodn(void *blob); FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \ +/* + * handle both old and new versioned SEC properties: + * "fsl,secX.Y" became "fsl,sec-vX.Y" during development + */ #define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \ SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\ offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \ + SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\ + offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum) /* This is a bit evil since we treat rtic param as both a string & hex value */ @@ -127,6 +135,11 @@ extern void fdt_fixup_liodn(void *blob); liodnA, \ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \ + SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \ + liodnA, \ + offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)) #define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \ diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 0a98bde..fc47a9f 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -1,5 +1,5 @@ /* - * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. + * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -25,6 +25,9 @@ #include <asm/fsl_serdes.h> #include <pci.h> +#define PEX_IP_BLK_REV_2_2 0x02080202 +#define PEX_IP_BLK_REV_2_3 0x02080203 + int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); void fsl_pci_config_unlock(struct pci_controller *hose); @@ -73,7 +76,8 @@ typedef struct ccsr_pci { u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */ u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */ u32 config; /* 0x014 - PCIE CONFIG Register */ - char res2[8]; + u32 int_status; /* 0x018 - PCIE interrupt status register */ + char res2[4]; u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */ u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ @@ -83,8 +87,11 @@ typedef struct ccsr_pci { u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */ - u32 res5[64]; - pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */ + u32 res5[24]; + pit_t pmit; /* 0xd00 - 0xd9c Inbound ATMU's MSI */ + u32 res6[24]; + pit_t pit[4]; /* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */ + #define PIT3 0 #define PIT2 1 #define PIT1 2 @@ -158,6 +165,11 @@ typedef struct ccsr_pci { u32 pdb_stat; /* 0xf00 - PCIE Debug Status */ char res24[252]; } ccsr_fsl_pci_t; +#define PCIE_CONFIG_PC 0x00020000 +#define PCIE_CONFIG_OB_CK 0x00002000 +#define PCIE_CONFIG_SAC 0x00000010 +#define PCIE_CONFIG_SP 0x80000002 +#define PCIE_CONFIG_SCC 0x80000001 struct fsl_pci_info { unsigned long regs; @@ -218,7 +230,9 @@ int fsl_pcie_init_board(int busno); #define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3) #define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4) -#if defined(CONFIG_FSL_CORENET) +#if !defined(CONFIG_PCI) +#define FT_FSL_PCI_SETUP +#elif defined(CONFIG_FSL_CORENET) #define FSL_PCIE_COMPAT "fsl,p4080-pcie" #define FT_FSL_PCI_SETUP \ FT_FSL_PCIE1_SETUP; \ diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h index cb32927..e1c1212 100644 --- a/arch/powerpc/include/asm/fsl_portals.h +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -51,6 +51,7 @@ extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, u32 *liodns, int liodn_offset); extern void setup_portals(void); extern void fdt_fixup_qportals(void *blob); +extern void fdt_fixup_bportals(void *blob); extern struct qportal_info qp_info[]; extern void fdt_portal(void *blob, const char *compat, const char *container, diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 85518eb..0f31af1 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -53,4 +53,11 @@ enum srds_prtcl { int is_serdes_configured(enum srds_prtcl device); void fsl_serdes_init(void); +#ifdef CONFIG_FSL_CORENET +int serdes_get_first_lane(enum srds_prtcl device); +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 +void serdes_reset_rx(enum srds_prtcl device); +#endif +#endif + #endif /* __FSL_SERDES_H */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 6bd83ba..f85cee2 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -31,6 +31,7 @@ #include <asm/types.h> #include <asm/fsl_dma.h> #include <asm/fsl_i2c.h> +#include <asm/fsl_ifc.h> #include <asm/fsl_lbc.h> #include <asm/fsl_fman.h> @@ -1864,8 +1865,13 @@ typedef struct ccsr_gur { #define MPC85xx_PORBMSR_HA_SHIFT 16 u32 porimpscr; /* POR I/O impedance status & control */ u32 pordevsr; /* POR I/O device status regsiter */ +#if defined(CONFIG_P1017) || defined(CONFIG_P1023) +#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000 +#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000 +#else #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 +#endif #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 @@ -1873,9 +1879,17 @@ typedef struct ccsr_gur { #if defined(CONFIG_P1013) || defined(CONFIG_P1022) #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 +#elif defined(CONFIG_P1017) || defined(CONFIG_P1023) +#define MPC85xx_PORDEVSR_IO_SEL 0x00600000 +#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 +#else +#if defined(CONFIG_P1010) +#define MPC85xx_PORDEVSR_IO_SEL 0x00600000 +#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 #else #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 +#endif /* if defined(CONFIG_P1010) */ #endif #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 @@ -1906,10 +1920,106 @@ typedef struct ccsr_gur { u32 gpindr; /* General-purpose input data */ u8 res5[12]; u32 pmuxcr; /* Alt. function signal multiplex control */ +#if defined(CONFIG_P1010) || defined(CONFIG_P1014) +#define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000 +#define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000 +#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000 +#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000 +#define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000 +#define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000 +#define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000 +#define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000 +#define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000 +#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000 +#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000 +#define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000 +#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000 +#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000 +#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000 +#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000 +#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000 +#define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000 +#define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000 +#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000 +#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000 +#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000 +#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000 +#define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000 +#define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000 +#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000 +#define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000 +#define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000 +#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400 +#define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800 +#define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00 +#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300 +#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200 +#define MPC85xx_PMUXCR_LCLK_RES 0x00000040 +#define MPC85xx_PMUXCR_LCLK_USB 0x00000080 +#define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0 +#define MPC85xx_PMUXCR_SPI_RES 0x00000030 +#define MPC85xx_PMUXCR_SPI_GPIO 0x00000020 +#define MPC85xx_PMUXCR_CAN1_UART 0x00000004 +#define MPC85xx_PMUXCR_CAN1_TDM 0x00000008 +#define MPC85xx_PMUXCR_CAN1_RES 0x0000000C +#define MPC85xx_PMUXCR_CAN2_UART 0x00000001 +#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002 +#define MPC85xx_PMUXCR_CAN2_RES 0x00000003 +#endif #define MPC85xx_PMUXCR_SD_DATA 0x80000000 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 +#define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000 +#define MPC85xx_PMUXCR_TDM_ENA 0x00800000 +#define MPC85xx_PMUXCR_QE0 0x00008000 +#define MPC85xx_PMUXCR_QE1 0x00004000 +#define MPC85xx_PMUXCR_QE2 0x00002000 +#define MPC85xx_PMUXCR_QE3 0x00001000 +#define MPC85xx_PMUXCR_QE4 0x00000800 +#define MPC85xx_PMUXCR_QE5 0x00000400 +#define MPC85xx_PMUXCR_QE6 0x00000200 +#define MPC85xx_PMUXCR_QE7 0x00000100 +#define MPC85xx_PMUXCR_QE8 0x00000080 +#define MPC85xx_PMUXCR_QE9 0x00000040 +#define MPC85xx_PMUXCR_QE10 0x00000020 +#define MPC85xx_PMUXCR_QE11 0x00000010 +#define MPC85xx_PMUXCR_QE12 0x00000008 +#if defined(CONFIG_P1013) || defined(CONFIG_P1022) +#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00 +#define MPC85xx_PMUXCR_TDM 0x00014800 +#define MPC85xx_PMUXCR_SPI_MASK 0x00600000 +#define MPC85xx_PMUXCR_SPI 0x00000000 +#endif u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ +#if defined(CONFIG_P1010) || defined(CONFIG_P1014) +#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 +#define MPC85xx_PMUXCR2_UART_TDM 0x80000000 +#define MPC85xx_PMUXCR2_UART_RES 0xC0000000 +#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000 +#define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000 +#define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000 +#define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000 +#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000 +#define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000 +#define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000 +#define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000 +#define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000 +#define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000 +#define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000 +#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000 +#define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000 +#define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000 +#define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000 +#define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000 +#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000 +#define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000 +#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 +#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 +#endif +#if defined(CONFIG_P1013) || defined(CONFIG_P1022) +#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f1000 +#define MPC85xx_PMUXCR2_USB 0x00150000 +#endif u8 res6[8]; u32 devdisr; /* Device disable control */ #define MPC85xx_DEVDISR_PCI1 0x80000000 @@ -1942,32 +2052,43 @@ typedef struct ccsr_gur { u8 res9[12]; u32 pvr; /* Processor version */ u32 svr; /* System version */ - u8 res10a[8]; + u8 res10[8]; u32 rstcr; /* Reset control */ #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) - u8 res10b[76]; + u8 res11a[76]; par_io_t qe_par_io[7]; - u8 res10c[1600]; + u8 res11b[1600]; +#elif defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ + defined(CONFIG_P1021) || defined(CONFIG_P1025) + u8 res11a[12]; + u32 iovselsr; + u8 res11b[60]; + par_io_t qe_par_io[3]; + u8 res11c[1496]; #else - u8 res10b[1868]; + u8 res11a[1868]; #endif u32 clkdvdr; /* Clock Divide register */ - u8 res10d[1532]; + u8 res12[1532]; u32 clkocr; /* Clock out select */ - u8 res11[12]; + u8 res13[12]; u32 ddrdllcr; /* DDR DLL control */ - u8 res12[12]; + u8 res14[12]; u32 lbcdllcr; /* LBC DLL control */ - u8 res13[248]; + u8 res15[248]; u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */ u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */ u32 ddrioovcr; /* DDR IO Override Control */ u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */ u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */ - u8 res15[61648]; + u8 res16[52]; + u32 sdhcdcr; /* SDHC debug control register */ + u8 res17[61592]; } ccsr_gur_t; #endif +#define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */ + typedef struct serdes_corenet { struct { u32 rstctl; /* Reset Control Register */ @@ -1980,6 +2101,7 @@ typedef struct serdes_corenet { #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 +#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000 @@ -2016,6 +2138,9 @@ typedef struct serdes_corenet { #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000 u32 res3; u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */ +#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000 +#define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000 +#define SRDS_TTLCR0_PM_DIS 0x00004000 u32 res4[7]; } lane[24]; u32 res6[384]; @@ -2164,6 +2289,13 @@ typedef struct ccsr_pme { u8 res4[0x400]; } ccsr_pme_t; +typedef struct ccsr_usb_phy { + u8 res0[0x18]; + u32 usb_enable_override; + u8 res[0xe4]; +} ccsr_usb_phy_t; +#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 + #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 @@ -2186,12 +2318,14 @@ typedef struct ccsr_pme { #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 #define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET +#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000 +#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 -#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 -#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 +#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 +#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 @@ -2227,6 +2361,7 @@ typedef struct ccsr_pme { #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 +#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 @@ -2240,6 +2375,12 @@ typedef struct ccsr_pme { #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 +#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000 +#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000 +#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000 +#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000 +#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000 +#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000 #endif #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 @@ -2247,10 +2388,10 @@ typedef struct ccsr_pme { #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) -#define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) -#define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) +#define CONFIG_SYS_FSL_QMAN_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) +#define CONFIG_SYS_FSL_BMAN_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET) #define CONFIG_SYS_FSL_CORENET_PME_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ @@ -2269,6 +2410,8 @@ typedef struct ccsr_pme { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) #define CONFIG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) +#define CONFIG_SYS_IFC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET) #define CONFIG_SYS_MPC85xx_ESPI_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) #define CONFIG_SYS_MPC85xx_PCIX_ADDR \ @@ -2299,6 +2442,10 @@ typedef struct ccsr_pme { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) #define CONFIG_SYS_MPC85xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) +#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET) +#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET) #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_FM1_ADDR \ diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h index 531cfc8..9be9dca 100644 --- a/arch/powerpc/include/asm/immap_qe.h +++ b/arch/powerpc/include/asm/immap_qe.h @@ -3,7 +3,7 @@ * The Internal Memory Map for devices with QE on them. This * is the superset of all QE devices (8360, etc.). * - * Copyright (c) 2006-2009 Freescale Semiconductor, Inc. + * Copyright (c) 2006-2009, 2011 Freescale Semiconductor, Inc. * Author: Shlomi Gridih <gridish@freescale.com> * * This program is free software; you can redistribute it and/or modify it @@ -15,8 +15,19 @@ #ifndef __IMMAP_QE_H__ #define __IMMAP_QE_H__ -/* QE I-RAM -*/ +#ifdef CONFIG_MPC83xx +#if defined(CONFIG_MPC8360) +#define QE_MURAM_SIZE 0xc000UL +#define MAX_QE_RISC 2 +#define QE_NUM_OF_SNUM 28 +#elif defined(CONFIG_MPC832x) +#define QE_MURAM_SIZE 0x4000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 +#endif +#endif + +/* QE I-RAM */ typedef struct qe_iram { u32 iadd; /* I-RAM Address Register */ u32 idata; /* I-RAM Data Register */ @@ -25,8 +36,7 @@ typedef struct qe_iram { u8 res1[0x70]; } __attribute__ ((packed)) qe_iram_t; -/* QE Interrupt Controller -*/ +/* QE Interrupt Controller */ typedef struct qe_ic { u32 qicr; u32 qivec; @@ -49,8 +59,7 @@ typedef struct qe_ic { u8 res3[0x1C]; } __attribute__ ((packed)) qe_ic_t; -/* Communications Processor -*/ +/* Communications Processor */ typedef struct cp_qe { u32 cecr; /* QE command register */ u32 ceccr; /* QE controller configuration register */ @@ -87,8 +96,7 @@ typedef struct cp_qe { u8 res13[0x280]; } __attribute__ ((packed)) cp_qe_t; -/* QE Multiplexer -*/ +/* QE Multiplexer */ typedef struct qe_mux { u32 cmxgcr; /* CMX general clock route register */ u32 cmxsi1cr_l; /* CMX SI1 clock route low register */ @@ -102,8 +110,7 @@ typedef struct qe_mux { u8 res0[0x1C]; } __attribute__ ((packed)) qe_mux_t; -/* QE Timers -*/ +/* QE Timers */ typedef struct qe_timers { u8 gtcfr1; /* Timer 1 2 global configuration register */ u8 res0[0x3]; @@ -133,8 +140,7 @@ typedef struct qe_timers { u8 res2[0x46]; } __attribute__ ((packed)) qe_timers_t; -/* BRG -*/ +/* BRG */ typedef struct qe_brg { u32 brgc1; /* BRG1 configuration register */ u32 brgc2; /* BRG2 configuration register */ @@ -155,8 +161,7 @@ typedef struct qe_brg { u8 res0[0x40]; } __attribute__ ((packed)) qe_brg_t; -/* SPI -*/ +/* SPI */ typedef struct spi { u8 res0[0x20]; u32 spmode; /* SPI mode register */ @@ -174,8 +179,7 @@ typedef struct spi { u8 res7[0x8]; } __attribute__ ((packed)) spi_t; -/* SI -*/ +/* SI */ typedef struct si1 { u16 siamr1; /* SI1 TDMA mode register */ u16 sibmr1; /* SI1 TDMB mode register */ @@ -222,16 +226,14 @@ typedef struct si1 { u8 res9[0xBB]; } __attribute__ ((packed)) si1_t; -/* SI Routing Tables -*/ +/* SI Routing Tables */ typedef struct sir { u8 tx[0x400]; u8 rx[0x400]; u8 res0[0x800]; } __attribute__ ((packed)) sir_t; -/* USB Controller. -*/ +/* USB Controller. */ typedef struct usb_ctlr { u8 usb_usmod; u8 usb_usadr; @@ -253,8 +255,7 @@ typedef struct usb_ctlr { u8 res6[0x22]; } __attribute__ ((packed)) usb_t; -/* MCC -*/ +/* MCC */ typedef struct mcc { u32 mcce; /* MCC event register */ u32 mccm; /* MCC mask register */ @@ -263,8 +264,7 @@ typedef struct mcc { u8 res0[0xF0]; } __attribute__ ((packed)) mcc_t; -/* QE UCC Slow -*/ +/* QE UCC Slow */ typedef struct ucc_slow { u32 gumr_l; /* UCCx general mode register (low) */ u32 gumr_h; /* UCCx general mode register (high) */ @@ -368,8 +368,7 @@ typedef struct ucc_ethernet { u8 res5[0x200 - 0x1c4]; } __attribute__ ((packed)) uec_t; -/* QE UCC Fast -*/ +/* QE UCC Fast */ typedef struct ucc_fast { u32 gumr; /* UCCx general mode register */ u32 upsmr; /* UCCx protocol-specific mode register */ @@ -403,8 +402,7 @@ typedef struct ucc_fast { uec_t ucc_eth; } __attribute__ ((packed)) ucc_fast_t; -/* QE UCC -*/ +/* QE UCC */ typedef struct ucc_common { u8 res1[0x90]; u8 guemr; @@ -419,8 +417,7 @@ typedef struct ucc { }; } __attribute__ ((packed)) ucc_t; -/* MultiPHY UTOPIA POS Controllers (UPC) -*/ +/* MultiPHY UTOPIA POS Controllers (UPC) */ typedef struct upc { u32 upgcr; /* UTOPIA/POS general configuration register */ u32 uplpa; /* UTOPIA/POS last PHY address */ @@ -476,8 +473,7 @@ typedef struct upc { u8 res2[0x150]; } __attribute__ ((packed)) upc_t; -/* SDMA -*/ +/* SDMA */ typedef struct sdma { u32 sdsr; /* Serial DMA status register */ u32 sdmr; /* Serial DMA mode register */ @@ -497,8 +493,7 @@ typedef struct sdma { u8 res2[0x38]; } __attribute__ ((packed)) sdma_t; -/* Debug Space -*/ +/* Debug Space */ typedef struct dbg { u32 bpdcr; /* Breakpoint debug command register */ u32 bpdsr; /* Breakpoint debug status register */ @@ -582,40 +577,9 @@ typedef struct qe_immap { u8 res14[0x300]; u8 res15[0x3A00]; u8 res16[0x8000]; /* 0x108000 - 0x110000 */ -#if defined(CONFIG_MPC8568) - u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */ - u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */ -#elif defined(CONFIG_MPC8569) - u8 muram[0x20000]; /* 0x1_0000 - 0x3_0000 Multi-user RAM */ - u8 res17[0x10000]; /* 0x3_0000 - 0x4_0000 */ -#else - u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ - u8 res17[0x24000]; /* 0x11C000 - 0x140000 */ - u8 res18[0xC0000]; /* 0x140000 - 0x200000 */ -#endif + u8 muram[QE_MURAM_SIZE]; } __attribute__ ((packed)) qe_map_t; extern qe_map_t *qe_immr; -#if defined(CONFIG_MPC8568) -#define QE_MURAM_SIZE 0x10000UL -#elif defined(CONFIG_MPC8569) -#define QE_MURAM_SIZE 0x20000UL -#elif defined(CONFIG_MPC8360) -#define QE_MURAM_SIZE 0xc000UL -#elif defined(CONFIG_MPC832x) -#define QE_MURAM_SIZE 0x4000UL -#endif - -#if defined(CONFIG_MPC8323) -#define MAX_QE_RISC 1 -#define QE_NUM_OF_SNUM 28 -#elif defined(CONFIG_MPC8569) -#define MAX_QE_RISC 4 -#define QE_NUM_OF_SNUM 46 -#else -#define MAX_QE_RISC 2 -#define QE_NUM_OF_SNUM 28 -#endif - #endif /* __IMMAP_QE_H__ */ diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index 4ddad26..56ac9fe 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -175,7 +175,10 @@ extern inline int in_8(const volatile unsigned char __iomem *addr) extern inline void out_8(volatile unsigned char __iomem *addr, int val) { - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("sync;\n" + "stb%U0%X0 %1,%0;\n" + : "=m" (*addr) + : "r" (val)); } extern inline int in_le16(const volatile unsigned short __iomem *addr) diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index fcee1a2..f5bf4dd 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1048,12 +1048,24 @@ #define SVR_P1013_E 0x80EF00 #define SVR_P1014 0x80F101 #define SVR_P1014_E 0x80F901 +#define SVR_P1015 0x80E502 +#define SVR_P1015_E 0x80ED02 +#define SVR_P1016 0x80E503 +#define SVR_P1016_E 0x80ED03 +#define SVR_P1017 0x80F700 +#define SVR_P1017_E 0x80FF00 #define SVR_P1020 0x80E400 #define SVR_P1020_E 0x80EC00 #define SVR_P1021 0x80E401 #define SVR_P1021_E 0x80EC01 #define SVR_P1022 0x80E600 #define SVR_P1022_E 0x80EE00 +#define SVR_P1023 0x80F600 +#define SVR_P1023_E 0x80FE00 +#define SVR_P1024 0x80E402 +#define SVR_P1024_E 0x80EC02 +#define SVR_P1025 0x80E403 +#define SVR_P1025_E 0x80EC03 #define SVR_P2010 0x80E300 #define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 4719f8c..aaa5add 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -186,6 +186,12 @@ int __board_flash_wp_on(void) } int board_flash_wp_on(void) __attribute__((weak, alias("__board_flash_wp_on"))); +void __cpu_secondary_init_r(void) +{ +} +void cpu_secondary_init_r(void) +__attribute__((weak, alias("__cpu_secondary_init_r"))); + static int init_func_ram (void) { #ifdef CONFIG_BOARD_TYPES @@ -453,9 +459,13 @@ void board_init_f (ulong bootflag) debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); #ifdef CONFIG_LCD +#ifdef CONFIG_FB_ADDR + gd->fb_base = CONFIG_FB_ADDR; +#else /* reserve memory for LCD display (always full pages) */ addr = lcd_setmem (addr); gd->fb_base = addr; +#endif /* CONFIG_FB_ADDR */ #endif /* CONFIG_LCD */ #if defined(CONFIG_VIDEO) && defined(CONFIG_8xx) @@ -798,6 +808,14 @@ void board_init_r (gd_t *id, ulong dest_addr) env_relocate (); /* + * after non-volatile devices & environment is setup and cpu code have + * another round to deal with any initialization that might require + * full access to the environment or loading of some image (firmware) + * from a non-volatile device + */ + cpu_secondary_init_r(); + + /* * Fill in missing fields of bd_info. * We do this here, where we have "normal" access to the * environment; we used to do this still running from ROM, diff --git a/arch/powerpc/lib/bootcount.c b/arch/powerpc/lib/bootcount.c index 07ef28d..f9ce539 100644 --- a/arch/powerpc/lib/bootcount.c +++ b/arch/powerpc/lib/bootcount.c @@ -51,7 +51,7 @@ #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR) #endif /* defined(CONFIG_MPC8260) */ -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_QE) #include <asm/immap_qe.h> #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \ diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 116d81b..e01787d 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -33,6 +33,7 @@ #include <bzlib.h> #include <environment.h> #include <asm/byteorder.h> +#include <asm/mp.h> #if defined(CONFIG_OF_LIBFDT) #include <fdt.h> @@ -95,7 +96,7 @@ static void boot_jump_linux(bootm_headers_t *images) debug (" Booting using OF flat tree...\n"); WATCHDOG_RESET (); (*kernel) ((bd_t *)of_flat_tree, 0, 0, EPAPR_MAGIC, - CONFIG_SYS_BOOTMAPSZ, 0, 0); + getenv_bootm_mapsize(), 0, 0); /* does not return */ } else #endif @@ -166,6 +167,10 @@ void arch_lmb_reserve(struct lmb *lmb) sp -= 4096; lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - sp)); +#ifdef CONFIG_MP + cpu_mp_lmb_reserve(lmb); +#endif + return ; } @@ -181,7 +186,6 @@ static void boot_prep_linux(void) static int boot_cmdline_linux(bootm_headers_t *images) { - ulong bootmap_base = getenv_bootm_low(); ulong of_size = images->ft_len; struct lmb *lmb = &images->lmb; ulong *cmd_start = &images->cmdline_start; @@ -191,7 +195,7 @@ static int boot_cmdline_linux(bootm_headers_t *images) if (!of_size) { /* allocate space and init command line */ - ret = boot_get_cmdline (lmb, cmd_start, cmd_end, bootmap_base); + ret = boot_get_cmdline (lmb, cmd_start, cmd_end); if (ret) { puts("ERROR with allocation of cmdline\n"); return ret; @@ -203,7 +207,6 @@ static int boot_cmdline_linux(bootm_headers_t *images) static int boot_bd_t_linux(bootm_headers_t *images) { - ulong bootmap_base = getenv_bootm_low(); ulong of_size = images->ft_len; struct lmb *lmb = &images->lmb; bd_t **kbd = &images->kbd; @@ -212,7 +215,7 @@ static int boot_bd_t_linux(bootm_headers_t *images) if (!of_size) { /* allocate space for kernel copy of board info */ - ret = boot_get_kbd (lmb, kbd, bootmap_base); + ret = boot_get_kbd (lmb, kbd); if (ret) { puts("ERROR with allocation of kernel bd\n"); return ret; @@ -230,13 +233,16 @@ static int boot_body_linux(bootm_headers_t *images) ulong *initrd_start = &images->initrd_start; ulong *initrd_end = &images->initrd_end; #if defined(CONFIG_OF_LIBFDT) - ulong bootmap_base = getenv_bootm_low(); ulong of_size = images->ft_len; char **of_flat_tree = &images->ft_addr; #endif int ret; +#if defined(CONFIG_OF_LIBFDT) + boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree); +#endif + /* allocate space and init command line */ ret = boot_cmdline_linux(images); if (ret) @@ -252,8 +258,8 @@ static int boot_body_linux(bootm_headers_t *images) if (ret) return ret; -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_SYS_BOOTMAPSZ) - ret = boot_relocate_fdt(lmb, bootmap_base, of_flat_tree, &of_size); +#if defined(CONFIG_OF_LIBFDT) + ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size); if (ret) return ret; @@ -291,7 +297,7 @@ static int boot_body_linux(bootm_headers_t *images) if (*initrd_start && *initrd_end) fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1); } -#endif /* CONFIG_OF_LIBFDT && CONFIG_SYS_BOOTMAPSZ */ +#endif /* CONFIG_OF_LIBFDT */ return 0; } |