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-rw-r--r--arch/powerpc/cpu/mpc85xx/mp.c2
-rw-r--r--arch/powerpc/cpu/ppc4xx/start.S2
-rw-r--r--arch/powerpc/include/asm/status_led.h2
3 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 88c8e65..0addf84 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -30,7 +30,7 @@ u32 get_my_id()
*/
int hold_cores_in_reset(int verbose)
{
- /* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */
+ /* Default to no, overridden by 'y', 'yes', 'Y', 'Yes', or '1' */
if (getenv_yesno("mp_holdoff") == 1) {
if (verbose) {
puts("Secondary cores are being held in reset.\n");
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index b432b18..5647d71 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -144,7 +144,7 @@
#endif
/*
- * Unless otherwise overriden, enable two 128MB cachable instruction regions
+ * Unless otherwise overridden, enable two 128MB cachable instruction regions
* at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
* NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
*/
diff --git a/arch/powerpc/include/asm/status_led.h b/arch/powerpc/include/asm/status_led.h
index 4416190..260a831 100644
--- a/arch/powerpc/include/asm/status_led.h
+++ b/arch/powerpc/include/asm/status_led.h
@@ -7,7 +7,7 @@
#ifndef __ASM_STATUS_LED_H__
#define __ASM_STATUS_LED_H__
-/* if not overriden */
+/* if not overridden */
#ifndef CONFIG_BOARD_SPECIFIC_LED
# if defined(CONFIG_8xx)
# include <mpc8xx.h>