diff options
Diffstat (limited to 'arch/powerpc')
32 files changed, 751 insertions, 516 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index 42387b4..6635109 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -126,72 +126,6 @@ int checkcpu(void) return 0; } - -/* - * Program a UPM with the code supplied in the table. - * - * The 'dummy' variable is used to increment the MAD. 'dummy' is - * supposed to be a pointer to the memory of the device being - * programmed by the UPM. The data in the MDR is written into - * memory and the MAD is incremented every time there's a write - * to 'dummy'. Unfortunately, the current prototype for this - * function doesn't allow for passing the address of this - * device, and changing the prototype will break a number lots - * of other code, so we need to use a round-about way of finding - * the value for 'dummy'. - * - * The value can be extracted from the base address bits of the - * Base Register (BR) associated with the specific UPM. To find - * that BR, we need to scan all 8 BRs until we find the one that - * has its MSEL bits matching the UPM we want. Once we know the - * right BR, we can extract the base address bits from it. - * - * The MxMR and the BR and OR of the chosen bank should all be - * configured before calling this function. - * - * Parameters: - * upm: 0=UPMA, 1=UPMB, 2=UPMC - * table: Pointer to an array of values to program - * size: Number of elements in the array. Must be 64 or less. - */ -void upmconfig (uint upm, uint *table, uint size) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbus = &immap->lbus; - volatile uchar *dummy = NULL; - const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */ - volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */ - uint i; - - /* Scan all the banks to determine the base address of the device */ - for (i = 0; i < 8; i++) { - if ((lbus->bank[i].br & BR_MSEL) == msel) { - dummy = (uchar *) (lbus->bank[i].br & BR_BA); - break; - } - } - - if (!dummy) { - printf("Error: %s() could not find matching BR\n", __FUNCTION__); - hang(); - } - - /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */ - *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000; - - for (i = 0; i < size; i++) { - lbus->mdr = table[i]; - __asm__ __volatile__ ("sync"); - *dummy = 0; /* Write the value to memory and increment MAD */ - __asm__ __volatile__ ("sync"); - while(((*mxmr & 0x3f) != ((i + 1) & 0x3f))); - } - - /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */ - *mxmr &= 0xCFFFFFC0; -} - - int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index f3b67ae..83cba93 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -236,8 +236,8 @@ void cpu_init_f (volatile immap_t * im) /* LCRR - Clock Ratio Register (10.3.1.16) * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description */ - clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val); - __raw_readl(&im->lbus.lcrr); + clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val); + __raw_readl(&im->im_lbc.lcrr); isync(); /* Enable Time Base & Decrementer ( so we will have udelay() )*/ @@ -267,80 +267,41 @@ void cpu_init_f (volatile immap_t * im) /* Config QE ioports */ config_qe_ioports(); #endif + /* Set up preliminary BR/OR regs */ + init_early_memctl_regs(); - /* - * Memory Controller: - */ - - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary - * addresses - these have to be modified later when FLASH size - * has been determined - */ - -#if defined(CONFIG_SYS_BR0_PRELIM) \ - && defined(CONFIG_SYS_OR0_PRELIM) \ - && defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \ - && defined(CONFIG_SYS_LBLAWAR0_PRELIM) - im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM; - im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM; + /* Local Access window setup */ +#if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM) im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM; im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM; #else -#error CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined +#error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined #endif -#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) - im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM; - im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM; -#endif #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM) im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM; im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM; #endif -#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) - im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM; - im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM; -#endif #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM) im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM; im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM; #endif -#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) - im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM; - im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM; -#endif #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM) im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM; im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM; #endif -#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) - im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM; - im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM; -#endif #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM) im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM; im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM; #endif -#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) - im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM; - im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM; -#endif #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM) im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM; im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM; #endif -#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) - im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM; - im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM; -#endif #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM) im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM; im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM; #endif -#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) - im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM; - im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM; -#endif #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM) im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM; im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM; diff --git a/arch/powerpc/cpu/mpc83xx/nand_init.c b/arch/powerpc/cpu/mpc83xx/nand_init.c index 38e141a..d1648b7 100644 --- a/arch/powerpc/cpu/mpc83xx/nand_init.c +++ b/arch/powerpc/cpu/mpc83xx/nand_init.c @@ -88,8 +88,8 @@ void cpu_init_f (volatile immap_t * im) && defined(CONFIG_SYS_NAND_OR_PRELIM) \ && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \ && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM) - im->lbus.bank[0].br = CONFIG_SYS_NAND_BR_PRELIM; - im->lbus.bank[0].or = CONFIG_SYS_NAND_OR_PRELIM; + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM; im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM; #else diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index d04b192..93e9f1c 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -393,7 +393,7 @@ int get_clocks(void) lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); - lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; + lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; switch (lcrr) { case 2: case 4: diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index f064fee..4ee0e9a 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -32,6 +32,7 @@ START = start.o resetvec.o SOBJS-$(CONFIG_MP) += release.o SOBJS = $(SOBJS-y) +COBJS-$(CONFIG_CMD_ERRATA) += cmd_errata.o COBJS-$(CONFIG_CPM2) += commproc.o # supports ddr1 @@ -63,6 +64,7 @@ COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o +COBJS-$(CONFIG_P1022) += p1022_serdes.o COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c new file mode 100644 index 0000000..d7835c8 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -0,0 +1,51 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <linux/compiler.h> +#include <asm/processor.h> + +static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + __maybe_unused u32 svr = get_svr(); + +#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) + if (IS_SVR_REV(svr, 1, 0)) { + switch (SVR_SOC_VER(svr)) { + case SVR_P1013: + case SVR_P1013_E: + case SVR_P1022: + case SVR_P1022_E: + puts("Work-around for Erratum SATA A001 enabled\n"); + } + } +#endif + + return 0; +} + +U_BOOT_CMD( + errata, 1, 0, do_errata, + "Report errata workarounds", + "" +); diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 6f81fdf..fe2b52d 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -32,6 +32,8 @@ #include <fsl_esdhc.h> #include <asm/cache.h> #include <asm/io.h> +#include <asm/mmu.h> +#include <asm/fsl_law.h> DECLARE_GLOBAL_DATA_PTR; @@ -93,18 +95,26 @@ int checkcpu (void) minor = PVR_MIN(pvr); printf("Core: "); - switch (fam) { - case PVR_FAM(PVR_85xx): - puts("E500"); - break; - default: - puts("Unknown"); - break; + if (PVR_FAM(PVR_85xx)) { + switch(PVR_MEM(pvr)) { + case 0x1: + case 0x2: + puts("E500"); + break; + case 0x3: + puts("E500MC"); + break; + case 0x4: + puts("E5500"); + break; + default: + puts("Unknown"); + break; + } + } else { + puts("Unknown"); } - if (PVR_MEM(pvr) == 0x03) - puts("MC"); - printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); @@ -250,71 +260,6 @@ reset_85xx_watchdog(void) #endif /* CONFIG_WATCHDOG */ /* - * Configures a UPM. The function requires the respective MxMR to be set - * before calling this function. "size" is the number or entries, not a sizeof. - */ -void upmconfig (uint upm, uint * table, uint size) -{ - int i, mdr, mad, old_mad = 0; - volatile u32 *mxmr; - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); - volatile u32 *brp,*orp; - volatile u8* dummy = NULL; - int upmmask; - - switch (upm) { - case UPMA: - mxmr = &lbc->mamr; - upmmask = BR_MS_UPMA; - break; - case UPMB: - mxmr = &lbc->mbmr; - upmmask = BR_MS_UPMB; - break; - case UPMC: - mxmr = &lbc->mcmr; - upmmask = BR_MS_UPMC; - break; - default: - printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm); - hang(); - } - - /* Find the address for the dummy write transaction */ - for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8; - i++, brp += 2, orp += 2) { - - /* Look for a valid BR with selected UPM */ - if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) { - dummy = (volatile u8*)(in_be32(brp) & BR_BA); - break; - } - } - - if (i == 8) { - printf("Error: %s() could not find matching BR\n", __FUNCTION__); - hang(); - } - - for (i = 0; i < size; i++) { - /* 1 */ - out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i); - /* 2 */ - out_be32(&lbc->mdr, table[i]); - /* 3 */ - mdr = in_be32(&lbc->mdr); - /* 4 */ - *(volatile u8 *)dummy = 0; - /* 5 */ - do { - mad = in_be32(mxmr) & MxMR_MAD_MSK; - } while (mad <= old_mad && !(!mad && i == (size-1))); - old_mad = mad; - } - out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM); -} - -/* * Initializes on-chip MMC controllers. * to override, implement board_mmc_init() */ @@ -326,3 +271,14 @@ int cpu_mmc_init(bd_t *bis) return 0; #endif } + +/* + * Print out the state of various machine registers. + * Currently prints out LAWs, BR0/OR0, and TLBs + */ +void mpc85xx_reginfo(void) +{ + print_tlbcam(); + print_laws(); + print_lbc_regs(); +} diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 99431dc..d491e2a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -154,7 +154,6 @@ static void corenet_tb_init(void) void cpu_init_f (void) { - volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); extern void m8560_cpm_reset (void); #ifdef CONFIG_MPC8548 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); @@ -177,60 +176,7 @@ void cpu_init_f (void) config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); #endif - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary - * addresses - these have to be modified later when FLASH size - * has been determined - */ -#if defined(CONFIG_SYS_OR0_REMAP) - out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP); -#endif -#if defined(CONFIG_SYS_OR1_REMAP) - out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP); -#endif - - /* now restrict to preliminary range */ - /* if cs1 is already set via debugger, leave cs0/cs1 alone */ - if (! memctl->br1 & 1) { -#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) - out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM); - out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) - out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM); - out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM); -#endif - } - -#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) - out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM); - out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) - out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM); - out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) - out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM); - out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) - out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM); - out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) - out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM); - out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) - out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM); - out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM); -#endif + init_early_memctl_regs(); #if defined(CONFIG_CPM2) m8560_cpm_reset(); @@ -263,7 +209,7 @@ void cpu_init_f (void) int cpu_init_r(void) { #ifdef CONFIG_SYS_LBC_LCRR - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; #endif puts ("L2: "); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c index 184cca4..8fb27ab 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c @@ -25,7 +25,7 @@ void cpu_init_f(void) { - ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + fsl_lbc_t *lbc = LBC_BASE_ADDR; /* * LCRR - Clock Ratio Register - set up local bus timing @@ -34,8 +34,8 @@ void cpu_init_f(void) out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8); #if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM) - out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM); - out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM); + set_lbc_br(0, CONFIG_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_NAND_OR_PRELIM); #else #error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 1d11ab4..2628cc5 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -404,8 +404,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_MP ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); -#endif ft_fixup_num_cores(blob); +#endif ft_fixup_cache(blob); diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index ddbc221..e05257c 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -77,6 +77,13 @@ int cpu_disable(int nr) return 0; } + +int is_core_disabled(int nr) { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 coredisrl = in_be32(&gur->coredisrl); + + return (coredisrl & (1 << nr)); +} #else int cpu_disable(int nr) { @@ -96,6 +103,22 @@ int cpu_disable(int nr) return 0; } + +int is_core_disabled(int nr) { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr = in_be32(&gur->devdisr); + + switch (nr) { + case 0: + return (devdisr & MPC85xx_DEVDISR_CPU0); + case 1: + return (devdisr & MPC85xx_DEVDISR_CPU1); + default: + printf("Invalid cpu number for disable %d\n", nr); + } + + return 0; +} #endif static u8 boot_entry_map[4] = { diff --git a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c new file mode 100644 index 0000000..6b0fbf2 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c @@ -0,0 +1,98 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Author: Timur Tabi <timur@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 +#define SRDS2_MAX_LANES 2 + +static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x00] = {NONE, NONE, NONE, NONE}, + [0x01] = {NONE, NONE, NONE, NONE}, + [0x02] = {NONE, NONE, NONE, NONE}, + [0x03] = {NONE, NONE, NONE, NONE}, + [0x04] = {NONE, NONE, NONE, NONE}, + [0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2}, + [0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2}, + [0x09] = {PCIE1, NONE, NONE, NONE}, + [0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2}, + [0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2}, + [0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x15] = {PCIE1, PCIE3, PCIE2, PCIE2}, + [0x16] = {PCIE1, PCIE3, PCIE2, PCIE2}, + [0x17] = {PCIE1, PCIE3, PCIE2, PCIE2}, + [0x18] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x19] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2}, +}; + +static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x00] = {PCIE3, PCIE3}, + [0x01] = {PCIE2, PCIE3}, + [0x02] = {SATA1, SATA2}, + [0x03] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x04] = {NONE, NONE}, + [0x06] = {SATA1, SATA2}, + [0x07] = {NONE, NONE}, + [0x09] = {PCIE3, PCIE2}, + [0x0a] = {SATA1, SATA2}, + [0x0b] = {NONE, NONE}, + [0x0d] = {PCIE3, PCIE2}, + [0x0e] = {SATA1, SATA2}, + [0x0f] = {NONE, NONE}, + [0x15] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x16] = {SATA1, SATA2}, + [0x17] = {NONE, NONE}, + [0x18] = {PCIE3, PCIE3}, + [0x19] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x1a] = {SATA1, SATA2}, + [0x1b] = {NONE, NONE}, + [0x1c] = {PCIE3, PCIE3}, + [0x1d] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x1e] = {SATA1, SATA2}, + [0x1f] = {NONE, NONE}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + unsigned int i; + + debug("%s: dev = %d\n", __FUNCTION__, device); + debug("PORDEVSR[IO_SEL] = 0x%x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds_cfg); + return 0; + } + + for (i = 0; i < SRDS1_MAX_LANES; i++) { + if (serdes1_cfg_tbl[srds_cfg][i] == device) + return 1; + if (serdes2_cfg_tbl[srds_cfg][i] == device) + return 1; + } + + return 0; +} diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 8132115..dd4c6b3 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -172,10 +172,7 @@ void get_sys_info (sys_info_t * sysInfo) /* We will program LCRR to this value later */ lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; #else - { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); - lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV; - } + lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; #endif if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { #if defined(CONFIG_FSL_CORENET) diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index b3037ac..f2833a5 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -55,7 +55,45 @@ void init_tlbs(void) return ; } +void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, + phys_addr_t *rpn) +{ + u32 _mas1; + + mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0)); + asm volatile("tlbre;isync"); + _mas1 = mfspr(MAS1); + + *valid = (_mas1 & MAS1_VALID); + *tsize = (_mas1 >> 8) & 0xf; + *epn = mfspr(MAS2) & MAS2_EPN; + *rpn = mfspr(MAS3) & MAS3_RPN; +#ifdef CONFIG_ENABLE_36BIT_PHYS + *rpn |= ((u64)mfspr(MAS7)) << 32; +#endif +} + #ifndef CONFIG_NAND_SPL +void print_tlbcam(void) +{ + int i; + unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; + + /* walk all the entries */ + printf("TLBCAM entries\n"); + for (i = 0; i < num_cam; i++) { + unsigned long epn; + u32 tsize, valid; + phys_addr_t rpn; + + read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn); + printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:", + i, (valid == 0) ? 0 : 1, (unsigned int)epn, + (unsigned long long)rpn); + print_size(TSIZE_TO_BYTES(tsize), "\n"); + } +} + static inline void use_tlb_cam(u8 idx) { int i = idx / 32; @@ -82,15 +120,9 @@ void init_used_tlb_cams(void) /* walk all the entries */ for (i = 0; i < num_cam; i++) { - u32 _mas1; - mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); - asm volatile("tlbre;isync"); - _mas1 = mfspr(MAS1); - - /* if the entry isn't valid skip it */ - if ((_mas1 & MAS1_VALID)) + if (mfspr(MAS1) & MAS1_VALID) use_tlb_cam(i); } } @@ -134,7 +166,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, #ifdef CONFIG_ADDR_MAP if ((tlb == 1) && (gd->flags & GD_FLG_RELOC)) - addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel); + addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel); #endif } @@ -201,26 +233,12 @@ void init_addr_map(void) /* walk all the entries */ for (i = 0; i < num_cam; i++) { unsigned long epn; - u32 tsize, _mas1; + u32 tsize, valid; phys_addr_t rpn; - mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); - - asm volatile("tlbre;isync"); - _mas1 = mfspr(MAS1); - - /* if the entry isn't valid skip it */ - if (!(_mas1 & MAS1_VALID)) - continue; - - tsize = (_mas1 >> 8) & 0xf; - epn = mfspr(MAS2) & MAS2_EPN; - rpn = mfspr(MAS3) & MAS3_RPN; -#ifdef CONFIG_ENABLE_36BIT_PHYS - rpn |= ((phys_addr_t)mfspr(MAS7)) << 32; -#endif - - addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), i); + read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn); + if (valid & MAS1_VALID) + addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i); } return ; diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c index 9064e78..4e90fd2 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu.c +++ b/arch/powerpc/cpu/mpc86xx/cpu.c @@ -180,22 +180,9 @@ watchdog_reset(void) */ void mpc86xx_reginfo(void) { - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - ccsr_lbc_t *lbc = &immap->im_lbc; - print_bats(); print_laws(); - - printf ("Local Bus Controller Registers\n" - "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0)); - printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1)); - printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2)); - printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3)); - printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4)); - printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5)); - printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6)); - printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7)); - + print_lbc_regs(); } /* diff --git a/arch/powerpc/cpu/mpc86xx/cpu_init.c b/arch/powerpc/cpu/mpc86xx/cpu_init.c index b4f047d..82c216b 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc86xx/cpu_init.c @@ -46,9 +46,6 @@ DECLARE_GLOBAL_DATA_PTR; void cpu_init_f(void) { - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_lbc_t *memctl = &immap->im_lbc; - /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); @@ -61,58 +58,8 @@ void cpu_init_f(void) setup_bats(); - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary - * addresses - these have to be modified later when FLASH size - * has been determined - */ - -#if defined(CONFIG_SYS_OR0_REMAP) - memctl->or0 = CONFIG_SYS_OR0_REMAP; -#endif -#if defined(CONFIG_SYS_OR1_REMAP) - memctl->or1 = CONFIG_SYS_OR1_REMAP; -#endif - - /* now restrict to preliminary range */ -#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) - memctl->br0 = CONFIG_SYS_BR0_PRELIM; - memctl->or0 = CONFIG_SYS_OR0_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) - memctl->or1 = CONFIG_SYS_OR1_PRELIM; - memctl->br1 = CONFIG_SYS_BR1_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) - memctl->or2 = CONFIG_SYS_OR2_PRELIM; - memctl->br2 = CONFIG_SYS_BR2_PRELIM; -#endif + init_early_memctl_regs(); -#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) - memctl->or3 = CONFIG_SYS_OR3_PRELIM; - memctl->br3 = CONFIG_SYS_BR3_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) - memctl->or4 = CONFIG_SYS_OR4_PRELIM; - memctl->br4 = CONFIG_SYS_BR4_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) - memctl->or5 = CONFIG_SYS_OR5_PRELIM; - memctl->br5 = CONFIG_SYS_BR5_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) - memctl->or6 = CONFIG_SYS_OR6_PRELIM; - memctl->br6 = CONFIG_SYS_BR6_PRELIM; -#endif - -#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) - memctl->or7 = CONFIG_SYS_OR7_PRELIM; - memctl->br7 = CONFIG_SYS_BR7_PRELIM; -#endif #if defined(CONFIG_FSL_DMA) dma_init(); #endif diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index 51f3f4c..ff89ee5 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008,2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -55,6 +55,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); if (off < 0) printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); -#endif + ft_fixup_num_cores(blob); +#endif } diff --git a/arch/powerpc/cpu/mpc86xx/mp.c b/arch/powerpc/cpu/mpc86xx/mp.c index 24eb30a..30c99eb 100644 --- a/arch/powerpc/cpu/mpc86xx/mp.c +++ b/arch/powerpc/cpu/mpc86xx/mp.c @@ -66,6 +66,23 @@ int cpu_disable(int nr) return 0; } +int is_core_disabled(int nr) { + immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; + ccsr_gur_t *gur = &immap->im_gur; + u32 devdisr = in_be32(&gur->devdisr); + + switch (nr) { + case 0: + return (devdisr & MPC86xx_DEVDISR_CPU0); + case 1: + return (devdisr & MPC86xx_DEVDISR_CPU1); + default: + printf("Invalid cpu number for disable %d\n", nr); + } + + return 0; +} + int cpu_release(int nr, int argc, char * const argv[]) { /* dummy function so common/cmd_mp.c will build diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c index 64a3479..a2d0a8a 100644 --- a/arch/powerpc/cpu/mpc86xx/speed.c +++ b/arch/powerpc/cpu/mpc86xx/speed.c @@ -97,10 +97,7 @@ void get_sys_info(sys_info_t *sysInfo) /* We will program LCRR to this value later */ lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; #else - { - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV; - } + lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV; #endif if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2); diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 481f9e5..ea51222 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2009 Freescale Semiconductor, Inc. +# Copyright 2009-2010 Freescale Semiconductor, Inc. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License @@ -10,9 +10,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib8xxx.a +ifneq ($(CPU),mpc83xx) COBJS-y += cpu.o -COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_PCI) += pci_cfg.o +endif + +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index ccefaf5..88c47d1 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains @@ -26,6 +26,27 @@ #include <common.h> #include <libfdt.h> #include <fdt_support.h> +#include <asm/mp.h> + +#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) +static int ft_del_cpuhandle(void *blob, int cpuhandle) +{ + int off, ret = -FDT_ERR_NOTFOUND; + + /* if we find a match, we'll delete at it which point the offsets are + * invalid so we start over from the beginning + */ + off = fdt_node_offset_by_prop_value(blob, -1, "cpu-handle", + &cpuhandle, 4); + while (off != -FDT_ERR_NOTFOUND) { + fdt_delprop(blob, off, "cpu-handle"); + ret = 1; + off = fdt_node_offset_by_prop_value(blob, -1, "cpu-handle", + &cpuhandle, 4); + } + + return ret; +} void ft_fixup_num_cores(void *blob) { int off, num_cores, del_cores; @@ -37,13 +58,18 @@ void ft_fixup_num_cores(void *blob) { while (off != -FDT_ERR_NOTFOUND) { u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); - /* if we find a cpu node outside of what we expect delete it - * and reset the offset back to the start since we can't - * trust the offsets anymore - */ - if (*reg > num_cores-1) { - fdt_del_node(blob, off); - del_cores++; + if ((*reg > num_cores-1) || (is_core_disabled(*reg))) { + int ph = fdt_get_phandle(blob, off); + + /* Delete the cpu node once there are no cpu handles */ + if (-FDT_ERR_NOTFOUND == ft_del_cpuhandle(blob, ph)) { + fdt_del_node(blob, off); + del_cores++; + } + /* either we deleted some cpu handles or the cpu node + * so we reset the offset back to the start since we + * can't trust the offsets anymore + */ off = -1; } off = fdt_node_offset_by_prop_value(blob, off, @@ -53,3 +79,139 @@ void ft_fixup_num_cores(void *blob) { debug ("deleted %d extra core entry entries from device tree\n", del_cores); } +#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */ + +#ifdef CONFIG_HAS_FSL_DR_USB +void fdt_fixup_dr_usb(void *blob, bd_t *bd) +{ + char *mode; + char *type; + const char *compat = "fsl-usb2-dr"; + const char *prop_mode = "dr_mode"; + const char *prop_type = "phy_type"; + int node_offset; + int err; + + mode = getenv("usb_dr_mode"); + type = getenv("usb_phy_type"); + if (!mode && !type) + return; + + node_offset = fdt_node_offset_by_compatible(blob, 0, compat); + if (node_offset < 0) { + printf("WARNING: could not find compatible node %s: %s.\n", + compat, fdt_strerror(node_offset)); + return; + } + + if (mode) { + err = fdt_setprop(blob, node_offset, prop_mode, mode, + strlen(mode) + 1); + if (err < 0) + printf("WARNING: could not set %s for %s: %s.\n", + prop_mode, compat, fdt_strerror(err)); + } + + if (type) { + err = fdt_setprop(blob, node_offset, prop_type, type, + strlen(type) + 1); + if (err < 0) + printf("WARNING: could not set %s for %s: %s.\n", + prop_type, compat, fdt_strerror(err)); + } +} +#endif /* CONFIG_HAS_FSL_DR_USB */ + +/* + * update crypto node properties to a specified revision of the SEC + * called with sec_rev == 0 if not on an E processor + */ +#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */ +void fdt_fixup_crypto_node(void *blob, int sec_rev) +{ + const struct sec_rev_prop { + u32 sec_rev; + u32 num_channels; + u32 channel_fifo_len; + u32 exec_units_mask; + u32 descriptor_types_mask; + } sec_rev_prop_list [] = { + { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */ + { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */ + { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */ + { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */ + { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */ + { 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */ + { 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */ + }; + char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) * + sizeof("fsl,secX.Y")]; + int crypto_node, sec_idx, err; + char *p; + u32 val; + + /* locate crypto node based on lowest common compatible */ + crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0"); + if (crypto_node == -FDT_ERR_NOTFOUND) + return; + + /* delete it if not on an E-processor */ + if (crypto_node > 0 && !sec_rev) { + fdt_del_node(blob, crypto_node); + return; + } + + /* else we got called for possible uprev */ + for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++) + if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev) + break; + + if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) { + puts("warning: unknown SEC revision number\n"); + return; + } + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels); + err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask); + err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask); + err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len); + err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); + + val = 0; + while (sec_idx >= 0) { + p = compat_strlist + val; + val += sprintf(p, "fsl,sec%d.%d", + (sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8, + sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1; + sec_idx--; + } + err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, val); + if (err < 0) + printf("WARNING: could not set crypto property: %s\n", + fdt_strerror(err)); +} +#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */ +void fdt_fixup_crypto_node(void *blob, int sec_rev) +{ + if (!sec_rev) + fdt_del_node_and_alias(blob, "crypto"); +} +#endif diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c new file mode 100644 index 0000000..fcef40c --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -0,0 +1,134 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <asm/fsl_lbc.h> + +void print_lbc_regs(void) +{ + int i; + + printf("\nLocal Bus Controller Registers\n"); + for (i = 0; i < 8; i++) { + printf("BR%d\t0x%08X\tOR%d\t0x%08X\n", + i, get_lbc_br(i), i, get_lbc_or(i)); + } +} + +void init_early_memctl_regs(void) +{ + uint init_br1 = 1; + +#ifdef CONFIG_MPC85xx + /* if cs1 is already set via debugger, leave cs0/cs1 alone */ + if (get_lbc_br(1) & BR_V) + init_br1 = 0; +#endif + + /* + * Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at + * preliminary addresses - these have to be modified later + * when FLASH size has been determined + */ +#if defined(CONFIG_SYS_OR0_REMAP) + set_lbc_or(0, CONFIG_SYS_OR0_REMAP); +#endif +#if defined(CONFIG_SYS_OR1_REMAP) + set_lbc_or(1, CONFIG_SYS_OR1_REMAP); +#endif + /* now restrict to preliminary range */ + if (init_br1) { + set_lbc_br(0, CONFIG_SYS_BR0_PRELIM); + set_lbc_or(0, CONFIG_SYS_OR0_PRELIM); + +#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) + set_lbc_or(1, CONFIG_SYS_OR1_PRELIM); + set_lbc_br(1, CONFIG_SYS_BR1_PRELIM); +#endif + } + +#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); +#endif + +#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) + set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); +#endif + +#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) + set_lbc_or(4, CONFIG_SYS_OR4_PRELIM); + set_lbc_br(4, CONFIG_SYS_BR4_PRELIM); +#endif + +#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) + set_lbc_or(5, CONFIG_SYS_OR5_PRELIM); + set_lbc_br(5, CONFIG_SYS_BR5_PRELIM); +#endif + +#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) + set_lbc_or(6, CONFIG_SYS_OR6_PRELIM); + set_lbc_br(6, CONFIG_SYS_BR6_PRELIM); +#endif + +#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) + set_lbc_or(7, CONFIG_SYS_OR7_PRELIM); + set_lbc_br(7, CONFIG_SYS_BR7_PRELIM); +#endif +} + +/* + * Configures a UPM. The function requires the respective MxMR to be set + * before calling this function. "size" is the number or entries, not a sizeof. + */ +void upmconfig(uint upm, uint *table, uint size) +{ + fsl_lbc_t *lbc = LBC_BASE_ADDR; + int i, mdr, mad, old_mad = 0; + u32 mask = (~MxMR_OP_MSK & ~MxMR_MAD_MSK); + u32 msel = BR_UPMx_TO_MSEL(upm); + u32 *mxmr = &lbc->mamr + upm; + volatile u8 *dummy = NULL; + + if (upm < UPMA || upm > UPMC) { + printf("Error: %s() Bad UPM index %d\n", __func__, upm); + hang(); + } + + /* + * Find the address for the dummy write - scan all of the BRs until we + * find one matching the UPM and extract the base address bits from it. + */ + for (i = 0; i < 8; i++) { + if ((get_lbc_br(i) & (BR_V | BR_MSEL)) == (BR_V | msel)) { + dummy = (volatile u8 *)(get_lbc_br(i) & BR_BA); + break; + } + } + + if (!dummy) { + printf("Error: %s() No matching BR\n", __func__); + hang(); + } + + /* Program UPM using steps outlined by the reference manual */ + for (i = 0; i < size; i++) { + out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_WARR | i); + out_be32(&lbc->mdr, table[i]); + mdr = in_be32(&lbc->mdr); + *dummy = 0; + do { + mad = in_be32(mxmr) & MxMR_MAD_MSK; + } while (mad <= old_mad && !(!mad && i == (size-1))); + old_mad = mad; + } + + /* Return to normal operation */ + out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_NORM); +} diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index fc3facb..d88c282 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -66,6 +66,15 @@ #define CONFIG_TSECV2 #endif +/* + * SEC (crypto unit) major compatible version determination + */ +#if defined(CONFIG_FSL_CORENET) +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx) +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#endif + /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) #define CONFIG_SYS_NUM_TLBCAMS 64 @@ -76,4 +85,10 @@ /* Relocation to SDRAM works on all PPC boards */ #define CONFIG_RELOC_FIXUP_WORKS +/* Since so many PPC SOCs have a semi-common LBC, define this here */ +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ + defined(CONFIG_MPC83xx) +#define CONFIG_FSL_LBC +#endif + #endif /* _ASM_CONFIG_H_ */ diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 34c56a2..12ba1a6 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -47,6 +47,7 @@ enum law_size { }; #define law_size_bits(sz) (__ilog2_u64(sz) - 1) +#define lawar_size(x) (1ULL << ((x & 0x3f) + 1)) #ifdef CONFIG_FSL_CORENET enum law_trgt_if { diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 03ae6a7..82d24ab 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -14,6 +14,7 @@ #define __ASM_PPC_FSL_LBC_H #include <config.h> +#include <common.h> /* BR - Base Registers */ @@ -61,6 +62,8 @@ #define BR_V 0x00000001 #define BR_V_SHIFT 0 +#define BR_UPMx_TO_MSEL(x) ((x + 4) << BR_MSEL_SHIFT) + #define UPMA 0 #define UPMB 1 #define UPMC 2 @@ -453,49 +456,70 @@ #define LTESR_CC 0x00000001 #ifndef __ASSEMBLY__ -/* - * Local Bus Controller Registers. - */ -typedef struct lbus_bank { - u32 br; /* Base Register */ - u32 or; /* Option Register */ -} lbus_bank_t; - -typedef struct fsl_lbus { - lbus_bank_t bank[8]; - u8 res0[0x28]; - u32 mar; /* UPM Address Register */ - u8 res1[0x4]; - u32 mamr; /* UPMA Mode Register */ - u32 mbmr; /* UPMB Mode Register */ - u32 mcmr; /* UPMC Mode Register */ - u8 res2[0x8]; - u32 mrtpr; /* Memory Refresh Timer Prescaler Register */ - u32 mdr; /* UPM Data Register */ - u8 res3[0x4]; - u32 lsor; /* Special Operation Initiation Register */ - u32 lsdmr; /* SDRAM Mode Register */ - u8 res4[0x8]; - u32 lurt; /* UPM Refresh Timer */ - u32 lsrt; /* SDRAM Refresh Timer */ - u8 res5[0x8]; - u32 ltesr; /* Transfer Error Status Register */ - u32 ltedr; /* Transfer Error Disable Register */ - u32 lteir; /* Transfer Error Interrupt Register */ - u32 lteatr; /* Transfer Error Attributes Register */ - u32 ltear; /* Transfer Error Address Register */ - u8 res6[0xC]; - u32 lbcr; /* Configuration Register */ - u32 lcrr; /* Clock Ratio Register */ - u8 res7[0x8]; - u32 fmr; /* Flash Mode Register */ - u32 fir; /* Flash Instruction Register */ - u32 fcr; /* Flash Command Register */ - u32 fbar; /* Flash Block Addr Register */ - u32 fpar; /* Flash Page Addr Register */ - u32 fbcr; /* Flash Byte Count Register */ - u8 res8[0xF08]; -} fsl_lbus_t; -#endif /* __ASSEMBLY__ */ +#include <asm/io.h> + +extern void print_lbc_regs(void); +extern void init_early_memctl_regs(void); +extern void upmconfig(uint upm, uint *table, uint size); + +#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR) +#define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br)) +#define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or)) +#define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v)) +#define set_lbc_or(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].or, v)) + +typedef struct lbc_bank { + u32 br; + u32 or; +} lbc_bank_t; +/* Local Bus Controller Registers */ +typedef struct fsl_lbc { + lbc_bank_t bank[8]; + u8 res1[40]; + u32 mar; /* LBC UPM Addr */ + u8 res2[4]; + u32 mamr; /* LBC UPMA Mode */ + u32 mbmr; /* LBC UPMB Mode */ + u32 mcmr; /* LBC UPMC Mode */ + u8 res3[8]; + u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */ + u32 mdr; /* LBC UPM Data */ +#ifdef CONFIG_FSL_ELBC + u8 res4[4]; + u32 lsor; + u8 res5[12]; + u32 lurt; /* LBC UPM Refresh Timer */ + u8 res6[4]; +#else + u8 res4[8]; + u32 lsdmr; /* LBC SDRAM Mode */ + u8 res5[8]; + u32 lurt; /* LBC UPM Refresh Timer */ + u32 lsrt; /* LBC SDRAM Refresh Timer */ +#endif + u8 res7[8]; + u32 ltesr; /* LBC Transfer Error Status */ + u32 ltedr; /* LBC Transfer Error Disable */ + u32 lteir; /* LBC Transfer Error IRQ */ + u32 lteatr; /* LBC Transfer Error Attrs */ + u32 ltear; /* LBC Transfer Error Addr */ + u8 res8[12]; + u32 lbcr; /* LBC Configuration */ + u32 lcrr; /* LBC Clock Ratio */ +#ifdef CONFIG_NAND_FSL_ELBC + u8 res9[0x8]; + u32 fmr; /* Flash Mode Register */ + u32 fir; /* Flash Instruction Register */ + u32 fcr; /* Flash Command Register */ + u32 fbar; /* Flash Block Addr Register */ + u32 fpar; /* Flash Page Addr Register */ + u32 fbcr; /* Flash Byte Count Register */ + u8 res10[0xF08]; +#else + u8 res9[0xF28]; +#endif +} fsl_lbc_t; + +#endif /* __ASSEMBLY__ */ #endif /* __ASM_PPC_FSL_LBC_H */ diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index db61e7e..bb87543 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -162,14 +162,15 @@ typedef struct ccsr_pci { } ccsr_fsl_pci_t; struct fsl_pci_info { - unsigned long regs; - pci_addr_t mem_bus; - phys_size_t mem_phys; - pci_size_t mem_size; - pci_addr_t io_bus; - phys_size_t io_phys; - pci_size_t io_size; - int pci_num; + unsigned long regs; + pci_addr_t mem_bus; + phys_size_t mem_phys; + pci_size_t mem_size; + pci_addr_t io_bus; + phys_size_t io_phys; + pci_size_t io_size; + enum law_trgt_if law; + int pci_num; }; int fsl_pci_init_port(struct fsl_pci_info *pci_info, @@ -184,6 +185,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \ x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \ x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \ + x.law = LAW_TRGT_IF_PCI_##num; \ x.pci_num = num; \ } @@ -196,6 +198,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \ x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \ x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \ + x.law = LAW_TRGT_IF_PCIE_##num; \ x.pci_num = num; \ } diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 3a9cdc4..cc0293a 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -646,7 +646,7 @@ typedef struct immap { u8 res2[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res3[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ u8 res4[0x1000]; spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ @@ -686,7 +686,7 @@ typedef struct immap { u8 res1[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res2[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ u8 res3[0x1000]; spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ @@ -721,7 +721,7 @@ typedef struct immap { u8 res1[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res2[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ u8 res3[0x1000]; spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ @@ -766,7 +766,7 @@ typedef struct immap { u8 res1[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res2[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ u8 res3[0x1000]; spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ @@ -816,7 +816,7 @@ typedef struct immap { u8 res4[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res5[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ u8 res6[0x2000]; dma83xx_t dma; /* DMA */ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ @@ -855,7 +855,7 @@ typedef struct immap { u8 res3[0x1300]; duart83xx_t duart[2]; /* DUART */ u8 res4[0x900]; - fsl_lbus_t lbus; /* Local Bus Controller Registers */ + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ u8 res5[0x2000]; dma83xx_t dma; /* DMA */ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ @@ -879,6 +879,7 @@ typedef struct immap { #endif #define CONFIG_SYS_MPC83xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET) +#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) #define CONFIG_SYS_TSEC1_OFFSET 0x24000 #define CONFIG_SYS_MDIO1_OFFSET 0x24000 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 5b205d1..4e665d3 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -266,50 +266,6 @@ typedef struct ccsr_duart { } ccsr_duart_t; #endif -/* Local Bus Controller Registers */ -typedef struct ccsr_lbc { - u32 br0; /* LBC Base 0 */ - u32 or0; /* LBC Options 0 */ - u32 br1; /* LBC Base 1 */ - u32 or1; /* LBC Options 1 */ - u32 br2; /* LBC Base 2 */ - u32 or2; /* LBC Options 2 */ - u32 br3; /* LBC Base 3 */ - u32 or3; /* LBC Options 3 */ - u32 br4; /* LBC Base 4 */ - u32 or4; /* LBC Options 4 */ - u32 br5; /* LBC Base 5 */ - u32 or5; /* LBC Options 5 */ - u32 br6; /* LBC Base 6 */ - u32 or6; /* LBC Options 6 */ - u32 br7; /* LBC Base 7 */ - u32 or7; /* LBC Options 7 */ - u8 res1[40]; - u32 mar; /* LBC UPM Addr */ - u8 res2[4]; - u32 mamr; /* LBC UPMA Mode */ - u32 mbmr; /* LBC UPMB Mode */ - u32 mcmr; /* LBC UPMC Mode */ - u8 res3[8]; - u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */ - u32 mdr; /* LBC UPM Data */ - u8 res4[8]; - u32 lsdmr; /* LBC SDRAM Mode */ - u8 res5[8]; - u32 lurt; /* LBC UPM Refresh Timer */ - u32 lsrt; /* LBC SDRAM Refresh Timer */ - u8 res6[8]; - u32 ltesr; /* LBC Transfer Error Status */ - u32 ltedr; /* LBC Transfer Error Disable */ - u32 lteir; /* LBC Transfer Error IRQ */ - u32 lteatr; /* LBC Transfer Error Attrs */ - u32 ltear; /* LBC Transfer Error Addr */ - u8 res7[12]; - u32 lbcr; /* LBC Configuration */ - u32 lcrr; /* LBC Clock Ratio */ - u8 res8[3880]; -} ccsr_lbc_t; - /* eSPI Registers */ typedef struct ccsr_espi { u32 mode; /* eSPI mode */ @@ -2045,6 +2001,41 @@ enum { FSL_SRDS_B3_LANE_D = 23, }; +/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ +#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 +typedef struct ccsr_sec { + u8 res1[0xfa0]; + u32 crnr_ms; /* CHA Revision Number Register, MS */ + u32 crnr_ls; /* CHA Revision Number Register, LS */ + u32 ctpr_ms; /* Compile Time Parameters Register, MS */ +#define SEC_CTPR_MS_AXI_LIODN 0x08000000 +#define SEC_CTPR_MS_QI 0x02000000 + u32 ctpr_ls; /* Compile Time Parameters Register, LS */ + u8 res2[0x10]; + u32 far_ms; /* Fault Address Register, MS */ + u32 far_ls; /* Fault Address Register, LS */ + u32 falr; /* Fault Address LIODN Register */ + u32 fadr; /* Fault Address Detail Register */ + u8 res3[0x4]; + u32 csta; /* CAAM Status Register */ + u8 res4[0x8]; + u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ +#define SEC_RVID_MA 0x0f000000 + u32 ccbvid; /* CHA Cluster Block Version ID Register */ + u32 chavid_ms; /* CHA Version ID Register, MS */ + u32 chavid_ls; /* CHA Version ID Register, LS */ + u32 chanum_ms; /* CHA Number Register, MS */ +#define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000 +#define SEC_CHANUM_MS_JQNUM_SHIFT 28 +#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 +#define SEC_CHANUM_MS_DECONUM_SHIFT 24 + u32 chanum_ls; /* CHA Number Register, LS */ + u32 caamvid_ms; /* CAAM Version ID Register, MS */ + u32 caamvid_ls; /* CAAM Version ID Register, LS */ + u8 res5[0xf000]; +} ccsr_sec_t; +#endif + #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 @@ -2059,6 +2050,7 @@ enum { #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000 +#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 #define CONFIG_SYS_TSEC1_OFFSET 0x4e0000 /* FM1@DTSEC0 */ @@ -2111,7 +2103,7 @@ enum { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) #define CONFIG_SYS_MPC85xx_DDR2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) -#define CONFIG_SYS_MPC85xx_LBC_ADDR \ +#define CONFIG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) #define CONFIG_SYS_MPC85xx_ESPI_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) @@ -2143,6 +2135,8 @@ enum { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) #define CONFIG_SYS_MPC85xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) +#define CONFIG_SYS_FSL_SEC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index fd7acdb..b9e02db 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -12,6 +12,7 @@ #include <asm/types.h> #include <asm/fsl_dma.h> +#include <asm/fsl_lbc.h> #include <asm/fsl_i2c.h> /* Local-Access Registers and MCM Registers(0x0000-0x2000) */ @@ -190,51 +191,6 @@ typedef struct ccsr_duart { char res5[2543]; } ccsr_duart_t; - -/* Local Bus Controller Registers(0x5000-0x6000) */ -typedef struct ccsr_lbc { - uint br0; /* 0x5000 - LBC Base Register 0 */ - uint or0; /* 0x5004 - LBC Options Register 0 */ - uint br1; /* 0x5008 - LBC Base Register 1 */ - uint or1; /* 0x500c - LBC Options Register 1 */ - uint br2; /* 0x5010 - LBC Base Register 2 */ - uint or2; /* 0x5014 - LBC Options Register 2 */ - uint br3; /* 0x5018 - LBC Base Register 3 */ - uint or3; /* 0x501c - LBC Options Register 3 */ - uint br4; /* 0x5020 - LBC Base Register 4 */ - uint or4; /* 0x5024 - LBC Options Register 4 */ - uint br5; /* 0x5028 - LBC Base Register 5 */ - uint or5; /* 0x502c - LBC Options Register 5 */ - uint br6; /* 0x5030 - LBC Base Register 6 */ - uint or6; /* 0x5034 - LBC Options Register 6 */ - uint br7; /* 0x5038 - LBC Base Register 7 */ - uint or7; /* 0x503c - LBC Options Register 7 */ - char res1[40]; - uint mar; /* 0x5068 - LBC UPM Address Register */ - char res2[4]; - uint mamr; /* 0x5070 - LBC UPMA Mode Register */ - uint mbmr; /* 0x5074 - LBC UPMB Mode Register */ - uint mcmr; /* 0x5078 - LBC UPMC Mode Register */ - char res3[8]; - uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */ - uint mdr; /* 0x5088 - LBC UPM Data Register */ - char res4[8]; - uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */ - char res5[8]; - uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */ - uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */ - char res6[8]; - uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */ - uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */ - uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */ - uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */ - uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */ - char res7[12]; - uint lbcr; /* 0x50d0 - LBC Configuration Register */ - uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */ - char res8[3880]; -} ccsr_lbc_t; - /* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */ typedef struct ccsr_pex { uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */ @@ -1270,7 +1226,7 @@ typedef struct immap { ccsr_ddr_t im_ddr1; ccsr_i2c_t im_i2c; ccsr_duart_t im_duart; - ccsr_lbc_t im_lbc; + fsl_lbc_t im_lbc; ccsr_ddr_t im_ddr2; char res1[4096]; ccsr_pex_t im_pex1; @@ -1303,6 +1259,7 @@ extern immap_t *immr; #define CONFIG_SYS_TSEC1_OFFSET 0x24000 #define CONFIG_SYS_MDIO1_OFFSET 0x24000 +#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index 5166507..c01c85f 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -402,6 +402,7 @@ extern void print_bats(void); #define MAS1_TID(x) ((x << 16) & 0x3FFF0000) #define MAS1_TS 0x00001000 #define MAS1_TSIZE(x) ((x << 8) & 0x00000F00) +#define TSIZE_TO_BYTES(x) ((phys_addr_t)(1UL << ((tsize * 2) + 10))) #define MAS2_EPN 0xFFFFF000 #define MAS2_X0 0x00000040 @@ -485,6 +486,7 @@ extern void init_tlbs(void); extern int find_tlb_idx(void *addr, u8 tlbsel); extern void init_used_tlb_cams(void); extern int find_free_tlbcam(void); +extern void print_tlbcam(void); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); diff --git a/arch/powerpc/include/asm/mp.h b/arch/powerpc/include/asm/mp.h index 5388c95..3ffa30b 100644 --- a/arch/powerpc/include/asm/mp.h +++ b/arch/powerpc/include/asm/mp.h @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -26,5 +26,6 @@ void setup_mp(void); void cpu_mp_lmb_reserve(struct lmb *lmb); u32 determine_mp_bootpg(void); +int is_core_disabled(int nr); #endif diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 9ec319a..844552c 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -534,9 +534,11 @@ #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ #define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ +#define BUCSR_STAC_EN 0x01000000 /* Segment target addr cache enable */ +#define BUCSR_LS_EN 0x00400000 /* Link stack enable */ #define BUCSR_BBFI 0x00000200 /* Branch buffer flash invalidate */ #define BUCSR_BPEN 0x00000001 /* Branch prediction enable */ -#define BUCSR_ENABLE (BUCSR_BBFI|BUCSR_BPEN) +#define BUCSR_ENABLE (BUCSR_STAC_EN|BUCSR_LS_EN|BUCSR_BBFI|BUCSR_BPEN) #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ #define SPRN_PID1 0x279 /* Process ID Register 1 */ |