7 files changed, 12 insertions, 12 deletions
diff --git a/arch/powerpc/include/asm/cpm_8260.h b/arch/powerpc/include/asm/cpm_8260.h
index 8302404..6a4a51a 100644
--- a/arch/powerpc/include/asm/cpm_8260.h
+++ b/arch/powerpc/include/asm/cpm_8260.h
@@ -117,7 +117,7 @@ typedef struct cpm_buf_desc {
 	uint	cbd_bufaddr;	/* Buffer address in host memory */
 } cbd_t;
 
-#define BD_SC_EMPTY	((ushort)0x8000)	/* Recieve is empty */
+#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
 #define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h
index a74a3a1..1681ecd 100644
--- a/arch/powerpc/include/asm/cpm_85xx.h
+++ b/arch/powerpc/include/asm/cpm_85xx.h
@@ -110,7 +110,7 @@ typedef struct cpm_buf_desc {
 	uint	cbd_bufaddr;	/* Buffer address in host memory */
 } cbd_t;
 
-#define BD_SC_EMPTY	((ushort)0x8000)	/* Recieve is empty */
+#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
 #define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
diff --git a/arch/powerpc/include/asm/ppc440ep_gr.h b/arch/powerpc/include/asm/ppc440ep_gr.h
index dfd1532..e790963 100644
--- a/arch/powerpc/include/asm/ppc440ep_gr.h
+++ b/arch/powerpc/include/asm/ppc440ep_gr.h
@@ -182,7 +182,7 @@
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
@@ -192,7 +192,7 @@
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
diff --git a/arch/powerpc/include/asm/ppc440epx_grx.h b/arch/powerpc/include/asm/ppc440epx_grx.h
index 6c21472..c841f0f 100644
--- a/arch/powerpc/include/asm/ppc440epx_grx.h
+++ b/arch/powerpc/include/asm/ppc440epx_grx.h
@@ -398,7 +398,7 @@
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
@@ -408,7 +408,7 @@
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
diff --git a/arch/powerpc/include/asm/ppc440gx.h b/arch/powerpc/include/asm/ppc440gx.h
index 6f8581b..9924525 100644
--- a/arch/powerpc/include/asm/ppc440gx.h
+++ b/arch/powerpc/include/asm/ppc440gx.h
@@ -71,7 +71,7 @@
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
@@ -81,7 +81,7 @@
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
diff --git a/arch/powerpc/include/asm/ppc440sp.h b/arch/powerpc/include/asm/ppc440sp.h
index 4387495..cc2ff68 100644
--- a/arch/powerpc/include/asm/ppc440sp.h
+++ b/arch/powerpc/include/asm/ppc440sp.h
@@ -67,7 +67,7 @@
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
@@ -77,7 +77,7 @@
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
diff --git a/arch/powerpc/include/asm/ppc440spe.h b/arch/powerpc/include/asm/ppc440spe.h
index bad9a40..d59d7d2 100644
--- a/arch/powerpc/include/asm/ppc440spe.h
+++ b/arch/powerpc/include/asm/ppc440spe.h
@@ -83,7 +83,7 @@
 #define PLLD_LFBDV_MASK		0x0000003f  /* PLL Local Feedback Divisor */
 
 #define OPBDDV_MASK		0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK		0x07000000  /* Periferal Clock Divisor */
+#define PERDV_MASK		0x07000000  /* Peripheral Clock Divisor */
 #define PRADV_MASK		0x07000000  /* Primary Divisor A */
 #define PRBDV_MASK		0x07000000  /* Primary Divisor B */
 #define SPCID_MASK		0x03000000  /* Sync PCI Divisor  */
@@ -93,7 +93,7 @@
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
 #define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
-#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Address reset vector */
 #define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
 #define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
 #define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */