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-rw-r--r--arch/powerpc/include/asm/cache.h2
-rw-r--r--arch/powerpc/include/asm/ppc405.h4
2 files changed, 1 insertions, 5 deletions
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index e6b8f69..5f9c640 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -8,7 +8,7 @@
#include <asm/processor.h>
/* bytes per L1 cache line */
-#if defined(CONFIG_8xx) || defined(CONFIG_IOP480)
+#if defined(CONFIG_8xx)
#define L1_CACHE_SHIFT 4
#elif defined(CONFIG_PPC64BRIDGE)
#define L1_CACHE_SHIFT 7
diff --git a/arch/powerpc/include/asm/ppc405.h b/arch/powerpc/include/asm/ppc405.h
index 14a7a37..892848a 100644
--- a/arch/powerpc/include/asm/ppc405.h
+++ b/arch/powerpc/include/asm/ppc405.h
@@ -28,11 +28,7 @@
#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
-#ifndef CONFIG_IOP480
#define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
-#else
-#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480(403)*/
-#endif
/* DCR registers */
#define PLB0_ACR 0x0087