diff options
Diffstat (limited to 'arch/powerpc/include/asm')
| -rw-r--r-- | arch/powerpc/include/asm/config.h | 4 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 205 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc86xx.h | 6 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/cpm_85xx.h | 2 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_law.h | 12 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_lbc.h | 6 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_secure_boot.h | 39 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 98 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_86xx.h | 2 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/processor.h | 2 |
10 files changed, 123 insertions, 253 deletions
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index bb23756..9d3a3b4 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -57,10 +57,6 @@ #endif #endif -#ifndef CONFIG_MAX_CPUS -#define CONFIG_MAX_CPUS 1 -#endif - /* * Provide a default boot page translation virtual address that lines up with * Freescale's default e500 reset page. diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 6d845e8..c92bc1e 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -35,8 +35,7 @@ #define CONFIG_SYS_NUM_TLBCAMS 16 #endif -#if defined(CONFIG_MPC8536) -#define CONFIG_MAX_CPUS 1 +#if defined(CONFIG_ARCH_MPC8536) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -44,21 +43,18 @@ #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 -#elif defined(CONFIG_MPC8540) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_MPC8540) #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#elif defined(CONFIG_MPC8541) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_MPC8541) #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#elif defined(CONFIG_MPC8544) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_MPC8544) #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 @@ -66,8 +62,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_A005125 -#elif defined(CONFIG_MPC8548) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_MPC8548) #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 @@ -85,21 +80,18 @@ #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 -#elif defined(CONFIG_MPC8555) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_MPC8555) #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#elif defined(CONFIG_MPC8560) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_MPC8560) #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#elif defined(CONFIG_MPC8568) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_MPC8568) #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -113,8 +105,7 @@ #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 -#elif defined(CONFIG_MPC8569) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_MPC8569) #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define QE_MURAM_SIZE 0x20000UL @@ -129,8 +120,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 -#elif defined(CONFIG_MPC8572) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_MPC8572) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -140,8 +130,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 -#elif defined(CONFIG_P1010) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 @@ -169,8 +158,7 @@ #define CONFIG_ESDHC_HC_BLK_ADDR /* P1011 is single core version of P1020 */ -#elif defined(CONFIG_P1011) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_P1011) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 @@ -183,75 +171,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 -/* P1012 is single core version of P1021 */ -#elif defined(CONFIG_P1012) -#define CONFIG_MAX_CPUS 1 -#define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 -#define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM -#define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define QE_MURAM_SIZE 0x6000UL -#define MAX_QE_RISC 1 -#define QE_NUM_OF_SNUM 28 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125 - -/* P1013 is single core version of P1022 */ -#elif defined(CONFIG_P1013) -#define CONFIG_MAX_CPUS 1 -#define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 -#define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_FSL_SATA_ERRATUM_A001 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125 - -#elif defined(CONFIG_P1014) -#define CONFIG_MAX_CPUS 1 -#define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 -#define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 -#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 -#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 -#define CONFIG_SYS_FSL_ERRATUM_A004508 - -/* P1017 is single core version of P1023 */ -#elif defined(CONFIG_P1017) -#define CONFIG_MAX_CPUS 1 -#define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 2 -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_QMAN_NUM_PORTALS 3 -#define CONFIG_SYS_BMAN_NUM_PORTALS 3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x10000 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125 - -#elif defined(CONFIG_P1020) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_P1020) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 @@ -266,8 +186,7 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif -#elif defined(CONFIG_P1021) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_P1021) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 @@ -283,8 +202,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#elif defined(CONFIG_P1022) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_P1022) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 @@ -298,8 +216,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_A004477 -#elif defined(CONFIG_P1023) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_P1023) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 @@ -317,8 +234,7 @@ #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 /* P1024 is lower end variant of P1020 */ -#elif defined(CONFIG_P1024) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_P1024) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 @@ -332,8 +248,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1025 is lower end variant of P1021 */ -#elif defined(CONFIG_P1025) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_P1025) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 @@ -349,21 +264,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 -/* P2010 is single core version of P2020 */ -#elif defined(CONFIG_P2010) -#define CONFIG_MAX_CPUS 1 -#define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 -#define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 -#define CONFIG_SYS_FSL_ERRATUM_A004508 -#define CONFIG_SYS_FSL_ERRATUM_A005125 - -#elif defined(CONFIG_P2020) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_P2020) #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -380,10 +281,9 @@ #define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ +#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -418,10 +318,9 @@ #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 -#elif defined(CONFIG_PPC_P3041) +#elif defined(CONFIG_ARCH_P3041) #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -458,10 +357,9 @@ #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 -#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ +#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_MAX_CPUS 8 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -509,11 +407,10 @@ #define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 -#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ +#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -545,11 +442,10 @@ #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 -#elif defined(CONFIG_PPC_P5040) +#elif defined(CONFIG_ARCH_P5040) #define CONFIG_SYS_PPC64 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -579,8 +475,7 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #define CONFIG_SYS_FSL_ERRATUM_A005812 -#elif defined(CONFIG_BSC9131) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 @@ -598,8 +493,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_ESDHC_HC_BLK_ADDR -#elif defined(CONFIG_BSC9132) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_BSC9132) #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 @@ -625,16 +519,14 @@ #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR -#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) +#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ -#ifdef CONFIG_PPC_T4240 -#define CONFIG_MAX_CPUS 12 +#ifdef CONFIG_ARCH_T4240 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 @@ -648,12 +540,8 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 8 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 -#if defined(CONFIG_PPC_T4160) -#define CONFIG_MAX_CPUS 8 +#if defined(CONFIG_ARCH_T4160) #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#elif defined(CONFIG_PPC_T4080) -#define CONFIG_MAX_CPUS 4 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } #endif #endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 @@ -691,7 +579,7 @@ #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_PCI_VER_3_X -#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) +#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -733,9 +621,8 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 -#ifdef CONFIG_PPC_B4860 +#ifdef CONFIG_ARCH_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 -#define CONFIG_MAX_CPUS 4 #define CONFIG_MAX_DSP_CPUS 12 #define CONFIG_NUM_DSP_CPUS 6 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 @@ -749,7 +636,6 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_SRIO_LIODN #else -#define CONFIG_MAX_CPUS 2 #define CONFIG_MAX_DSP_CPUS 2 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 @@ -759,7 +645,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #endif -#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ +#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -769,11 +655,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #ifdef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDRC_GEN4 #endif -#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) -#define CONFIG_MAX_CPUS 4 -#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) -#define CONFIG_MAX_CPUS 2 -#endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_NUM_LAWS 16 @@ -810,7 +691,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_ERRATUM_A008378 #define CONFIG_SYS_FSL_ERRATUM_A009663 -#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ +#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -821,11 +702,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #ifdef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDRC_GEN4 #endif -#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) -#define CONFIG_MAX_CPUS 2 -#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) -#define CONFIG_MAX_CPUS 1 -#endif #define CONFIG_SYS_FSL_NUM_CC_PLL 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_NUM_LAWS 16 @@ -859,7 +735,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_ERRATUM_A008378 #define CONFIG_SYS_FSL_ERRATUM_A009663 -#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -867,14 +743,13 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_QMAN_V3 -#define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_PCI_VER_3_X -#if defined(CONFIG_PPC_T2080) +#if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 4 #define CONFIG_SYS_FSL_SRDS_2 @@ -882,7 +757,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#elif defined(CONFIG_PPC_T2081) +#elif defined(CONFIG_ARCH_T2081) #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 #endif @@ -914,8 +789,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_SFP_VER_3_0 -#elif defined(CONFIG_PPC_C29X) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_C29X) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 @@ -930,8 +804,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 -#elif defined(CONFIG_QEMU_E500) -#define CONFIG_MAX_CPUS 1 +#elif defined(CONFIG_ARCH_QEMU_E500) #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000 #else @@ -955,7 +828,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_DDRC_GEN3 #endif -#if !defined(CONFIG_PPC_C29X) +#if !defined(CONFIG_ARCH_C29X) #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #endif diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h index 4f9b225..c41dc99 100644 --- a/arch/powerpc/include/asm/config_mpc86xx.h +++ b/arch/powerpc/include/asm/config_mpc86xx.h @@ -11,12 +11,10 @@ /* SoC specific defines for Freescale MPC86xx processors */ -#if defined(CONFIG_MPC8610) -#define CONFIG_MAX_CPUS 1 +#if defined(CONFIG_ARCH_MPC8610) #define CONFIG_SYS_FSL_NUM_LAWS 10 -#elif defined(CONFIG_MPC8641) -#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_ARCH_MPC8641) #define CONFIG_SYS_FSL_NUM_LAWS 10 #else diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h index b137a71..b46e20e 100644 --- a/arch/powerpc/include/asm/cpm_85xx.h +++ b/arch/powerpc/include/asm/cpm_85xx.h @@ -77,7 +77,7 @@ */ #define CPM_DATAONLY_BASE ((uint)128) #define CPM_DP_NOSPACE ((uint)0x7FFFFFFF) -#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) #define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) #else /* MPC8540, MPC8560 */ diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 2a759c8..b348cc1 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -79,13 +79,13 @@ enum law_trgt_if { enum law_trgt_if { LAW_TRGT_IF_PCI = 0x00, LAW_TRGT_IF_PCI_2 = 0x01, -#ifndef CONFIG_MPC8641 +#ifndef CONFIG_ARCH_MPC8641 LAW_TRGT_IF_PCIE_1 = 0x02, #endif -#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) +#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) LAW_TRGT_IF_OCN_DSP = 0x03, #else -#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020) +#if !defined(CONFIG_ARCH_MPC8572) && !defined(CONFIG_ARCH_P2020) LAW_TRGT_IF_PCIE_3 = 0x03, #endif #endif @@ -95,7 +95,7 @@ enum law_trgt_if { LAW_TRGT_IF_PLATFORM_SRAM = 0x0a, LAW_TRGT_IF_DDR_INTRLV = 0x0b, LAW_TRGT_IF_RIO = 0x0c, -#if defined(CONFIG_BSC9132) +#if defined(CONFIG_ARCH_BSC9132) LAW_TRGT_IF_CLASS_DSP = 0x0d, #else LAW_TRGT_IF_RIO_2 = 0x0d, @@ -117,11 +117,11 @@ enum law_trgt_if { #define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO #define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC -#ifdef CONFIG_MPC8641 +#ifdef CONFIG_ARCH_MPC8641 #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI #endif -#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) +#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020) #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI #endif #endif /* CONFIG_FSL_CORENET */ diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 402edd7..b8270c5 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -325,9 +325,9 @@ void lbc_sdram_init(void); */ #define LCRR_CLKDIV 0x0000001F #define LCRR_CLKDIV_SHIFT 0 -#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \ - defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \ - defined(CONFIG_MPC8560) +#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \ + defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) || \ + defined(CONFIG_ARCH_MPC8560) #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 #define LCRR_CLKDIV_8 0x00000008 diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index f9154d3..808adae 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -16,25 +16,30 @@ #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 -#elif defined(CONFIG_BSC9132QDS) +#elif defined(CONFIG_TARGET_BSC9132QDS) #define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 -#elif defined(CONFIG_C29XPCIE) +#elif defined(CONFIG_TARGET_C29XPCIE) #define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000 #else #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 #endif #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 -#if defined(CONFIG_B4860QDS) || \ - defined(CONFIG_T4240QDS) || \ +#if defined(CONFIG_TARGET_B4860QDS) || \ + defined(CONFIG_TARGET_B4420QDS) || \ + defined(CONFIG_TARGET_T4160QDS) || \ + defined(CONFIG_TARGET_T4240QDS) || \ defined(CONFIG_T2080QDS) || \ defined(CONFIG_T2080RDB) || \ defined(CONFIG_T1040QDS) || \ defined(CONFIG_T104xD4QDS) || \ - defined(CONFIG_T104xRDB) || \ - defined(CONFIG_T104xD4RDB) || \ - defined(CONFIG_PPC_T1023) || \ - defined(CONFIG_PPC_T1024) + defined(CONFIG_TARGET_T1040RDB) || \ + defined(CONFIG_TARGET_T1040D4RDB) || \ + defined(CONFIG_TARGET_T1042RDB) || \ + defined(CONFIG_TARGET_T1042D4RDB) || \ + defined(CONFIG_TARGET_T1042RDB_PI) || \ + defined(CONFIG_ARCH_T1023) || \ + defined(CONFIG_ARCH_T1024) #ifndef CONFIG_SYS_RAMBOOT #define CONFIG_SYS_CPC_REINIT_F #endif @@ -54,15 +59,15 @@ #endif #endif -#if defined(CONFIG_C29XPCIE) +#if defined(CONFIG_TARGET_C29XPCIE) #define CONFIG_KEY_REVOCATION #endif -#if defined(CONFIG_PPC_P3041) || \ - defined(CONFIG_PPC_P4080) || \ - defined(CONFIG_PPC_P5020) || \ - defined(CONFIG_PPC_P5040) || \ - defined(CONFIG_PPC_P2041) +#if defined(CONFIG_ARCH_P3041) || \ + defined(CONFIG_ARCH_P4080) || \ + defined(CONFIG_ARCH_P5020) || \ + defined(CONFIG_ARCH_P5040) || \ + defined(CONFIG_ARCH_P2041) #define CONFIG_FSL_TRUST_ARCH_v1 #endif @@ -134,13 +139,13 @@ /* The bootscript header address is different for B4860 because the NOR * mapping is different on B4 due to reduced NOR size. */ -#if defined(CONFIG_B4860QDS) +#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS) #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000 #elif defined(CONFIG_FSL_CORENET) #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000 -#elif defined(CONFIG_BSC9132QDS) +#elif defined(CONFIG_TARGET_BSC9132QDS) #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000 -#elif defined(CONFIG_C29XPCIE) +#elif defined(CONFIG_TARGET_C29XPCIE) #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000 #else #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 76ea00b..786e4f6 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -124,10 +124,10 @@ typedef struct ccsr_i2c { u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)]; } ccsr_i2c_t; -#if defined(CONFIG_MPC8540) \ - || defined(CONFIG_MPC8541) \ - || defined(CONFIG_MPC8548) \ - || defined(CONFIG_MPC8555) +#if defined(CONFIG_ARCH_MPC8540) || \ + defined(CONFIG_ARCH_MPC8541) || \ + defined(CONFIG_ARCH_MPC8548) || \ + defined(CONFIG_ARCH_MPC8555) /* DUART Registers */ typedef struct ccsr_duart { u8 res1[1280]; @@ -1759,8 +1759,7 @@ typedef struct ccsr_gur { /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) +#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 @@ -1770,13 +1769,13 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 -#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) +#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 -#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ +#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 @@ -1797,7 +1796,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 -#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) || \ +#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) || \ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23 @@ -1812,7 +1811,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 -#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 @@ -1848,7 +1847,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */ -#ifdef CONFIG_PPC_P4080 +#ifdef CONFIG_ARCH_P4080 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */ @@ -1856,8 +1855,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 #endif -#if defined(CONFIG_PPC_P2041) \ - || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020) +#if defined(CONFIG_ARCH_P2041) || \ + defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020) #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000 @@ -1866,7 +1865,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_PPC_P5040) +#if defined(CONFIG_ARCH_P5040) #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000 @@ -1875,8 +1874,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) +#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 @@ -1885,7 +1883,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 #endif -#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000 @@ -2120,16 +2118,16 @@ typedef struct ccsr_rcpm { #else typedef struct ccsr_gur { u32 porpllsr; /* POR PLL ratio status */ -#ifdef CONFIG_MPC8536 +#ifdef CONFIG_ARCH_MPC8536 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 -#elif defined(CONFIG_PPC_C29X) +#elif defined(CONFIG_ARCH_C29X) #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \ & MPC85xx_PORDEVSR2_DDR_SPD_0) \ >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT)) #else -#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) +#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 #else #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 @@ -2150,7 +2148,7 @@ typedef struct ccsr_gur { #define PORBMSR_ROMLOC_NOR 0xf u32 porimpscr; /* POR I/O impedance status & control */ u32 pordevsr; /* POR I/O device status regsiter */ -#if defined(CONFIG_P1017) || defined(CONFIG_P1023) +#if defined(CONFIG_ARCH_P1023) #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000 #define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000 @@ -2162,26 +2160,26 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 #define MPC85xx_PORDEVSR_PCI1 0x00800000 -#if defined(CONFIG_P1013) || defined(CONFIG_P1022) +#if defined(CONFIG_ARCH_P1022) #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 -#elif defined(CONFIG_P1017) || defined(CONFIG_P1023) +#elif defined(CONFIG_ARCH_P1023) #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 #else -#if defined(CONFIG_P1010) +#if defined(CONFIG_ARCH_P1010) #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 -#elif defined(CONFIG_BSC9132) +#elif defined(CONFIG_ARCH_BSC9132) #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17 -#elif defined(CONFIG_PPC_C29X) +#elif defined(CONFIG_ARCH_C29X) #define MPC85xx_PORDEVSR_IO_SEL 0x00e00000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 #else #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 -#endif /* if defined(CONFIG_P1010) */ +#endif /* if defined(CONFIG_ARCH_P1010) */ #endif #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 @@ -2193,7 +2191,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 u32 pordbgmsr; /* POR debug mode status */ u32 pordevsr2; /* POR I/O device status 2 */ -#if defined(CONFIG_PPC_C29X) +#if defined(CONFIG_ARCH_C29X) #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3 #endif @@ -2203,14 +2201,14 @@ typedef struct ccsr_gur { u8 res1[8]; u32 gpporcr; /* General-purpose POR configuration */ u8 res2[12]; -#if defined(CONFIG_MPC8536) +#if defined(CONFIG_ARCH_MPC8536) u32 gencfgr; /* General Configuration Register */ #define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000 #else u32 gpiocr; /* GPIO control */ #endif u8 res3[12]; -#if defined(CONFIG_MPC8569) +#if defined(CONFIG_ARCH_MPC8569) u32 plppar1; /* Platform port pin assignment 1 */ u32 plppar2; /* Platform port pin assignment 2 */ u32 plpdir1; /* Platform port pin direction 1 */ @@ -2222,7 +2220,7 @@ typedef struct ccsr_gur { u32 gpindr; /* General-purpose input data */ u8 res5[12]; u32 pmuxcr; /* Alt. function signal multiplex control */ -#if defined(CONFIG_P1010) || defined(CONFIG_P1014) +#if defined(CONFIG_ARCH_P1010) #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000 #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000 @@ -2268,7 +2266,7 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002 #define MPC85xx_PMUXCR_CAN2_RES 0x00000003 #endif -#if defined(CONFIG_P1017) || defined(CONFIG_P1023) +#if defined(CONFIG_ARCH_P1023) #define MPC85xx_PMUXCR_TSEC1_1 0x10000000 #else #define MPC85xx_PMUXCR_SD_DATA 0x80000000 @@ -2290,13 +2288,13 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_QE11 0x00000010 #define MPC85xx_PMUXCR_QE12 0x00000008 #endif -#if defined(CONFIG_P1013) || defined(CONFIG_P1022) +#if defined(CONFIG_ARCH_P1022) #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00 #define MPC85xx_PMUXCR_TDM 0x00014800 #define MPC85xx_PMUXCR_SPI_MASK 0x00600000 #define MPC85xx_PMUXCR_SPI 0x00000000 #endif -#if defined(CONFIG_BSC9131) +#if defined(CONFIG_ARCH_BSC9131) #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000 #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000 #define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000 @@ -2340,17 +2338,17 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003 #endif -#ifdef CONFIG_BSC9132 +#ifdef CONFIG_ARCH_BSC9132 #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000 #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000 #endif -#if defined(CONFIG_PPC_C29X) +#if defined(CONFIG_ARCH_C29X) #define MPC85xx_PMUXCR_SPI_MASK 0x00000300 #define MPC85xx_PMUXCR_SPI 0x00000000 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000100 #endif u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ -#if defined(CONFIG_P1010) || defined(CONFIG_P1014) +#if defined(CONFIG_ARCH_P1010) #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 #define MPC85xx_PMUXCR2_UART_TDM 0x80000000 #define MPC85xx_PMUXCR2_UART_RES 0xC0000000 @@ -2375,12 +2373,12 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 #endif -#if defined(CONFIG_P1013) || defined(CONFIG_P1022) +#if defined(CONFIG_ARCH_P1022) #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 #define MPC85xx_PMUXCR2_USB 0x00150000 #endif -#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) -#if defined(CONFIG_BSC9131) +#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) +#if defined(CONFIG_ARCH_BSC9131) #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000 #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000 @@ -2425,7 +2423,7 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002 #endif u32 pmuxcr3; -#if defined(CONFIG_BSC9131) +#if defined(CONFIG_ARCH_BSC9131) #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000 @@ -2441,7 +2439,7 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000 #define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000 #endif -#ifdef CONFIG_BSC9132 +#ifdef CONFIG_ARCH_BSC9132 #define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00 #define MPC85xx_PMUXCR3_UART2_SEL 0x00005000 #define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000 @@ -2484,11 +2482,11 @@ typedef struct ccsr_gur { u32 svr; /* System version */ u8 res10[8]; u32 rstcr; /* Reset control */ -#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) +#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569) u8 res11a[76]; par_io_t qe_par_io[7]; u8 res11b[1600]; -#elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) +#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) u8 res11a[12]; u32 iovselsr; u8 res11b[60]; @@ -2504,7 +2502,7 @@ typedef struct ccsr_gur { u32 ddrdllcr; /* DDR DLL control */ u8 res14[12]; u32 lbcdllcr; /* LBC DLL control */ -#if defined(CONFIG_BSC9131) +#if defined(CONFIG_ARCH_BSC9131) u8 res15[12]; u32 halt_req_mask; #define HALTED_TO_HALT_REQ_MASK_0 0x80000000 @@ -2883,8 +2881,8 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000 #define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 -#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\ - && !defined(CONFIG_PPC_B4420) +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \ + !defined(CONFIG_ARCH_B4420) #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000 @@ -2940,7 +2938,7 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000 -#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) +#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020) #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000 #else #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000 @@ -2964,7 +2962,7 @@ struct ccsr_pman { #endif #define CONFIG_SYS_MDIO1_OFFSET 0x24000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 -#if defined(CONFIG_PPC_C29X) +#if defined(CONFIG_ARCH_C29X) #define CONFIG_SYS_FSL_SEC_OFFSET 0x80000 #define CONFIG_SYS_FSL_JR0_OFFSET 0x81000 #else @@ -2988,7 +2986,7 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 -#if defined(CONFIG_BSC9132) +#if defined(CONFIG_ARCH_BSC9132) #define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \ (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET) diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index b078569..1fbc63a 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -1195,7 +1195,7 @@ extern immap_t *immr; #define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000 -#ifdef CONFIG_MPC8610 +#ifdef CONFIG_ARCH_MPC8610 #define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0xa000 #else #define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0x8000 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index fdfca90..fbf72bb 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1048,7 +1048,7 @@ #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ -#ifdef CONFIG_MPC8536 +#ifdef CONFIG_ARCH_MPC8536 #define SVR_MAJ(svr) (((svr) >> 4) & 0x7) /* Major revision field*/ #else #define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ |