diff options
Diffstat (limited to 'arch/powerpc/include/asm/immap_85xx.h')
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 6c11178..7c35b41 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1761,6 +1761,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000 +#define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */ #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */ @@ -1786,6 +1787,15 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000 #endif +#if defined(CONFIG_PPC_P5040) +#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000 +#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000 +#define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */ +#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 +#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 +#endif u8 res18[192]; u32 scratchrw[4]; /* Scratch Read/Write */ u8 res19[240]; @@ -2395,6 +2405,7 @@ typedef struct serdes_corenet { #define SRDS_RSTCTL_SDPD 0x00000020 u32 pllcr0; /* PLL Control Register 0 */ #define SRDS_PLLCR0_RFCK_SEL_MASK 0x30000000 +#define SRDS_PLLCR0_PVCOCNT_EN 0x02000000 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 @@ -2423,6 +2434,7 @@ typedef struct serdes_corenet { u32 gcr0; /* General Control Register 0 */ #define SRDS_GCR0_RRST 0x00400000 #define SRDS_GCR0_1STLANE 0x00010000 +#define SRDS_GCR0_UOTHL 0x00100000 u32 gcr1; /* General Control Register 1 */ #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000 #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000 @@ -2627,6 +2639,7 @@ struct ccsr_rman { #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 +#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 @@ -2777,6 +2790,8 @@ struct ccsr_rman { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) +#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET) #define CONFIG_SYS_MPC85xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \ |